1 /* 2 * QEMU Sun4u/Sun4v System Emulator 3 * 4 * Copyright (c) 2005 Fabrice Bellard 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a copy 7 * of this software and associated documentation files (the "Software"), to deal 8 * in the Software without restriction, including without limitation the rights 9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 10 * copies of the Software, and to permit persons to whom the Software is 11 * furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 22 * THE SOFTWARE. 23 */ 24 25 #include "qemu/osdep.h" 26 #include "qemu/units.h" 27 #include "qemu/error-report.h" 28 #include "qapi/error.h" 29 #include "qemu/datadir.h" 30 #include "cpu.h" 31 #include "hw/irq.h" 32 #include "hw/pci/pci.h" 33 #include "hw/pci/pci_bridge.h" 34 #include "hw/pci/pci_host.h" 35 #include "hw/qdev-properties.h" 36 #include "hw/pci-host/sabre.h" 37 #include "hw/char/serial-isa.h" 38 #include "hw/char/serial-mm.h" 39 #include "hw/char/parallel-isa.h" 40 #include "hw/rtc/m48t59.h" 41 #include "migration/vmstate.h" 42 #include "hw/input/i8042.h" 43 #include "hw/block/fdc.h" 44 #include "net/net.h" 45 #include "qemu/timer.h" 46 #include "system/runstate.h" 47 #include "system/system.h" 48 #include "hw/boards.h" 49 #include "hw/nvram/sun_nvram.h" 50 #include "hw/nvram/chrp_nvram.h" 51 #include "hw/sparc/sparc64.h" 52 #include "hw/nvram/fw_cfg.h" 53 #include "hw/sysbus.h" 54 #include "hw/ide/pci.h" 55 #include "hw/loader.h" 56 #include "hw/fw-path-provider.h" 57 #include "elf.h" 58 #include "trace.h" 59 #include "qom/object.h" 60 61 #define KERNEL_LOAD_ADDR 0x00404000 62 #define CMDLINE_ADDR 0x003ff000 63 #define PROM_SIZE_MAX (4 * MiB) 64 #define PROM_VADDR 0x000ffd00000ULL 65 #define PBM_SPECIAL_BASE 0x1fe00000000ULL 66 #define PBM_MEM_BASE 0x1ff00000000ULL 67 #define PBM_PCI_IO_BASE (PBM_SPECIAL_BASE + 0x02000000ULL) 68 #define PROM_FILENAME "openbios-sparc64" 69 #define NVRAM_SIZE 0x2000 70 #define BIOS_CFG_IOPORT 0x510 71 #define FW_CFG_SPARC64_WIDTH (FW_CFG_ARCH_LOCAL + 0x00) 72 #define FW_CFG_SPARC64_HEIGHT (FW_CFG_ARCH_LOCAL + 0x01) 73 #define FW_CFG_SPARC64_DEPTH (FW_CFG_ARCH_LOCAL + 0x02) 74 75 #define IVEC_MAX 0x40 76 77 struct hwdef { 78 uint16_t machine_id; 79 uint64_t prom_addr; 80 uint64_t console_serial_base; 81 }; 82 83 struct EbusState { 84 /*< private >*/ 85 PCIDevice parent_obj; 86 87 ISABus *isa_bus; 88 qemu_irq *isa_irqs_in; 89 qemu_irq isa_irqs_out[ISA_NUM_IRQS]; 90 uint64_t console_serial_base; 91 MemoryRegion bar0; 92 MemoryRegion bar1; 93 }; 94 95 #define TYPE_EBUS "ebus" 96 OBJECT_DECLARE_SIMPLE_TYPE(EbusState, EBUS) 97 98 const char *fw_cfg_arch_key_name(uint16_t key) 99 { 100 static const struct { 101 uint16_t key; 102 const char *name; 103 } fw_cfg_arch_wellknown_keys[] = { 104 {FW_CFG_SPARC64_WIDTH, "width"}, 105 {FW_CFG_SPARC64_HEIGHT, "height"}, 106 {FW_CFG_SPARC64_DEPTH, "depth"}, 107 }; 108 109 for (size_t i = 0; i < ARRAY_SIZE(fw_cfg_arch_wellknown_keys); i++) { 110 if (fw_cfg_arch_wellknown_keys[i].key == key) { 111 return fw_cfg_arch_wellknown_keys[i].name; 112 } 113 } 114 return NULL; 115 } 116 117 static void fw_cfg_boot_set(void *opaque, const char *boot_device, 118 Error **errp) 119 { 120 fw_cfg_modify_i16(opaque, FW_CFG_BOOT_DEVICE, boot_device[0]); 121 } 122 123 static int sun4u_NVRAM_set_params(Nvram *nvram, uint16_t NVRAM_size, 124 const char *arch, ram_addr_t RAM_size, 125 const char *boot_devices, 126 uint32_t kernel_image, uint32_t kernel_size, 127 const char *cmdline, 128 uint32_t initrd_image, uint32_t initrd_size, 129 uint32_t NVRAM_image, 130 int width, int height, int depth, 131 const uint8_t *macaddr) 132 { 133 unsigned int i; 134 int sysp_end; 135 uint8_t image[0x1ff0]; 136 NvramClass *k = NVRAM_GET_CLASS(nvram); 137 138 memset(image, '\0', sizeof(image)); 139 140 /* OpenBIOS nvram variables partition */ 141 sysp_end = chrp_nvram_create_system_partition(image, 0, 0x1fd0); 142 143 /* Free space partition */ 144 chrp_nvram_create_free_partition(&image[sysp_end], 0x1fd0 - sysp_end); 145 146 Sun_init_header((struct Sun_nvram *)&image[0x1fd8], macaddr, 0x80); 147 148 for (i = 0; i < sizeof(image); i++) { 149 (k->write)(nvram, i, image[i]); 150 } 151 152 return 0; 153 } 154 155 static uint64_t sun4u_load_kernel(const char *kernel_filename, 156 const char *initrd_filename, 157 ram_addr_t RAM_size, uint64_t *initrd_size, 158 uint64_t *initrd_addr, uint64_t *kernel_addr, 159 uint64_t *kernel_entry) 160 { 161 int linux_boot; 162 unsigned int i; 163 long kernel_size; 164 uint8_t *ptr; 165 uint64_t kernel_top = 0; 166 167 linux_boot = (kernel_filename != NULL); 168 169 kernel_size = 0; 170 if (linux_boot) { 171 kernel_size = load_elf(kernel_filename, NULL, NULL, NULL, kernel_entry, 172 kernel_addr, &kernel_top, NULL, 173 ELFDATA2MSB, EM_SPARCV9, 0, 0); 174 if (kernel_size < 0) { 175 *kernel_addr = KERNEL_LOAD_ADDR; 176 *kernel_entry = KERNEL_LOAD_ADDR; 177 kernel_size = load_aout(kernel_filename, KERNEL_LOAD_ADDR, 178 RAM_size - KERNEL_LOAD_ADDR, true, 179 TARGET_PAGE_SIZE); 180 } 181 if (kernel_size < 0) { 182 kernel_size = load_image_targphys(kernel_filename, 183 KERNEL_LOAD_ADDR, 184 RAM_size - KERNEL_LOAD_ADDR); 185 } 186 if (kernel_size < 0) { 187 error_report("could not load kernel '%s'", kernel_filename); 188 exit(1); 189 } 190 /* load initrd above kernel */ 191 *initrd_size = 0; 192 if (initrd_filename && kernel_top) { 193 *initrd_addr = TARGET_PAGE_ALIGN(kernel_top); 194 195 *initrd_size = load_image_targphys(initrd_filename, 196 *initrd_addr, 197 RAM_size - *initrd_addr); 198 if ((int)*initrd_size < 0) { 199 error_report("could not load initial ram disk '%s'", 200 initrd_filename); 201 exit(1); 202 } 203 } 204 if (*initrd_size > 0) { 205 for (i = 0; i < 64 * TARGET_PAGE_SIZE; i += TARGET_PAGE_SIZE) { 206 ptr = rom_ptr(*kernel_addr + i, 32); 207 if (ptr && ldl_p(ptr + 8) == 0x48647253) { /* HdrS */ 208 stl_p(ptr + 24, *initrd_addr + *kernel_addr); 209 stl_p(ptr + 28, *initrd_size); 210 break; 211 } 212 } 213 } 214 } 215 return kernel_size; 216 } 217 218 typedef struct ResetData { 219 SPARCCPU *cpu; 220 uint64_t prom_addr; 221 } ResetData; 222 223 #define TYPE_SUN4U_POWER "power" 224 OBJECT_DECLARE_SIMPLE_TYPE(PowerDevice, SUN4U_POWER) 225 226 struct PowerDevice { 227 SysBusDevice parent_obj; 228 229 MemoryRegion power_mmio; 230 }; 231 232 /* Power */ 233 static uint64_t power_mem_read(void *opaque, hwaddr addr, unsigned size) 234 { 235 return 0; 236 } 237 238 static void power_mem_write(void *opaque, hwaddr addr, 239 uint64_t val, unsigned size) 240 { 241 /* According to a real Ultra 5, bit 24 controls the power */ 242 if (val & 0x1000000) { 243 qemu_system_shutdown_request(SHUTDOWN_CAUSE_GUEST_SHUTDOWN); 244 } 245 } 246 247 static const MemoryRegionOps power_mem_ops = { 248 .read = power_mem_read, 249 .write = power_mem_write, 250 .endianness = DEVICE_BIG_ENDIAN, 251 .valid = { 252 .min_access_size = 4, 253 .max_access_size = 4, 254 }, 255 }; 256 257 static void power_realize(DeviceState *dev, Error **errp) 258 { 259 PowerDevice *d = SUN4U_POWER(dev); 260 SysBusDevice *sbd = SYS_BUS_DEVICE(dev); 261 262 memory_region_init_io(&d->power_mmio, OBJECT(dev), &power_mem_ops, d, 263 "power", sizeof(uint32_t)); 264 265 sysbus_init_mmio(sbd, &d->power_mmio); 266 } 267 268 static void power_class_init(ObjectClass *klass, void *data) 269 { 270 DeviceClass *dc = DEVICE_CLASS(klass); 271 272 dc->realize = power_realize; 273 } 274 275 static const TypeInfo power_info = { 276 .name = TYPE_SUN4U_POWER, 277 .parent = TYPE_SYS_BUS_DEVICE, 278 .instance_size = sizeof(PowerDevice), 279 .class_init = power_class_init, 280 }; 281 282 static void ebus_isa_irq_handler(void *opaque, int n, int level) 283 { 284 EbusState *s = EBUS(opaque); 285 qemu_irq irq = s->isa_irqs_out[n]; 286 287 /* Pass ISA bus IRQs onto their gpio equivalent */ 288 trace_ebus_isa_irq_handler(n, level); 289 if (irq) { 290 qemu_set_irq(irq, level); 291 } 292 } 293 294 /* EBUS (Eight bit bus) bridge */ 295 static void ebus_realize(PCIDevice *pci_dev, Error **errp) 296 { 297 EbusState *s = EBUS(pci_dev); 298 ISADevice *isa_dev; 299 SysBusDevice *sbd; 300 DeviceState *dev; 301 DriveInfo *fd[MAX_FD]; 302 int i; 303 304 s->isa_bus = isa_bus_new(DEVICE(pci_dev), get_system_memory(), 305 pci_address_space_io(pci_dev), errp); 306 if (!s->isa_bus) { 307 error_setg(errp, "unable to instantiate EBUS ISA bus"); 308 return; 309 } 310 311 /* ISA bus */ 312 s->isa_irqs_in = qemu_allocate_irqs(ebus_isa_irq_handler, s, ISA_NUM_IRQS); 313 isa_bus_register_input_irqs(s->isa_bus, s->isa_irqs_in); 314 qdev_init_gpio_out_named(DEVICE(s), s->isa_irqs_out, "isa-irq", 315 ISA_NUM_IRQS); 316 317 /* Serial ports */ 318 i = 0; 319 if (s->console_serial_base) { 320 serial_mm_init(pci_address_space(pci_dev), s->console_serial_base, 321 0, NULL, 115200, serial_hd(i), DEVICE_BIG_ENDIAN); 322 i++; 323 } 324 serial_hds_isa_init(s->isa_bus, i, MAX_ISA_SERIAL_PORTS); 325 326 /* Parallel ports */ 327 parallel_hds_isa_init(s->isa_bus, MAX_PARALLEL_PORTS); 328 329 /* Keyboard */ 330 isa_create_simple(s->isa_bus, TYPE_I8042); 331 332 /* Floppy */ 333 for (i = 0; i < MAX_FD; i++) { 334 fd[i] = drive_get(IF_FLOPPY, 0, i); 335 } 336 isa_dev = isa_new(TYPE_ISA_FDC); 337 dev = DEVICE(isa_dev); 338 qdev_prop_set_uint32(dev, "dma", -1); 339 isa_realize_and_unref(isa_dev, s->isa_bus, &error_fatal); 340 isa_fdc_init_drives(isa_dev, fd); 341 342 /* Power */ 343 dev = qdev_new(TYPE_SUN4U_POWER); 344 sbd = SYS_BUS_DEVICE(dev); 345 sysbus_realize_and_unref(sbd, &error_fatal); 346 memory_region_add_subregion(pci_address_space_io(pci_dev), 0x7240, 347 sysbus_mmio_get_region(sbd, 0)); 348 349 /* PCI */ 350 pci_dev->config[0x04] = 0x06; // command = bus master, pci mem 351 pci_dev->config[0x05] = 0x00; 352 pci_dev->config[0x06] = 0xa0; // status = fast back-to-back, 66MHz, no error 353 pci_dev->config[0x07] = 0x03; // status = medium devsel 354 pci_dev->config[0x09] = 0x00; // programming i/f 355 pci_dev->config[0x0D] = 0x0a; // latency_timer 356 357 /* 358 * BAR0 is accessed by OpenBSD but not for ebus device access: allow any 359 * memory access to this region to succeed which allows the OpenBSD kernel 360 * to boot. 361 */ 362 memory_region_init_io(&s->bar0, OBJECT(s), &unassigned_io_ops, s, 363 "bar0", 0x1000000); 364 pci_register_bar(pci_dev, 0, PCI_BASE_ADDRESS_SPACE_MEMORY, &s->bar0); 365 memory_region_init_alias(&s->bar1, OBJECT(s), "bar1", 366 pci_address_space_io(pci_dev), 0, 0x8000); 367 pci_register_bar(pci_dev, 1, PCI_BASE_ADDRESS_SPACE_IO, &s->bar1); 368 } 369 370 static const Property ebus_properties[] = { 371 DEFINE_PROP_UINT64("console-serial-base", EbusState, 372 console_serial_base, 0), 373 }; 374 375 static void ebus_class_init(ObjectClass *klass, void *data) 376 { 377 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); 378 DeviceClass *dc = DEVICE_CLASS(klass); 379 380 k->realize = ebus_realize; 381 k->vendor_id = PCI_VENDOR_ID_SUN; 382 k->device_id = PCI_DEVICE_ID_SUN_EBUS; 383 k->revision = 0x01; 384 k->class_id = PCI_CLASS_BRIDGE_OTHER; 385 device_class_set_props(dc, ebus_properties); 386 } 387 388 static const TypeInfo ebus_info = { 389 .name = TYPE_EBUS, 390 .parent = TYPE_PCI_DEVICE, 391 .class_init = ebus_class_init, 392 .instance_size = sizeof(EbusState), 393 .interfaces = (InterfaceInfo[]) { 394 { INTERFACE_CONVENTIONAL_PCI_DEVICE }, 395 { }, 396 }, 397 }; 398 399 #define TYPE_OPENPROM "openprom" 400 typedef struct PROMState PROMState; 401 DECLARE_INSTANCE_CHECKER(PROMState, OPENPROM, 402 TYPE_OPENPROM) 403 404 struct PROMState { 405 SysBusDevice parent_obj; 406 407 MemoryRegion prom; 408 }; 409 410 static uint64_t translate_prom_address(void *opaque, uint64_t addr) 411 { 412 hwaddr *base_addr = (hwaddr *)opaque; 413 return addr + *base_addr - PROM_VADDR; 414 } 415 416 /* Boot PROM (OpenBIOS) */ 417 static void prom_init(hwaddr addr, const char *bios_name) 418 { 419 DeviceState *dev; 420 SysBusDevice *s; 421 char *filename; 422 int ret; 423 424 dev = qdev_new(TYPE_OPENPROM); 425 s = SYS_BUS_DEVICE(dev); 426 sysbus_realize_and_unref(s, &error_fatal); 427 428 sysbus_mmio_map(s, 0, addr); 429 430 /* load boot prom */ 431 if (bios_name == NULL) { 432 bios_name = PROM_FILENAME; 433 } 434 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name); 435 if (filename) { 436 ret = load_elf(filename, NULL, translate_prom_address, &addr, 437 NULL, NULL, NULL, NULL, ELFDATA2MSB, EM_SPARCV9, 0, 0); 438 if (ret < 0 || ret > PROM_SIZE_MAX) { 439 ret = load_image_targphys(filename, addr, PROM_SIZE_MAX); 440 } 441 g_free(filename); 442 } else { 443 ret = -1; 444 } 445 if (ret < 0 || ret > PROM_SIZE_MAX) { 446 error_report("could not load prom '%s'", bios_name); 447 exit(1); 448 } 449 } 450 451 static void prom_realize(DeviceState *ds, Error **errp) 452 { 453 PROMState *s = OPENPROM(ds); 454 SysBusDevice *dev = SYS_BUS_DEVICE(ds); 455 456 if (!memory_region_init_ram_nomigrate(&s->prom, OBJECT(ds), "sun4u.prom", 457 PROM_SIZE_MAX, errp)) { 458 return; 459 } 460 461 vmstate_register_ram_global(&s->prom); 462 memory_region_set_readonly(&s->prom, true); 463 sysbus_init_mmio(dev, &s->prom); 464 } 465 466 static void prom_class_init(ObjectClass *klass, void *data) 467 { 468 DeviceClass *dc = DEVICE_CLASS(klass); 469 470 dc->realize = prom_realize; 471 } 472 473 static const TypeInfo prom_info = { 474 .name = TYPE_OPENPROM, 475 .parent = TYPE_SYS_BUS_DEVICE, 476 .instance_size = sizeof(PROMState), 477 .class_init = prom_class_init, 478 }; 479 480 481 #define TYPE_SUN4U_MEMORY "memory" 482 typedef struct RamDevice RamDevice; 483 DECLARE_INSTANCE_CHECKER(RamDevice, SUN4U_RAM, 484 TYPE_SUN4U_MEMORY) 485 486 struct RamDevice { 487 SysBusDevice parent_obj; 488 489 MemoryRegion ram; 490 uint64_t size; 491 }; 492 493 /* System RAM */ 494 static void ram_realize(DeviceState *dev, Error **errp) 495 { 496 RamDevice *d = SUN4U_RAM(dev); 497 SysBusDevice *sbd = SYS_BUS_DEVICE(dev); 498 499 memory_region_init_ram_nomigrate(&d->ram, OBJECT(d), "sun4u.ram", d->size, 500 &error_fatal); 501 vmstate_register_ram_global(&d->ram); 502 sysbus_init_mmio(sbd, &d->ram); 503 } 504 505 static void ram_init(hwaddr addr, ram_addr_t RAM_size) 506 { 507 DeviceState *dev; 508 SysBusDevice *s; 509 RamDevice *d; 510 511 /* allocate RAM */ 512 dev = qdev_new(TYPE_SUN4U_MEMORY); 513 s = SYS_BUS_DEVICE(dev); 514 515 d = SUN4U_RAM(dev); 516 d->size = RAM_size; 517 sysbus_realize_and_unref(s, &error_fatal); 518 519 sysbus_mmio_map(s, 0, addr); 520 } 521 522 static const Property ram_properties[] = { 523 DEFINE_PROP_UINT64("size", RamDevice, size, 0), 524 }; 525 526 static void ram_class_init(ObjectClass *klass, void *data) 527 { 528 DeviceClass *dc = DEVICE_CLASS(klass); 529 530 dc->realize = ram_realize; 531 device_class_set_props(dc, ram_properties); 532 } 533 534 static const TypeInfo ram_info = { 535 .name = TYPE_SUN4U_MEMORY, 536 .parent = TYPE_SYS_BUS_DEVICE, 537 .instance_size = sizeof(RamDevice), 538 .class_init = ram_class_init, 539 }; 540 541 static void sun4uv_init(MemoryRegion *address_space_mem, 542 MachineState *machine, 543 const struct hwdef *hwdef) 544 { 545 MachineClass *mc = MACHINE_GET_CLASS(machine); 546 SPARCCPU *cpu; 547 Nvram *nvram; 548 unsigned int i; 549 uint64_t initrd_addr, initrd_size, kernel_addr, kernel_size, kernel_entry; 550 SabreState *sabre; 551 PCIBus *pci_bus, *pci_busA, *pci_busB; 552 PCIDevice *ebus, *pci_dev; 553 SysBusDevice *s; 554 DeviceState *iommu, *dev; 555 FWCfgState *fw_cfg; 556 NICInfo *nd; 557 MACAddr macaddr; 558 bool onboard_nic; 559 560 /* init CPUs */ 561 cpu = sparc64_cpu_devinit(machine->cpu_type, hwdef->prom_addr); 562 563 /* IOMMU */ 564 iommu = qdev_new(TYPE_SUN4U_IOMMU); 565 sysbus_realize_and_unref(SYS_BUS_DEVICE(iommu), &error_fatal); 566 567 /* set up devices */ 568 ram_init(0, machine->ram_size); 569 570 prom_init(hwdef->prom_addr, machine->firmware); 571 572 /* Init sabre (PCI host bridge) */ 573 sabre = SABRE(qdev_new(TYPE_SABRE)); 574 qdev_prop_set_uint64(DEVICE(sabre), "special-base", PBM_SPECIAL_BASE); 575 qdev_prop_set_uint64(DEVICE(sabre), "mem-base", PBM_MEM_BASE); 576 object_property_set_link(OBJECT(sabre), "iommu", OBJECT(iommu), 577 &error_abort); 578 sysbus_realize_and_unref(SYS_BUS_DEVICE(sabre), &error_fatal); 579 580 /* sabre_config */ 581 sysbus_mmio_map(SYS_BUS_DEVICE(sabre), 0, PBM_SPECIAL_BASE); 582 /* PCI configuration space */ 583 sysbus_mmio_map(SYS_BUS_DEVICE(sabre), 1, PBM_SPECIAL_BASE + 0x1000000ULL); 584 /* pci_ioport */ 585 sysbus_mmio_map(SYS_BUS_DEVICE(sabre), 2, PBM_SPECIAL_BASE + 0x2000000ULL); 586 587 /* Wire up PCI interrupts to CPU */ 588 for (i = 0; i < IVEC_MAX; i++) { 589 qdev_connect_gpio_out_named(DEVICE(sabre), "ivec-irq", i, 590 qdev_get_gpio_in_named(DEVICE(cpu), "ivec-irq", i)); 591 } 592 593 pci_bus = PCI_HOST_BRIDGE(sabre)->bus; 594 pci_busA = pci_bridge_get_sec_bus(sabre->bridgeA); 595 pci_busB = pci_bridge_get_sec_bus(sabre->bridgeB); 596 597 /* Only in-built Simba APBs can exist on the root bus, slot 0 on busA is 598 reserved (leaving no slots free after on-board devices) however slots 599 0-3 are free on busB */ 600 pci_bus_set_slot_reserved_mask(pci_bus, 0xfffffffc); 601 pci_bus_set_slot_reserved_mask(pci_busA, 0xfffffff1); 602 pci_bus_set_slot_reserved_mask(pci_busB, 0xfffffff0); 603 604 ebus = pci_new_multifunction(PCI_DEVFN(1, 0), TYPE_EBUS); 605 qdev_prop_set_uint64(DEVICE(ebus), "console-serial-base", 606 hwdef->console_serial_base); 607 pci_realize_and_unref(ebus, pci_busA, &error_fatal); 608 609 /* Wire up "well-known" ISA IRQs to PBM legacy obio IRQs */ 610 qdev_connect_gpio_out_named(DEVICE(ebus), "isa-irq", 7, 611 qdev_get_gpio_in_named(DEVICE(sabre), "pbm-irq", OBIO_LPT_IRQ)); 612 qdev_connect_gpio_out_named(DEVICE(ebus), "isa-irq", 6, 613 qdev_get_gpio_in_named(DEVICE(sabre), "pbm-irq", OBIO_FDD_IRQ)); 614 qdev_connect_gpio_out_named(DEVICE(ebus), "isa-irq", 1, 615 qdev_get_gpio_in_named(DEVICE(sabre), "pbm-irq", OBIO_KBD_IRQ)); 616 qdev_connect_gpio_out_named(DEVICE(ebus), "isa-irq", 12, 617 qdev_get_gpio_in_named(DEVICE(sabre), "pbm-irq", OBIO_MSE_IRQ)); 618 qdev_connect_gpio_out_named(DEVICE(ebus), "isa-irq", 4, 619 qdev_get_gpio_in_named(DEVICE(sabre), "pbm-irq", OBIO_SER_IRQ)); 620 621 switch (vga_interface_type) { 622 case VGA_STD: 623 pci_create_simple(pci_busA, PCI_DEVFN(2, 0), "VGA"); 624 vga_interface_created = true; 625 break; 626 case VGA_NONE: 627 break; 628 default: 629 abort(); /* Should not happen - types are checked in vl.c already */ 630 } 631 632 memset(&macaddr, 0, sizeof(MACAddr)); 633 onboard_nic = false; 634 635 nd = qemu_find_nic_info(mc->default_nic, true, NULL); 636 if (nd) { 637 pci_dev = pci_new_multifunction(PCI_DEVFN(1, 1), mc->default_nic); 638 dev = &pci_dev->qdev; 639 qdev_set_nic_properties(dev, nd); 640 pci_realize_and_unref(pci_dev, pci_busA, &error_fatal); 641 642 memcpy(&macaddr, &nd->macaddr.a, sizeof(MACAddr)); 643 onboard_nic = true; 644 } 645 pci_init_nic_devices(pci_busB, mc->default_nic); 646 647 /* If we don't have an onboard NIC, grab a default MAC address so that 648 * we have a valid machine id */ 649 if (!onboard_nic) { 650 qemu_macaddr_default_if_unset(&macaddr); 651 } 652 653 pci_dev = pci_new(PCI_DEVFN(3, 0), "cmd646-ide"); 654 qdev_prop_set_uint32(&pci_dev->qdev, "secondary", 1); 655 pci_realize_and_unref(pci_dev, pci_busA, &error_fatal); 656 pci_ide_create_devs(pci_dev); 657 658 /* Map NVRAM into I/O (ebus) space */ 659 dev = qdev_new("sysbus-m48t59"); 660 qdev_prop_set_int32(dev, "base-year", 1968); 661 s = SYS_BUS_DEVICE(dev); 662 sysbus_realize_and_unref(s, &error_fatal); 663 memory_region_add_subregion(pci_address_space_io(ebus), 0x2000, 664 sysbus_mmio_get_region(s, 0)); 665 nvram = NVRAM(dev); 666 667 initrd_size = 0; 668 initrd_addr = 0; 669 kernel_size = sun4u_load_kernel(machine->kernel_filename, 670 machine->initrd_filename, 671 machine->ram_size, &initrd_size, &initrd_addr, 672 &kernel_addr, &kernel_entry); 673 674 sun4u_NVRAM_set_params(nvram, NVRAM_SIZE, "Sun4u", machine->ram_size, 675 machine->boot_config.order, 676 kernel_addr, kernel_size, 677 machine->kernel_cmdline, 678 initrd_addr, initrd_size, 679 /* XXX: need an option to load a NVRAM image */ 680 0, 681 graphic_width, graphic_height, graphic_depth, 682 (uint8_t *)&macaddr); 683 684 dev = qdev_new(TYPE_FW_CFG_IO); 685 qdev_prop_set_bit(dev, "dma_enabled", false); 686 object_property_add_child(OBJECT(ebus), TYPE_FW_CFG, OBJECT(dev)); 687 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 688 memory_region_add_subregion(pci_address_space_io(ebus), BIOS_CFG_IOPORT, 689 &FW_CFG_IO(dev)->comb_iomem); 690 691 fw_cfg = FW_CFG(dev); 692 fw_cfg_add_i16(fw_cfg, FW_CFG_NB_CPUS, (uint16_t)machine->smp.cpus); 693 fw_cfg_add_i16(fw_cfg, FW_CFG_MAX_CPUS, (uint16_t)machine->smp.max_cpus); 694 fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, (uint64_t)machine->ram_size); 695 fw_cfg_add_i16(fw_cfg, FW_CFG_MACHINE_ID, hwdef->machine_id); 696 fw_cfg_add_i64(fw_cfg, FW_CFG_KERNEL_ADDR, kernel_entry); 697 fw_cfg_add_i64(fw_cfg, FW_CFG_KERNEL_SIZE, kernel_size); 698 if (machine->kernel_cmdline) { 699 fw_cfg_add_i32(fw_cfg, FW_CFG_CMDLINE_SIZE, 700 strlen(machine->kernel_cmdline) + 1); 701 fw_cfg_add_string(fw_cfg, FW_CFG_CMDLINE_DATA, machine->kernel_cmdline); 702 } else { 703 fw_cfg_add_i32(fw_cfg, FW_CFG_CMDLINE_SIZE, 0); 704 } 705 fw_cfg_add_i64(fw_cfg, FW_CFG_INITRD_ADDR, initrd_addr); 706 fw_cfg_add_i64(fw_cfg, FW_CFG_INITRD_SIZE, initrd_size); 707 fw_cfg_add_i16(fw_cfg, FW_CFG_BOOT_DEVICE, machine->boot_config.order[0]); 708 709 fw_cfg_add_i16(fw_cfg, FW_CFG_SPARC64_WIDTH, graphic_width); 710 fw_cfg_add_i16(fw_cfg, FW_CFG_SPARC64_HEIGHT, graphic_height); 711 fw_cfg_add_i16(fw_cfg, FW_CFG_SPARC64_DEPTH, graphic_depth); 712 713 qemu_register_boot_set(fw_cfg_boot_set, fw_cfg); 714 } 715 716 enum { 717 sun4u_id = 0, 718 sun4v_id = 64, 719 }; 720 721 /* 722 * Implementation of an interface to adjust firmware path 723 * for the bootindex property handling. 724 */ 725 static char *sun4u_fw_dev_path(FWPathProvider *p, BusState *bus, 726 DeviceState *dev) 727 { 728 PCIDevice *pci; 729 730 if (!strcmp(object_get_typename(OBJECT(dev)), "pbm-bridge")) { 731 pci = PCI_DEVICE(dev); 732 733 if (PCI_FUNC(pci->devfn)) { 734 return g_strdup_printf("pci@%x,%x", PCI_SLOT(pci->devfn), 735 PCI_FUNC(pci->devfn)); 736 } else { 737 return g_strdup_printf("pci@%x", PCI_SLOT(pci->devfn)); 738 } 739 } 740 741 if (!strcmp(object_get_typename(OBJECT(dev)), "ide-hd")) { 742 return g_strdup("disk"); 743 } 744 745 if (!strcmp(object_get_typename(OBJECT(dev)), "ide-cd")) { 746 return g_strdup("cdrom"); 747 } 748 749 if (!strcmp(object_get_typename(OBJECT(dev)), "virtio-blk-device")) { 750 return g_strdup("disk"); 751 } 752 753 return NULL; 754 } 755 756 static const struct hwdef hwdefs[] = { 757 /* Sun4u generic PC-like machine */ 758 { 759 .machine_id = sun4u_id, 760 .prom_addr = 0x1fff0000000ULL, 761 .console_serial_base = 0, 762 }, 763 /* Sun4v generic PC-like machine */ 764 { 765 .machine_id = sun4v_id, 766 .prom_addr = 0x1fff0000000ULL, 767 .console_serial_base = 0, 768 }, 769 }; 770 771 /* Sun4u hardware initialisation */ 772 static void sun4u_init(MachineState *machine) 773 { 774 sun4uv_init(get_system_memory(), machine, &hwdefs[0]); 775 } 776 777 /* Sun4v hardware initialisation */ 778 static void sun4v_init(MachineState *machine) 779 { 780 sun4uv_init(get_system_memory(), machine, &hwdefs[1]); 781 } 782 783 static GlobalProperty hw_compat_sparc64[] = { 784 { "virtio-pci", "disable-legacy", "on", .optional = true }, 785 { "virtio-device", "iommu_platform", "on" }, 786 }; 787 static const size_t hw_compat_sparc64_len = G_N_ELEMENTS(hw_compat_sparc64); 788 789 static void sun4u_class_init(ObjectClass *oc, void *data) 790 { 791 MachineClass *mc = MACHINE_CLASS(oc); 792 FWPathProviderClass *fwc = FW_PATH_PROVIDER_CLASS(oc); 793 794 mc->desc = "Sun4u platform"; 795 mc->init = sun4u_init; 796 mc->block_default_type = IF_IDE; 797 mc->max_cpus = 1; /* XXX for now */ 798 mc->is_default = true; 799 mc->default_boot_order = "c"; 800 mc->default_cpu_type = SPARC_CPU_TYPE_NAME("TI-UltraSparc-IIi"); 801 mc->ignore_boot_device_suffixes = true; 802 mc->default_display = "std"; 803 mc->default_nic = "sunhme"; 804 mc->no_parallel = !module_object_class_by_name(TYPE_ISA_PARALLEL); 805 fwc->get_dev_path = sun4u_fw_dev_path; 806 compat_props_add(mc->compat_props, hw_compat_sparc64, hw_compat_sparc64_len); 807 } 808 809 static const TypeInfo sun4u_type = { 810 .name = MACHINE_TYPE_NAME("sun4u"), 811 .parent = TYPE_MACHINE, 812 .class_init = sun4u_class_init, 813 .interfaces = (InterfaceInfo[]) { 814 { TYPE_FW_PATH_PROVIDER }, 815 { } 816 }, 817 }; 818 819 static void sun4v_class_init(ObjectClass *oc, void *data) 820 { 821 MachineClass *mc = MACHINE_CLASS(oc); 822 823 mc->desc = "Sun4v platform"; 824 mc->init = sun4v_init; 825 mc->block_default_type = IF_IDE; 826 mc->max_cpus = 1; /* XXX for now */ 827 mc->default_boot_order = "c"; 828 mc->default_cpu_type = SPARC_CPU_TYPE_NAME("Sun-UltraSparc-T1"); 829 mc->default_display = "std"; 830 mc->default_nic = "sunhme"; 831 mc->no_parallel = !module_object_class_by_name(TYPE_ISA_PARALLEL); 832 } 833 834 static const TypeInfo sun4v_type = { 835 .name = MACHINE_TYPE_NAME("sun4v"), 836 .parent = TYPE_MACHINE, 837 .class_init = sun4v_class_init, 838 }; 839 840 static void sun4u_register_types(void) 841 { 842 type_register_static(&power_info); 843 type_register_static(&ebus_info); 844 type_register_static(&prom_info); 845 type_register_static(&ram_info); 846 847 type_register_static(&sun4u_type); 848 type_register_static(&sun4v_type); 849 } 850 851 type_init(sun4u_register_types) 852