1 /* 2 * QEMU Sun4m & Sun4d & Sun4c System Emulator 3 * 4 * Copyright (c) 2003-2005 Fabrice Bellard 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a copy 7 * of this software and associated documentation files (the "Software"), to deal 8 * in the Software without restriction, including without limitation the rights 9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 10 * copies of the Software, and to permit persons to whom the Software is 11 * furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 22 * THE SOFTWARE. 23 */ 24 25 #include "qemu/osdep.h" 26 #include "qemu/units.h" 27 #include "qapi/error.h" 28 #include "qemu/datadir.h" 29 #include "cpu.h" 30 #include "hw/sysbus.h" 31 #include "qemu/error-report.h" 32 #include "qemu/timer.h" 33 #include "hw/sparc/sun4m_iommu.h" 34 #include "hw/rtc/m48t59.h" 35 #include "migration/vmstate.h" 36 #include "hw/sparc/sparc32_dma.h" 37 #include "hw/block/fdc.h" 38 #include "system/reset.h" 39 #include "system/runstate.h" 40 #include "system/system.h" 41 #include "net/net.h" 42 #include "hw/boards.h" 43 #include "hw/scsi/esp.h" 44 #include "hw/nvram/sun_nvram.h" 45 #include "hw/qdev-properties.h" 46 #include "hw/nvram/chrp_nvram.h" 47 #include "hw/nvram/fw_cfg.h" 48 #include "hw/char/escc.h" 49 #include "hw/misc/empty_slot.h" 50 #include "hw/misc/unimp.h" 51 #include "hw/irq.h" 52 #include "hw/or-irq.h" 53 #include "hw/loader.h" 54 #include "elf.h" 55 #include "trace.h" 56 #include "qom/object.h" 57 58 /* 59 * Sun4m architecture was used in the following machines: 60 * 61 * SPARCserver 6xxMP/xx 62 * SPARCclassic (SPARCclassic Server)(SPARCstation LC) (4/15), 63 * SPARCclassic X (4/10) 64 * SPARCstation LX/ZX (4/30) 65 * SPARCstation Voyager 66 * SPARCstation 10/xx, SPARCserver 10/xx 67 * SPARCstation 5, SPARCserver 5 68 * SPARCstation 20/xx, SPARCserver 20 69 * SPARCstation 4 70 * 71 * See for example: http://www.sunhelp.org/faq/sunref1.html 72 */ 73 74 #define KERNEL_LOAD_ADDR 0x00004000 75 #define CMDLINE_ADDR 0x007ff000 76 #define INITRD_LOAD_ADDR 0x00800000 77 #define PROM_SIZE_MAX (1 * MiB) 78 #define PROM_VADDR 0xffd00000 79 #define PROM_FILENAME "openbios-sparc32" 80 #define CFG_ADDR 0xd00000510ULL 81 #define FW_CFG_SUN4M_DEPTH (FW_CFG_ARCH_LOCAL + 0x00) 82 #define FW_CFG_SUN4M_WIDTH (FW_CFG_ARCH_LOCAL + 0x01) 83 #define FW_CFG_SUN4M_HEIGHT (FW_CFG_ARCH_LOCAL + 0x02) 84 85 #define MAX_CPUS 16 86 #define MAX_PILS 16 87 #define MAX_VSIMMS 4 88 89 #define ESCC_CLOCK 4915200 90 91 struct sun4m_hwdef { 92 hwaddr iommu_base, iommu_pad_base, iommu_pad_len, slavio_base; 93 hwaddr intctl_base, counter_base, nvram_base, ms_kb_base; 94 hwaddr serial_base, fd_base; 95 hwaddr afx_base, idreg_base, dma_base, esp_base, le_base; 96 hwaddr tcx_base, cs_base, apc_base, aux1_base, aux2_base; 97 hwaddr bpp_base, dbri_base, sx_base; 98 struct { 99 hwaddr reg_base, vram_base; 100 } vsimm[MAX_VSIMMS]; 101 hwaddr ecc_base; 102 uint64_t max_mem; 103 uint32_t ecc_version; 104 uint32_t iommu_version; 105 uint16_t machine_id; 106 uint8_t nvram_machine_id; 107 }; 108 109 struct Sun4mMachineClass { 110 /*< private >*/ 111 MachineClass parent_obj; 112 /*< public >*/ 113 const struct sun4m_hwdef *hwdef; 114 }; 115 typedef struct Sun4mMachineClass Sun4mMachineClass; 116 117 #define TYPE_SUN4M_MACHINE MACHINE_TYPE_NAME("sun4m-common") 118 DECLARE_CLASS_CHECKERS(Sun4mMachineClass, SUN4M_MACHINE, TYPE_SUN4M_MACHINE) 119 120 const char *fw_cfg_arch_key_name(uint16_t key) 121 { 122 static const struct { 123 uint16_t key; 124 const char *name; 125 } fw_cfg_arch_wellknown_keys[] = { 126 {FW_CFG_SUN4M_DEPTH, "depth"}, 127 {FW_CFG_SUN4M_WIDTH, "width"}, 128 {FW_CFG_SUN4M_HEIGHT, "height"}, 129 }; 130 131 for (size_t i = 0; i < ARRAY_SIZE(fw_cfg_arch_wellknown_keys); i++) { 132 if (fw_cfg_arch_wellknown_keys[i].key == key) { 133 return fw_cfg_arch_wellknown_keys[i].name; 134 } 135 } 136 return NULL; 137 } 138 139 static void fw_cfg_boot_set(void *opaque, const char *boot_device, 140 Error **errp) 141 { 142 fw_cfg_modify_i16(opaque, FW_CFG_BOOT_DEVICE, boot_device[0]); 143 } 144 145 static void nvram_init(Nvram *nvram, uint8_t *macaddr, 146 const char *cmdline, const char *boot_devices, 147 ram_addr_t RAM_size, uint32_t kernel_size, 148 int width, int height, int depth, 149 int nvram_machine_id, const char *arch) 150 { 151 unsigned int i; 152 int sysp_end; 153 uint8_t image[0x1ff0]; 154 NvramClass *k = NVRAM_GET_CLASS(nvram); 155 156 memset(image, '\0', sizeof(image)); 157 158 /* OpenBIOS nvram variables partition */ 159 sysp_end = chrp_nvram_create_system_partition(image, 0, 0x1fd0); 160 161 /* Free space partition */ 162 chrp_nvram_create_free_partition(&image[sysp_end], 0x1fd0 - sysp_end); 163 164 Sun_init_header((struct Sun_nvram *)&image[0x1fd8], macaddr, 165 nvram_machine_id); 166 167 for (i = 0; i < sizeof(image); i++) { 168 (k->write)(nvram, i, image[i]); 169 } 170 } 171 172 static void cpu_kick_irq(SPARCCPU *cpu) 173 { 174 CPUSPARCState *env = &cpu->env; 175 CPUState *cs = CPU(cpu); 176 177 cs->halted = 0; 178 cpu_check_irqs(env); 179 qemu_cpu_kick(cs); 180 } 181 182 static void cpu_set_irq(void *opaque, int irq, int level) 183 { 184 SPARCCPU *cpu = opaque; 185 CPUSPARCState *env = &cpu->env; 186 187 if (level) { 188 trace_sun4m_cpu_set_irq_raise(irq); 189 env->pil_in |= 1 << irq; 190 cpu_kick_irq(cpu); 191 } else { 192 trace_sun4m_cpu_set_irq_lower(irq); 193 env->pil_in &= ~(1 << irq); 194 cpu_check_irqs(env); 195 } 196 } 197 198 static void dummy_cpu_set_irq(void *opaque, int irq, int level) 199 { 200 } 201 202 static void sun4m_cpu_reset(void *opaque) 203 { 204 SPARCCPU *cpu = opaque; 205 CPUState *cs = CPU(cpu); 206 207 cpu_reset(cs); 208 } 209 210 static void cpu_halt_signal(void *opaque, int irq, int level) 211 { 212 if (level && current_cpu) { 213 cpu_interrupt(current_cpu, CPU_INTERRUPT_HALT); 214 } 215 } 216 217 static uint64_t translate_kernel_address(void *opaque, uint64_t addr) 218 { 219 return addr - 0xf0000000ULL; 220 } 221 222 static unsigned long sun4m_load_kernel(const char *kernel_filename, 223 const char *initrd_filename, 224 ram_addr_t RAM_size, 225 uint32_t *initrd_size) 226 { 227 int linux_boot; 228 unsigned int i; 229 long kernel_size; 230 uint8_t *ptr; 231 232 linux_boot = (kernel_filename != NULL); 233 234 kernel_size = 0; 235 if (linux_boot) { 236 int bswap_needed; 237 238 #ifdef BSWAP_NEEDED 239 bswap_needed = 1; 240 #else 241 bswap_needed = 0; 242 #endif 243 kernel_size = load_elf(kernel_filename, NULL, 244 translate_kernel_address, NULL, 245 NULL, NULL, NULL, NULL, 246 ELFDATA2MSB, EM_SPARC, 0, 0); 247 if (kernel_size < 0) 248 kernel_size = load_aout(kernel_filename, KERNEL_LOAD_ADDR, 249 RAM_size - KERNEL_LOAD_ADDR, bswap_needed, 250 TARGET_PAGE_SIZE); 251 if (kernel_size < 0) 252 kernel_size = load_image_targphys(kernel_filename, 253 KERNEL_LOAD_ADDR, 254 RAM_size - KERNEL_LOAD_ADDR); 255 if (kernel_size < 0) { 256 error_report("could not load kernel '%s'", kernel_filename); 257 exit(1); 258 } 259 260 /* load initrd */ 261 *initrd_size = 0; 262 if (initrd_filename) { 263 *initrd_size = load_image_targphys(initrd_filename, 264 INITRD_LOAD_ADDR, 265 RAM_size - INITRD_LOAD_ADDR); 266 if ((int)*initrd_size < 0) { 267 error_report("could not load initial ram disk '%s'", 268 initrd_filename); 269 exit(1); 270 } 271 } 272 if (*initrd_size > 0) { 273 for (i = 0; i < 64 * TARGET_PAGE_SIZE; i += TARGET_PAGE_SIZE) { 274 ptr = rom_ptr(KERNEL_LOAD_ADDR + i, 24); 275 if (ptr && ldl_p(ptr) == 0x48647253) { /* HdrS */ 276 stl_p(ptr + 16, INITRD_LOAD_ADDR); 277 stl_p(ptr + 20, *initrd_size); 278 break; 279 } 280 } 281 } 282 } 283 return kernel_size; 284 } 285 286 static void *iommu_init(hwaddr addr, uint32_t version, qemu_irq irq) 287 { 288 DeviceState *dev; 289 SysBusDevice *s; 290 291 dev = qdev_new(TYPE_SUN4M_IOMMU); 292 qdev_prop_set_uint32(dev, "version", version); 293 s = SYS_BUS_DEVICE(dev); 294 sysbus_realize_and_unref(s, &error_fatal); 295 sysbus_connect_irq(s, 0, irq); 296 sysbus_mmio_map(s, 0, addr); 297 298 return s; 299 } 300 301 static void *sparc32_dma_init(hwaddr dma_base, 302 hwaddr esp_base, qemu_irq espdma_irq, 303 hwaddr le_base, qemu_irq ledma_irq, 304 MACAddr *mac) 305 { 306 DeviceState *dma; 307 ESPDMADeviceState *espdma; 308 LEDMADeviceState *ledma; 309 SysBusESPState *esp; 310 SysBusPCNetState *lance; 311 NICInfo *nd = qemu_find_nic_info("lance", true, NULL); 312 313 dma = qdev_new(TYPE_SPARC32_DMA); 314 espdma = SPARC32_ESPDMA_DEVICE(object_resolve_path_component( 315 OBJECT(dma), "espdma")); 316 317 esp = SYSBUS_ESP(object_resolve_path_component(OBJECT(espdma), "esp")); 318 319 ledma = SPARC32_LEDMA_DEVICE(object_resolve_path_component( 320 OBJECT(dma), "ledma")); 321 322 lance = SYSBUS_PCNET(object_resolve_path_component( 323 OBJECT(ledma), "lance")); 324 325 if (nd) { 326 qdev_set_nic_properties(DEVICE(lance), nd); 327 memcpy(mac->a, nd->macaddr.a, sizeof(mac->a)); 328 } else { 329 qemu_macaddr_default_if_unset(mac); 330 qdev_prop_set_macaddr(DEVICE(lance), "mac", mac->a); 331 } 332 333 sysbus_realize_and_unref(SYS_BUS_DEVICE(dma), &error_fatal); 334 335 sysbus_connect_irq(SYS_BUS_DEVICE(espdma), 0, espdma_irq); 336 337 sysbus_connect_irq(SYS_BUS_DEVICE(ledma), 0, ledma_irq); 338 339 sysbus_mmio_map(SYS_BUS_DEVICE(dma), 0, dma_base); 340 341 sysbus_mmio_map(SYS_BUS_DEVICE(esp), 0, esp_base); 342 scsi_bus_legacy_handle_cmdline(&esp->esp.bus); 343 344 sysbus_mmio_map(SYS_BUS_DEVICE(lance), 0, le_base); 345 346 return dma; 347 } 348 349 static DeviceState *slavio_intctl_init(hwaddr addr, 350 hwaddr addrg, 351 qemu_irq **parent_irq) 352 { 353 DeviceState *dev; 354 SysBusDevice *s; 355 unsigned int i, j; 356 357 dev = qdev_new("slavio_intctl"); 358 359 s = SYS_BUS_DEVICE(dev); 360 sysbus_realize_and_unref(s, &error_fatal); 361 362 for (i = 0; i < MAX_CPUS; i++) { 363 for (j = 0; j < MAX_PILS; j++) { 364 sysbus_connect_irq(s, i * MAX_PILS + j, parent_irq[i][j]); 365 } 366 } 367 sysbus_mmio_map(s, 0, addrg); 368 for (i = 0; i < MAX_CPUS; i++) { 369 sysbus_mmio_map(s, i + 1, addr + i * TARGET_PAGE_SIZE); 370 } 371 372 return dev; 373 } 374 375 #define SYS_TIMER_OFFSET 0x10000ULL 376 #define CPU_TIMER_OFFSET(cpu) (0x1000ULL * cpu) 377 378 static void slavio_timer_init_all(hwaddr addr, qemu_irq master_irq, 379 qemu_irq *cpu_irqs, unsigned int num_cpus) 380 { 381 DeviceState *dev; 382 SysBusDevice *s; 383 unsigned int i; 384 385 dev = qdev_new("slavio_timer"); 386 qdev_prop_set_uint32(dev, "num_cpus", num_cpus); 387 s = SYS_BUS_DEVICE(dev); 388 sysbus_realize_and_unref(s, &error_fatal); 389 sysbus_connect_irq(s, 0, master_irq); 390 sysbus_mmio_map(s, 0, addr + SYS_TIMER_OFFSET); 391 392 for (i = 0; i < MAX_CPUS; i++) { 393 sysbus_mmio_map(s, i + 1, addr + (hwaddr)CPU_TIMER_OFFSET(i)); 394 sysbus_connect_irq(s, i + 1, cpu_irqs[i]); 395 } 396 } 397 398 static qemu_irq slavio_system_powerdown; 399 400 static void slavio_powerdown_req(Notifier *n, void *opaque) 401 { 402 qemu_irq_raise(slavio_system_powerdown); 403 } 404 405 static Notifier slavio_system_powerdown_notifier = { 406 .notify = slavio_powerdown_req 407 }; 408 409 #define MISC_LEDS 0x01600000 410 #define MISC_CFG 0x01800000 411 #define MISC_DIAG 0x01a00000 412 #define MISC_MDM 0x01b00000 413 #define MISC_SYS 0x01f00000 414 415 static void slavio_misc_init(hwaddr base, 416 hwaddr aux1_base, 417 hwaddr aux2_base, qemu_irq irq, 418 qemu_irq fdc_tc) 419 { 420 DeviceState *dev; 421 SysBusDevice *s; 422 423 dev = qdev_new("slavio_misc"); 424 s = SYS_BUS_DEVICE(dev); 425 sysbus_realize_and_unref(s, &error_fatal); 426 if (base) { 427 /* 8 bit registers */ 428 /* Slavio control */ 429 sysbus_mmio_map(s, 0, base + MISC_CFG); 430 /* Diagnostics */ 431 sysbus_mmio_map(s, 1, base + MISC_DIAG); 432 /* Modem control */ 433 sysbus_mmio_map(s, 2, base + MISC_MDM); 434 /* 16 bit registers */ 435 /* ss600mp diag LEDs */ 436 sysbus_mmio_map(s, 3, base + MISC_LEDS); 437 /* 32 bit registers */ 438 /* System control */ 439 sysbus_mmio_map(s, 4, base + MISC_SYS); 440 } 441 if (aux1_base) { 442 /* AUX 1 (Misc System Functions) */ 443 sysbus_mmio_map(s, 5, aux1_base); 444 } 445 if (aux2_base) { 446 /* AUX 2 (Software Powerdown Control) */ 447 sysbus_mmio_map(s, 6, aux2_base); 448 } 449 sysbus_connect_irq(s, 0, irq); 450 sysbus_connect_irq(s, 1, fdc_tc); 451 slavio_system_powerdown = qdev_get_gpio_in(dev, 0); 452 qemu_register_powerdown_notifier(&slavio_system_powerdown_notifier); 453 } 454 455 static void ecc_init(hwaddr base, qemu_irq irq, uint32_t version) 456 { 457 DeviceState *dev; 458 SysBusDevice *s; 459 460 dev = qdev_new("eccmemctl"); 461 qdev_prop_set_uint32(dev, "version", version); 462 s = SYS_BUS_DEVICE(dev); 463 sysbus_realize_and_unref(s, &error_fatal); 464 sysbus_connect_irq(s, 0, irq); 465 sysbus_mmio_map(s, 0, base); 466 if (version == 0) { // SS-600MP only 467 sysbus_mmio_map(s, 1, base + 0x1000); 468 } 469 } 470 471 static void apc_init(hwaddr power_base, qemu_irq cpu_halt) 472 { 473 DeviceState *dev; 474 SysBusDevice *s; 475 476 dev = qdev_new("apc"); 477 s = SYS_BUS_DEVICE(dev); 478 sysbus_realize_and_unref(s, &error_fatal); 479 /* Power management (APC) XXX: not a Slavio device */ 480 sysbus_mmio_map(s, 0, power_base); 481 sysbus_connect_irq(s, 0, cpu_halt); 482 } 483 484 static void tcx_init(hwaddr addr, qemu_irq irq, int vram_size, int width, 485 int height, int depth) 486 { 487 DeviceState *dev; 488 SysBusDevice *s; 489 490 dev = qdev_new("sun-tcx"); 491 qdev_prop_set_uint32(dev, "vram_size", vram_size); 492 qdev_prop_set_uint16(dev, "width", width); 493 qdev_prop_set_uint16(dev, "height", height); 494 qdev_prop_set_uint16(dev, "depth", depth); 495 s = SYS_BUS_DEVICE(dev); 496 sysbus_realize_and_unref(s, &error_fatal); 497 498 /* 10/ROM : FCode ROM */ 499 sysbus_mmio_map(s, 0, addr); 500 /* 2/STIP : Stipple */ 501 sysbus_mmio_map(s, 1, addr + 0x04000000ULL); 502 /* 3/BLIT : Blitter */ 503 sysbus_mmio_map(s, 2, addr + 0x06000000ULL); 504 /* 5/RSTIP : Raw Stipple */ 505 sysbus_mmio_map(s, 3, addr + 0x0c000000ULL); 506 /* 6/RBLIT : Raw Blitter */ 507 sysbus_mmio_map(s, 4, addr + 0x0e000000ULL); 508 /* 7/TEC : Transform Engine */ 509 sysbus_mmio_map(s, 5, addr + 0x00700000ULL); 510 /* 8/CMAP : DAC */ 511 sysbus_mmio_map(s, 6, addr + 0x00200000ULL); 512 /* 9/THC : */ 513 if (depth == 8) { 514 sysbus_mmio_map(s, 7, addr + 0x00300000ULL); 515 } else { 516 sysbus_mmio_map(s, 7, addr + 0x00301000ULL); 517 } 518 /* 11/DHC : */ 519 sysbus_mmio_map(s, 8, addr + 0x00240000ULL); 520 /* 12/ALT : */ 521 sysbus_mmio_map(s, 9, addr + 0x00280000ULL); 522 /* 0/DFB8 : 8-bit plane */ 523 sysbus_mmio_map(s, 10, addr + 0x00800000ULL); 524 /* 1/DFB24 : 24bit plane */ 525 sysbus_mmio_map(s, 11, addr + 0x02000000ULL); 526 /* 4/RDFB32: Raw framebuffer. Control plane */ 527 sysbus_mmio_map(s, 12, addr + 0x0a000000ULL); 528 /* 9/THC24bits : NetBSD writes here even with 8-bit display: dummy */ 529 if (depth == 8) { 530 sysbus_mmio_map(s, 13, addr + 0x00301000ULL); 531 } 532 533 sysbus_connect_irq(s, 0, irq); 534 } 535 536 static void cg3_init(hwaddr addr, qemu_irq irq, int vram_size, int width, 537 int height, int depth) 538 { 539 DeviceState *dev; 540 SysBusDevice *s; 541 542 dev = qdev_new("cgthree"); 543 qdev_prop_set_uint32(dev, "vram-size", vram_size); 544 qdev_prop_set_uint16(dev, "width", width); 545 qdev_prop_set_uint16(dev, "height", height); 546 qdev_prop_set_uint16(dev, "depth", depth); 547 s = SYS_BUS_DEVICE(dev); 548 sysbus_realize_and_unref(s, &error_fatal); 549 550 /* FCode ROM */ 551 sysbus_mmio_map(s, 0, addr); 552 /* DAC */ 553 sysbus_mmio_map(s, 1, addr + 0x400000ULL); 554 /* 8-bit plane */ 555 sysbus_mmio_map(s, 2, addr + 0x800000ULL); 556 557 sysbus_connect_irq(s, 0, irq); 558 } 559 560 /* NCR89C100/MACIO Internal ID register */ 561 562 #define TYPE_MACIO_ID_REGISTER "macio_idreg" 563 564 static const uint8_t idreg_data[] = { 0xfe, 0x81, 0x01, 0x03 }; 565 566 static void idreg_init(hwaddr addr) 567 { 568 DeviceState *dev; 569 SysBusDevice *s; 570 571 dev = qdev_new(TYPE_MACIO_ID_REGISTER); 572 s = SYS_BUS_DEVICE(dev); 573 sysbus_realize_and_unref(s, &error_fatal); 574 575 sysbus_mmio_map(s, 0, addr); 576 address_space_write_rom(&address_space_memory, addr, 577 MEMTXATTRS_UNSPECIFIED, 578 idreg_data, sizeof(idreg_data)); 579 } 580 581 OBJECT_DECLARE_SIMPLE_TYPE(IDRegState, MACIO_ID_REGISTER) 582 583 struct IDRegState { 584 SysBusDevice parent_obj; 585 586 MemoryRegion mem; 587 }; 588 589 static void idreg_realize(DeviceState *ds, Error **errp) 590 { 591 IDRegState *s = MACIO_ID_REGISTER(ds); 592 SysBusDevice *dev = SYS_BUS_DEVICE(ds); 593 594 if (!memory_region_init_ram_nomigrate(&s->mem, OBJECT(ds), "sun4m.idreg", 595 sizeof(idreg_data), errp)) { 596 return; 597 } 598 599 vmstate_register_ram_global(&s->mem); 600 memory_region_set_readonly(&s->mem, true); 601 sysbus_init_mmio(dev, &s->mem); 602 } 603 604 static void idreg_class_init(ObjectClass *oc, void *data) 605 { 606 DeviceClass *dc = DEVICE_CLASS(oc); 607 608 dc->realize = idreg_realize; 609 } 610 611 static const TypeInfo idreg_info = { 612 .name = TYPE_MACIO_ID_REGISTER, 613 .parent = TYPE_SYS_BUS_DEVICE, 614 .instance_size = sizeof(IDRegState), 615 .class_init = idreg_class_init, 616 }; 617 618 #define TYPE_TCX_AFX "tcx_afx" 619 OBJECT_DECLARE_SIMPLE_TYPE(AFXState, TCX_AFX) 620 621 struct AFXState { 622 SysBusDevice parent_obj; 623 624 MemoryRegion mem; 625 }; 626 627 /* SS-5 TCX AFX register */ 628 static void afx_init(hwaddr addr) 629 { 630 DeviceState *dev; 631 SysBusDevice *s; 632 633 dev = qdev_new(TYPE_TCX_AFX); 634 s = SYS_BUS_DEVICE(dev); 635 sysbus_realize_and_unref(s, &error_fatal); 636 637 sysbus_mmio_map(s, 0, addr); 638 } 639 640 static void afx_realize(DeviceState *ds, Error **errp) 641 { 642 AFXState *s = TCX_AFX(ds); 643 SysBusDevice *dev = SYS_BUS_DEVICE(ds); 644 645 if (!memory_region_init_ram_nomigrate(&s->mem, OBJECT(ds), "sun4m.afx", 646 4, errp)) { 647 return; 648 } 649 650 vmstate_register_ram_global(&s->mem); 651 sysbus_init_mmio(dev, &s->mem); 652 } 653 654 static void afx_class_init(ObjectClass *oc, void *data) 655 { 656 DeviceClass *dc = DEVICE_CLASS(oc); 657 658 dc->realize = afx_realize; 659 } 660 661 static const TypeInfo afx_info = { 662 .name = TYPE_TCX_AFX, 663 .parent = TYPE_SYS_BUS_DEVICE, 664 .instance_size = sizeof(AFXState), 665 .class_init = afx_class_init, 666 }; 667 668 #define TYPE_OPENPROM "openprom" 669 typedef struct PROMState PROMState; 670 DECLARE_INSTANCE_CHECKER(PROMState, OPENPROM, 671 TYPE_OPENPROM) 672 673 struct PROMState { 674 SysBusDevice parent_obj; 675 676 MemoryRegion prom; 677 }; 678 679 /* Boot PROM (OpenBIOS) */ 680 static uint64_t translate_prom_address(void *opaque, uint64_t addr) 681 { 682 hwaddr *base_addr = (hwaddr *)opaque; 683 return addr + *base_addr - PROM_VADDR; 684 } 685 686 static void prom_init(hwaddr addr, const char *bios_name) 687 { 688 DeviceState *dev; 689 SysBusDevice *s; 690 char *filename; 691 int ret; 692 693 dev = qdev_new(TYPE_OPENPROM); 694 s = SYS_BUS_DEVICE(dev); 695 sysbus_realize_and_unref(s, &error_fatal); 696 697 sysbus_mmio_map(s, 0, addr); 698 699 /* load boot prom */ 700 if (bios_name == NULL) { 701 bios_name = PROM_FILENAME; 702 } 703 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name); 704 if (filename) { 705 ret = load_elf(filename, NULL, 706 translate_prom_address, &addr, NULL, 707 NULL, NULL, NULL, ELFDATA2MSB, EM_SPARC, 0, 0); 708 if (ret < 0 || ret > PROM_SIZE_MAX) { 709 ret = load_image_targphys(filename, addr, PROM_SIZE_MAX); 710 } 711 g_free(filename); 712 } else { 713 ret = -1; 714 } 715 if (ret < 0 || ret > PROM_SIZE_MAX) { 716 error_report("could not load prom '%s'", bios_name); 717 exit(1); 718 } 719 } 720 721 static void prom_realize(DeviceState *ds, Error **errp) 722 { 723 PROMState *s = OPENPROM(ds); 724 SysBusDevice *dev = SYS_BUS_DEVICE(ds); 725 726 if (!memory_region_init_ram_nomigrate(&s->prom, OBJECT(ds), "sun4m.prom", 727 PROM_SIZE_MAX, errp)) { 728 return; 729 } 730 731 vmstate_register_ram_global(&s->prom); 732 memory_region_set_readonly(&s->prom, true); 733 sysbus_init_mmio(dev, &s->prom); 734 } 735 736 static void prom_class_init(ObjectClass *klass, void *data) 737 { 738 DeviceClass *dc = DEVICE_CLASS(klass); 739 740 dc->realize = prom_realize; 741 } 742 743 static const TypeInfo prom_info = { 744 .name = TYPE_OPENPROM, 745 .parent = TYPE_SYS_BUS_DEVICE, 746 .instance_size = sizeof(PROMState), 747 .class_init = prom_class_init, 748 }; 749 750 #define TYPE_SUN4M_MEMORY "memory" 751 typedef struct RamDevice RamDevice; 752 DECLARE_INSTANCE_CHECKER(RamDevice, SUN4M_RAM, 753 TYPE_SUN4M_MEMORY) 754 755 struct RamDevice { 756 SysBusDevice parent_obj; 757 HostMemoryBackend *memdev; 758 }; 759 760 /* System RAM */ 761 static void ram_realize(DeviceState *dev, Error **errp) 762 { 763 RamDevice *d = SUN4M_RAM(dev); 764 MemoryRegion *ram = host_memory_backend_get_memory(d->memdev); 765 766 sysbus_init_mmio(SYS_BUS_DEVICE(dev), ram); 767 } 768 769 static void ram_initfn(Object *obj) 770 { 771 RamDevice *d = SUN4M_RAM(obj); 772 object_property_add_link(obj, "memdev", TYPE_MEMORY_BACKEND, 773 (Object **)&d->memdev, 774 object_property_allow_set_link, 775 OBJ_PROP_LINK_STRONG); 776 object_property_set_description(obj, "memdev", "Set RAM backend" 777 "Valid value is ID of a hostmem backend"); 778 } 779 780 static void ram_class_init(ObjectClass *klass, void *data) 781 { 782 DeviceClass *dc = DEVICE_CLASS(klass); 783 784 dc->realize = ram_realize; 785 } 786 787 static const TypeInfo ram_info = { 788 .name = TYPE_SUN4M_MEMORY, 789 .parent = TYPE_SYS_BUS_DEVICE, 790 .instance_size = sizeof(RamDevice), 791 .instance_init = ram_initfn, 792 .class_init = ram_class_init, 793 }; 794 795 static void cpu_devinit(const char *cpu_type, unsigned int id, 796 uint64_t prom_addr, qemu_irq **cpu_irqs) 797 { 798 SPARCCPU *cpu; 799 CPUSPARCState *env; 800 801 cpu = SPARC_CPU(object_new(cpu_type)); 802 env = &cpu->env; 803 804 qemu_register_reset(sun4m_cpu_reset, cpu); 805 object_property_set_bool(OBJECT(cpu), "start-powered-off", id != 0, 806 &error_abort); 807 qdev_realize_and_unref(DEVICE(cpu), NULL, &error_fatal); 808 cpu_sparc_set_id(env, id); 809 *cpu_irqs = qemu_allocate_irqs(cpu_set_irq, cpu, MAX_PILS); 810 env->prom_addr = prom_addr; 811 } 812 813 static void dummy_fdc_tc(void *opaque, int irq, int level) 814 { 815 } 816 817 static void sun4m_hw_init(MachineState *machine) 818 { 819 const struct sun4m_hwdef *hwdef = SUN4M_MACHINE_GET_CLASS(machine)->hwdef; 820 DeviceState *slavio_intctl; 821 unsigned int i; 822 Nvram *nvram; 823 qemu_irq *cpu_irqs[MAX_CPUS], slavio_irq[32], slavio_cpu_irq[MAX_CPUS]; 824 qemu_irq fdc_tc; 825 unsigned long kernel_size; 826 uint32_t initrd_size; 827 DriveInfo *fd[MAX_FD]; 828 FWCfgState *fw_cfg; 829 DeviceState *dev, *ms_kb_orgate, *serial_orgate; 830 SysBusDevice *s; 831 unsigned int smp_cpus = machine->smp.cpus; 832 unsigned int max_cpus = machine->smp.max_cpus; 833 HostMemoryBackend *ram_memdev = machine->memdev; 834 MACAddr hostid; 835 836 if (machine->ram_size > hwdef->max_mem) { 837 error_report("Too much memory for this machine: %" PRId64 "," 838 " maximum %" PRId64, 839 machine->ram_size / MiB, hwdef->max_mem / MiB); 840 exit(1); 841 } 842 843 /* init CPUs */ 844 for(i = 0; i < smp_cpus; i++) { 845 cpu_devinit(machine->cpu_type, i, hwdef->slavio_base, &cpu_irqs[i]); 846 } 847 848 for (i = smp_cpus; i < MAX_CPUS; i++) 849 cpu_irqs[i] = qemu_allocate_irqs(dummy_cpu_set_irq, NULL, MAX_PILS); 850 851 /* Create and map RAM frontend */ 852 dev = qdev_new("memory"); 853 object_property_set_link(OBJECT(dev), "memdev", OBJECT(ram_memdev), &error_fatal); 854 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 855 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, 0); 856 857 /* models without ECC don't trap when missing ram is accessed */ 858 if (!hwdef->ecc_base) { 859 empty_slot_init("ecc", machine->ram_size, 860 hwdef->max_mem - machine->ram_size); 861 } 862 863 prom_init(hwdef->slavio_base, machine->firmware); 864 865 slavio_intctl = slavio_intctl_init(hwdef->intctl_base, 866 hwdef->intctl_base + 0x10000ULL, 867 cpu_irqs); 868 869 for (i = 0; i < 32; i++) { 870 slavio_irq[i] = qdev_get_gpio_in(slavio_intctl, i); 871 } 872 for (i = 0; i < MAX_CPUS; i++) { 873 slavio_cpu_irq[i] = qdev_get_gpio_in(slavio_intctl, 32 + i); 874 } 875 876 if (hwdef->idreg_base) { 877 idreg_init(hwdef->idreg_base); 878 } 879 880 if (hwdef->afx_base) { 881 afx_init(hwdef->afx_base); 882 } 883 884 iommu_init(hwdef->iommu_base, hwdef->iommu_version, slavio_irq[30]); 885 886 if (hwdef->iommu_pad_base) { 887 /* On the real hardware (SS-5, LX) the MMU is not padded, but aliased. 888 Software shouldn't use aliased addresses, neither should it crash 889 when does. Using empty_slot instead of aliasing can help with 890 debugging such accesses */ 891 empty_slot_init("iommu.alias", 892 hwdef->iommu_pad_base, hwdef->iommu_pad_len); 893 } 894 895 sparc32_dma_init(hwdef->dma_base, 896 hwdef->esp_base, slavio_irq[18], 897 hwdef->le_base, slavio_irq[16], &hostid); 898 899 if (graphic_depth != 8 && graphic_depth != 24) { 900 error_report("Unsupported depth: %d", graphic_depth); 901 exit (1); 902 } 903 if (vga_interface_type != VGA_NONE) { 904 if (vga_interface_type == VGA_CG3) { 905 if (graphic_depth != 8) { 906 error_report("Unsupported depth: %d", graphic_depth); 907 exit(1); 908 } 909 910 if (!(graphic_width == 1024 && graphic_height == 768) && 911 !(graphic_width == 1152 && graphic_height == 900)) { 912 error_report("Unsupported resolution: %d x %d", graphic_width, 913 graphic_height); 914 exit(1); 915 } 916 917 /* sbus irq 5 */ 918 cg3_init(hwdef->tcx_base, slavio_irq[11], 0x00100000, 919 graphic_width, graphic_height, graphic_depth); 920 vga_interface_created = true; 921 } else { 922 /* If no display specified, default to TCX */ 923 if (graphic_depth != 8 && graphic_depth != 24) { 924 error_report("Unsupported depth: %d", graphic_depth); 925 exit(1); 926 } 927 928 if (!(graphic_width == 1024 && graphic_height == 768)) { 929 error_report("Unsupported resolution: %d x %d", 930 graphic_width, graphic_height); 931 exit(1); 932 } 933 934 tcx_init(hwdef->tcx_base, slavio_irq[11], 0x00100000, 935 graphic_width, graphic_height, graphic_depth); 936 vga_interface_created = true; 937 } 938 } 939 940 for (i = 0; i < MAX_VSIMMS; i++) { 941 /* vsimm registers probed by OBP */ 942 if (hwdef->vsimm[i].reg_base) { 943 char *name = g_strdup_printf("vsimm[%d]", i); 944 empty_slot_init(name, hwdef->vsimm[i].reg_base, 0x2000); 945 g_free(name); 946 } 947 } 948 949 if (hwdef->sx_base) { 950 create_unimplemented_device("sun-sx", hwdef->sx_base, 0x2000); 951 } 952 953 dev = qdev_new("sysbus-m48t08"); 954 qdev_prop_set_int32(dev, "base-year", 1968); 955 s = SYS_BUS_DEVICE(dev); 956 sysbus_realize_and_unref(s, &error_fatal); 957 sysbus_connect_irq(s, 0, slavio_irq[0]); 958 sysbus_mmio_map(s, 0, hwdef->nvram_base); 959 nvram = NVRAM(dev); 960 961 slavio_timer_init_all(hwdef->counter_base, slavio_irq[19], slavio_cpu_irq, smp_cpus); 962 963 /* Slavio TTYA (base+4, Linux ttyS0) is the first QEMU serial device 964 Slavio TTYB (base+0, Linux ttyS1) is the second QEMU serial device */ 965 dev = qdev_new(TYPE_ESCC); 966 qdev_prop_set_uint32(dev, "disabled", !machine->enable_graphics); 967 qdev_prop_set_uint32(dev, "frequency", ESCC_CLOCK); 968 qdev_prop_set_uint32(dev, "it_shift", 1); 969 qdev_prop_set_chr(dev, "chrB", NULL); 970 qdev_prop_set_chr(dev, "chrA", NULL); 971 qdev_prop_set_uint32(dev, "chnBtype", escc_mouse); 972 qdev_prop_set_uint32(dev, "chnAtype", escc_kbd); 973 s = SYS_BUS_DEVICE(dev); 974 sysbus_realize_and_unref(s, &error_fatal); 975 sysbus_mmio_map(s, 0, hwdef->ms_kb_base); 976 977 /* Logically OR both its IRQs together */ 978 ms_kb_orgate = qdev_new(TYPE_OR_IRQ); 979 object_property_set_int(OBJECT(ms_kb_orgate), "num-lines", 2, &error_fatal); 980 qdev_realize_and_unref(ms_kb_orgate, NULL, &error_fatal); 981 sysbus_connect_irq(s, 0, qdev_get_gpio_in(ms_kb_orgate, 0)); 982 sysbus_connect_irq(s, 1, qdev_get_gpio_in(ms_kb_orgate, 1)); 983 qdev_connect_gpio_out(ms_kb_orgate, 0, slavio_irq[14]); 984 985 dev = qdev_new(TYPE_ESCC); 986 qdev_prop_set_uint32(dev, "disabled", 0); 987 qdev_prop_set_uint32(dev, "frequency", ESCC_CLOCK); 988 qdev_prop_set_uint32(dev, "it_shift", 1); 989 qdev_prop_set_chr(dev, "chrB", serial_hd(1)); 990 qdev_prop_set_chr(dev, "chrA", serial_hd(0)); 991 qdev_prop_set_uint32(dev, "chnBtype", escc_serial); 992 qdev_prop_set_uint32(dev, "chnAtype", escc_serial); 993 994 s = SYS_BUS_DEVICE(dev); 995 sysbus_realize_and_unref(s, &error_fatal); 996 sysbus_mmio_map(s, 0, hwdef->serial_base); 997 998 /* Logically OR both its IRQs together */ 999 serial_orgate = qdev_new(TYPE_OR_IRQ); 1000 object_property_set_int(OBJECT(serial_orgate), "num-lines", 2, 1001 &error_fatal); 1002 qdev_realize_and_unref(serial_orgate, NULL, &error_fatal); 1003 sysbus_connect_irq(s, 0, qdev_get_gpio_in(serial_orgate, 0)); 1004 sysbus_connect_irq(s, 1, qdev_get_gpio_in(serial_orgate, 1)); 1005 qdev_connect_gpio_out(serial_orgate, 0, slavio_irq[15]); 1006 1007 if (hwdef->apc_base) { 1008 apc_init(hwdef->apc_base, qemu_allocate_irq(cpu_halt_signal, NULL, 0)); 1009 } 1010 1011 if (hwdef->fd_base) { 1012 /* there is zero or one floppy drive */ 1013 memset(fd, 0, sizeof(fd)); 1014 fd[0] = drive_get(IF_FLOPPY, 0, 0); 1015 sun4m_fdctrl_init(slavio_irq[22], hwdef->fd_base, fd, 1016 &fdc_tc); 1017 } else { 1018 fdc_tc = qemu_allocate_irq(dummy_fdc_tc, NULL, 0); 1019 } 1020 1021 slavio_misc_init(hwdef->slavio_base, hwdef->aux1_base, hwdef->aux2_base, 1022 slavio_irq[30], fdc_tc); 1023 1024 if (hwdef->cs_base) { 1025 sysbus_create_simple("sun-CS4231", hwdef->cs_base, 1026 slavio_irq[5]); 1027 } 1028 1029 if (hwdef->dbri_base) { 1030 /* ISDN chip with attached CS4215 audio codec */ 1031 /* prom space */ 1032 create_unimplemented_device("sun-DBRI.prom", 1033 hwdef->dbri_base + 0x1000, 0x30); 1034 /* reg space */ 1035 create_unimplemented_device("sun-DBRI", 1036 hwdef->dbri_base + 0x10000, 0x100); 1037 } 1038 1039 if (hwdef->bpp_base) { 1040 /* parallel port */ 1041 create_unimplemented_device("sun-bpp", hwdef->bpp_base, 0x20); 1042 } 1043 1044 initrd_size = 0; 1045 kernel_size = sun4m_load_kernel(machine->kernel_filename, 1046 machine->initrd_filename, 1047 machine->ram_size, &initrd_size); 1048 1049 nvram_init(nvram, hostid.a, machine->kernel_cmdline, 1050 machine->boot_config.order, machine->ram_size, kernel_size, 1051 graphic_width, graphic_height, graphic_depth, 1052 hwdef->nvram_machine_id, "Sun4m"); 1053 1054 if (hwdef->ecc_base) 1055 ecc_init(hwdef->ecc_base, slavio_irq[28], 1056 hwdef->ecc_version); 1057 1058 dev = qdev_new(TYPE_FW_CFG_MEM); 1059 fw_cfg = FW_CFG(dev); 1060 qdev_prop_set_uint32(dev, "data_width", 1); 1061 qdev_prop_set_bit(dev, "dma_enabled", false); 1062 object_property_add_child(OBJECT(qdev_get_machine()), TYPE_FW_CFG, 1063 OBJECT(fw_cfg)); 1064 s = SYS_BUS_DEVICE(dev); 1065 sysbus_realize_and_unref(s, &error_fatal); 1066 sysbus_mmio_map(s, 0, CFG_ADDR); 1067 sysbus_mmio_map(s, 1, CFG_ADDR + 2); 1068 1069 fw_cfg_add_i16(fw_cfg, FW_CFG_NB_CPUS, (uint16_t)smp_cpus); 1070 fw_cfg_add_i16(fw_cfg, FW_CFG_MAX_CPUS, (uint16_t)max_cpus); 1071 fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, (uint64_t)machine->ram_size); 1072 fw_cfg_add_i16(fw_cfg, FW_CFG_MACHINE_ID, hwdef->machine_id); 1073 fw_cfg_add_i16(fw_cfg, FW_CFG_SUN4M_DEPTH, graphic_depth); 1074 fw_cfg_add_i16(fw_cfg, FW_CFG_SUN4M_WIDTH, graphic_width); 1075 fw_cfg_add_i16(fw_cfg, FW_CFG_SUN4M_HEIGHT, graphic_height); 1076 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_ADDR, KERNEL_LOAD_ADDR); 1077 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_SIZE, kernel_size); 1078 if (machine->kernel_cmdline) { 1079 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_CMDLINE, CMDLINE_ADDR); 1080 pstrcpy_targphys("cmdline", CMDLINE_ADDR, TARGET_PAGE_SIZE, 1081 machine->kernel_cmdline); 1082 fw_cfg_add_string(fw_cfg, FW_CFG_CMDLINE_DATA, machine->kernel_cmdline); 1083 fw_cfg_add_i32(fw_cfg, FW_CFG_CMDLINE_SIZE, 1084 strlen(machine->kernel_cmdline) + 1); 1085 } else { 1086 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_CMDLINE, 0); 1087 fw_cfg_add_i32(fw_cfg, FW_CFG_CMDLINE_SIZE, 0); 1088 } 1089 fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_ADDR, INITRD_LOAD_ADDR); 1090 fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_SIZE, initrd_size); 1091 fw_cfg_add_i16(fw_cfg, FW_CFG_BOOT_DEVICE, machine->boot_config.order[0]); 1092 qemu_register_boot_set(fw_cfg_boot_set, fw_cfg); 1093 } 1094 1095 enum { 1096 ss5_id = 32, 1097 vger_id, 1098 lx_id, 1099 ss4_id, 1100 scls_id, 1101 sbook_id, 1102 ss10_id = 64, 1103 ss20_id, 1104 ss600mp_id, 1105 }; 1106 1107 static void sun4m_machine_class_init(ObjectClass *oc, void *data) 1108 { 1109 MachineClass *mc = MACHINE_CLASS(oc); 1110 1111 mc->init = sun4m_hw_init; 1112 mc->block_default_type = IF_SCSI; 1113 mc->default_boot_order = "c"; 1114 mc->default_display = "tcx"; 1115 mc->default_ram_id = "sun4m.ram"; 1116 } 1117 1118 static void ss5_class_init(ObjectClass *oc, void *data) 1119 { 1120 MachineClass *mc = MACHINE_CLASS(oc); 1121 Sun4mMachineClass *smc = SUN4M_MACHINE_CLASS(mc); 1122 static const struct sun4m_hwdef ss5_hwdef = { 1123 .iommu_base = 0x10000000, 1124 .iommu_pad_base = 0x10004000, 1125 .iommu_pad_len = 0x0fffb000, 1126 .tcx_base = 0x50000000, 1127 .cs_base = 0x6c000000, 1128 .slavio_base = 0x70000000, 1129 .ms_kb_base = 0x71000000, 1130 .serial_base = 0x71100000, 1131 .nvram_base = 0x71200000, 1132 .fd_base = 0x71400000, 1133 .counter_base = 0x71d00000, 1134 .intctl_base = 0x71e00000, 1135 .idreg_base = 0x78000000, 1136 .dma_base = 0x78400000, 1137 .esp_base = 0x78800000, 1138 .le_base = 0x78c00000, 1139 .apc_base = 0x6a000000, 1140 .afx_base = 0x6e000000, 1141 .aux1_base = 0x71900000, 1142 .aux2_base = 0x71910000, 1143 .nvram_machine_id = 0x80, 1144 .machine_id = ss5_id, 1145 .iommu_version = 0x05000000, 1146 .max_mem = 0x10000000, 1147 }; 1148 1149 mc->desc = "Sun4m platform, SPARCstation 5"; 1150 mc->is_default = true; 1151 mc->default_cpu_type = SPARC_CPU_TYPE_NAME("Fujitsu-MB86904"); 1152 smc->hwdef = &ss5_hwdef; 1153 } 1154 1155 static void ss10_class_init(ObjectClass *oc, void *data) 1156 { 1157 MachineClass *mc = MACHINE_CLASS(oc); 1158 Sun4mMachineClass *smc = SUN4M_MACHINE_CLASS(mc); 1159 static const struct sun4m_hwdef ss10_hwdef = { 1160 .iommu_base = 0xfe0000000ULL, 1161 .tcx_base = 0xe20000000ULL, 1162 .slavio_base = 0xff0000000ULL, 1163 .ms_kb_base = 0xff1000000ULL, 1164 .serial_base = 0xff1100000ULL, 1165 .nvram_base = 0xff1200000ULL, 1166 .fd_base = 0xff1700000ULL, 1167 .counter_base = 0xff1300000ULL, 1168 .intctl_base = 0xff1400000ULL, 1169 .idreg_base = 0xef0000000ULL, 1170 .dma_base = 0xef0400000ULL, 1171 .esp_base = 0xef0800000ULL, 1172 .le_base = 0xef0c00000ULL, 1173 .apc_base = 0xefa000000ULL, /* XXX should not exist */ 1174 .aux1_base = 0xff1800000ULL, 1175 .aux2_base = 0xff1a01000ULL, 1176 .ecc_base = 0xf00000000ULL, 1177 .ecc_version = 0x10000000, /* version 0, implementation 1 */ 1178 .nvram_machine_id = 0x72, 1179 .machine_id = ss10_id, 1180 .iommu_version = 0x03000000, 1181 .max_mem = 0xf00000000ULL, 1182 }; 1183 1184 mc->desc = "Sun4m platform, SPARCstation 10"; 1185 mc->max_cpus = 4; 1186 mc->default_cpu_type = SPARC_CPU_TYPE_NAME("TI-SuperSparc-II"); 1187 smc->hwdef = &ss10_hwdef; 1188 } 1189 1190 static void ss600mp_class_init(ObjectClass *oc, void *data) 1191 { 1192 MachineClass *mc = MACHINE_CLASS(oc); 1193 Sun4mMachineClass *smc = SUN4M_MACHINE_CLASS(mc); 1194 static const struct sun4m_hwdef ss600mp_hwdef = { 1195 .iommu_base = 0xfe0000000ULL, 1196 .tcx_base = 0xe20000000ULL, 1197 .slavio_base = 0xff0000000ULL, 1198 .ms_kb_base = 0xff1000000ULL, 1199 .serial_base = 0xff1100000ULL, 1200 .nvram_base = 0xff1200000ULL, 1201 .counter_base = 0xff1300000ULL, 1202 .intctl_base = 0xff1400000ULL, 1203 .dma_base = 0xef0081000ULL, 1204 .esp_base = 0xef0080000ULL, 1205 .le_base = 0xef0060000ULL, 1206 .apc_base = 0xefa000000ULL, /* XXX should not exist */ 1207 .aux1_base = 0xff1800000ULL, 1208 .aux2_base = 0xff1a01000ULL, /* XXX should not exist */ 1209 .ecc_base = 0xf00000000ULL, 1210 .ecc_version = 0x00000000, /* version 0, implementation 0 */ 1211 .nvram_machine_id = 0x71, 1212 .machine_id = ss600mp_id, 1213 .iommu_version = 0x01000000, 1214 .max_mem = 0xf00000000ULL, 1215 }; 1216 1217 mc->desc = "Sun4m platform, SPARCserver 600MP"; 1218 mc->max_cpus = 4; 1219 mc->default_cpu_type = SPARC_CPU_TYPE_NAME("TI-SuperSparc-II"); 1220 smc->hwdef = &ss600mp_hwdef; 1221 } 1222 1223 static void ss20_class_init(ObjectClass *oc, void *data) 1224 { 1225 MachineClass *mc = MACHINE_CLASS(oc); 1226 Sun4mMachineClass *smc = SUN4M_MACHINE_CLASS(mc); 1227 static const struct sun4m_hwdef ss20_hwdef = { 1228 .iommu_base = 0xfe0000000ULL, 1229 .tcx_base = 0xe20000000ULL, 1230 .slavio_base = 0xff0000000ULL, 1231 .ms_kb_base = 0xff1000000ULL, 1232 .serial_base = 0xff1100000ULL, 1233 .nvram_base = 0xff1200000ULL, 1234 .fd_base = 0xff1700000ULL, 1235 .counter_base = 0xff1300000ULL, 1236 .intctl_base = 0xff1400000ULL, 1237 .idreg_base = 0xef0000000ULL, 1238 .dma_base = 0xef0400000ULL, 1239 .esp_base = 0xef0800000ULL, 1240 .le_base = 0xef0c00000ULL, 1241 .bpp_base = 0xef4800000ULL, 1242 .apc_base = 0xefa000000ULL, /* XXX should not exist */ 1243 .aux1_base = 0xff1800000ULL, 1244 .aux2_base = 0xff1a01000ULL, 1245 .dbri_base = 0xee0000000ULL, 1246 .sx_base = 0xf80000000ULL, 1247 .vsimm = { 1248 { 1249 .reg_base = 0x9c000000ULL, 1250 .vram_base = 0xfc000000ULL 1251 }, { 1252 .reg_base = 0x90000000ULL, 1253 .vram_base = 0xf0000000ULL 1254 }, { 1255 .reg_base = 0x94000000ULL 1256 }, { 1257 .reg_base = 0x98000000ULL 1258 } 1259 }, 1260 .ecc_base = 0xf00000000ULL, 1261 .ecc_version = 0x20000000, /* version 0, implementation 2 */ 1262 .nvram_machine_id = 0x72, 1263 .machine_id = ss20_id, 1264 .iommu_version = 0x13000000, 1265 .max_mem = 0xf00000000ULL, 1266 }; 1267 1268 mc->desc = "Sun4m platform, SPARCstation 20"; 1269 mc->max_cpus = 4; 1270 mc->default_cpu_type = SPARC_CPU_TYPE_NAME("TI-SuperSparc-II"); 1271 smc->hwdef = &ss20_hwdef; 1272 } 1273 1274 static void voyager_class_init(ObjectClass *oc, void *data) 1275 { 1276 MachineClass *mc = MACHINE_CLASS(oc); 1277 Sun4mMachineClass *smc = SUN4M_MACHINE_CLASS(mc); 1278 static const struct sun4m_hwdef voyager_hwdef = { 1279 .iommu_base = 0x10000000, 1280 .tcx_base = 0x50000000, 1281 .slavio_base = 0x70000000, 1282 .ms_kb_base = 0x71000000, 1283 .serial_base = 0x71100000, 1284 .nvram_base = 0x71200000, 1285 .fd_base = 0x71400000, 1286 .counter_base = 0x71d00000, 1287 .intctl_base = 0x71e00000, 1288 .idreg_base = 0x78000000, 1289 .dma_base = 0x78400000, 1290 .esp_base = 0x78800000, 1291 .le_base = 0x78c00000, 1292 .apc_base = 0x71300000, /* pmc */ 1293 .aux1_base = 0x71900000, 1294 .aux2_base = 0x71910000, 1295 .nvram_machine_id = 0x80, 1296 .machine_id = vger_id, 1297 .iommu_version = 0x05000000, 1298 .max_mem = 0x10000000, 1299 }; 1300 1301 mc->desc = "Sun4m platform, SPARCstation Voyager"; 1302 mc->default_cpu_type = SPARC_CPU_TYPE_NAME("Fujitsu-MB86904"); 1303 smc->hwdef = &voyager_hwdef; 1304 } 1305 1306 static void ss_lx_class_init(ObjectClass *oc, void *data) 1307 { 1308 MachineClass *mc = MACHINE_CLASS(oc); 1309 Sun4mMachineClass *smc = SUN4M_MACHINE_CLASS(mc); 1310 static const struct sun4m_hwdef ss_lx_hwdef = { 1311 .iommu_base = 0x10000000, 1312 .iommu_pad_base = 0x10004000, 1313 .iommu_pad_len = 0x0fffb000, 1314 .tcx_base = 0x50000000, 1315 .slavio_base = 0x70000000, 1316 .ms_kb_base = 0x71000000, 1317 .serial_base = 0x71100000, 1318 .nvram_base = 0x71200000, 1319 .fd_base = 0x71400000, 1320 .counter_base = 0x71d00000, 1321 .intctl_base = 0x71e00000, 1322 .idreg_base = 0x78000000, 1323 .dma_base = 0x78400000, 1324 .esp_base = 0x78800000, 1325 .le_base = 0x78c00000, 1326 .aux1_base = 0x71900000, 1327 .aux2_base = 0x71910000, 1328 .nvram_machine_id = 0x80, 1329 .machine_id = lx_id, 1330 .iommu_version = 0x04000000, 1331 .max_mem = 0x10000000, 1332 }; 1333 1334 mc->desc = "Sun4m platform, SPARCstation LX"; 1335 mc->default_cpu_type = SPARC_CPU_TYPE_NAME("TI-MicroSparc-I"); 1336 smc->hwdef = &ss_lx_hwdef; 1337 } 1338 1339 static void ss4_class_init(ObjectClass *oc, void *data) 1340 { 1341 MachineClass *mc = MACHINE_CLASS(oc); 1342 Sun4mMachineClass *smc = SUN4M_MACHINE_CLASS(mc); 1343 static const struct sun4m_hwdef ss4_hwdef = { 1344 .iommu_base = 0x10000000, 1345 .tcx_base = 0x50000000, 1346 .cs_base = 0x6c000000, 1347 .slavio_base = 0x70000000, 1348 .ms_kb_base = 0x71000000, 1349 .serial_base = 0x71100000, 1350 .nvram_base = 0x71200000, 1351 .fd_base = 0x71400000, 1352 .counter_base = 0x71d00000, 1353 .intctl_base = 0x71e00000, 1354 .idreg_base = 0x78000000, 1355 .dma_base = 0x78400000, 1356 .esp_base = 0x78800000, 1357 .le_base = 0x78c00000, 1358 .apc_base = 0x6a000000, 1359 .aux1_base = 0x71900000, 1360 .aux2_base = 0x71910000, 1361 .nvram_machine_id = 0x80, 1362 .machine_id = ss4_id, 1363 .iommu_version = 0x05000000, 1364 .max_mem = 0x10000000, 1365 }; 1366 1367 mc->desc = "Sun4m platform, SPARCstation 4"; 1368 mc->default_cpu_type = SPARC_CPU_TYPE_NAME("Fujitsu-MB86904"); 1369 smc->hwdef = &ss4_hwdef; 1370 } 1371 1372 static void scls_class_init(ObjectClass *oc, void *data) 1373 { 1374 MachineClass *mc = MACHINE_CLASS(oc); 1375 Sun4mMachineClass *smc = SUN4M_MACHINE_CLASS(mc); 1376 static const struct sun4m_hwdef scls_hwdef = { 1377 .iommu_base = 0x10000000, 1378 .tcx_base = 0x50000000, 1379 .slavio_base = 0x70000000, 1380 .ms_kb_base = 0x71000000, 1381 .serial_base = 0x71100000, 1382 .nvram_base = 0x71200000, 1383 .fd_base = 0x71400000, 1384 .counter_base = 0x71d00000, 1385 .intctl_base = 0x71e00000, 1386 .idreg_base = 0x78000000, 1387 .dma_base = 0x78400000, 1388 .esp_base = 0x78800000, 1389 .le_base = 0x78c00000, 1390 .apc_base = 0x6a000000, 1391 .aux1_base = 0x71900000, 1392 .aux2_base = 0x71910000, 1393 .nvram_machine_id = 0x80, 1394 .machine_id = scls_id, 1395 .iommu_version = 0x05000000, 1396 .max_mem = 0x10000000, 1397 }; 1398 1399 mc->desc = "Sun4m platform, SPARCClassic"; 1400 mc->default_cpu_type = SPARC_CPU_TYPE_NAME("TI-MicroSparc-I"); 1401 smc->hwdef = &scls_hwdef; 1402 } 1403 1404 static void sbook_class_init(ObjectClass *oc, void *data) 1405 { 1406 MachineClass *mc = MACHINE_CLASS(oc); 1407 Sun4mMachineClass *smc = SUN4M_MACHINE_CLASS(mc); 1408 static const struct sun4m_hwdef sbook_hwdef = { 1409 .iommu_base = 0x10000000, 1410 .tcx_base = 0x50000000, /* XXX */ 1411 .slavio_base = 0x70000000, 1412 .ms_kb_base = 0x71000000, 1413 .serial_base = 0x71100000, 1414 .nvram_base = 0x71200000, 1415 .fd_base = 0x71400000, 1416 .counter_base = 0x71d00000, 1417 .intctl_base = 0x71e00000, 1418 .idreg_base = 0x78000000, 1419 .dma_base = 0x78400000, 1420 .esp_base = 0x78800000, 1421 .le_base = 0x78c00000, 1422 .apc_base = 0x6a000000, 1423 .aux1_base = 0x71900000, 1424 .aux2_base = 0x71910000, 1425 .nvram_machine_id = 0x80, 1426 .machine_id = sbook_id, 1427 .iommu_version = 0x05000000, 1428 .max_mem = 0x10000000, 1429 }; 1430 1431 mc->desc = "Sun4m platform, SPARCbook"; 1432 mc->default_cpu_type = SPARC_CPU_TYPE_NAME("TI-MicroSparc-I"); 1433 smc->hwdef = &sbook_hwdef; 1434 } 1435 1436 static const TypeInfo sun4m_machine_types[] = { 1437 { 1438 .name = MACHINE_TYPE_NAME("SS-5"), 1439 .parent = TYPE_SUN4M_MACHINE, 1440 .class_init = ss5_class_init, 1441 }, { 1442 .name = MACHINE_TYPE_NAME("SS-10"), 1443 .parent = TYPE_SUN4M_MACHINE, 1444 .class_init = ss10_class_init, 1445 }, { 1446 .name = MACHINE_TYPE_NAME("SS-600MP"), 1447 .parent = TYPE_SUN4M_MACHINE, 1448 .class_init = ss600mp_class_init, 1449 }, { 1450 .name = MACHINE_TYPE_NAME("SS-20"), 1451 .parent = TYPE_SUN4M_MACHINE, 1452 .class_init = ss20_class_init, 1453 }, { 1454 .name = MACHINE_TYPE_NAME("Voyager"), 1455 .parent = TYPE_SUN4M_MACHINE, 1456 .class_init = voyager_class_init, 1457 }, { 1458 .name = MACHINE_TYPE_NAME("LX"), 1459 .parent = TYPE_SUN4M_MACHINE, 1460 .class_init = ss_lx_class_init, 1461 }, { 1462 .name = MACHINE_TYPE_NAME("SS-4"), 1463 .parent = TYPE_SUN4M_MACHINE, 1464 .class_init = ss4_class_init, 1465 }, { 1466 .name = MACHINE_TYPE_NAME("SPARCClassic"), 1467 .parent = TYPE_SUN4M_MACHINE, 1468 .class_init = scls_class_init, 1469 }, { 1470 .name = MACHINE_TYPE_NAME("SPARCbook"), 1471 .parent = TYPE_SUN4M_MACHINE, 1472 .class_init = sbook_class_init, 1473 }, { 1474 .name = TYPE_SUN4M_MACHINE, 1475 .parent = TYPE_MACHINE, 1476 .class_size = sizeof(Sun4mMachineClass), 1477 .class_init = sun4m_machine_class_init, 1478 .abstract = true, 1479 } 1480 }; 1481 1482 DEFINE_TYPES(sun4m_machine_types) 1483 1484 static void sun4m_register_types(void) 1485 { 1486 type_register_static(&idreg_info); 1487 type_register_static(&afx_info); 1488 type_register_static(&prom_info); 1489 type_register_static(&ram_info); 1490 } 1491 1492 type_init(sun4m_register_types) 1493