1 /* 2 * SMBIOS Support 3 * 4 * Copyright (C) 2009 Hewlett-Packard Development Company, L.P. 5 * Copyright (C) 2013 Red Hat, Inc. 6 * 7 * Authors: 8 * Alex Williamson <alex.williamson@hp.com> 9 * Markus Armbruster <armbru@redhat.com> 10 * 11 * This work is licensed under the terms of the GNU GPL, version 2. See 12 * the COPYING file in the top-level directory. 13 * 14 * Contributions after 2012-01-13 are licensed under the terms of the 15 * GNU GPL, version 2 or (at your option) any later version. 16 */ 17 18 #include "qemu/osdep.h" 19 #include "qemu/units.h" 20 #include "qapi/error.h" 21 #include "qemu/config-file.h" 22 #include "qemu/error-report.h" 23 #include "qemu/module.h" 24 #include "qemu/option.h" 25 #include "sysemu/sysemu.h" 26 #include "qemu/uuid.h" 27 #include "hw/firmware/smbios.h" 28 #include "hw/loader.h" 29 #include "hw/boards.h" 30 #include "hw/pci/pci_bus.h" 31 #include "hw/pci/pci_device.h" 32 #include "smbios_build.h" 33 34 /* legacy structures and constants for <= 2.0 machines */ 35 struct smbios_header { 36 uint16_t length; 37 uint8_t type; 38 } QEMU_PACKED; 39 40 struct smbios_field { 41 struct smbios_header header; 42 uint8_t type; 43 uint16_t offset; 44 uint8_t data[]; 45 } QEMU_PACKED; 46 47 struct smbios_table { 48 struct smbios_header header; 49 uint8_t data[]; 50 } QEMU_PACKED; 51 52 #define SMBIOS_FIELD_ENTRY 0 53 #define SMBIOS_TABLE_ENTRY 1 54 55 static uint8_t *smbios_entries; 56 static size_t smbios_entries_len; 57 static bool smbios_uuid_encoded = true; 58 /* end: legacy structures & constants for <= 2.0 machines */ 59 60 /* 61 * SMBIOS tables provided by user with '-smbios file=<foo>' option 62 */ 63 uint8_t *usr_blobs; 64 size_t usr_blobs_len; 65 static GArray *usr_blobs_sizes; 66 static unsigned usr_table_max; 67 static unsigned usr_table_cnt; 68 69 uint8_t *smbios_tables; 70 size_t smbios_tables_len; 71 unsigned smbios_table_max; 72 unsigned smbios_table_cnt; 73 static SmbiosEntryPointType smbios_ep_type = SMBIOS_ENTRY_POINT_TYPE_32; 74 75 static SmbiosEntryPoint ep; 76 77 static int smbios_type4_count = 0; 78 static bool smbios_have_defaults; 79 static uint32_t smbios_cpuid_version, smbios_cpuid_features; 80 81 DECLARE_BITMAP(smbios_have_binfile_bitmap, SMBIOS_MAX_TYPE + 1); 82 DECLARE_BITMAP(smbios_have_fields_bitmap, SMBIOS_MAX_TYPE + 1); 83 84 smbios_type0_t smbios_type0; 85 smbios_type1_t smbios_type1; 86 87 static struct { 88 const char *manufacturer, *product, *version, *serial, *asset, *location; 89 } type2; 90 91 static struct { 92 const char *manufacturer, *version, *serial, *asset, *sku; 93 } type3; 94 95 /* 96 * SVVP requires max_speed and current_speed to be set and not being 97 * 0 which counts as unknown (SMBIOS 3.1.0/Table 21). Set the 98 * default value to 2000MHz as we did before. 99 */ 100 #define DEFAULT_CPU_SPEED 2000 101 102 static struct { 103 uint16_t processor_family; 104 const char *sock_pfx, *manufacturer, *version, *serial, *asset, *part; 105 uint64_t max_speed; 106 uint64_t current_speed; 107 uint64_t processor_id; 108 } type4 = { 109 .max_speed = DEFAULT_CPU_SPEED, 110 .current_speed = DEFAULT_CPU_SPEED, 111 .processor_id = 0, 112 .processor_family = 0x01, /* Other */ 113 }; 114 115 struct type8_instance { 116 const char *internal_reference, *external_reference; 117 uint8_t connector_type, port_type; 118 QTAILQ_ENTRY(type8_instance) next; 119 }; 120 static QTAILQ_HEAD(, type8_instance) type8 = QTAILQ_HEAD_INITIALIZER(type8); 121 122 /* type 9 instance for parsing */ 123 struct type9_instance { 124 const char *slot_designation, *pcidev; 125 uint8_t slot_type, slot_data_bus_width, current_usage, slot_length, 126 slot_characteristics1, slot_characteristics2; 127 uint16_t slot_id; 128 QTAILQ_ENTRY(type9_instance) next; 129 }; 130 static QTAILQ_HEAD(, type9_instance) type9 = QTAILQ_HEAD_INITIALIZER(type9); 131 132 static struct { 133 size_t nvalues; 134 char **values; 135 } type11; 136 137 static struct { 138 const char *loc_pfx, *bank, *manufacturer, *serial, *asset, *part; 139 uint16_t speed; 140 } type17; 141 142 static QEnumLookup type41_kind_lookup = { 143 .array = (const char *const[]) { 144 "other", 145 "unknown", 146 "video", 147 "scsi", 148 "ethernet", 149 "tokenring", 150 "sound", 151 "pata", 152 "sata", 153 "sas", 154 }, 155 .size = 10 156 }; 157 struct type41_instance { 158 const char *designation, *pcidev; 159 uint8_t instance, kind; 160 QTAILQ_ENTRY(type41_instance) next; 161 }; 162 static QTAILQ_HEAD(, type41_instance) type41 = QTAILQ_HEAD_INITIALIZER(type41); 163 164 static QemuOptsList qemu_smbios_opts = { 165 .name = "smbios", 166 .head = QTAILQ_HEAD_INITIALIZER(qemu_smbios_opts.head), 167 .desc = { 168 /* 169 * no elements => accept any params 170 * validation will happen later 171 */ 172 { /* end of list */ } 173 } 174 }; 175 176 static const QemuOptDesc qemu_smbios_file_opts[] = { 177 { 178 .name = "file", 179 .type = QEMU_OPT_STRING, 180 .help = "binary file containing an SMBIOS element", 181 }, 182 { /* end of list */ } 183 }; 184 185 static const QemuOptDesc qemu_smbios_type0_opts[] = { 186 { 187 .name = "type", 188 .type = QEMU_OPT_NUMBER, 189 .help = "SMBIOS element type", 190 },{ 191 .name = "vendor", 192 .type = QEMU_OPT_STRING, 193 .help = "vendor name", 194 },{ 195 .name = "version", 196 .type = QEMU_OPT_STRING, 197 .help = "version number", 198 },{ 199 .name = "date", 200 .type = QEMU_OPT_STRING, 201 .help = "release date", 202 },{ 203 .name = "release", 204 .type = QEMU_OPT_STRING, 205 .help = "revision number", 206 },{ 207 .name = "uefi", 208 .type = QEMU_OPT_BOOL, 209 .help = "uefi support", 210 }, 211 { /* end of list */ } 212 }; 213 214 static const QemuOptDesc qemu_smbios_type1_opts[] = { 215 { 216 .name = "type", 217 .type = QEMU_OPT_NUMBER, 218 .help = "SMBIOS element type", 219 },{ 220 .name = "manufacturer", 221 .type = QEMU_OPT_STRING, 222 .help = "manufacturer name", 223 },{ 224 .name = "product", 225 .type = QEMU_OPT_STRING, 226 .help = "product name", 227 },{ 228 .name = "version", 229 .type = QEMU_OPT_STRING, 230 .help = "version number", 231 },{ 232 .name = "serial", 233 .type = QEMU_OPT_STRING, 234 .help = "serial number", 235 },{ 236 .name = "uuid", 237 .type = QEMU_OPT_STRING, 238 .help = "UUID", 239 },{ 240 .name = "sku", 241 .type = QEMU_OPT_STRING, 242 .help = "SKU number", 243 },{ 244 .name = "family", 245 .type = QEMU_OPT_STRING, 246 .help = "family name", 247 }, 248 { /* end of list */ } 249 }; 250 251 static const QemuOptDesc qemu_smbios_type2_opts[] = { 252 { 253 .name = "type", 254 .type = QEMU_OPT_NUMBER, 255 .help = "SMBIOS element type", 256 },{ 257 .name = "manufacturer", 258 .type = QEMU_OPT_STRING, 259 .help = "manufacturer name", 260 },{ 261 .name = "product", 262 .type = QEMU_OPT_STRING, 263 .help = "product name", 264 },{ 265 .name = "version", 266 .type = QEMU_OPT_STRING, 267 .help = "version number", 268 },{ 269 .name = "serial", 270 .type = QEMU_OPT_STRING, 271 .help = "serial number", 272 },{ 273 .name = "asset", 274 .type = QEMU_OPT_STRING, 275 .help = "asset tag number", 276 },{ 277 .name = "location", 278 .type = QEMU_OPT_STRING, 279 .help = "location in chassis", 280 }, 281 { /* end of list */ } 282 }; 283 284 static const QemuOptDesc qemu_smbios_type3_opts[] = { 285 { 286 .name = "type", 287 .type = QEMU_OPT_NUMBER, 288 .help = "SMBIOS element type", 289 },{ 290 .name = "manufacturer", 291 .type = QEMU_OPT_STRING, 292 .help = "manufacturer name", 293 },{ 294 .name = "version", 295 .type = QEMU_OPT_STRING, 296 .help = "version number", 297 },{ 298 .name = "serial", 299 .type = QEMU_OPT_STRING, 300 .help = "serial number", 301 },{ 302 .name = "asset", 303 .type = QEMU_OPT_STRING, 304 .help = "asset tag number", 305 },{ 306 .name = "sku", 307 .type = QEMU_OPT_STRING, 308 .help = "SKU number", 309 }, 310 { /* end of list */ } 311 }; 312 313 static const QemuOptDesc qemu_smbios_type4_opts[] = { 314 { 315 .name = "type", 316 .type = QEMU_OPT_NUMBER, 317 .help = "SMBIOS element type", 318 },{ 319 .name = "sock_pfx", 320 .type = QEMU_OPT_STRING, 321 .help = "socket designation string prefix", 322 },{ 323 .name = "manufacturer", 324 .type = QEMU_OPT_STRING, 325 .help = "manufacturer name", 326 },{ 327 .name = "version", 328 .type = QEMU_OPT_STRING, 329 .help = "version number", 330 },{ 331 .name = "max-speed", 332 .type = QEMU_OPT_NUMBER, 333 .help = "max speed in MHz", 334 },{ 335 .name = "current-speed", 336 .type = QEMU_OPT_NUMBER, 337 .help = "speed at system boot in MHz", 338 },{ 339 .name = "serial", 340 .type = QEMU_OPT_STRING, 341 .help = "serial number", 342 },{ 343 .name = "asset", 344 .type = QEMU_OPT_STRING, 345 .help = "asset tag number", 346 },{ 347 .name = "part", 348 .type = QEMU_OPT_STRING, 349 .help = "part number", 350 }, { 351 .name = "processor-family", 352 .type = QEMU_OPT_NUMBER, 353 .help = "processor family", 354 }, { 355 .name = "processor-id", 356 .type = QEMU_OPT_NUMBER, 357 .help = "processor id", 358 }, 359 { /* end of list */ } 360 }; 361 362 static const QemuOptDesc qemu_smbios_type8_opts[] = { 363 { 364 .name = "type", 365 .type = QEMU_OPT_NUMBER, 366 .help = "SMBIOS element type", 367 }, 368 { 369 .name = "internal_reference", 370 .type = QEMU_OPT_STRING, 371 .help = "internal reference designator", 372 }, 373 { 374 .name = "external_reference", 375 .type = QEMU_OPT_STRING, 376 .help = "external reference designator", 377 }, 378 { 379 .name = "connector_type", 380 .type = QEMU_OPT_NUMBER, 381 .help = "connector type", 382 }, 383 { 384 .name = "port_type", 385 .type = QEMU_OPT_NUMBER, 386 .help = "port type", 387 }, 388 { /* end of list */ } 389 }; 390 391 static const QemuOptDesc qemu_smbios_type9_opts[] = { 392 { 393 .name = "type", 394 .type = QEMU_OPT_NUMBER, 395 .help = "SMBIOS element type", 396 }, 397 { 398 .name = "slot_designation", 399 .type = QEMU_OPT_STRING, 400 .help = "string number for reference designation", 401 }, 402 { 403 .name = "slot_type", 404 .type = QEMU_OPT_NUMBER, 405 .help = "connector type", 406 }, 407 { 408 .name = "slot_data_bus_width", 409 .type = QEMU_OPT_NUMBER, 410 .help = "port type", 411 }, 412 { 413 .name = "current_usage", 414 .type = QEMU_OPT_NUMBER, 415 .help = "current usage", 416 }, 417 { 418 .name = "slot_length", 419 .type = QEMU_OPT_NUMBER, 420 .help = "system slot length", 421 }, 422 { 423 .name = "slot_id", 424 .type = QEMU_OPT_NUMBER, 425 .help = "system slot id", 426 }, 427 { 428 .name = "slot_characteristics1", 429 .type = QEMU_OPT_NUMBER, 430 .help = "slot characteristics1, see the spec", 431 }, 432 { 433 .name = "slot_characteristics2", 434 .type = QEMU_OPT_NUMBER, 435 .help = "slot characteristics2, see the spec", 436 }, 437 { 438 .name = "pci_device", 439 .type = QEMU_OPT_STRING, 440 .help = "PCI device, if provided." 441 } 442 }; 443 444 static const QemuOptDesc qemu_smbios_type11_opts[] = { 445 { 446 .name = "type", 447 .type = QEMU_OPT_NUMBER, 448 .help = "SMBIOS element type", 449 }, 450 { 451 .name = "value", 452 .type = QEMU_OPT_STRING, 453 .help = "OEM string data", 454 }, 455 { 456 .name = "path", 457 .type = QEMU_OPT_STRING, 458 .help = "OEM string data from file", 459 }, 460 { /* end of list */ } 461 }; 462 463 static const QemuOptDesc qemu_smbios_type17_opts[] = { 464 { 465 .name = "type", 466 .type = QEMU_OPT_NUMBER, 467 .help = "SMBIOS element type", 468 },{ 469 .name = "loc_pfx", 470 .type = QEMU_OPT_STRING, 471 .help = "device locator string prefix", 472 },{ 473 .name = "bank", 474 .type = QEMU_OPT_STRING, 475 .help = "bank locator string", 476 },{ 477 .name = "manufacturer", 478 .type = QEMU_OPT_STRING, 479 .help = "manufacturer name", 480 },{ 481 .name = "serial", 482 .type = QEMU_OPT_STRING, 483 .help = "serial number", 484 },{ 485 .name = "asset", 486 .type = QEMU_OPT_STRING, 487 .help = "asset tag number", 488 },{ 489 .name = "part", 490 .type = QEMU_OPT_STRING, 491 .help = "part number", 492 },{ 493 .name = "speed", 494 .type = QEMU_OPT_NUMBER, 495 .help = "maximum capable speed", 496 }, 497 { /* end of list */ } 498 }; 499 500 static const QemuOptDesc qemu_smbios_type41_opts[] = { 501 { 502 .name = "type", 503 .type = QEMU_OPT_NUMBER, 504 .help = "SMBIOS element type", 505 },{ 506 .name = "designation", 507 .type = QEMU_OPT_STRING, 508 .help = "reference designation string", 509 },{ 510 .name = "kind", 511 .type = QEMU_OPT_STRING, 512 .help = "device type", 513 .def_value_str = "other", 514 },{ 515 .name = "instance", 516 .type = QEMU_OPT_NUMBER, 517 .help = "device type instance", 518 },{ 519 .name = "pcidev", 520 .type = QEMU_OPT_STRING, 521 .help = "PCI device", 522 }, 523 { /* end of list */ } 524 }; 525 526 static void smbios_register_config(void) 527 { 528 qemu_add_opts(&qemu_smbios_opts); 529 } 530 531 opts_init(smbios_register_config); 532 533 /* 534 * The SMBIOS 2.1 "structure table length" field in the 535 * entry point uses a 16-bit integer, so we're limited 536 * in total table size 537 */ 538 #define SMBIOS_21_MAX_TABLES_LEN 0xffff 539 540 static void smbios_check_type4_count(uint32_t expected_t4_count) 541 { 542 if (smbios_type4_count && smbios_type4_count != expected_t4_count) { 543 error_report("Expected %d SMBIOS Type 4 tables, got %d instead", 544 expected_t4_count, smbios_type4_count); 545 exit(1); 546 } 547 } 548 549 static void smbios_validate_table(void) 550 { 551 if (smbios_ep_type == SMBIOS_ENTRY_POINT_TYPE_32 && 552 smbios_tables_len > SMBIOS_21_MAX_TABLES_LEN) { 553 error_report("SMBIOS 2.1 table length %zu exceeds %d", 554 smbios_tables_len, SMBIOS_21_MAX_TABLES_LEN); 555 exit(1); 556 } 557 } 558 559 560 /* legacy setup functions for <= 2.0 machines */ 561 static void smbios_add_field(int type, int offset, const void *data, size_t len) 562 { 563 struct smbios_field *field; 564 565 if (!smbios_entries) { 566 smbios_entries_len = sizeof(uint16_t); 567 smbios_entries = g_malloc0(smbios_entries_len); 568 } 569 smbios_entries = g_realloc(smbios_entries, smbios_entries_len + 570 sizeof(*field) + len); 571 field = (struct smbios_field *)(smbios_entries + smbios_entries_len); 572 field->header.type = SMBIOS_FIELD_ENTRY; 573 field->header.length = cpu_to_le16(sizeof(*field) + len); 574 575 field->type = type; 576 field->offset = cpu_to_le16(offset); 577 memcpy(field->data, data, len); 578 579 smbios_entries_len += sizeof(*field) + len; 580 (*(uint16_t *)smbios_entries) = 581 cpu_to_le16(le16_to_cpu(*(uint16_t *)smbios_entries) + 1); 582 } 583 584 static void smbios_maybe_add_str(int type, int offset, const char *data) 585 { 586 if (data) { 587 smbios_add_field(type, offset, data, strlen(data) + 1); 588 } 589 } 590 591 static void smbios_build_type_0_fields(void) 592 { 593 smbios_maybe_add_str(0, offsetof(struct smbios_type_0, vendor_str), 594 smbios_type0.vendor); 595 smbios_maybe_add_str(0, offsetof(struct smbios_type_0, bios_version_str), 596 smbios_type0.version); 597 smbios_maybe_add_str(0, offsetof(struct smbios_type_0, 598 bios_release_date_str), 599 smbios_type0.date); 600 if (smbios_type0.have_major_minor) { 601 smbios_add_field(0, offsetof(struct smbios_type_0, 602 system_bios_major_release), 603 &smbios_type0.major, 1); 604 smbios_add_field(0, offsetof(struct smbios_type_0, 605 system_bios_minor_release), 606 &smbios_type0.minor, 1); 607 } 608 } 609 610 static void smbios_build_type_1_fields(void) 611 { 612 smbios_maybe_add_str(1, offsetof(struct smbios_type_1, manufacturer_str), 613 smbios_type1.manufacturer); 614 smbios_maybe_add_str(1, offsetof(struct smbios_type_1, product_name_str), 615 smbios_type1.product); 616 smbios_maybe_add_str(1, offsetof(struct smbios_type_1, version_str), 617 smbios_type1.version); 618 smbios_maybe_add_str(1, offsetof(struct smbios_type_1, serial_number_str), 619 smbios_type1.serial); 620 smbios_maybe_add_str(1, offsetof(struct smbios_type_1, sku_number_str), 621 smbios_type1.sku); 622 smbios_maybe_add_str(1, offsetof(struct smbios_type_1, family_str), 623 smbios_type1.family); 624 if (qemu_uuid_set) { 625 /* We don't encode the UUID in the "wire format" here because this 626 * function is for legacy mode and needs to keep the guest ABI, and 627 * because we don't know what's the SMBIOS version advertised by the 628 * BIOS. 629 */ 630 smbios_add_field(1, offsetof(struct smbios_type_1, uuid), 631 &qemu_uuid, 16); 632 } 633 } 634 635 uint8_t *smbios_get_table_legacy(size_t *length) 636 { 637 int i; 638 size_t usr_offset; 639 640 /* also complain if fields were given for types > 1 */ 641 if (find_next_bit(smbios_have_fields_bitmap, 642 SMBIOS_MAX_TYPE + 1, 2) < SMBIOS_MAX_TYPE + 1) { 643 error_report("can't process fields for smbios " 644 "types > 1 on machine versions < 2.1!"); 645 exit(1); 646 } 647 648 if (test_bit(4, smbios_have_binfile_bitmap)) { 649 error_report("can't process table for smbios " 650 "type 4 on machine versions < 2.1!"); 651 exit(1); 652 } 653 654 g_free(smbios_entries); 655 smbios_entries_len = sizeof(uint16_t); 656 smbios_entries = g_malloc0(smbios_entries_len); 657 658 for (i = 0, usr_offset = 0; usr_blobs_sizes && i < usr_blobs_sizes->len; 659 i++) 660 { 661 struct smbios_table *table; 662 struct smbios_structure_header *header; 663 size_t size = g_array_index(usr_blobs_sizes, size_t, i); 664 665 header = (struct smbios_structure_header *)(usr_blobs + usr_offset); 666 smbios_entries = g_realloc(smbios_entries, smbios_entries_len + 667 size + sizeof(*table)); 668 table = (struct smbios_table *)(smbios_entries + smbios_entries_len); 669 table->header.type = SMBIOS_TABLE_ENTRY; 670 table->header.length = cpu_to_le16(sizeof(*table) + size); 671 memcpy(table->data, header, size); 672 smbios_entries_len += sizeof(*table) + size; 673 (*(uint16_t *)smbios_entries) = 674 cpu_to_le16(le16_to_cpu(*(uint16_t *)smbios_entries) + 1); 675 usr_offset += size; 676 } 677 678 smbios_build_type_0_fields(); 679 smbios_build_type_1_fields(); 680 smbios_validate_table(); 681 *length = smbios_entries_len; 682 return smbios_entries; 683 } 684 /* end: legacy setup functions for <= 2.0 machines */ 685 686 687 bool smbios_skip_table(uint8_t type, bool required_table) 688 { 689 if (test_bit(type, smbios_have_binfile_bitmap)) { 690 return true; /* user provided their own binary blob(s) */ 691 } 692 if (test_bit(type, smbios_have_fields_bitmap)) { 693 return false; /* user provided fields via command line */ 694 } 695 if (smbios_have_defaults && required_table) { 696 return false; /* we're building tables, and this one's required */ 697 } 698 return true; 699 } 700 701 #define T0_BASE 0x000 702 #define T1_BASE 0x100 703 #define T2_BASE 0x200 704 #define T3_BASE 0x300 705 #define T4_BASE 0x400 706 #define T9_BASE 0x900 707 #define T11_BASE 0xe00 708 709 #define T16_BASE 0x1000 710 #define T17_BASE 0x1100 711 #define T19_BASE 0x1300 712 #define T32_BASE 0x2000 713 #define T41_BASE 0x2900 714 #define T127_BASE 0x7F00 715 716 static void smbios_build_type_0_table(void) 717 { 718 SMBIOS_BUILD_TABLE_PRE(0, T0_BASE, false); /* optional, leave up to BIOS */ 719 720 SMBIOS_TABLE_SET_STR(0, vendor_str, smbios_type0.vendor); 721 SMBIOS_TABLE_SET_STR(0, bios_version_str, smbios_type0.version); 722 723 t->bios_starting_address_segment = cpu_to_le16(0xE800); /* from SeaBIOS */ 724 725 SMBIOS_TABLE_SET_STR(0, bios_release_date_str, smbios_type0.date); 726 727 t->bios_rom_size = 0; /* hardcoded in SeaBIOS with FIXME comment */ 728 729 t->bios_characteristics = cpu_to_le64(0x08); /* Not supported */ 730 t->bios_characteristics_extension_bytes[0] = 0; 731 t->bios_characteristics_extension_bytes[1] = 0x14; /* TCD/SVVP | VM */ 732 if (smbios_type0.uefi) { 733 t->bios_characteristics_extension_bytes[1] |= 0x08; /* |= UEFI */ 734 } 735 736 if (smbios_type0.have_major_minor) { 737 t->system_bios_major_release = smbios_type0.major; 738 t->system_bios_minor_release = smbios_type0.minor; 739 } else { 740 t->system_bios_major_release = 0; 741 t->system_bios_minor_release = 0; 742 } 743 744 /* hardcoded in SeaBIOS */ 745 t->embedded_controller_major_release = 0xFF; 746 t->embedded_controller_minor_release = 0xFF; 747 748 SMBIOS_BUILD_TABLE_POST; 749 } 750 751 /* Encode UUID from the big endian encoding described on RFC4122 to the wire 752 * format specified by SMBIOS version 2.6. 753 */ 754 static void smbios_encode_uuid(struct smbios_uuid *uuid, QemuUUID *in) 755 { 756 memcpy(uuid, in, 16); 757 if (smbios_uuid_encoded) { 758 uuid->time_low = bswap32(uuid->time_low); 759 uuid->time_mid = bswap16(uuid->time_mid); 760 uuid->time_hi_and_version = bswap16(uuid->time_hi_and_version); 761 } 762 } 763 764 static void smbios_build_type_1_table(void) 765 { 766 SMBIOS_BUILD_TABLE_PRE(1, T1_BASE, true); /* required */ 767 768 SMBIOS_TABLE_SET_STR(1, manufacturer_str, smbios_type1.manufacturer); 769 SMBIOS_TABLE_SET_STR(1, product_name_str, smbios_type1.product); 770 SMBIOS_TABLE_SET_STR(1, version_str, smbios_type1.version); 771 SMBIOS_TABLE_SET_STR(1, serial_number_str, smbios_type1.serial); 772 if (qemu_uuid_set) { 773 smbios_encode_uuid(&t->uuid, &qemu_uuid); 774 } else { 775 memset(&t->uuid, 0, 16); 776 } 777 t->wake_up_type = 0x06; /* power switch */ 778 SMBIOS_TABLE_SET_STR(1, sku_number_str, smbios_type1.sku); 779 SMBIOS_TABLE_SET_STR(1, family_str, smbios_type1.family); 780 781 SMBIOS_BUILD_TABLE_POST; 782 } 783 784 static void smbios_build_type_2_table(void) 785 { 786 SMBIOS_BUILD_TABLE_PRE(2, T2_BASE, false); /* optional */ 787 788 SMBIOS_TABLE_SET_STR(2, manufacturer_str, type2.manufacturer); 789 SMBIOS_TABLE_SET_STR(2, product_str, type2.product); 790 SMBIOS_TABLE_SET_STR(2, version_str, type2.version); 791 SMBIOS_TABLE_SET_STR(2, serial_number_str, type2.serial); 792 SMBIOS_TABLE_SET_STR(2, asset_tag_number_str, type2.asset); 793 t->feature_flags = 0x01; /* Motherboard */ 794 SMBIOS_TABLE_SET_STR(2, location_str, type2.location); 795 t->chassis_handle = cpu_to_le16(0x300); /* Type 3 (System enclosure) */ 796 t->board_type = 0x0A; /* Motherboard */ 797 t->contained_element_count = 0; 798 799 SMBIOS_BUILD_TABLE_POST; 800 } 801 802 static void smbios_build_type_3_table(void) 803 { 804 SMBIOS_BUILD_TABLE_PRE(3, T3_BASE, true); /* required */ 805 806 SMBIOS_TABLE_SET_STR(3, manufacturer_str, type3.manufacturer); 807 t->type = 0x01; /* Other */ 808 SMBIOS_TABLE_SET_STR(3, version_str, type3.version); 809 SMBIOS_TABLE_SET_STR(3, serial_number_str, type3.serial); 810 SMBIOS_TABLE_SET_STR(3, asset_tag_number_str, type3.asset); 811 t->boot_up_state = 0x03; /* Safe */ 812 t->power_supply_state = 0x03; /* Safe */ 813 t->thermal_state = 0x03; /* Safe */ 814 t->security_status = 0x02; /* Unknown */ 815 t->oem_defined = cpu_to_le32(0); 816 t->height = 0; 817 t->number_of_power_cords = 0; 818 t->contained_element_count = 0; 819 t->contained_element_record_length = 0; 820 SMBIOS_TABLE_SET_STR(3, sku_number_str, type3.sku); 821 822 SMBIOS_BUILD_TABLE_POST; 823 } 824 825 static void smbios_build_type_4_table(MachineState *ms, unsigned instance) 826 { 827 char sock_str[128]; 828 size_t tbl_len = SMBIOS_TYPE_4_LEN_V28; 829 unsigned threads_per_socket; 830 unsigned cores_per_socket; 831 832 if (smbios_ep_type == SMBIOS_ENTRY_POINT_TYPE_64) { 833 tbl_len = SMBIOS_TYPE_4_LEN_V30; 834 } 835 836 SMBIOS_BUILD_TABLE_PRE_SIZE(4, T4_BASE + instance, 837 true, tbl_len); /* required */ 838 839 snprintf(sock_str, sizeof(sock_str), "%s%2x", type4.sock_pfx, instance); 840 SMBIOS_TABLE_SET_STR(4, socket_designation_str, sock_str); 841 t->processor_type = 0x03; /* CPU */ 842 t->processor_family = 0xfe; /* use Processor Family 2 field */ 843 SMBIOS_TABLE_SET_STR(4, processor_manufacturer_str, type4.manufacturer); 844 if (type4.processor_id == 0) { 845 t->processor_id[0] = cpu_to_le32(smbios_cpuid_version); 846 t->processor_id[1] = cpu_to_le32(smbios_cpuid_features); 847 } else { 848 t->processor_id[0] = cpu_to_le32((uint32_t)type4.processor_id); 849 t->processor_id[1] = cpu_to_le32(type4.processor_id >> 32); 850 } 851 SMBIOS_TABLE_SET_STR(4, processor_version_str, type4.version); 852 t->voltage = 0; 853 t->external_clock = cpu_to_le16(0); /* Unknown */ 854 t->max_speed = cpu_to_le16(type4.max_speed); 855 t->current_speed = cpu_to_le16(type4.current_speed); 856 t->status = 0x41; /* Socket populated, CPU enabled */ 857 t->processor_upgrade = 0x01; /* Other */ 858 t->l1_cache_handle = cpu_to_le16(0xFFFF); /* N/A */ 859 t->l2_cache_handle = cpu_to_le16(0xFFFF); /* N/A */ 860 t->l3_cache_handle = cpu_to_le16(0xFFFF); /* N/A */ 861 SMBIOS_TABLE_SET_STR(4, serial_number_str, type4.serial); 862 SMBIOS_TABLE_SET_STR(4, asset_tag_number_str, type4.asset); 863 SMBIOS_TABLE_SET_STR(4, part_number_str, type4.part); 864 865 threads_per_socket = machine_topo_get_threads_per_socket(ms); 866 cores_per_socket = machine_topo_get_cores_per_socket(ms); 867 868 t->core_count = (cores_per_socket > 255) ? 0xFF : cores_per_socket; 869 t->core_enabled = t->core_count; 870 871 t->thread_count = (threads_per_socket > 255) ? 0xFF : threads_per_socket; 872 873 t->processor_characteristics = cpu_to_le16(0x02); /* Unknown */ 874 t->processor_family2 = cpu_to_le16(type4.processor_family); 875 876 if (tbl_len == SMBIOS_TYPE_4_LEN_V30) { 877 t->core_count2 = t->core_enabled2 = cpu_to_le16(cores_per_socket); 878 t->thread_count2 = cpu_to_le16(threads_per_socket); 879 } 880 881 SMBIOS_BUILD_TABLE_POST; 882 smbios_type4_count++; 883 } 884 885 static void smbios_build_type_8_table(void) 886 { 887 unsigned instance = 0; 888 struct type8_instance *t8; 889 890 QTAILQ_FOREACH(t8, &type8, next) { 891 SMBIOS_BUILD_TABLE_PRE(8, T0_BASE + instance, true); 892 893 SMBIOS_TABLE_SET_STR(8, internal_reference_str, t8->internal_reference); 894 SMBIOS_TABLE_SET_STR(8, external_reference_str, t8->external_reference); 895 /* most vendors seem to set this to None */ 896 t->internal_connector_type = 0x0; 897 t->external_connector_type = t8->connector_type; 898 t->port_type = t8->port_type; 899 900 SMBIOS_BUILD_TABLE_POST; 901 instance++; 902 } 903 } 904 905 static void smbios_build_type_9_table(Error **errp) 906 { 907 unsigned instance = 0; 908 struct type9_instance *t9; 909 910 QTAILQ_FOREACH(t9, &type9, next) { 911 SMBIOS_BUILD_TABLE_PRE(9, T9_BASE + instance, true); 912 913 SMBIOS_TABLE_SET_STR(9, slot_designation, t9->slot_designation); 914 t->slot_type = t9->slot_type; 915 t->slot_data_bus_width = t9->slot_data_bus_width; 916 t->current_usage = t9->current_usage; 917 t->slot_length = t9->slot_length; 918 t->slot_id = t9->slot_id; 919 t->slot_characteristics1 = t9->slot_characteristics1; 920 t->slot_characteristics2 = t9->slot_characteristics2; 921 922 if (t9->pcidev) { 923 PCIDevice *pdev = NULL; 924 int rc = pci_qdev_find_device(t9->pcidev, &pdev); 925 if (rc != 0) { 926 error_setg(errp, 927 "No PCI device %s for SMBIOS type 9 entry %s", 928 t9->pcidev, t9->slot_designation); 929 return; 930 } 931 /* 932 * We only handle the case were the device is attached to 933 * the PCI root bus. The general case is more complex as 934 * bridges are enumerated later and the table would need 935 * to be updated at this moment. 936 */ 937 if (!pci_bus_is_root(pci_get_bus(pdev))) { 938 error_setg(errp, 939 "Cannot create type 9 entry for PCI device %s: " 940 "not attached to the root bus", 941 t9->pcidev); 942 return; 943 } 944 t->segment_group_number = cpu_to_le16(0); 945 t->bus_number = pci_dev_bus_num(pdev); 946 t->device_number = pdev->devfn; 947 } else { 948 /* 949 * Per SMBIOS spec, For slots that are not of the PCI, AGP, PCI-X, 950 * or PCI-Express type that do not have bus/device/function 951 * information, 0FFh should be populated in the fields of Segment 952 * Group Number, Bus Number, Device/Function Number. 953 */ 954 t->segment_group_number = 0xff; 955 t->bus_number = 0xff; 956 t->device_number = 0xff; 957 } 958 959 SMBIOS_BUILD_TABLE_POST; 960 instance++; 961 } 962 } 963 964 static void smbios_build_type_11_table(void) 965 { 966 char count_str[128]; 967 size_t i; 968 969 if (type11.nvalues == 0) { 970 return; 971 } 972 973 SMBIOS_BUILD_TABLE_PRE(11, T11_BASE, true); /* required */ 974 975 snprintf(count_str, sizeof(count_str), "%zu", type11.nvalues); 976 t->count = type11.nvalues; 977 978 for (i = 0; i < type11.nvalues; i++) { 979 SMBIOS_TABLE_SET_STR_LIST(11, type11.values[i]); 980 g_free(type11.values[i]); 981 type11.values[i] = NULL; 982 } 983 984 SMBIOS_BUILD_TABLE_POST; 985 } 986 987 #define MAX_T16_STD_SZ 0x80000000 /* 2T in Kilobytes */ 988 989 static void smbios_build_type_16_table(unsigned dimm_cnt) 990 { 991 uint64_t size_kb; 992 993 SMBIOS_BUILD_TABLE_PRE(16, T16_BASE, true); /* required */ 994 995 t->location = 0x01; /* Other */ 996 t->use = 0x03; /* System memory */ 997 t->error_correction = 0x06; /* Multi-bit ECC (for Microsoft, per SeaBIOS) */ 998 size_kb = QEMU_ALIGN_UP(current_machine->ram_size, KiB) / KiB; 999 if (size_kb < MAX_T16_STD_SZ) { 1000 t->maximum_capacity = cpu_to_le32(size_kb); 1001 t->extended_maximum_capacity = cpu_to_le64(0); 1002 } else { 1003 t->maximum_capacity = cpu_to_le32(MAX_T16_STD_SZ); 1004 t->extended_maximum_capacity = cpu_to_le64(current_machine->ram_size); 1005 } 1006 t->memory_error_information_handle = cpu_to_le16(0xFFFE); /* Not provided */ 1007 t->number_of_memory_devices = cpu_to_le16(dimm_cnt); 1008 1009 SMBIOS_BUILD_TABLE_POST; 1010 } 1011 1012 #define MAX_T17_STD_SZ 0x7FFF /* (32G - 1M), in Megabytes */ 1013 #define MAX_T17_EXT_SZ 0x80000000 /* 2P, in Megabytes */ 1014 1015 static void smbios_build_type_17_table(unsigned instance, uint64_t size) 1016 { 1017 char loc_str[128]; 1018 uint64_t size_mb; 1019 1020 SMBIOS_BUILD_TABLE_PRE(17, T17_BASE + instance, true); /* required */ 1021 1022 t->physical_memory_array_handle = cpu_to_le16(0x1000); /* Type 16 above */ 1023 t->memory_error_information_handle = cpu_to_le16(0xFFFE); /* Not provided */ 1024 t->total_width = cpu_to_le16(0xFFFF); /* Unknown */ 1025 t->data_width = cpu_to_le16(0xFFFF); /* Unknown */ 1026 size_mb = QEMU_ALIGN_UP(size, MiB) / MiB; 1027 if (size_mb < MAX_T17_STD_SZ) { 1028 t->size = cpu_to_le16(size_mb); 1029 t->extended_size = cpu_to_le32(0); 1030 } else { 1031 assert(size_mb < MAX_T17_EXT_SZ); 1032 t->size = cpu_to_le16(MAX_T17_STD_SZ); 1033 t->extended_size = cpu_to_le32(size_mb); 1034 } 1035 t->form_factor = 0x09; /* DIMM */ 1036 t->device_set = 0; /* Not in a set */ 1037 snprintf(loc_str, sizeof(loc_str), "%s %d", type17.loc_pfx, instance); 1038 SMBIOS_TABLE_SET_STR(17, device_locator_str, loc_str); 1039 SMBIOS_TABLE_SET_STR(17, bank_locator_str, type17.bank); 1040 t->memory_type = 0x07; /* RAM */ 1041 t->type_detail = cpu_to_le16(0x02); /* Other */ 1042 t->speed = cpu_to_le16(type17.speed); 1043 SMBIOS_TABLE_SET_STR(17, manufacturer_str, type17.manufacturer); 1044 SMBIOS_TABLE_SET_STR(17, serial_number_str, type17.serial); 1045 SMBIOS_TABLE_SET_STR(17, asset_tag_number_str, type17.asset); 1046 SMBIOS_TABLE_SET_STR(17, part_number_str, type17.part); 1047 t->attributes = 0; /* Unknown */ 1048 t->configured_clock_speed = t->speed; /* reuse value for max speed */ 1049 t->minimum_voltage = cpu_to_le16(0); /* Unknown */ 1050 t->maximum_voltage = cpu_to_le16(0); /* Unknown */ 1051 t->configured_voltage = cpu_to_le16(0); /* Unknown */ 1052 1053 SMBIOS_BUILD_TABLE_POST; 1054 } 1055 1056 static void smbios_build_type_19_table(unsigned instance, unsigned offset, 1057 uint64_t start, uint64_t size) 1058 { 1059 uint64_t end, start_kb, end_kb; 1060 1061 SMBIOS_BUILD_TABLE_PRE(19, T19_BASE + offset + instance, 1062 true); /* required */ 1063 1064 end = start + size - 1; 1065 assert(end > start); 1066 start_kb = start / KiB; 1067 end_kb = end / KiB; 1068 if (start_kb < UINT32_MAX && end_kb < UINT32_MAX) { 1069 t->starting_address = cpu_to_le32(start_kb); 1070 t->ending_address = cpu_to_le32(end_kb); 1071 t->extended_starting_address = 1072 t->extended_ending_address = cpu_to_le64(0); 1073 } else { 1074 t->starting_address = t->ending_address = cpu_to_le32(UINT32_MAX); 1075 t->extended_starting_address = cpu_to_le64(start); 1076 t->extended_ending_address = cpu_to_le64(end); 1077 } 1078 t->memory_array_handle = cpu_to_le16(0x1000); /* Type 16 above */ 1079 t->partition_width = 1; /* One device per row */ 1080 1081 SMBIOS_BUILD_TABLE_POST; 1082 } 1083 1084 static void smbios_build_type_32_table(void) 1085 { 1086 SMBIOS_BUILD_TABLE_PRE(32, T32_BASE, true); /* required */ 1087 1088 memset(t->reserved, 0, 6); 1089 t->boot_status = 0; /* No errors detected */ 1090 1091 SMBIOS_BUILD_TABLE_POST; 1092 } 1093 1094 static void smbios_build_type_41_table(Error **errp) 1095 { 1096 unsigned instance = 0; 1097 struct type41_instance *t41; 1098 1099 QTAILQ_FOREACH(t41, &type41, next) { 1100 SMBIOS_BUILD_TABLE_PRE(41, T41_BASE + instance, true); 1101 1102 SMBIOS_TABLE_SET_STR(41, reference_designation_str, t41->designation); 1103 t->device_type = t41->kind; 1104 t->device_type_instance = t41->instance; 1105 t->segment_group_number = cpu_to_le16(0); 1106 t->bus_number = 0; 1107 t->device_number = 0; 1108 1109 if (t41->pcidev) { 1110 PCIDevice *pdev = NULL; 1111 int rc = pci_qdev_find_device(t41->pcidev, &pdev); 1112 if (rc != 0) { 1113 error_setg(errp, 1114 "No PCI device %s for SMBIOS type 41 entry %s", 1115 t41->pcidev, t41->designation); 1116 return; 1117 } 1118 /* 1119 * We only handle the case were the device is attached to 1120 * the PCI root bus. The general case is more complex as 1121 * bridges are enumerated later and the table would need 1122 * to be updated at this moment. 1123 */ 1124 if (!pci_bus_is_root(pci_get_bus(pdev))) { 1125 error_setg(errp, 1126 "Cannot create type 41 entry for PCI device %s: " 1127 "not attached to the root bus", 1128 t41->pcidev); 1129 return; 1130 } 1131 t->segment_group_number = cpu_to_le16(0); 1132 t->bus_number = pci_dev_bus_num(pdev); 1133 t->device_number = pdev->devfn; 1134 } 1135 1136 SMBIOS_BUILD_TABLE_POST; 1137 instance++; 1138 } 1139 } 1140 1141 static void smbios_build_type_127_table(void) 1142 { 1143 SMBIOS_BUILD_TABLE_PRE(127, T127_BASE, true); /* required */ 1144 SMBIOS_BUILD_TABLE_POST; 1145 } 1146 1147 void smbios_set_cpuid(uint32_t version, uint32_t features) 1148 { 1149 smbios_cpuid_version = version; 1150 smbios_cpuid_features = features; 1151 } 1152 1153 #define SMBIOS_SET_DEFAULT(field, value) \ 1154 if (!field) { \ 1155 field = value; \ 1156 } 1157 1158 void smbios_set_default_processor_family(uint16_t processor_family) 1159 { 1160 if (type4.processor_family <= 0x01) { 1161 type4.processor_family = processor_family; 1162 } 1163 } 1164 1165 void smbios_set_defaults(const char *manufacturer, const char *product, 1166 const char *version, 1167 bool uuid_encoded, SmbiosEntryPointType ep_type) 1168 { 1169 smbios_have_defaults = true; 1170 smbios_uuid_encoded = uuid_encoded; 1171 smbios_ep_type = ep_type; 1172 1173 SMBIOS_SET_DEFAULT(smbios_type1.manufacturer, manufacturer); 1174 SMBIOS_SET_DEFAULT(smbios_type1.product, product); 1175 SMBIOS_SET_DEFAULT(smbios_type1.version, version); 1176 SMBIOS_SET_DEFAULT(type2.manufacturer, manufacturer); 1177 SMBIOS_SET_DEFAULT(type2.product, product); 1178 SMBIOS_SET_DEFAULT(type2.version, version); 1179 SMBIOS_SET_DEFAULT(type3.manufacturer, manufacturer); 1180 SMBIOS_SET_DEFAULT(type3.version, version); 1181 SMBIOS_SET_DEFAULT(type4.sock_pfx, "CPU"); 1182 SMBIOS_SET_DEFAULT(type4.manufacturer, manufacturer); 1183 SMBIOS_SET_DEFAULT(type4.version, version); 1184 SMBIOS_SET_DEFAULT(type17.loc_pfx, "DIMM"); 1185 SMBIOS_SET_DEFAULT(type17.manufacturer, manufacturer); 1186 } 1187 1188 static void smbios_entry_point_setup(void) 1189 { 1190 switch (smbios_ep_type) { 1191 case SMBIOS_ENTRY_POINT_TYPE_32: 1192 memcpy(ep.ep21.anchor_string, "_SM_", 4); 1193 memcpy(ep.ep21.intermediate_anchor_string, "_DMI_", 5); 1194 ep.ep21.length = sizeof(struct smbios_21_entry_point); 1195 ep.ep21.entry_point_revision = 0; /* formatted_area reserved */ 1196 memset(ep.ep21.formatted_area, 0, 5); 1197 1198 /* compliant with smbios spec v2.8 */ 1199 ep.ep21.smbios_major_version = 2; 1200 ep.ep21.smbios_minor_version = 8; 1201 ep.ep21.smbios_bcd_revision = 0x28; 1202 1203 /* set during table construction, but BIOS may override: */ 1204 ep.ep21.structure_table_length = cpu_to_le16(smbios_tables_len); 1205 ep.ep21.max_structure_size = cpu_to_le16(smbios_table_max); 1206 ep.ep21.number_of_structures = cpu_to_le16(smbios_table_cnt); 1207 1208 /* BIOS must recalculate */ 1209 ep.ep21.checksum = 0; 1210 ep.ep21.intermediate_checksum = 0; 1211 ep.ep21.structure_table_address = cpu_to_le32(0); 1212 1213 break; 1214 case SMBIOS_ENTRY_POINT_TYPE_64: 1215 memcpy(ep.ep30.anchor_string, "_SM3_", 5); 1216 ep.ep30.length = sizeof(struct smbios_30_entry_point); 1217 ep.ep30.entry_point_revision = 1; 1218 ep.ep30.reserved = 0; 1219 1220 /* compliant with smbios spec 3.0 */ 1221 ep.ep30.smbios_major_version = 3; 1222 ep.ep30.smbios_minor_version = 0; 1223 ep.ep30.smbios_doc_rev = 0; 1224 1225 /* set during table construct, but BIOS might override */ 1226 ep.ep30.structure_table_max_size = cpu_to_le32(smbios_tables_len); 1227 1228 /* BIOS must recalculate */ 1229 ep.ep30.checksum = 0; 1230 ep.ep30.structure_table_address = cpu_to_le64(0); 1231 1232 break; 1233 default: 1234 abort(); 1235 break; 1236 } 1237 } 1238 1239 void smbios_get_tables(MachineState *ms, 1240 const struct smbios_phys_mem_area *mem_array, 1241 const unsigned int mem_array_size, 1242 uint8_t **tables, size_t *tables_len, 1243 uint8_t **anchor, size_t *anchor_len, 1244 Error **errp) 1245 { 1246 unsigned i, dimm_cnt, offset; 1247 1248 g_free(smbios_tables); 1249 smbios_tables = g_memdup2(usr_blobs, usr_blobs_len); 1250 smbios_tables_len = usr_blobs_len; 1251 smbios_table_max = usr_table_max; 1252 smbios_table_cnt = usr_table_cnt; 1253 1254 smbios_build_type_0_table(); 1255 smbios_build_type_1_table(); 1256 smbios_build_type_2_table(); 1257 smbios_build_type_3_table(); 1258 1259 assert(ms->smp.sockets >= 1); 1260 1261 for (i = 0; i < ms->smp.sockets; i++) { 1262 smbios_build_type_4_table(ms, i); 1263 } 1264 1265 smbios_build_type_8_table(); 1266 smbios_build_type_9_table(errp); 1267 smbios_build_type_11_table(); 1268 1269 #define MAX_DIMM_SZ (16 * GiB) 1270 #define GET_DIMM_SZ ((i < dimm_cnt - 1) ? MAX_DIMM_SZ \ 1271 : ((current_machine->ram_size - 1) % MAX_DIMM_SZ) + 1) 1272 1273 dimm_cnt = QEMU_ALIGN_UP(current_machine->ram_size, MAX_DIMM_SZ) / 1274 MAX_DIMM_SZ; 1275 1276 /* 1277 * The offset determines if we need to keep additional space between 1278 * table 17 and table 19 header handle numbers so that they do 1279 * not overlap. For example, for a VM with larger than 8 TB guest 1280 * memory and DIMM like chunks of 16 GiB, the default space between 1281 * the two tables (T19_BASE - T17_BASE = 512) is not enough. 1282 */ 1283 offset = (dimm_cnt > (T19_BASE - T17_BASE)) ? \ 1284 dimm_cnt - (T19_BASE - T17_BASE) : 0; 1285 1286 smbios_build_type_16_table(dimm_cnt); 1287 1288 for (i = 0; i < dimm_cnt; i++) { 1289 smbios_build_type_17_table(i, GET_DIMM_SZ); 1290 } 1291 1292 for (i = 0; i < mem_array_size; i++) { 1293 smbios_build_type_19_table(i, offset, mem_array[i].address, 1294 mem_array[i].length); 1295 } 1296 1297 /* 1298 * make sure 16 bit handle numbers in the headers of tables 19 1299 * and 32 do not overlap. 1300 */ 1301 assert((mem_array_size + offset) < (T32_BASE - T19_BASE)); 1302 1303 smbios_build_type_32_table(); 1304 smbios_build_type_38_table(); 1305 smbios_build_type_41_table(errp); 1306 smbios_build_type_127_table(); 1307 1308 smbios_check_type4_count(ms->smp.sockets); 1309 smbios_validate_table(); 1310 smbios_entry_point_setup(); 1311 1312 /* return tables blob and entry point (anchor), and their sizes */ 1313 *tables = smbios_tables; 1314 *tables_len = smbios_tables_len; 1315 *anchor = (uint8_t *)&ep; 1316 1317 /* calculate length based on anchor string */ 1318 if (!strncmp((char *)&ep, "_SM_", 4)) { 1319 *anchor_len = sizeof(struct smbios_21_entry_point); 1320 } else if (!strncmp((char *)&ep, "_SM3_", 5)) { 1321 *anchor_len = sizeof(struct smbios_30_entry_point); 1322 } else { 1323 abort(); 1324 } 1325 } 1326 1327 static void save_opt(const char **dest, QemuOpts *opts, const char *name) 1328 { 1329 const char *val = qemu_opt_get(opts, name); 1330 1331 if (val) { 1332 *dest = val; 1333 } 1334 } 1335 1336 1337 struct opt_list { 1338 size_t *ndest; 1339 char ***dest; 1340 }; 1341 1342 static int save_opt_one(void *opaque, 1343 const char *name, const char *value, 1344 Error **errp) 1345 { 1346 struct opt_list *opt = opaque; 1347 1348 if (g_str_equal(name, "path")) { 1349 g_autoptr(GByteArray) data = g_byte_array_new(); 1350 g_autofree char *buf = g_new(char, 4096); 1351 ssize_t ret; 1352 int fd = qemu_open(value, O_RDONLY, errp); 1353 if (fd < 0) { 1354 return -1; 1355 } 1356 1357 while (1) { 1358 ret = read(fd, buf, 4096); 1359 if (ret == 0) { 1360 break; 1361 } 1362 if (ret < 0) { 1363 error_setg(errp, "Unable to read from %s: %s", 1364 value, strerror(errno)); 1365 qemu_close(fd); 1366 return -1; 1367 } 1368 if (memchr(buf, '\0', ret)) { 1369 error_setg(errp, "NUL in OEM strings value in %s", value); 1370 qemu_close(fd); 1371 return -1; 1372 } 1373 g_byte_array_append(data, (guint8 *)buf, ret); 1374 } 1375 1376 qemu_close(fd); 1377 1378 *opt->dest = g_renew(char *, *opt->dest, (*opt->ndest) + 1); 1379 (*opt->dest)[*opt->ndest] = (char *)g_byte_array_free(data, FALSE); 1380 (*opt->ndest)++; 1381 data = NULL; 1382 } else if (g_str_equal(name, "value")) { 1383 *opt->dest = g_renew(char *, *opt->dest, (*opt->ndest) + 1); 1384 (*opt->dest)[*opt->ndest] = g_strdup(value); 1385 (*opt->ndest)++; 1386 } else if (!g_str_equal(name, "type")) { 1387 error_setg(errp, "Unexpected option %s", name); 1388 return -1; 1389 } 1390 1391 return 0; 1392 } 1393 1394 static bool save_opt_list(size_t *ndest, char ***dest, QemuOpts *opts, 1395 Error **errp) 1396 { 1397 struct opt_list opt = { 1398 ndest, dest, 1399 }; 1400 if (!qemu_opt_foreach(opts, save_opt_one, &opt, errp)) { 1401 return false; 1402 } 1403 return true; 1404 } 1405 1406 static void smbios_add_usr_blob_size(size_t size) 1407 { 1408 if (!usr_blobs_sizes) { 1409 usr_blobs_sizes = g_array_new(false, false, sizeof(size_t)); 1410 } 1411 g_array_append_val(usr_blobs_sizes, size); 1412 } 1413 1414 void smbios_entry_add(QemuOpts *opts, Error **errp) 1415 { 1416 const char *val; 1417 1418 val = qemu_opt_get(opts, "file"); 1419 if (val) { 1420 struct smbios_structure_header *header; 1421 size_t size; 1422 1423 if (!qemu_opts_validate(opts, qemu_smbios_file_opts, errp)) { 1424 return; 1425 } 1426 1427 size = get_image_size(val); 1428 if (size == -1 || size < sizeof(struct smbios_structure_header)) { 1429 error_setg(errp, "Cannot read SMBIOS file %s", val); 1430 return; 1431 } 1432 1433 /* 1434 * NOTE: standard double '\0' terminator expected, per smbios spec. 1435 * (except in legacy mode, where the second '\0' is implicit and 1436 * will be inserted by the BIOS). 1437 */ 1438 usr_blobs = g_realloc(usr_blobs, usr_blobs_len + size); 1439 header = (struct smbios_structure_header *)(usr_blobs + 1440 usr_blobs_len); 1441 1442 if (load_image_size(val, (uint8_t *)header, size) != size) { 1443 error_setg(errp, "Failed to load SMBIOS file %s", val); 1444 return; 1445 } 1446 1447 if (header->type <= SMBIOS_MAX_TYPE) { 1448 if (test_bit(header->type, smbios_have_fields_bitmap)) { 1449 error_setg(errp, 1450 "can't load type %d struct, fields already specified!", 1451 header->type); 1452 return; 1453 } 1454 set_bit(header->type, smbios_have_binfile_bitmap); 1455 } 1456 1457 if (header->type == 4) { 1458 smbios_type4_count++; 1459 } 1460 1461 /* 1462 * preserve blob size for legacy mode so it could build its 1463 * blobs flavor from 'usr_blobs' 1464 */ 1465 smbios_add_usr_blob_size(size); 1466 1467 usr_blobs_len += size; 1468 if (size > usr_table_max) { 1469 usr_table_max = size; 1470 } 1471 usr_table_cnt++; 1472 1473 return; 1474 } 1475 1476 val = qemu_opt_get(opts, "type"); 1477 if (val) { 1478 unsigned long type = strtoul(val, NULL, 0); 1479 1480 if (type > SMBIOS_MAX_TYPE) { 1481 error_setg(errp, "out of range!"); 1482 return; 1483 } 1484 1485 if (test_bit(type, smbios_have_binfile_bitmap)) { 1486 error_setg(errp, "can't add fields, binary file already loaded!"); 1487 return; 1488 } 1489 set_bit(type, smbios_have_fields_bitmap); 1490 1491 switch (type) { 1492 case 0: 1493 if (!qemu_opts_validate(opts, qemu_smbios_type0_opts, errp)) { 1494 return; 1495 } 1496 save_opt(&smbios_type0.vendor, opts, "vendor"); 1497 save_opt(&smbios_type0.version, opts, "version"); 1498 save_opt(&smbios_type0.date, opts, "date"); 1499 smbios_type0.uefi = qemu_opt_get_bool(opts, "uefi", false); 1500 1501 val = qemu_opt_get(opts, "release"); 1502 if (val) { 1503 if (sscanf(val, "%hhu.%hhu", &smbios_type0.major, 1504 &smbios_type0.minor) != 2) { 1505 error_setg(errp, "Invalid release"); 1506 return; 1507 } 1508 smbios_type0.have_major_minor = true; 1509 } 1510 return; 1511 case 1: 1512 if (!qemu_opts_validate(opts, qemu_smbios_type1_opts, errp)) { 1513 return; 1514 } 1515 save_opt(&smbios_type1.manufacturer, opts, "manufacturer"); 1516 save_opt(&smbios_type1.product, opts, "product"); 1517 save_opt(&smbios_type1.version, opts, "version"); 1518 save_opt(&smbios_type1.serial, opts, "serial"); 1519 save_opt(&smbios_type1.sku, opts, "sku"); 1520 save_opt(&smbios_type1.family, opts, "family"); 1521 1522 val = qemu_opt_get(opts, "uuid"); 1523 if (val) { 1524 if (qemu_uuid_parse(val, &qemu_uuid) != 0) { 1525 error_setg(errp, "Invalid UUID"); 1526 return; 1527 } 1528 qemu_uuid_set = true; 1529 } 1530 return; 1531 case 2: 1532 if (!qemu_opts_validate(opts, qemu_smbios_type2_opts, errp)) { 1533 return; 1534 } 1535 save_opt(&type2.manufacturer, opts, "manufacturer"); 1536 save_opt(&type2.product, opts, "product"); 1537 save_opt(&type2.version, opts, "version"); 1538 save_opt(&type2.serial, opts, "serial"); 1539 save_opt(&type2.asset, opts, "asset"); 1540 save_opt(&type2.location, opts, "location"); 1541 return; 1542 case 3: 1543 if (!qemu_opts_validate(opts, qemu_smbios_type3_opts, errp)) { 1544 return; 1545 } 1546 save_opt(&type3.manufacturer, opts, "manufacturer"); 1547 save_opt(&type3.version, opts, "version"); 1548 save_opt(&type3.serial, opts, "serial"); 1549 save_opt(&type3.asset, opts, "asset"); 1550 save_opt(&type3.sku, opts, "sku"); 1551 return; 1552 case 4: 1553 if (!qemu_opts_validate(opts, qemu_smbios_type4_opts, errp)) { 1554 return; 1555 } 1556 save_opt(&type4.sock_pfx, opts, "sock_pfx"); 1557 type4.processor_family = qemu_opt_get_number(opts, 1558 "processor-family", 1559 0x01 /* Other */); 1560 save_opt(&type4.manufacturer, opts, "manufacturer"); 1561 save_opt(&type4.version, opts, "version"); 1562 save_opt(&type4.serial, opts, "serial"); 1563 save_opt(&type4.asset, opts, "asset"); 1564 save_opt(&type4.part, opts, "part"); 1565 /* If the value is 0, it will take the value from the CPU model. */ 1566 type4.processor_id = qemu_opt_get_number(opts, "processor-id", 0); 1567 type4.max_speed = qemu_opt_get_number(opts, "max-speed", 1568 DEFAULT_CPU_SPEED); 1569 type4.current_speed = qemu_opt_get_number(opts, "current-speed", 1570 DEFAULT_CPU_SPEED); 1571 if (type4.max_speed > UINT16_MAX || 1572 type4.current_speed > UINT16_MAX) { 1573 error_setg(errp, "SMBIOS CPU speed is too large (> %d)", 1574 UINT16_MAX); 1575 } 1576 return; 1577 case 8: 1578 if (!qemu_opts_validate(opts, qemu_smbios_type8_opts, errp)) { 1579 return; 1580 } 1581 struct type8_instance *t8_i; 1582 t8_i = g_new0(struct type8_instance, 1); 1583 save_opt(&t8_i->internal_reference, opts, "internal_reference"); 1584 save_opt(&t8_i->external_reference, opts, "external_reference"); 1585 t8_i->connector_type = qemu_opt_get_number(opts, 1586 "connector_type", 0); 1587 t8_i->port_type = qemu_opt_get_number(opts, "port_type", 0); 1588 QTAILQ_INSERT_TAIL(&type8, t8_i, next); 1589 return; 1590 case 9: { 1591 if (!qemu_opts_validate(opts, qemu_smbios_type9_opts, errp)) { 1592 return; 1593 } 1594 struct type9_instance *t; 1595 t = g_new0(struct type9_instance, 1); 1596 save_opt(&t->slot_designation, opts, "slot_designation"); 1597 t->slot_type = qemu_opt_get_number(opts, "slot_type", 0); 1598 t->slot_data_bus_width = 1599 qemu_opt_get_number(opts, "slot_data_bus_width", 0); 1600 t->current_usage = qemu_opt_get_number(opts, "current_usage", 0); 1601 t->slot_length = qemu_opt_get_number(opts, "slot_length", 0); 1602 t->slot_id = qemu_opt_get_number(opts, "slot_id", 0); 1603 t->slot_characteristics1 = 1604 qemu_opt_get_number(opts, "slot_characteristics1", 0); 1605 t->slot_characteristics2 = 1606 qemu_opt_get_number(opts, "slot_characteristics2", 0); 1607 save_opt(&t->pcidev, opts, "pcidev"); 1608 QTAILQ_INSERT_TAIL(&type9, t, next); 1609 return; 1610 } 1611 case 11: 1612 if (!qemu_opts_validate(opts, qemu_smbios_type11_opts, errp)) { 1613 return; 1614 } 1615 if (!save_opt_list(&type11.nvalues, &type11.values, opts, errp)) { 1616 return; 1617 } 1618 return; 1619 case 17: 1620 if (!qemu_opts_validate(opts, qemu_smbios_type17_opts, errp)) { 1621 return; 1622 } 1623 save_opt(&type17.loc_pfx, opts, "loc_pfx"); 1624 save_opt(&type17.bank, opts, "bank"); 1625 save_opt(&type17.manufacturer, opts, "manufacturer"); 1626 save_opt(&type17.serial, opts, "serial"); 1627 save_opt(&type17.asset, opts, "asset"); 1628 save_opt(&type17.part, opts, "part"); 1629 type17.speed = qemu_opt_get_number(opts, "speed", 0); 1630 return; 1631 case 41: { 1632 struct type41_instance *t41_i; 1633 Error *local_err = NULL; 1634 1635 if (!qemu_opts_validate(opts, qemu_smbios_type41_opts, errp)) { 1636 return; 1637 } 1638 t41_i = g_new0(struct type41_instance, 1); 1639 save_opt(&t41_i->designation, opts, "designation"); 1640 t41_i->kind = qapi_enum_parse(&type41_kind_lookup, 1641 qemu_opt_get(opts, "kind"), 1642 0, &local_err) + 1; 1643 t41_i->kind |= 0x80; /* enabled */ 1644 if (local_err != NULL) { 1645 error_propagate(errp, local_err); 1646 g_free(t41_i); 1647 return; 1648 } 1649 t41_i->instance = qemu_opt_get_number(opts, "instance", 1); 1650 save_opt(&t41_i->pcidev, opts, "pcidev"); 1651 1652 QTAILQ_INSERT_TAIL(&type41, t41_i, next); 1653 return; 1654 } 1655 default: 1656 error_setg(errp, 1657 "Don't know how to build fields for SMBIOS type %ld", 1658 type); 1659 return; 1660 } 1661 } 1662 1663 error_setg(errp, "Must specify type= or file="); 1664 } 1665