127c7ca7eSbellard /* 227c7ca7eSbellard * SH-7750 memory-mapped registers 327c7ca7eSbellard * This file based on information provided in the following document: 427c7ca7eSbellard * "Hitachi SuperH (tm) RISC engine. SH7750 Series (SH7750, SH7750S) 527c7ca7eSbellard * Hardware Manual" 627c7ca7eSbellard * Document Number ADE-602-124C, Rev. 4.0, 4/21/00, Hitachi Ltd. 727c7ca7eSbellard * 827c7ca7eSbellard * Copyright (C) 2001 OKTET Ltd., St.-Petersburg, Russia 927c7ca7eSbellard * Author: Alexandra Kossovsky <sasha@oktet.ru> 1027c7ca7eSbellard * Victor V. Vengerov <vvv@oktet.ru> 1127c7ca7eSbellard * 1227c7ca7eSbellard * The license and distribution terms for this file may be 13ef95ca03SPhilippe Mathieu-Daudé * found in this file hereafter or at http://www.rtems.com/license/LICENSE. 14ef95ca03SPhilippe Mathieu-Daudé * 15ef95ca03SPhilippe Mathieu-Daudé * LICENSE INFORMATION 16ef95ca03SPhilippe Mathieu-Daudé * 17ef95ca03SPhilippe Mathieu-Daudé * RTEMS is free software; you can redistribute it and/or modify it under 18ef95ca03SPhilippe Mathieu-Daudé * terms of the GNU General Public License as published by the 19ef95ca03SPhilippe Mathieu-Daudé * Free Software Foundation; either version 2, or (at your option) any 20ef95ca03SPhilippe Mathieu-Daudé * later version. RTEMS is distributed in the hope that it will be useful, 21ef95ca03SPhilippe Mathieu-Daudé * but WITHOUT ANY WARRANTY; without even the implied warranty of 22ef95ca03SPhilippe Mathieu-Daudé * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 23ef95ca03SPhilippe Mathieu-Daudé * General Public License for more details. You should have received 24ef95ca03SPhilippe Mathieu-Daudé * a copy of the GNU General Public License along with RTEMS; see 25ef95ca03SPhilippe Mathieu-Daudé * file COPYING. If not, write to the Free Software Foundation, 675 26ef95ca03SPhilippe Mathieu-Daudé * Mass Ave, Cambridge, MA 02139, USA. 27ef95ca03SPhilippe Mathieu-Daudé * 28ef95ca03SPhilippe Mathieu-Daudé * As a special exception, including RTEMS header files in a file, 29ef95ca03SPhilippe Mathieu-Daudé * instantiating RTEMS generics or templates, or linking other files 30ef95ca03SPhilippe Mathieu-Daudé * with RTEMS objects to produce an executable application, does not 31ef95ca03SPhilippe Mathieu-Daudé * by itself cause the resulting executable application to be covered 32ef95ca03SPhilippe Mathieu-Daudé * by the GNU General Public License. This exception does not 33ef95ca03SPhilippe Mathieu-Daudé * however invalidate any other reasons why the executable file might be 34ef95ca03SPhilippe Mathieu-Daudé * covered by the GNU Public License. 3527c7ca7eSbellard * 3627c7ca7eSbellard * @(#) sh7750_regs.h,v 1.2.4.1 2003/09/04 18:46:00 joel Exp 3727c7ca7eSbellard */ 3827c7ca7eSbellard 392a6a4076SMarkus Armbruster #ifndef SH7750_REGS_H 402a6a4076SMarkus Armbruster #define SH7750_REGS_H 4127c7ca7eSbellard 4227c7ca7eSbellard /* 4327c7ca7eSbellard * All register has 2 addresses: in 0xff000000 - 0xffffffff (P4 address) and 4427c7ca7eSbellard * in 0x1f000000 - 0x1fffffff (area 7 address) 4527c7ca7eSbellard */ 46*22138965SBALATON Zoltan #define SH7750_P4_BASE 0xff000000 /* Accessible only in privileged mode */ 4764c7b9d8SStefan Weil #define SH7750_A7_BASE 0x1f000000 /* Accessible only using TLB */ 4827c7ca7eSbellard 4927c7ca7eSbellard #define SH7750_P4_REG32(ofs) (SH7750_P4_BASE + (ofs)) 5027c7ca7eSbellard #define SH7750_A7_REG32(ofs) (SH7750_A7_BASE + (ofs)) 5127c7ca7eSbellard 5227c7ca7eSbellard /* 5327c7ca7eSbellard * MMU Registers 5427c7ca7eSbellard */ 5527c7ca7eSbellard 5627c7ca7eSbellard /* Page Table Entry High register - PTEH */ 5727c7ca7eSbellard #define SH7750_PTEH_REGOFS 0x000000 /* offset */ 5827c7ca7eSbellard #define SH7750_PTEH SH7750_P4_REG32(SH7750_PTEH_REGOFS) 5927c7ca7eSbellard #define SH7750_PTEH_A7 SH7750_A7_REG32(SH7750_PTEH_REGOFS) 6027c7ca7eSbellard #define SH7750_PTEH_VPN 0xfffffd00 /* Virtual page number */ 6127c7ca7eSbellard #define SH7750_PTEH_VPN_S 10 6227c7ca7eSbellard #define SH7750_PTEH_ASID 0x000000ff /* Address space identifier */ 6327c7ca7eSbellard #define SH7750_PTEH_ASID_S 0 6427c7ca7eSbellard 6527c7ca7eSbellard /* Page Table Entry Low register - PTEL */ 6627c7ca7eSbellard #define SH7750_PTEL_REGOFS 0x000004 /* offset */ 6727c7ca7eSbellard #define SH7750_PTEL SH7750_P4_REG32(SH7750_PTEL_REGOFS) 6827c7ca7eSbellard #define SH7750_PTEL_A7 SH7750_A7_REG32(SH7750_PTEL_REGOFS) 6927c7ca7eSbellard #define SH7750_PTEL_PPN 0x1ffffc00 /* Physical page number */ 7027c7ca7eSbellard #define SH7750_PTEL_PPN_S 10 7127c7ca7eSbellard #define SH7750_PTEL_V 0x00000100 /* Validity (0-entry is invalid) */ 7227c7ca7eSbellard #define SH7750_PTEL_SZ1 0x00000080 /* Page size bit 1 */ 7327c7ca7eSbellard #define SH7750_PTEL_SZ0 0x00000010 /* Page size bit 0 */ 7427c7ca7eSbellard #define SH7750_PTEL_SZ_1KB 0x00000000 /* 1-kbyte page */ 7527c7ca7eSbellard #define SH7750_PTEL_SZ_4KB 0x00000010 /* 4-kbyte page */ 7627c7ca7eSbellard #define SH7750_PTEL_SZ_64KB 0x00000080 /* 64-kbyte page */ 7727c7ca7eSbellard #define SH7750_PTEL_SZ_1MB 0x00000090 /* 1-Mbyte page */ 7827c7ca7eSbellard #define SH7750_PTEL_PR 0x00000060 /* Protection Key Data */ 7927c7ca7eSbellard #define SH7750_PTEL_PR_ROPO 0x00000000 /* read-only in priv mode */ 8027c7ca7eSbellard #define SH7750_PTEL_PR_RWPO 0x00000020 /* read-write in priv mode */ 8127c7ca7eSbellard #define SH7750_PTEL_PR_ROPU 0x00000040 /* read-only in priv or user mode */ 8227c7ca7eSbellard #define SH7750_PTEL_PR_RWPU 0x00000060 /* read-write in priv or user mode */ 83*22138965SBALATON Zoltan #define SH7750_PTEL_C 0x00000008 /* Cacheability */ 84*22138965SBALATON Zoltan /* (0 - page not cacheable) */ 85*22138965SBALATON Zoltan #define SH7750_PTEL_D 0x00000004 /* Dirty bit (1 - write has been */ 86*22138965SBALATON Zoltan /* performed to a page) */ 87*22138965SBALATON Zoltan #define SH7750_PTEL_SH 0x00000002 /* Share Status bit (1 - page are */ 88*22138965SBALATON Zoltan /* shared by processes) */ 89*22138965SBALATON Zoltan #define SH7750_PTEL_WT 0x00000001 /* Write-through bit, specifies the */ 90*22138965SBALATON Zoltan /* cache write mode: */ 91*22138965SBALATON Zoltan /* 0 - Copy-back mode */ 92*22138965SBALATON Zoltan /* 1 - Write-through mode */ 9327c7ca7eSbellard 9427c7ca7eSbellard /* Page Table Entry Assistance register - PTEA */ 9527c7ca7eSbellard #define SH7750_PTEA_REGOFS 0x000034 /* offset */ 9627c7ca7eSbellard #define SH7750_PTEA SH7750_P4_REG32(SH7750_PTEA_REGOFS) 9727c7ca7eSbellard #define SH7750_PTEA_A7 SH7750_A7_REG32(SH7750_PTEA_REGOFS) 98*22138965SBALATON Zoltan #define SH7750_PTEA_TC 0x00000008 /* Timing Control bit */ 99*22138965SBALATON Zoltan /* 0 - use area 5 wait states */ 100*22138965SBALATON Zoltan /* 1 - use area 6 wait states */ 10127c7ca7eSbellard #define SH7750_PTEA_SA 0x00000007 /* Space Attribute bits: */ 10227c7ca7eSbellard #define SH7750_PTEA_SA_UNDEF 0x00000000 /* 0 - undefined */ 10327c7ca7eSbellard #define SH7750_PTEA_SA_IOVAR 0x00000001 /* 1 - variable-size I/O space */ 10427c7ca7eSbellard #define SH7750_PTEA_SA_IO8 0x00000002 /* 2 - 8-bit I/O space */ 10527c7ca7eSbellard #define SH7750_PTEA_SA_IO16 0x00000003 /* 3 - 16-bit I/O space */ 10627c7ca7eSbellard #define SH7750_PTEA_SA_CMEM8 0x00000004 /* 4 - 8-bit common memory space */ 10727c7ca7eSbellard #define SH7750_PTEA_SA_CMEM16 0x00000005 /* 5 - 16-bit common memory space */ 10827c7ca7eSbellard #define SH7750_PTEA_SA_AMEM8 0x00000006 /* 6 - 8-bit attr memory space */ 10927c7ca7eSbellard #define SH7750_PTEA_SA_AMEM16 0x00000007 /* 7 - 16-bit attr memory space */ 11027c7ca7eSbellard 11127c7ca7eSbellard 11227c7ca7eSbellard /* Translation table base register */ 11327c7ca7eSbellard #define SH7750_TTB_REGOFS 0x000008 /* offset */ 11427c7ca7eSbellard #define SH7750_TTB SH7750_P4_REG32(SH7750_TTB_REGOFS) 11527c7ca7eSbellard #define SH7750_TTB_A7 SH7750_A7_REG32(SH7750_TTB_REGOFS) 11627c7ca7eSbellard 11727c7ca7eSbellard /* TLB exeption address register - TEA */ 11827c7ca7eSbellard #define SH7750_TEA_REGOFS 0x00000c /* offset */ 11927c7ca7eSbellard #define SH7750_TEA SH7750_P4_REG32(SH7750_TEA_REGOFS) 12027c7ca7eSbellard #define SH7750_TEA_A7 SH7750_A7_REG32(SH7750_TEA_REGOFS) 12127c7ca7eSbellard 12227c7ca7eSbellard /* MMU control register - MMUCR */ 12327c7ca7eSbellard #define SH7750_MMUCR_REGOFS 0x000010 /* offset */ 12427c7ca7eSbellard #define SH7750_MMUCR SH7750_P4_REG32(SH7750_MMUCR_REGOFS) 12527c7ca7eSbellard #define SH7750_MMUCR_A7 SH7750_A7_REG32(SH7750_MMUCR_REGOFS) 12627c7ca7eSbellard #define SH7750_MMUCR_AT 0x00000001 /* Address translation bit */ 12727c7ca7eSbellard #define SH7750_MMUCR_TI 0x00000004 /* TLB invalidate */ 12827c7ca7eSbellard #define SH7750_MMUCR_SV 0x00000100 /* Single Virtual Mode bit */ 12927c7ca7eSbellard #define SH7750_MMUCR_SQMD 0x00000200 /* Store Queue Mode bit */ 13027c7ca7eSbellard #define SH7750_MMUCR_URC 0x0000FC00 /* UTLB Replace Counter */ 13127c7ca7eSbellard #define SH7750_MMUCR_URC_S 10 13227c7ca7eSbellard #define SH7750_MMUCR_URB 0x00FC0000 /* UTLB Replace Boundary */ 13327c7ca7eSbellard #define SH7750_MMUCR_URB_S 18 13427c7ca7eSbellard #define SH7750_MMUCR_LRUI 0xFC000000 /* Least Recently Used ITLB */ 13527c7ca7eSbellard #define SH7750_MMUCR_LRUI_S 26 13627c7ca7eSbellard 13727c7ca7eSbellard 13827c7ca7eSbellard 13927c7ca7eSbellard 14027c7ca7eSbellard /* 14127c7ca7eSbellard * Cache registers 14227c7ca7eSbellard * IC -- instructions cache 14327c7ca7eSbellard * OC -- operand cache 14427c7ca7eSbellard */ 14527c7ca7eSbellard 14627c7ca7eSbellard /* Cache Control Register - CCR */ 14727c7ca7eSbellard #define SH7750_CCR_REGOFS 0x00001c /* offset */ 14827c7ca7eSbellard #define SH7750_CCR SH7750_P4_REG32(SH7750_CCR_REGOFS) 14927c7ca7eSbellard #define SH7750_CCR_A7 SH7750_A7_REG32(SH7750_CCR_REGOFS) 15027c7ca7eSbellard 15127c7ca7eSbellard #define SH7750_CCR_IIX 0x00008000 /* IC index enable bit */ 152*22138965SBALATON Zoltan #define SH7750_CCR_ICI 0x00000800 /* IC invalidation bit: */ 153*22138965SBALATON Zoltan /* set it to clear IC */ 15427c7ca7eSbellard #define SH7750_CCR_ICE 0x00000100 /* IC enable bit */ 15527c7ca7eSbellard #define SH7750_CCR_OIX 0x00000080 /* OC index enable bit */ 156*22138965SBALATON Zoltan #define SH7750_CCR_ORA 0x00000020 /* OC RAM enable bit */ 157*22138965SBALATON Zoltan /* if you set OCE = 0, */ 158*22138965SBALATON Zoltan /* you should set ORA = 0 */ 15927c7ca7eSbellard #define SH7750_CCR_OCI 0x00000008 /* OC invalidation bit */ 16027c7ca7eSbellard #define SH7750_CCR_CB 0x00000004 /* Copy-back bit for P1 area */ 16127c7ca7eSbellard #define SH7750_CCR_WT 0x00000002 /* Write-through bit for P0,U0,P3 area */ 16227c7ca7eSbellard #define SH7750_CCR_OCE 0x00000001 /* OC enable bit */ 16327c7ca7eSbellard 16427c7ca7eSbellard /* Queue address control register 0 - QACR0 */ 16527c7ca7eSbellard #define SH7750_QACR0_REGOFS 0x000038 /* offset */ 16627c7ca7eSbellard #define SH7750_QACR0 SH7750_P4_REG32(SH7750_QACR0_REGOFS) 16727c7ca7eSbellard #define SH7750_QACR0_A7 SH7750_A7_REG32(SH7750_QACR0_REGOFS) 16827c7ca7eSbellard 16927c7ca7eSbellard /* Queue address control register 1 - QACR1 */ 17027c7ca7eSbellard #define SH7750_QACR1_REGOFS 0x00003c /* offset */ 17127c7ca7eSbellard #define SH7750_QACR1 SH7750_P4_REG32(SH7750_QACR1_REGOFS) 17227c7ca7eSbellard #define SH7750_QACR1_A7 SH7750_A7_REG32(SH7750_QACR1_REGOFS) 17327c7ca7eSbellard 17427c7ca7eSbellard 17527c7ca7eSbellard /* 17627c7ca7eSbellard * Exeption-related registers 17727c7ca7eSbellard */ 17827c7ca7eSbellard 17966a0a2cbSDong Xu Wang /* Immediate data for TRAPA instruction - TRA */ 18027c7ca7eSbellard #define SH7750_TRA_REGOFS 0x000020 /* offset */ 18127c7ca7eSbellard #define SH7750_TRA SH7750_P4_REG32(SH7750_TRA_REGOFS) 18227c7ca7eSbellard #define SH7750_TRA_A7 SH7750_A7_REG32(SH7750_TRA_REGOFS) 18327c7ca7eSbellard 18427c7ca7eSbellard #define SH7750_TRA_IMM 0x000003fd /* Immediate data operand */ 18527c7ca7eSbellard #define SH7750_TRA_IMM_S 2 18627c7ca7eSbellard 18727c7ca7eSbellard /* Exeption event register - EXPEVT */ 18827c7ca7eSbellard #define SH7750_EXPEVT_REGOFS 0x000024 18927c7ca7eSbellard #define SH7750_EXPEVT SH7750_P4_REG32(SH7750_EXPEVT_REGOFS) 19027c7ca7eSbellard #define SH7750_EXPEVT_A7 SH7750_A7_REG32(SH7750_EXPEVT_REGOFS) 19127c7ca7eSbellard 19227c7ca7eSbellard #define SH7750_EXPEVT_EX 0x00000fff /* Exeption code */ 19327c7ca7eSbellard #define SH7750_EXPEVT_EX_S 0 19427c7ca7eSbellard 19527c7ca7eSbellard /* Interrupt event register */ 19627c7ca7eSbellard #define SH7750_INTEVT_REGOFS 0x000028 19727c7ca7eSbellard #define SH7750_INTEVT SH7750_P4_REG32(SH7750_INTEVT_REGOFS) 19827c7ca7eSbellard #define SH7750_INTEVT_A7 SH7750_A7_REG32(SH7750_INTEVT_REGOFS) 19927c7ca7eSbellard #define SH7750_INTEVT_EX 0x00000fff /* Exeption code */ 20027c7ca7eSbellard #define SH7750_INTEVT_EX_S 0 20127c7ca7eSbellard 20227c7ca7eSbellard /* 20327c7ca7eSbellard * Exception/interrupt codes 20427c7ca7eSbellard */ 20527c7ca7eSbellard #define SH7750_EVT_TO_NUM(evt) ((evt) >> 5) 20627c7ca7eSbellard 20727c7ca7eSbellard /* Reset exception category */ 20827c7ca7eSbellard #define SH7750_EVT_POWER_ON_RST 0x000 /* Power-on reset */ 20927c7ca7eSbellard #define SH7750_EVT_MANUAL_RST 0x020 /* Manual reset */ 21027c7ca7eSbellard #define SH7750_EVT_TLB_MULT_HIT 0x140 /* TLB multiple-hit exception */ 21127c7ca7eSbellard 21227c7ca7eSbellard /* General exception category */ 21327c7ca7eSbellard #define SH7750_EVT_USER_BREAK 0x1E0 /* User break */ 21427c7ca7eSbellard #define SH7750_EVT_IADDR_ERR 0x0E0 /* Instruction address error */ 215*22138965SBALATON Zoltan #define SH7750_EVT_TLB_READ_MISS 0x040 /* ITLB miss exception / */ 216*22138965SBALATON Zoltan /* DTLB miss exception (read) */ 217*22138965SBALATON Zoltan #define SH7750_EVT_TLB_READ_PROTV 0x0A0 /* ITLB protection violation, */ 218*22138965SBALATON Zoltan /* DTLB protection violation */ 219*22138965SBALATON Zoltan /* (read) */ 220*22138965SBALATON Zoltan #define SH7750_EVT_ILLEGAL_INSTR 0x180 /* General Illegal Instruction */ 221*22138965SBALATON Zoltan /* exception */ 222*22138965SBALATON Zoltan #define SH7750_EVT_SLOT_ILLEGAL_INSTR 0x1A0 /* Slot Illegal Instruction */ 223*22138965SBALATON Zoltan /* exception */ 22427c7ca7eSbellard #define SH7750_EVT_FPU_DISABLE 0x800 /* General FPU disable exception */ 22527c7ca7eSbellard #define SH7750_EVT_SLOT_FPU_DISABLE 0x820 /* Slot FPU disable exception */ 22627c7ca7eSbellard #define SH7750_EVT_DATA_READ_ERR 0x0E0 /* Data address error (read) */ 22727c7ca7eSbellard #define SH7750_EVT_DATA_WRITE_ERR 0x100 /* Data address error (write) */ 22827c7ca7eSbellard #define SH7750_EVT_DTLB_WRITE_MISS 0x060 /* DTLB miss exception (write) */ 229*22138965SBALATON Zoltan #define SH7750_EVT_DTLB_WRITE_PROTV 0x0C0 /* DTLB protection violation */ 230*22138965SBALATON Zoltan /* exception (write) */ 23127c7ca7eSbellard #define SH7750_EVT_FPU_EXCEPTION 0x120 /* FPU exception */ 23227c7ca7eSbellard #define SH7750_EVT_INITIAL_PGWRITE 0x080 /* Initial Page Write exception */ 23327c7ca7eSbellard #define SH7750_EVT_TRAPA 0x160 /* Unconditional trap (TRAPA) */ 23427c7ca7eSbellard 23527c7ca7eSbellard /* Interrupt exception category */ 23627c7ca7eSbellard #define SH7750_EVT_NMI 0x1C0 /* Non-maskable interrupt */ 23727c7ca7eSbellard #define SH7750_EVT_IRQ0 0x200 /* External Interrupt 0 */ 23827c7ca7eSbellard #define SH7750_EVT_IRQ1 0x220 /* External Interrupt 1 */ 23927c7ca7eSbellard #define SH7750_EVT_IRQ2 0x240 /* External Interrupt 2 */ 24027c7ca7eSbellard #define SH7750_EVT_IRQ3 0x260 /* External Interrupt 3 */ 24127c7ca7eSbellard #define SH7750_EVT_IRQ4 0x280 /* External Interrupt 4 */ 24227c7ca7eSbellard #define SH7750_EVT_IRQ5 0x2A0 /* External Interrupt 5 */ 24327c7ca7eSbellard #define SH7750_EVT_IRQ6 0x2C0 /* External Interrupt 6 */ 24427c7ca7eSbellard #define SH7750_EVT_IRQ7 0x2E0 /* External Interrupt 7 */ 24527c7ca7eSbellard #define SH7750_EVT_IRQ8 0x300 /* External Interrupt 8 */ 24627c7ca7eSbellard #define SH7750_EVT_IRQ9 0x320 /* External Interrupt 9 */ 24727c7ca7eSbellard #define SH7750_EVT_IRQA 0x340 /* External Interrupt A */ 24827c7ca7eSbellard #define SH7750_EVT_IRQB 0x360 /* External Interrupt B */ 24927c7ca7eSbellard #define SH7750_EVT_IRQC 0x380 /* External Interrupt C */ 25027c7ca7eSbellard #define SH7750_EVT_IRQD 0x3A0 /* External Interrupt D */ 25127c7ca7eSbellard #define SH7750_EVT_IRQE 0x3C0 /* External Interrupt E */ 25227c7ca7eSbellard 25327c7ca7eSbellard /* Peripheral Module Interrupts - Timer Unit (TMU) */ 25427c7ca7eSbellard #define SH7750_EVT_TUNI0 0x400 /* TMU Underflow Interrupt 0 */ 25527c7ca7eSbellard #define SH7750_EVT_TUNI1 0x420 /* TMU Underflow Interrupt 1 */ 25627c7ca7eSbellard #define SH7750_EVT_TUNI2 0x440 /* TMU Underflow Interrupt 2 */ 25727c7ca7eSbellard #define SH7750_EVT_TICPI2 0x460 /* TMU Input Capture Interrupt 2 */ 25827c7ca7eSbellard 25927c7ca7eSbellard /* Peripheral Module Interrupts - Real-Time Clock (RTC) */ 26027c7ca7eSbellard #define SH7750_EVT_RTC_ATI 0x480 /* Alarm Interrupt Request */ 26127c7ca7eSbellard #define SH7750_EVT_RTC_PRI 0x4A0 /* Periodic Interrupt Request */ 26227c7ca7eSbellard #define SH7750_EVT_RTC_CUI 0x4C0 /* Carry Interrupt Request */ 26327c7ca7eSbellard 26427c7ca7eSbellard /* Peripheral Module Interrupts - Serial Communication Interface (SCI) */ 26527c7ca7eSbellard #define SH7750_EVT_SCI_ERI 0x4E0 /* Receive Error */ 26627c7ca7eSbellard #define SH7750_EVT_SCI_RXI 0x500 /* Receive Data Register Full */ 26727c7ca7eSbellard #define SH7750_EVT_SCI_TXI 0x520 /* Transmit Data Register Empty */ 26827c7ca7eSbellard #define SH7750_EVT_SCI_TEI 0x540 /* Transmit End */ 26927c7ca7eSbellard 27027c7ca7eSbellard /* Peripheral Module Interrupts - Watchdog Timer (WDT) */ 271*22138965SBALATON Zoltan #define SH7750_EVT_WDT_ITI 0x560 /* Interval Timer Interrupt */ 272*22138965SBALATON Zoltan /* (used when WDT operates in */ 273*22138965SBALATON Zoltan /* interval timer mode) */ 27427c7ca7eSbellard 27527c7ca7eSbellard /* Peripheral Module Interrupts - Memory Refresh Unit (REF) */ 27627c7ca7eSbellard #define SH7750_EVT_REF_RCMI 0x580 /* Compare-match Interrupt */ 277*22138965SBALATON Zoltan #define SH7750_EVT_REF_ROVI 0x5A0 /* Refresh Counter Overflow */ 278*22138965SBALATON Zoltan /* interrupt */ 27927c7ca7eSbellard 28027c7ca7eSbellard /* Peripheral Module Interrupts - Hitachi User Debug Interface (H-UDI) */ 28127c7ca7eSbellard #define SH7750_EVT_HUDI 0x600 /* UDI interrupt */ 28227c7ca7eSbellard 28327c7ca7eSbellard /* Peripheral Module Interrupts - General-Purpose I/O (GPIO) */ 28427c7ca7eSbellard #define SH7750_EVT_GPIO 0x620 /* GPIO Interrupt */ 28527c7ca7eSbellard 28627c7ca7eSbellard /* Peripheral Module Interrupts - DMA Controller (DMAC) */ 28727c7ca7eSbellard #define SH7750_EVT_DMAC_DMTE0 0x640 /* DMAC 0 Transfer End Interrupt */ 28827c7ca7eSbellard #define SH7750_EVT_DMAC_DMTE1 0x660 /* DMAC 1 Transfer End Interrupt */ 28927c7ca7eSbellard #define SH7750_EVT_DMAC_DMTE2 0x680 /* DMAC 2 Transfer End Interrupt */ 29027c7ca7eSbellard #define SH7750_EVT_DMAC_DMTE3 0x6A0 /* DMAC 3 Transfer End Interrupt */ 29127c7ca7eSbellard #define SH7750_EVT_DMAC_DMAE 0x6C0 /* DMAC Address Error Interrupt */ 29227c7ca7eSbellard 293*22138965SBALATON Zoltan /* Peripheral Module Interrupts Serial Communication Interface w/ FIFO (SCIF) */ 29427c7ca7eSbellard #define SH7750_EVT_SCIF_ERI 0x700 /* Receive Error */ 295*22138965SBALATON Zoltan #define SH7750_EVT_SCIF_RXI 0x720 /* Receive FIFO Data Full or */ 296*22138965SBALATON Zoltan /* Receive Data ready interrupt */ 29727c7ca7eSbellard #define SH7750_EVT_SCIF_BRI 0x740 /* Break or overrun error */ 29827c7ca7eSbellard #define SH7750_EVT_SCIF_TXI 0x760 /* Transmit FIFO Data Empty */ 29927c7ca7eSbellard 30027c7ca7eSbellard /* 30127c7ca7eSbellard * Power Management 30227c7ca7eSbellard */ 30327c7ca7eSbellard #define SH7750_STBCR_REGOFS 0xC00004 /* offset */ 30427c7ca7eSbellard #define SH7750_STBCR SH7750_P4_REG32(SH7750_STBCR_REGOFS) 30527c7ca7eSbellard #define SH7750_STBCR_A7 SH7750_A7_REG32(SH7750_STBCR_REGOFS) 30627c7ca7eSbellard 307*22138965SBALATON Zoltan #define SH7750_STBCR_STBY 0x80 /* Specifies a transition to standby mode: */ 308*22138965SBALATON Zoltan /* 0 Transition to SLEEP mode on SLEEP */ 309*22138965SBALATON Zoltan /* 1 Transition to STANDBY mode on SLEEP */ 310*22138965SBALATON Zoltan #define SH7750_STBCR_PHZ 0x40 /* State of peripheral module pins in */ 311*22138965SBALATON Zoltan /* standby mode: */ 312*22138965SBALATON Zoltan /* 0 normal state */ 313*22138965SBALATON Zoltan /* 1 high-impendance state */ 31427c7ca7eSbellard 31527c7ca7eSbellard #define SH7750_STBCR_PPU 0x20 /* Peripheral module pins pull-up controls */ 31627c7ca7eSbellard #define SH7750_STBCR_MSTP4 0x10 /* Stopping the clock supply to DMAC */ 31727c7ca7eSbellard #define SH7750_STBCR_DMAC_STP SH7750_STBCR_MSTP4 31827c7ca7eSbellard #define SH7750_STBCR_MSTP3 0x08 /* Stopping the clock supply to SCIF */ 31927c7ca7eSbellard #define SH7750_STBCR_SCIF_STP SH7750_STBCR_MSTP3 32027c7ca7eSbellard #define SH7750_STBCR_MSTP2 0x04 /* Stopping the clock supply to TMU */ 32127c7ca7eSbellard #define SH7750_STBCR_TMU_STP SH7750_STBCR_MSTP2 32227c7ca7eSbellard #define SH7750_STBCR_MSTP1 0x02 /* Stopping the clock supply to RTC */ 32327c7ca7eSbellard #define SH7750_STBCR_RTC_STP SH7750_STBCR_MSTP1 32427c7ca7eSbellard #define SH7750_STBCR_MSPT0 0x01 /* Stopping the clock supply to SCI */ 32527c7ca7eSbellard #define SH7750_STBCR_SCI_STP SH7750_STBCR_MSTP0 32627c7ca7eSbellard 32727c7ca7eSbellard #define SH7750_STBCR_STBY 0x80 32827c7ca7eSbellard 32927c7ca7eSbellard 33027c7ca7eSbellard #define SH7750_STBCR2_REGOFS 0xC00010 /* offset */ 33127c7ca7eSbellard #define SH7750_STBCR2 SH7750_P4_REG32(SH7750_STBCR2_REGOFS) 33227c7ca7eSbellard #define SH7750_STBCR2_A7 SH7750_A7_REG32(SH7750_STBCR2_REGOFS) 33327c7ca7eSbellard 334*22138965SBALATON Zoltan #define SH7750_STBCR2_DSLP 0x80 /* Specifies transition to deep sleep mode */ 335*22138965SBALATON Zoltan /* 0 transition to sleep or standby mode */ 336*22138965SBALATON Zoltan /* as it is specified in STBY bit */ 337*22138965SBALATON Zoltan /* 1 transition to deep sleep mode on */ 338*22138965SBALATON Zoltan /* execution of SLEEP instruction */ 339*22138965SBALATON Zoltan #define SH7750_STBCR2_MSTP6 0x02 /* Stopping the clock supply to the */ 340*22138965SBALATON Zoltan /* Store Queue in the cache controller */ 34127c7ca7eSbellard #define SH7750_STBCR2_SQ_STP SH7750_STBCR2_MSTP6 342*22138965SBALATON Zoltan #define SH7750_STBCR2_MSTP5 0x01 /* Stopping the clock supply to the */ 343*22138965SBALATON Zoltan /* User Break Controller (UBC) */ 34427c7ca7eSbellard #define SH7750_STBCR2_UBC_STP SH7750_STBCR2_MSTP5 34527c7ca7eSbellard 34627c7ca7eSbellard /* 34727c7ca7eSbellard * Clock Pulse Generator (CPG) 34827c7ca7eSbellard */ 34927c7ca7eSbellard #define SH7750_FRQCR_REGOFS 0xC00000 /* offset */ 35027c7ca7eSbellard #define SH7750_FRQCR SH7750_P4_REG32(SH7750_FRQCR_REGOFS) 35127c7ca7eSbellard #define SH7750_FRQCR_A7 SH7750_A7_REG32(SH7750_FRQCR_REGOFS) 35227c7ca7eSbellard 353*22138965SBALATON Zoltan #define SH7750_FRQCR_CKOEN 0x0800 /* Clock Output Enable */ 354*22138965SBALATON Zoltan /* 0 - CKIO pin goes to HiZ/pullup */ 355*22138965SBALATON Zoltan /* 1 - Clock is output from CKIO */ 35627c7ca7eSbellard #define SH7750_FRQCR_PLL1EN 0x0400 /* PLL circuit 1 enable */ 35727c7ca7eSbellard #define SH7750_FRQCR_PLL2EN 0x0200 /* PLL circuit 2 enable */ 35827c7ca7eSbellard 35927c7ca7eSbellard #define SH7750_FRQCR_IFC 0x01C0 /* CPU clock frequency division ratio: */ 36027c7ca7eSbellard #define SH7750_FRQCR_IFCDIV1 0x0000 /* 0 - * 1 */ 36127c7ca7eSbellard #define SH7750_FRQCR_IFCDIV2 0x0040 /* 1 - * 1/2 */ 36227c7ca7eSbellard #define SH7750_FRQCR_IFCDIV3 0x0080 /* 2 - * 1/3 */ 36327c7ca7eSbellard #define SH7750_FRQCR_IFCDIV4 0x00C0 /* 3 - * 1/4 */ 36427c7ca7eSbellard #define SH7750_FRQCR_IFCDIV6 0x0100 /* 4 - * 1/6 */ 36527c7ca7eSbellard #define SH7750_FRQCR_IFCDIV8 0x0140 /* 5 - * 1/8 */ 36627c7ca7eSbellard 36727c7ca7eSbellard #define SH7750_FRQCR_BFC 0x0038 /* Bus clock frequency division ratio: */ 36827c7ca7eSbellard #define SH7750_FRQCR_BFCDIV1 0x0000 /* 0 - * 1 */ 36927c7ca7eSbellard #define SH7750_FRQCR_BFCDIV2 0x0008 /* 1 - * 1/2 */ 37027c7ca7eSbellard #define SH7750_FRQCR_BFCDIV3 0x0010 /* 2 - * 1/3 */ 37127c7ca7eSbellard #define SH7750_FRQCR_BFCDIV4 0x0018 /* 3 - * 1/4 */ 37227c7ca7eSbellard #define SH7750_FRQCR_BFCDIV6 0x0020 /* 4 - * 1/6 */ 37327c7ca7eSbellard #define SH7750_FRQCR_BFCDIV8 0x0028 /* 5 - * 1/8 */ 37427c7ca7eSbellard 375*22138965SBALATON Zoltan #define SH7750_FRQCR_PFC 0x0007 /* Peripheral module clock frequency */ 376*22138965SBALATON Zoltan /* division ratio: */ 37727c7ca7eSbellard #define SH7750_FRQCR_PFCDIV2 0x0000 /* 0 - * 1/2 */ 37827c7ca7eSbellard #define SH7750_FRQCR_PFCDIV3 0x0001 /* 1 - * 1/3 */ 37927c7ca7eSbellard #define SH7750_FRQCR_PFCDIV4 0x0002 /* 2 - * 1/4 */ 38027c7ca7eSbellard #define SH7750_FRQCR_PFCDIV6 0x0003 /* 3 - * 1/6 */ 38127c7ca7eSbellard #define SH7750_FRQCR_PFCDIV8 0x0004 /* 4 - * 1/8 */ 38227c7ca7eSbellard 38327c7ca7eSbellard /* 38427c7ca7eSbellard * Watchdog Timer (WDT) 38527c7ca7eSbellard */ 38627c7ca7eSbellard 38727c7ca7eSbellard /* Watchdog Timer Counter register - WTCNT */ 38827c7ca7eSbellard #define SH7750_WTCNT_REGOFS 0xC00008 /* offset */ 38927c7ca7eSbellard #define SH7750_WTCNT SH7750_P4_REG32(SH7750_WTCNT_REGOFS) 39027c7ca7eSbellard #define SH7750_WTCNT_A7 SH7750_A7_REG32(SH7750_WTCNT_REGOFS) 391*22138965SBALATON Zoltan #define SH7750_WTCNT_KEY 0x5A00 /* When WTCNT byte register written, you */ 392*22138965SBALATON Zoltan /* have to set the upper byte to 0x5A */ 39327c7ca7eSbellard 39427c7ca7eSbellard /* Watchdog Timer Control/Status register - WTCSR */ 39527c7ca7eSbellard #define SH7750_WTCSR_REGOFS 0xC0000C /* offset */ 39627c7ca7eSbellard #define SH7750_WTCSR SH7750_P4_REG32(SH7750_WTCSR_REGOFS) 39727c7ca7eSbellard #define SH7750_WTCSR_A7 SH7750_A7_REG32(SH7750_WTCSR_REGOFS) 398*22138965SBALATON Zoltan #define SH7750_WTCSR_KEY 0xA500 /* When WTCSR byte register written, you */ 399*22138965SBALATON Zoltan /* have to set the upper byte to 0xA5 */ 40027c7ca7eSbellard #define SH7750_WTCSR_TME 0x80 /* Timer enable (1-upcount start) */ 40127c7ca7eSbellard #define SH7750_WTCSR_MODE 0x40 /* Timer Mode Select: */ 40227c7ca7eSbellard #define SH7750_WTCSR_MODE_WT 0x40 /* Watchdog Timer Mode */ 40327c7ca7eSbellard #define SH7750_WTCSR_MODE_IT 0x00 /* Interval Timer Mode */ 40427c7ca7eSbellard #define SH7750_WTCSR_RSTS 0x20 /* Reset Select: */ 40527c7ca7eSbellard #define SH7750_WTCSR_RST_MAN 0x20 /* Manual Reset */ 40627c7ca7eSbellard #define SH7750_WTCSR_RST_PWR 0x00 /* Power-on Reset */ 40727c7ca7eSbellard #define SH7750_WTCSR_WOVF 0x10 /* Watchdog Timer Overflow Flag */ 40827c7ca7eSbellard #define SH7750_WTCSR_IOVF 0x08 /* Interval Timer Overflow Flag */ 40927c7ca7eSbellard #define SH7750_WTCSR_CKS 0x07 /* Clock Select: */ 41027c7ca7eSbellard #define SH7750_WTCSR_CKS_DIV32 0x00 /* 1/32 of frequency divider 2 input */ 41127c7ca7eSbellard #define SH7750_WTCSR_CKS_DIV64 0x01 /* 1/64 */ 41227c7ca7eSbellard #define SH7750_WTCSR_CKS_DIV128 0x02 /* 1/128 */ 41327c7ca7eSbellard #define SH7750_WTCSR_CKS_DIV256 0x03 /* 1/256 */ 41427c7ca7eSbellard #define SH7750_WTCSR_CKS_DIV512 0x04 /* 1/512 */ 41527c7ca7eSbellard #define SH7750_WTCSR_CKS_DIV1024 0x05 /* 1/1024 */ 41627c7ca7eSbellard #define SH7750_WTCSR_CKS_DIV2048 0x06 /* 1/2048 */ 41727c7ca7eSbellard #define SH7750_WTCSR_CKS_DIV4096 0x07 /* 1/4096 */ 41827c7ca7eSbellard 41927c7ca7eSbellard /* 42027c7ca7eSbellard * Real-Time Clock (RTC) 42127c7ca7eSbellard */ 42227c7ca7eSbellard /* 64-Hz Counter Register (byte, read-only) - R64CNT */ 42327c7ca7eSbellard #define SH7750_R64CNT_REGOFS 0xC80000 /* offset */ 42427c7ca7eSbellard #define SH7750_R64CNT SH7750_P4_REG32(SH7750_R64CNT_REGOFS) 42527c7ca7eSbellard #define SH7750_R64CNT_A7 SH7750_A7_REG32(SH7750_R64CNT_REGOFS) 42627c7ca7eSbellard 42727c7ca7eSbellard /* Second Counter Register (byte, BCD-coded) - RSECCNT */ 42827c7ca7eSbellard #define SH7750_RSECCNT_REGOFS 0xC80004 /* offset */ 42927c7ca7eSbellard #define SH7750_RSECCNT SH7750_P4_REG32(SH7750_RSECCNT_REGOFS) 43027c7ca7eSbellard #define SH7750_RSECCNT_A7 SH7750_A7_REG32(SH7750_RSECCNT_REGOFS) 43127c7ca7eSbellard 43227c7ca7eSbellard /* Minute Counter Register (byte, BCD-coded) - RMINCNT */ 43327c7ca7eSbellard #define SH7750_RMINCNT_REGOFS 0xC80008 /* offset */ 43427c7ca7eSbellard #define SH7750_RMINCNT SH7750_P4_REG32(SH7750_RMINCNT_REGOFS) 43527c7ca7eSbellard #define SH7750_RMINCNT_A7 SH7750_A7_REG32(SH7750_RMINCNT_REGOFS) 43627c7ca7eSbellard 43727c7ca7eSbellard /* Hour Counter Register (byte, BCD-coded) - RHRCNT */ 43827c7ca7eSbellard #define SH7750_RHRCNT_REGOFS 0xC8000C /* offset */ 43927c7ca7eSbellard #define SH7750_RHRCNT SH7750_P4_REG32(SH7750_RHRCNT_REGOFS) 44027c7ca7eSbellard #define SH7750_RHRCNT_A7 SH7750_A7_REG32(SH7750_RHRCNT_REGOFS) 44127c7ca7eSbellard 44227c7ca7eSbellard /* Day-of-Week Counter Register (byte) - RWKCNT */ 44327c7ca7eSbellard #define SH7750_RWKCNT_REGOFS 0xC80010 /* offset */ 44427c7ca7eSbellard #define SH7750_RWKCNT SH7750_P4_REG32(SH7750_RWKCNT_REGOFS) 44527c7ca7eSbellard #define SH7750_RWKCNT_A7 SH7750_A7_REG32(SH7750_RWKCNT_REGOFS) 44627c7ca7eSbellard 44727c7ca7eSbellard #define SH7750_RWKCNT_SUN 0 /* Sunday */ 44827c7ca7eSbellard #define SH7750_RWKCNT_MON 1 /* Monday */ 44927c7ca7eSbellard #define SH7750_RWKCNT_TUE 2 /* Tuesday */ 45027c7ca7eSbellard #define SH7750_RWKCNT_WED 3 /* Wednesday */ 45127c7ca7eSbellard #define SH7750_RWKCNT_THU 4 /* Thursday */ 45227c7ca7eSbellard #define SH7750_RWKCNT_FRI 5 /* Friday */ 45327c7ca7eSbellard #define SH7750_RWKCNT_SAT 6 /* Saturday */ 45427c7ca7eSbellard 45527c7ca7eSbellard /* Day Counter Register (byte, BCD-coded) - RDAYCNT */ 45627c7ca7eSbellard #define SH7750_RDAYCNT_REGOFS 0xC80014 /* offset */ 45727c7ca7eSbellard #define SH7750_RDAYCNT SH7750_P4_REG32(SH7750_RDAYCNT_REGOFS) 45827c7ca7eSbellard #define SH7750_RDAYCNT_A7 SH7750_A7_REG32(SH7750_RDAYCNT_REGOFS) 45927c7ca7eSbellard 46027c7ca7eSbellard /* Month Counter Register (byte, BCD-coded) - RMONCNT */ 46127c7ca7eSbellard #define SH7750_RMONCNT_REGOFS 0xC80018 /* offset */ 46227c7ca7eSbellard #define SH7750_RMONCNT SH7750_P4_REG32(SH7750_RMONCNT_REGOFS) 46327c7ca7eSbellard #define SH7750_RMONCNT_A7 SH7750_A7_REG32(SH7750_RMONCNT_REGOFS) 46427c7ca7eSbellard 46527c7ca7eSbellard /* Year Counter Register (half, BCD-coded) - RYRCNT */ 46627c7ca7eSbellard #define SH7750_RYRCNT_REGOFS 0xC8001C /* offset */ 46727c7ca7eSbellard #define SH7750_RYRCNT SH7750_P4_REG32(SH7750_RYRCNT_REGOFS) 46827c7ca7eSbellard #define SH7750_RYRCNT_A7 SH7750_A7_REG32(SH7750_RYRCNT_REGOFS) 46927c7ca7eSbellard 47027c7ca7eSbellard /* Second Alarm Register (byte, BCD-coded) - RSECAR */ 47127c7ca7eSbellard #define SH7750_RSECAR_REGOFS 0xC80020 /* offset */ 47227c7ca7eSbellard #define SH7750_RSECAR SH7750_P4_REG32(SH7750_RSECAR_REGOFS) 47327c7ca7eSbellard #define SH7750_RSECAR_A7 SH7750_A7_REG32(SH7750_RSECAR_REGOFS) 47427c7ca7eSbellard #define SH7750_RSECAR_ENB 0x80 /* Second Alarm Enable */ 47527c7ca7eSbellard 47627c7ca7eSbellard /* Minute Alarm Register (byte, BCD-coded) - RMINAR */ 47727c7ca7eSbellard #define SH7750_RMINAR_REGOFS 0xC80024 /* offset */ 47827c7ca7eSbellard #define SH7750_RMINAR SH7750_P4_REG32(SH7750_RMINAR_REGOFS) 47927c7ca7eSbellard #define SH7750_RMINAR_A7 SH7750_A7_REG32(SH7750_RMINAR_REGOFS) 48027c7ca7eSbellard #define SH7750_RMINAR_ENB 0x80 /* Minute Alarm Enable */ 48127c7ca7eSbellard 48227c7ca7eSbellard /* Hour Alarm Register (byte, BCD-coded) - RHRAR */ 48327c7ca7eSbellard #define SH7750_RHRAR_REGOFS 0xC80028 /* offset */ 48427c7ca7eSbellard #define SH7750_RHRAR SH7750_P4_REG32(SH7750_RHRAR_REGOFS) 48527c7ca7eSbellard #define SH7750_RHRAR_A7 SH7750_A7_REG32(SH7750_RHRAR_REGOFS) 48627c7ca7eSbellard #define SH7750_RHRAR_ENB 0x80 /* Hour Alarm Enable */ 48727c7ca7eSbellard 48827c7ca7eSbellard /* Day-of-Week Alarm Register (byte) - RWKAR */ 48927c7ca7eSbellard #define SH7750_RWKAR_REGOFS 0xC8002C /* offset */ 49027c7ca7eSbellard #define SH7750_RWKAR SH7750_P4_REG32(SH7750_RWKAR_REGOFS) 49127c7ca7eSbellard #define SH7750_RWKAR_A7 SH7750_A7_REG32(SH7750_RWKAR_REGOFS) 49227c7ca7eSbellard #define SH7750_RWKAR_ENB 0x80 /* Day-of-week Alarm Enable */ 49327c7ca7eSbellard 49427c7ca7eSbellard #define SH7750_RWKAR_SUN 0 /* Sunday */ 49527c7ca7eSbellard #define SH7750_RWKAR_MON 1 /* Monday */ 49627c7ca7eSbellard #define SH7750_RWKAR_TUE 2 /* Tuesday */ 49727c7ca7eSbellard #define SH7750_RWKAR_WED 3 /* Wednesday */ 49827c7ca7eSbellard #define SH7750_RWKAR_THU 4 /* Thursday */ 49927c7ca7eSbellard #define SH7750_RWKAR_FRI 5 /* Friday */ 50027c7ca7eSbellard #define SH7750_RWKAR_SAT 6 /* Saturday */ 50127c7ca7eSbellard 50227c7ca7eSbellard /* Day Alarm Register (byte, BCD-coded) - RDAYAR */ 50327c7ca7eSbellard #define SH7750_RDAYAR_REGOFS 0xC80030 /* offset */ 50427c7ca7eSbellard #define SH7750_RDAYAR SH7750_P4_REG32(SH7750_RDAYAR_REGOFS) 50527c7ca7eSbellard #define SH7750_RDAYAR_A7 SH7750_A7_REG32(SH7750_RDAYAR_REGOFS) 50627c7ca7eSbellard #define SH7750_RDAYAR_ENB 0x80 /* Day Alarm Enable */ 50727c7ca7eSbellard 50827c7ca7eSbellard /* Month Counter Register (byte, BCD-coded) - RMONAR */ 50927c7ca7eSbellard #define SH7750_RMONAR_REGOFS 0xC80034 /* offset */ 51027c7ca7eSbellard #define SH7750_RMONAR SH7750_P4_REG32(SH7750_RMONAR_REGOFS) 51127c7ca7eSbellard #define SH7750_RMONAR_A7 SH7750_A7_REG32(SH7750_RMONAR_REGOFS) 51227c7ca7eSbellard #define SH7750_RMONAR_ENB 0x80 /* Month Alarm Enable */ 51327c7ca7eSbellard 51427c7ca7eSbellard /* RTC Control Register 1 (byte) - RCR1 */ 51527c7ca7eSbellard #define SH7750_RCR1_REGOFS 0xC80038 /* offset */ 51627c7ca7eSbellard #define SH7750_RCR1 SH7750_P4_REG32(SH7750_RCR1_REGOFS) 51727c7ca7eSbellard #define SH7750_RCR1_A7 SH7750_A7_REG32(SH7750_RCR1_REGOFS) 51827c7ca7eSbellard #define SH7750_RCR1_CF 0x80 /* Carry Flag */ 51927c7ca7eSbellard #define SH7750_RCR1_CIE 0x10 /* Carry Interrupt Enable */ 52027c7ca7eSbellard #define SH7750_RCR1_AIE 0x08 /* Alarm Interrupt Enable */ 52127c7ca7eSbellard #define SH7750_RCR1_AF 0x01 /* Alarm Flag */ 52227c7ca7eSbellard 52327c7ca7eSbellard /* RTC Control Register 2 (byte) - RCR2 */ 52427c7ca7eSbellard #define SH7750_RCR2_REGOFS 0xC8003C /* offset */ 52527c7ca7eSbellard #define SH7750_RCR2 SH7750_P4_REG32(SH7750_RCR2_REGOFS) 52627c7ca7eSbellard #define SH7750_RCR2_A7 SH7750_A7_REG32(SH7750_RCR2_REGOFS) 52727c7ca7eSbellard #define SH7750_RCR2_PEF 0x80 /* Periodic Interrupt Flag */ 52827c7ca7eSbellard #define SH7750_RCR2_PES 0x70 /* Periodic Interrupt Enable: */ 52927c7ca7eSbellard #define SH7750_RCR2_PES_DIS 0x00 /* Periodic Interrupt Disabled */ 53027c7ca7eSbellard #define SH7750_RCR2_PES_DIV256 0x10 /* Generated at 1/256 sec interval */ 53127c7ca7eSbellard #define SH7750_RCR2_PES_DIV64 0x20 /* Generated at 1/64 sec interval */ 53227c7ca7eSbellard #define SH7750_RCR2_PES_DIV16 0x30 /* Generated at 1/16 sec interval */ 53327c7ca7eSbellard #define SH7750_RCR2_PES_DIV4 0x40 /* Generated at 1/4 sec interval */ 53427c7ca7eSbellard #define SH7750_RCR2_PES_DIV2 0x50 /* Generated at 1/2 sec interval */ 53527c7ca7eSbellard #define SH7750_RCR2_PES_x1 0x60 /* Generated at 1 sec interval */ 53627c7ca7eSbellard #define SH7750_RCR2_PES_x2 0x70 /* Generated at 2 sec interval */ 53727c7ca7eSbellard #define SH7750_RCR2_RTCEN 0x08 /* RTC Crystal Oscillator is Operated */ 53827c7ca7eSbellard #define SH7750_RCR2_ADJ 0x04 /* 30-Second Adjastment */ 53927c7ca7eSbellard #define SH7750_RCR2_RESET 0x02 /* Frequency divider circuits are reset */ 540*22138965SBALATON Zoltan #define SH7750_RCR2_START 0x01 /* 0 - sec, min, hr, day-of-week, month, */ 541*22138965SBALATON Zoltan /* year counters are stopped */ 542*22138965SBALATON Zoltan /* 1 - sec, min, hr, day-of-week, month, */ 543*22138965SBALATON Zoltan /* year counters operate normally */ 54427c7ca7eSbellard /* 54527c7ca7eSbellard * Bus State Controller - BSC 54627c7ca7eSbellard */ 54727c7ca7eSbellard /* Bus Control Register 1 - BCR1 */ 54827c7ca7eSbellard #define SH7750_BCR1_REGOFS 0x800000 /* offset */ 54927c7ca7eSbellard #define SH7750_BCR1 SH7750_P4_REG32(SH7750_BCR1_REGOFS) 55027c7ca7eSbellard #define SH7750_BCR1_A7 SH7750_A7_REG32(SH7750_BCR1_REGOFS) 55127c7ca7eSbellard #define SH7750_BCR1_ENDIAN 0x80000000 /* Endianness (1 - little endian) */ 55227c7ca7eSbellard #define SH7750_BCR1_MASTER 0x40000000 /* Master/Slave mode (1-master) */ 55327c7ca7eSbellard #define SH7750_BCR1_A0MPX 0x20000000 /* Area 0 Memory Type (0-SRAM,1-MPX) */ 554*22138965SBALATON Zoltan #define SH7750_BCR1_IPUP 0x02000000 /* Input Pin Pull-up Control: */ 555*22138965SBALATON Zoltan /* 0 - pull-up resistor is on for */ 556*22138965SBALATON Zoltan /* control input pins */ 557*22138965SBALATON Zoltan /* 1 - pull-up resistor is off */ 558*22138965SBALATON Zoltan #define SH7750_BCR1_OPUP 0x01000000 /* Output Pin Pull-up Control: */ 559*22138965SBALATON Zoltan /* 0 - pull-up resistor is on for */ 560*22138965SBALATON Zoltan /* control output pins */ 561*22138965SBALATON Zoltan /* 1 - pull-up resistor is off */ 562*22138965SBALATON Zoltan #define SH7750_BCR1_A1MBC 0x00200000 /* Area 1 SRAM Byte Control Mode: */ 563*22138965SBALATON Zoltan /* 0 - Area 1 SRAM is set to */ 564*22138965SBALATON Zoltan /* normal mode */ 565*22138965SBALATON Zoltan /* 1 - Area 1 SRAM is set to byte */ 566*22138965SBALATON Zoltan /* control mode */ 567*22138965SBALATON Zoltan #define SH7750_BCR1_A4MBC 0x00100000 /* Area 4 SRAM Byte Control Mode: */ 568*22138965SBALATON Zoltan /* 0 - Area 4 SRAM is set to */ 569*22138965SBALATON Zoltan /* normal mode */ 570*22138965SBALATON Zoltan /* 1 - Area 4 SRAM is set to byte */ 571*22138965SBALATON Zoltan /* control mode */ 572*22138965SBALATON Zoltan #define SH7750_BCR1_BREQEN 0x00080000 /* BREQ Enable: */ 573*22138965SBALATON Zoltan /* 0 - External requests are not */ 574*22138965SBALATON Zoltan /* accepted */ 575*22138965SBALATON Zoltan /* 1 - External requests are */ 576*22138965SBALATON Zoltan /* accepted */ 577*22138965SBALATON Zoltan #define SH7750_BCR1_PSHR 0x00040000 /* Partial Sharing Bit: */ 578*22138965SBALATON Zoltan /* 0 - Master Mode */ 579*22138965SBALATON Zoltan /* 1 - Partial-sharing Mode */ 580*22138965SBALATON Zoltan #define SH7750_BCR1_MEMMPX 0x00020000 /* Area 1 to 6 MPX Interface: */ 581*22138965SBALATON Zoltan /* 0 - SRAM/burst ROM interface */ 582*22138965SBALATON Zoltan /* 1 - MPX interface */ 583*22138965SBALATON Zoltan #define SH7750_BCR1_HIZMEM 0x00008000 /* High Impendance Control. */ 584*22138965SBALATON Zoltan /* Specifies the state of A[25:0], */ 585*22138965SBALATON Zoltan /* BS\, CSn\, RD/WR\, CE2A\, CE2B\ */ 586*22138965SBALATON Zoltan /* in standby mode and when bus is */ 587*22138965SBALATON Zoltan /* released: */ 588*22138965SBALATON Zoltan /* 0 - signals go to High-Z mode */ 589*22138965SBALATON Zoltan /* 1 - signals driven */ 590*22138965SBALATON Zoltan #define SH7750_BCR1_HIZCNT 0x00004000 /* High Impendance Control. */ 591*22138965SBALATON Zoltan /* Specifies the state of the */ 592*22138965SBALATON Zoltan /* RAS\, RAS2\, WEn\, CASn\, DQMn, */ 593*22138965SBALATON Zoltan /* RD\, CASS\, FRAME\, RD2\ */ 594*22138965SBALATON Zoltan /* signals in standby mode and */ 595*22138965SBALATON Zoltan /* when bus is released: */ 596*22138965SBALATON Zoltan /* 0 - signals go to High-Z mode */ 597*22138965SBALATON Zoltan /* 1 - signals driven */ 59827c7ca7eSbellard #define SH7750_BCR1_A0BST 0x00003800 /* Area 0 Burst ROM Control */ 59927c7ca7eSbellard #define SH7750_BCR1_A0BST_SRAM 0x0000 /* Area 0 accessed as SRAM i/f */ 600*22138965SBALATON Zoltan #define SH7750_BCR1_A0BST_ROM4 0x0800 /* Area 0 accessed as burst ROM */ 601*22138965SBALATON Zoltan /* interface, 4 cosequtive access */ 602*22138965SBALATON Zoltan #define SH7750_BCR1_A0BST_ROM8 0x1000 /* Area 0 accessed as burst ROM */ 603*22138965SBALATON Zoltan /* interface, 8 cosequtive access */ 604*22138965SBALATON Zoltan #define SH7750_BCR1_A0BST_ROM16 0x1800 /* Area 0 accessed as burst ROM */ 605*22138965SBALATON Zoltan /* interface, 16 cosequtive access */ 606*22138965SBALATON Zoltan #define SH7750_BCR1_A0BST_ROM32 0x2000 /* Area 0 accessed as burst ROM */ 607*22138965SBALATON Zoltan /* interface, 32 cosequtive access */ 60827c7ca7eSbellard 60927c7ca7eSbellard #define SH7750_BCR1_A5BST 0x00000700 /* Area 5 Burst ROM Control */ 61027c7ca7eSbellard #define SH7750_BCR1_A5BST_SRAM 0x0000 /* Area 5 accessed as SRAM i/f */ 611*22138965SBALATON Zoltan #define SH7750_BCR1_A5BST_ROM4 0x0100 /* Area 5 accessed as burst ROM */ 612*22138965SBALATON Zoltan /* interface, 4 cosequtive access */ 613*22138965SBALATON Zoltan #define SH7750_BCR1_A5BST_ROM8 0x0200 /* Area 5 accessed as burst ROM */ 614*22138965SBALATON Zoltan /* interface, 8 cosequtive access */ 615*22138965SBALATON Zoltan #define SH7750_BCR1_A5BST_ROM16 0x0300 /* Area 5 accessed as burst ROM */ 616*22138965SBALATON Zoltan /* interface, 16 cosequtive access */ 617*22138965SBALATON Zoltan #define SH7750_BCR1_A5BST_ROM32 0x0400 /* Area 5 accessed as burst ROM */ 618*22138965SBALATON Zoltan /* interface, 32 cosequtive access */ 61927c7ca7eSbellard 62027c7ca7eSbellard #define SH7750_BCR1_A6BST 0x000000E0 /* Area 6 Burst ROM Control */ 62127c7ca7eSbellard #define SH7750_BCR1_A6BST_SRAM 0x0000 /* Area 6 accessed as SRAM i/f */ 622*22138965SBALATON Zoltan #define SH7750_BCR1_A6BST_ROM4 0x0020 /* Area 6 accessed as burst ROM */ 623*22138965SBALATON Zoltan /* interface, 4 cosequtive access */ 624*22138965SBALATON Zoltan #define SH7750_BCR1_A6BST_ROM8 0x0040 /* Area 6 accessed as burst ROM */ 625*22138965SBALATON Zoltan /* interface, 8 cosequtive access */ 626*22138965SBALATON Zoltan #define SH7750_BCR1_A6BST_ROM16 0x0060 /* Area 6 accessed as burst ROM */ 627*22138965SBALATON Zoltan /* interface, 16 cosequtive access */ 628*22138965SBALATON Zoltan #define SH7750_BCR1_A6BST_ROM32 0x0080 /* Area 6 accessed as burst ROM */ 629*22138965SBALATON Zoltan /* interface, 32 cosequtive access */ 63027c7ca7eSbellard 63127c7ca7eSbellard #define SH7750_BCR1_DRAMTP 0x001C /* Area 2 and 3 Memory Type */ 632*22138965SBALATON Zoltan #define SH7750_BCR1_DRAMTP_2SRAM_3SRAM 0x0000 /* Area 2 and 3 are SRAM or */ 633*22138965SBALATON Zoltan /* MPX interface. */ 634*22138965SBALATON Zoltan #define SH7750_BCR1_DRAMTP_2SRAM_3SDRAM 0x0008 /* Area 2 - SRAM/MPX, Area 3 */ 635*22138965SBALATON Zoltan /* synchronous DRAM */ 636*22138965SBALATON Zoltan #define SH7750_BCR1_DRAMTP_2SDRAM_3SDRAM 0x000C /* Area 2 and 3 are */ 637*22138965SBALATON Zoltan /* synchronous DRAM interface */ 638*22138965SBALATON Zoltan #define SH7750_BCR1_DRAMTP_2SRAM_3DRAM 0x0010 /* Area 2 - SRAM/MPX, Area 3 */ 639*22138965SBALATON Zoltan /* DRAM interface */ 640*22138965SBALATON Zoltan #define SH7750_BCR1_DRAMTP_2DRAM_3DRAM 0x0014 /* Area 2 and 3 are DRAM */ 641*22138965SBALATON Zoltan /* interface */ 64227c7ca7eSbellard 643*22138965SBALATON Zoltan #define SH7750_BCR1_A56PCM 0x00000001 /* Area 5 and 6 Bus Type: */ 644*22138965SBALATON Zoltan /* 0 - SRAM interface */ 645*22138965SBALATON Zoltan /* 1 - PCMCIA interface */ 64627c7ca7eSbellard 64727c7ca7eSbellard /* Bus Control Register 2 (half) - BCR2 */ 64827c7ca7eSbellard #define SH7750_BCR2_REGOFS 0x800004 /* offset */ 64927c7ca7eSbellard #define SH7750_BCR2 SH7750_P4_REG32(SH7750_BCR2_REGOFS) 65027c7ca7eSbellard #define SH7750_BCR2_A7 SH7750_A7_REG32(SH7750_BCR2_REGOFS) 65127c7ca7eSbellard 65227c7ca7eSbellard #define SH7750_BCR2_A0SZ 0xC000 /* Area 0 Bus Width */ 65327c7ca7eSbellard #define SH7750_BCR2_A0SZ_S 14 65427c7ca7eSbellard #define SH7750_BCR2_A6SZ 0x3000 /* Area 6 Bus Width */ 65527c7ca7eSbellard #define SH7750_BCR2_A6SZ_S 12 65627c7ca7eSbellard #define SH7750_BCR2_A5SZ 0x0C00 /* Area 5 Bus Width */ 65727c7ca7eSbellard #define SH7750_BCR2_A5SZ_S 10 65827c7ca7eSbellard #define SH7750_BCR2_A4SZ 0x0300 /* Area 4 Bus Width */ 65927c7ca7eSbellard #define SH7750_BCR2_A4SZ_S 8 66027c7ca7eSbellard #define SH7750_BCR2_A3SZ 0x00C0 /* Area 3 Bus Width */ 66127c7ca7eSbellard #define SH7750_BCR2_A3SZ_S 6 66227c7ca7eSbellard #define SH7750_BCR2_A2SZ 0x0030 /* Area 2 Bus Width */ 66327c7ca7eSbellard #define SH7750_BCR2_A2SZ_S 4 66427c7ca7eSbellard #define SH7750_BCR2_A1SZ 0x000C /* Area 1 Bus Width */ 66527c7ca7eSbellard #define SH7750_BCR2_A1SZ_S 2 66627c7ca7eSbellard #define SH7750_BCR2_SZ_64 0 /* 64 bits */ 66727c7ca7eSbellard #define SH7750_BCR2_SZ_8 1 /* 8 bits */ 66827c7ca7eSbellard #define SH7750_BCR2_SZ_16 2 /* 16 bits */ 66927c7ca7eSbellard #define SH7750_BCR2_SZ_32 3 /* 32 bits */ 670*22138965SBALATON Zoltan #define SH7750_BCR2_PORTEN 0x0001 /* Port Function Enable */ 671*22138965SBALATON Zoltan /* 0 - D51-D32 are not used as a port */ 672*22138965SBALATON Zoltan /* 1 - D51-D32 are used as a port */ 67327c7ca7eSbellard 67427c7ca7eSbellard /* Wait Control Register 1 - WCR1 */ 67527c7ca7eSbellard #define SH7750_WCR1_REGOFS 0x800008 /* offset */ 67627c7ca7eSbellard #define SH7750_WCR1 SH7750_P4_REG32(SH7750_WCR1_REGOFS) 67727c7ca7eSbellard #define SH7750_WCR1_A7 SH7750_A7_REG32(SH7750_WCR1_REGOFS) 678*22138965SBALATON Zoltan #define SH7750_WCR1_DMAIW 0x70000000 /* DACK Device Inter-Cycle Idle */ 679*22138965SBALATON Zoltan /* specification */ 68027c7ca7eSbellard #define SH7750_WCR1_DMAIW_S 28 68127c7ca7eSbellard #define SH7750_WCR1_A6IW 0x07000000 /* Area 6 Inter-Cycle Idle spec. */ 68227c7ca7eSbellard #define SH7750_WCR1_A6IW_S 24 68327c7ca7eSbellard #define SH7750_WCR1_A5IW 0x00700000 /* Area 5 Inter-Cycle Idle spec. */ 68427c7ca7eSbellard #define SH7750_WCR1_A5IW_S 20 68527c7ca7eSbellard #define SH7750_WCR1_A4IW 0x00070000 /* Area 4 Inter-Cycle Idle spec. */ 68627c7ca7eSbellard #define SH7750_WCR1_A4IW_S 16 68727c7ca7eSbellard #define SH7750_WCR1_A3IW 0x00007000 /* Area 3 Inter-Cycle Idle spec. */ 68827c7ca7eSbellard #define SH7750_WCR1_A3IW_S 12 68927c7ca7eSbellard #define SH7750_WCR1_A2IW 0x00000700 /* Area 2 Inter-Cycle Idle spec. */ 69027c7ca7eSbellard #define SH7750_WCR1_A2IW_S 8 69127c7ca7eSbellard #define SH7750_WCR1_A1IW 0x00000070 /* Area 1 Inter-Cycle Idle spec. */ 69227c7ca7eSbellard #define SH7750_WCR1_A1IW_S 4 69327c7ca7eSbellard #define SH7750_WCR1_A0IW 0x00000007 /* Area 0 Inter-Cycle Idle spec. */ 69427c7ca7eSbellard #define SH7750_WCR1_A0IW_S 0 69527c7ca7eSbellard 69627c7ca7eSbellard /* Wait Control Register 2 - WCR2 */ 69727c7ca7eSbellard #define SH7750_WCR2_REGOFS 0x80000C /* offset */ 69827c7ca7eSbellard #define SH7750_WCR2 SH7750_P4_REG32(SH7750_WCR2_REGOFS) 69927c7ca7eSbellard #define SH7750_WCR2_A7 SH7750_A7_REG32(SH7750_WCR2_REGOFS) 70027c7ca7eSbellard 70127c7ca7eSbellard #define SH7750_WCR2_A6W 0xE0000000 /* Area 6 Wait Control */ 70227c7ca7eSbellard #define SH7750_WCR2_A6W_S 29 70327c7ca7eSbellard #define SH7750_WCR2_A6B 0x1C000000 /* Area 6 Burst Pitch */ 70427c7ca7eSbellard #define SH7750_WCR2_A6B_S 26 70527c7ca7eSbellard #define SH7750_WCR2_A5W 0x03800000 /* Area 5 Wait Control */ 70627c7ca7eSbellard #define SH7750_WCR2_A5W_S 23 70727c7ca7eSbellard #define SH7750_WCR2_A5B 0x00700000 /* Area 5 Burst Pitch */ 70827c7ca7eSbellard #define SH7750_WCR2_A5B_S 20 70927c7ca7eSbellard #define SH7750_WCR2_A4W 0x000E0000 /* Area 4 Wait Control */ 71027c7ca7eSbellard #define SH7750_WCR2_A4W_S 17 71127c7ca7eSbellard #define SH7750_WCR2_A3W 0x0000E000 /* Area 3 Wait Control */ 71227c7ca7eSbellard #define SH7750_WCR2_A3W_S 13 71327c7ca7eSbellard #define SH7750_WCR2_A2W 0x00000E00 /* Area 2 Wait Control */ 71427c7ca7eSbellard #define SH7750_WCR2_A2W_S 9 71527c7ca7eSbellard #define SH7750_WCR2_A1W 0x000001C0 /* Area 1 Wait Control */ 71627c7ca7eSbellard #define SH7750_WCR2_A1W_S 6 71727c7ca7eSbellard #define SH7750_WCR2_A0W 0x00000038 /* Area 0 Wait Control */ 71827c7ca7eSbellard #define SH7750_WCR2_A0W_S 3 71927c7ca7eSbellard #define SH7750_WCR2_A0B 0x00000007 /* Area 0 Burst Pitch */ 72027c7ca7eSbellard #define SH7750_WCR2_A0B_S 0 72127c7ca7eSbellard 72227c7ca7eSbellard #define SH7750_WCR2_WS0 0 /* 0 wait states inserted */ 72327c7ca7eSbellard #define SH7750_WCR2_WS1 1 /* 1 wait states inserted */ 72427c7ca7eSbellard #define SH7750_WCR2_WS2 2 /* 2 wait states inserted */ 72527c7ca7eSbellard #define SH7750_WCR2_WS3 3 /* 3 wait states inserted */ 72627c7ca7eSbellard #define SH7750_WCR2_WS6 4 /* 6 wait states inserted */ 72727c7ca7eSbellard #define SH7750_WCR2_WS9 5 /* 9 wait states inserted */ 72827c7ca7eSbellard #define SH7750_WCR2_WS12 6 /* 12 wait states inserted */ 72927c7ca7eSbellard #define SH7750_WCR2_WS15 7 /* 15 wait states inserted */ 73027c7ca7eSbellard 73127c7ca7eSbellard #define SH7750_WCR2_BPWS0 0 /* 0 wait states inserted from 2nd access */ 73227c7ca7eSbellard #define SH7750_WCR2_BPWS1 1 /* 1 wait states inserted from 2nd access */ 73327c7ca7eSbellard #define SH7750_WCR2_BPWS2 2 /* 2 wait states inserted from 2nd access */ 73427c7ca7eSbellard #define SH7750_WCR2_BPWS3 3 /* 3 wait states inserted from 2nd access */ 73527c7ca7eSbellard #define SH7750_WCR2_BPWS4 4 /* 4 wait states inserted from 2nd access */ 73627c7ca7eSbellard #define SH7750_WCR2_BPWS5 5 /* 5 wait states inserted from 2nd access */ 73727c7ca7eSbellard #define SH7750_WCR2_BPWS6 6 /* 6 wait states inserted from 2nd access */ 73827c7ca7eSbellard #define SH7750_WCR2_BPWS7 7 /* 7 wait states inserted from 2nd access */ 73927c7ca7eSbellard 74027c7ca7eSbellard /* DRAM CAS\ Assertion Delay (area 3,2) */ 74127c7ca7eSbellard #define SH7750_WCR2_DRAM_CAS_ASW1 0 /* 1 cycle */ 74227c7ca7eSbellard #define SH7750_WCR2_DRAM_CAS_ASW2 1 /* 2 cycles */ 74327c7ca7eSbellard #define SH7750_WCR2_DRAM_CAS_ASW3 2 /* 3 cycles */ 74427c7ca7eSbellard #define SH7750_WCR2_DRAM_CAS_ASW4 3 /* 4 cycles */ 74527c7ca7eSbellard #define SH7750_WCR2_DRAM_CAS_ASW7 4 /* 7 cycles */ 74627c7ca7eSbellard #define SH7750_WCR2_DRAM_CAS_ASW10 5 /* 10 cycles */ 74727c7ca7eSbellard #define SH7750_WCR2_DRAM_CAS_ASW13 6 /* 13 cycles */ 74827c7ca7eSbellard #define SH7750_WCR2_DRAM_CAS_ASW16 7 /* 16 cycles */ 74927c7ca7eSbellard 75027c7ca7eSbellard /* SDRAM CAS\ Latency Cycles */ 75127c7ca7eSbellard #define SH7750_WCR2_SDRAM_CAS_LAT1 1 /* 1 cycle */ 75227c7ca7eSbellard #define SH7750_WCR2_SDRAM_CAS_LAT2 2 /* 2 cycles */ 75327c7ca7eSbellard #define SH7750_WCR2_SDRAM_CAS_LAT3 3 /* 3 cycles */ 75427c7ca7eSbellard #define SH7750_WCR2_SDRAM_CAS_LAT4 4 /* 4 cycles */ 75527c7ca7eSbellard #define SH7750_WCR2_SDRAM_CAS_LAT5 5 /* 5 cycles */ 75627c7ca7eSbellard 75727c7ca7eSbellard /* Wait Control Register 3 - WCR3 */ 75827c7ca7eSbellard #define SH7750_WCR3_REGOFS 0x800010 /* offset */ 75927c7ca7eSbellard #define SH7750_WCR3 SH7750_P4_REG32(SH7750_WCR3_REGOFS) 76027c7ca7eSbellard #define SH7750_WCR3_A7 SH7750_A7_REG32(SH7750_WCR3_REGOFS) 76127c7ca7eSbellard 76227c7ca7eSbellard #define SH7750_WCR3_A6S 0x04000000 /* Area 6 Write Strobe Setup time */ 76327c7ca7eSbellard #define SH7750_WCR3_A6H 0x03000000 /* Area 6 Data Hold Time */ 76427c7ca7eSbellard #define SH7750_WCR3_A6H_S 24 76527c7ca7eSbellard #define SH7750_WCR3_A5S 0x00400000 /* Area 5 Write Strobe Setup time */ 76627c7ca7eSbellard #define SH7750_WCR3_A5H 0x00300000 /* Area 5 Data Hold Time */ 76727c7ca7eSbellard #define SH7750_WCR3_A5H_S 20 76827c7ca7eSbellard #define SH7750_WCR3_A4S 0x00040000 /* Area 4 Write Strobe Setup time */ 76927c7ca7eSbellard #define SH7750_WCR3_A4H 0x00030000 /* Area 4 Data Hold Time */ 77027c7ca7eSbellard #define SH7750_WCR3_A4H_S 16 77127c7ca7eSbellard #define SH7750_WCR3_A3S 0x00004000 /* Area 3 Write Strobe Setup time */ 77227c7ca7eSbellard #define SH7750_WCR3_A3H 0x00003000 /* Area 3 Data Hold Time */ 77327c7ca7eSbellard #define SH7750_WCR3_A3H_S 12 77427c7ca7eSbellard #define SH7750_WCR3_A2S 0x00000400 /* Area 2 Write Strobe Setup time */ 77527c7ca7eSbellard #define SH7750_WCR3_A2H 0x00000300 /* Area 2 Data Hold Time */ 77627c7ca7eSbellard #define SH7750_WCR3_A2H_S 8 77727c7ca7eSbellard #define SH7750_WCR3_A1S 0x00000040 /* Area 1 Write Strobe Setup time */ 77827c7ca7eSbellard #define SH7750_WCR3_A1H 0x00000030 /* Area 1 Data Hold Time */ 77927c7ca7eSbellard #define SH7750_WCR3_A1H_S 4 78027c7ca7eSbellard #define SH7750_WCR3_A0S 0x00000004 /* Area 0 Write Strobe Setup time */ 78127c7ca7eSbellard #define SH7750_WCR3_A0H 0x00000003 /* Area 0 Data Hold Time */ 78227c7ca7eSbellard #define SH7750_WCR3_A0H_S 0 78327c7ca7eSbellard 78427c7ca7eSbellard #define SH7750_WCR3_DHWS_0 0 /* 0 wait states data hold time */ 78527c7ca7eSbellard #define SH7750_WCR3_DHWS_1 1 /* 1 wait states data hold time */ 78627c7ca7eSbellard #define SH7750_WCR3_DHWS_2 2 /* 2 wait states data hold time */ 78727c7ca7eSbellard #define SH7750_WCR3_DHWS_3 3 /* 3 wait states data hold time */ 78827c7ca7eSbellard 78927c7ca7eSbellard #define SH7750_MCR_REGOFS 0x800014 /* offset */ 79027c7ca7eSbellard #define SH7750_MCR SH7750_P4_REG32(SH7750_MCR_REGOFS) 79127c7ca7eSbellard #define SH7750_MCR_A7 SH7750_A7_REG32(SH7750_MCR_REGOFS) 79227c7ca7eSbellard 79327c7ca7eSbellard #define SH7750_MCR_RASD 0x80000000 /* RAS Down mode */ 79427c7ca7eSbellard #define SH7750_MCR_MRSET 0x40000000 /* SDRAM Mode Register Set */ 79527c7ca7eSbellard #define SH7750_MCR_PALL 0x00000000 /* SDRAM Precharge All cmd. Mode */ 796*22138965SBALATON Zoltan #define SH7750_MCR_TRC 0x38000000 /* RAS Precharge Time at End of */ 797*22138965SBALATON Zoltan /* Refresh: */ 79827c7ca7eSbellard #define SH7750_MCR_TRC_0 0x00000000 /* 0 */ 79927c7ca7eSbellard #define SH7750_MCR_TRC_3 0x08000000 /* 3 */ 80027c7ca7eSbellard #define SH7750_MCR_TRC_6 0x10000000 /* 6 */ 80127c7ca7eSbellard #define SH7750_MCR_TRC_9 0x18000000 /* 9 */ 80227c7ca7eSbellard #define SH7750_MCR_TRC_12 0x20000000 /* 12 */ 80327c7ca7eSbellard #define SH7750_MCR_TRC_15 0x28000000 /* 15 */ 80427c7ca7eSbellard #define SH7750_MCR_TRC_18 0x30000000 /* 18 */ 80527c7ca7eSbellard #define SH7750_MCR_TRC_21 0x38000000 /* 21 */ 80627c7ca7eSbellard 80727c7ca7eSbellard #define SH7750_MCR_TCAS 0x00800000 /* CAS Negation Period */ 80827c7ca7eSbellard #define SH7750_MCR_TCAS_1 0x00000000 /* 1 */ 80927c7ca7eSbellard #define SH7750_MCR_TCAS_2 0x00800000 /* 2 */ 81027c7ca7eSbellard 811*22138965SBALATON Zoltan #define SH7750_MCR_TPC 0x00380000 /* DRAM: RAS Precharge Period */ 812*22138965SBALATON Zoltan /* SDRAM: minimum number of cycles */ 813*22138965SBALATON Zoltan /* until the next bank active cmd */ 814*22138965SBALATON Zoltan /* is output after precharging */ 81527c7ca7eSbellard #define SH7750_MCR_TPC_S 19 81627c7ca7eSbellard #define SH7750_MCR_TPC_SDRAM_1 0x00000000 /* 1 cycle */ 81727c7ca7eSbellard #define SH7750_MCR_TPC_SDRAM_2 0x00080000 /* 2 cycles */ 81827c7ca7eSbellard #define SH7750_MCR_TPC_SDRAM_3 0x00100000 /* 3 cycles */ 81927c7ca7eSbellard #define SH7750_MCR_TPC_SDRAM_4 0x00180000 /* 4 cycles */ 82027c7ca7eSbellard #define SH7750_MCR_TPC_SDRAM_5 0x00200000 /* 5 cycles */ 82127c7ca7eSbellard #define SH7750_MCR_TPC_SDRAM_6 0x00280000 /* 6 cycles */ 82227c7ca7eSbellard #define SH7750_MCR_TPC_SDRAM_7 0x00300000 /* 7 cycles */ 82327c7ca7eSbellard #define SH7750_MCR_TPC_SDRAM_8 0x00380000 /* 8 cycles */ 82427c7ca7eSbellard 825*22138965SBALATON Zoltan #define SH7750_MCR_RCD 0x00030000 /* DRAM: RAS-CAS Assertion Delay */ 826*22138965SBALATON Zoltan /* time */ 827*22138965SBALATON Zoltan /* SDRAM: bank active-read/write */ 828*22138965SBALATON Zoltan /* command delay time */ 82927c7ca7eSbellard #define SH7750_MCR_RCD_DRAM_2 0x00000000 /* DRAM delay 2 clocks */ 83027c7ca7eSbellard #define SH7750_MCR_RCD_DRAM_3 0x00010000 /* DRAM delay 3 clocks */ 83127c7ca7eSbellard #define SH7750_MCR_RCD_DRAM_4 0x00020000 /* DRAM delay 4 clocks */ 83227c7ca7eSbellard #define SH7750_MCR_RCD_DRAM_5 0x00030000 /* DRAM delay 5 clocks */ 83327c7ca7eSbellard #define SH7750_MCR_RCD_SDRAM_2 0x00010000 /* DRAM delay 2 clocks */ 83427c7ca7eSbellard #define SH7750_MCR_RCD_SDRAM_3 0x00020000 /* DRAM delay 3 clocks */ 83527c7ca7eSbellard #define SH7750_MCR_RCD_SDRAM_4 0x00030000 /* DRAM delay 4 clocks */ 83627c7ca7eSbellard 83727c7ca7eSbellard #define SH7750_MCR_TRWL 0x0000E000 /* SDRAM Write Precharge Delay */ 83827c7ca7eSbellard #define SH7750_MCR_TRWL_1 0x00000000 /* 1 */ 83927c7ca7eSbellard #define SH7750_MCR_TRWL_2 0x00002000 /* 2 */ 84027c7ca7eSbellard #define SH7750_MCR_TRWL_3 0x00004000 /* 3 */ 84127c7ca7eSbellard #define SH7750_MCR_TRWL_4 0x00006000 /* 4 */ 84227c7ca7eSbellard #define SH7750_MCR_TRWL_5 0x00008000 /* 5 */ 84327c7ca7eSbellard 844*22138965SBALATON Zoltan #define SH7750_MCR_TRAS 0x00001C00 /* DRAM: CAS-Before-RAS Refresh RAS */ 845*22138965SBALATON Zoltan /* asserting period */ 846*22138965SBALATON Zoltan /* SDRAM: Command interval after */ 847*22138965SBALATON Zoltan /* synchronous DRAM refresh */ 84827c7ca7eSbellard #define SH7750_MCR_TRAS_DRAM_2 0x00000000 /* 2 */ 84927c7ca7eSbellard #define SH7750_MCR_TRAS_DRAM_3 0x00000400 /* 3 */ 85027c7ca7eSbellard #define SH7750_MCR_TRAS_DRAM_4 0x00000800 /* 4 */ 85127c7ca7eSbellard #define SH7750_MCR_TRAS_DRAM_5 0x00000C00 /* 5 */ 85227c7ca7eSbellard #define SH7750_MCR_TRAS_DRAM_6 0x00001000 /* 6 */ 85327c7ca7eSbellard #define SH7750_MCR_TRAS_DRAM_7 0x00001400 /* 7 */ 85427c7ca7eSbellard #define SH7750_MCR_TRAS_DRAM_8 0x00001800 /* 8 */ 85527c7ca7eSbellard #define SH7750_MCR_TRAS_DRAM_9 0x00001C00 /* 9 */ 85627c7ca7eSbellard 85727c7ca7eSbellard #define SH7750_MCR_TRAS_SDRAM_TRC_4 0x00000000 /* 4 + TRC */ 85827c7ca7eSbellard #define SH7750_MCR_TRAS_SDRAM_TRC_5 0x00000400 /* 5 + TRC */ 85927c7ca7eSbellard #define SH7750_MCR_TRAS_SDRAM_TRC_6 0x00000800 /* 6 + TRC */ 86027c7ca7eSbellard #define SH7750_MCR_TRAS_SDRAM_TRC_7 0x00000C00 /* 7 + TRC */ 86127c7ca7eSbellard #define SH7750_MCR_TRAS_SDRAM_TRC_8 0x00001000 /* 8 + TRC */ 86227c7ca7eSbellard #define SH7750_MCR_TRAS_SDRAM_TRC_9 0x00001400 /* 9 + TRC */ 86327c7ca7eSbellard #define SH7750_MCR_TRAS_SDRAM_TRC_10 0x00001800 /* 10 + TRC */ 86427c7ca7eSbellard #define SH7750_MCR_TRAS_SDRAM_TRC_11 0x00001C00 /* 11 + TRC */ 86527c7ca7eSbellard 86627c7ca7eSbellard #define SH7750_MCR_BE 0x00000200 /* Burst Enable */ 86727c7ca7eSbellard #define SH7750_MCR_SZ 0x00000180 /* Memory Data Size */ 86827c7ca7eSbellard #define SH7750_MCR_SZ_64 0x00000000 /* 64 bits */ 86927c7ca7eSbellard #define SH7750_MCR_SZ_16 0x00000100 /* 16 bits */ 87027c7ca7eSbellard #define SH7750_MCR_SZ_32 0x00000180 /* 32 bits */ 87127c7ca7eSbellard 87227c7ca7eSbellard #define SH7750_MCR_AMX 0x00000078 /* Address Multiplexing */ 87327c7ca7eSbellard #define SH7750_MCR_AMX_S 3 87427c7ca7eSbellard #define SH7750_MCR_AMX_DRAM_8BIT_COL 0x00000000 /* 8-bit column addr */ 87527c7ca7eSbellard #define SH7750_MCR_AMX_DRAM_9BIT_COL 0x00000008 /* 9-bit column addr */ 87627c7ca7eSbellard #define SH7750_MCR_AMX_DRAM_10BIT_COL 0x00000010 /* 10-bit column addr */ 87727c7ca7eSbellard #define SH7750_MCR_AMX_DRAM_11BIT_COL 0x00000018 /* 11-bit column addr */ 87827c7ca7eSbellard #define SH7750_MCR_AMX_DRAM_12BIT_COL 0x00000020 /* 12-bit column addr */ 87927c7ca7eSbellard /* See SH7750 Hardware Manual for SDRAM address multiplexor selection */ 88027c7ca7eSbellard 88127c7ca7eSbellard #define SH7750_MCR_RFSH 0x00000004 /* Refresh Control */ 88227c7ca7eSbellard #define SH7750_MCR_RMODE 0x00000002 /* Refresh Mode: */ 88327c7ca7eSbellard #define SH7750_MCR_RMODE_NORMAL 0x00000000 /* Normal Refresh Mode */ 88427c7ca7eSbellard #define SH7750_MCR_RMODE_SELF 0x00000002 /* Self-Refresh Mode */ 88527c7ca7eSbellard #define SH7750_MCR_RMODE_EDO 0x00000001 /* EDO Mode */ 88627c7ca7eSbellard 88727c7ca7eSbellard /* SDRAM Mode Set address */ 88827c7ca7eSbellard #define SH7750_SDRAM_MODE_A2_BASE 0xFF900000 88927c7ca7eSbellard #define SH7750_SDRAM_MODE_A3_BASE 0xFF940000 89027c7ca7eSbellard #define SH7750_SDRAM_MODE_A2_32BIT(x) (SH7750_SDRAM_MODE_A2_BASE + ((x) << 2)) 89127c7ca7eSbellard #define SH7750_SDRAM_MODE_A3_32BIT(x) (SH7750_SDRAM_MODE_A3_BASE + ((x) << 2)) 89227c7ca7eSbellard #define SH7750_SDRAM_MODE_A2_64BIT(x) (SH7750_SDRAM_MODE_A2_BASE + ((x) << 3)) 89327c7ca7eSbellard #define SH7750_SDRAM_MODE_A3_64BIT(x) (SH7750_SDRAM_MODE_A3_BASE + ((x) << 3)) 89427c7ca7eSbellard 89527c7ca7eSbellard 89627c7ca7eSbellard /* PCMCIA Control Register (half) - PCR */ 89727c7ca7eSbellard #define SH7750_PCR_REGOFS 0x800018 /* offset */ 89827c7ca7eSbellard #define SH7750_PCR SH7750_P4_REG32(SH7750_PCR_REGOFS) 89927c7ca7eSbellard #define SH7750_PCR_A7 SH7750_A7_REG32(SH7750_PCR_REGOFS) 90027c7ca7eSbellard 901*22138965SBALATON Zoltan #define SH7750_PCR_A5PCW 0xC000 /* Area 5 PCMCIA Wait - Number of wait */ 902*22138965SBALATON Zoltan /* states to be added to the number of */ 903*22138965SBALATON Zoltan /* waits specified by WCR2 in a */ 904*22138965SBALATON Zoltan /* low-speed PCMCIA wait cycle */ 90527c7ca7eSbellard #define SH7750_PCR_A5PCW_0 0x0000 /* 0 waits inserted */ 90627c7ca7eSbellard #define SH7750_PCR_A5PCW_15 0x4000 /* 15 waits inserted */ 90727c7ca7eSbellard #define SH7750_PCR_A5PCW_30 0x8000 /* 30 waits inserted */ 90827c7ca7eSbellard #define SH7750_PCR_A5PCW_50 0xC000 /* 50 waits inserted */ 90927c7ca7eSbellard 910*22138965SBALATON Zoltan #define SH7750_PCR_A6PCW 0x3000 /* Area 6 PCMCIA Wait - Number of wait */ 911*22138965SBALATON Zoltan /* states to be added to the number of */ 912*22138965SBALATON Zoltan /* waits specified by WCR2 in a */ 913*22138965SBALATON Zoltan /* low-speed PCMCIA wait cycle */ 91427c7ca7eSbellard #define SH7750_PCR_A6PCW_0 0x0000 /* 0 waits inserted */ 91527c7ca7eSbellard #define SH7750_PCR_A6PCW_15 0x1000 /* 15 waits inserted */ 91627c7ca7eSbellard #define SH7750_PCR_A6PCW_30 0x2000 /* 30 waits inserted */ 91727c7ca7eSbellard #define SH7750_PCR_A6PCW_50 0x3000 /* 50 waits inserted */ 91827c7ca7eSbellard 919*22138965SBALATON Zoltan #define SH7750_PCR_A5TED 0x0E00 /* Area 5 Addr-OE\/WE\ Assertion Delay */ 920*22138965SBALATON Zoltan /* delay time from address output to */ 921*22138965SBALATON Zoltan /* OE\/WE\ assertion on the connected */ 922*22138965SBALATON Zoltan /* PCMCIA interface */ 92327c7ca7eSbellard #define SH7750_PCR_A5TED_S 9 924*22138965SBALATON Zoltan #define SH7750_PCR_A6TED 0x01C0 /* Area 6 Addr-OE\/WE\ Assertion Delay */ 92527c7ca7eSbellard #define SH7750_PCR_A6TED_S 6 92627c7ca7eSbellard 92727c7ca7eSbellard #define SH7750_PCR_TED_0WS 0 /* 0 Waits inserted */ 92827c7ca7eSbellard #define SH7750_PCR_TED_1WS 1 /* 1 Waits inserted */ 92927c7ca7eSbellard #define SH7750_PCR_TED_2WS 2 /* 2 Waits inserted */ 93027c7ca7eSbellard #define SH7750_PCR_TED_3WS 3 /* 3 Waits inserted */ 93127c7ca7eSbellard #define SH7750_PCR_TED_6WS 4 /* 6 Waits inserted */ 93227c7ca7eSbellard #define SH7750_PCR_TED_9WS 5 /* 9 Waits inserted */ 93327c7ca7eSbellard #define SH7750_PCR_TED_12WS 6 /* 12 Waits inserted */ 93427c7ca7eSbellard #define SH7750_PCR_TED_15WS 7 /* 15 Waits inserted */ 93527c7ca7eSbellard 936*22138965SBALATON Zoltan #define SH7750_PCR_A5TEH 0x0038 /* Area 5 OE\/WE\ Negation Addr delay, */ 937*22138965SBALATON Zoltan /* address hold delay time from OE\/WE\ */ 938*22138965SBALATON Zoltan /* negation in a write on the connected */ 939*22138965SBALATON Zoltan /* PCMCIA interface */ 94027c7ca7eSbellard #define SH7750_PCR_A5TEH_S 3 94127c7ca7eSbellard 94227c7ca7eSbellard #define SH7750_PCR_A6TEH 0x0007 /* Area 6 OE\/WE\ Negation Address delay */ 94327c7ca7eSbellard #define SH7750_PCR_A6TEH_S 0 94427c7ca7eSbellard 94527c7ca7eSbellard #define SH7750_PCR_TEH_0WS 0 /* 0 Waits inserted */ 94627c7ca7eSbellard #define SH7750_PCR_TEH_1WS 1 /* 1 Waits inserted */ 94727c7ca7eSbellard #define SH7750_PCR_TEH_2WS 2 /* 2 Waits inserted */ 94827c7ca7eSbellard #define SH7750_PCR_TEH_3WS 3 /* 3 Waits inserted */ 94927c7ca7eSbellard #define SH7750_PCR_TEH_6WS 4 /* 6 Waits inserted */ 95027c7ca7eSbellard #define SH7750_PCR_TEH_9WS 5 /* 9 Waits inserted */ 95127c7ca7eSbellard #define SH7750_PCR_TEH_12WS 6 /* 12 Waits inserted */ 95227c7ca7eSbellard #define SH7750_PCR_TEH_15WS 7 /* 15 Waits inserted */ 95327c7ca7eSbellard 95427c7ca7eSbellard /* Refresh Timer Control/Status Register (half) - RTSCR */ 95527c7ca7eSbellard #define SH7750_RTCSR_REGOFS 0x80001C /* offset */ 95627c7ca7eSbellard #define SH7750_RTCSR SH7750_P4_REG32(SH7750_RTCSR_REGOFS) 95727c7ca7eSbellard #define SH7750_RTCSR_A7 SH7750_A7_REG32(SH7750_RTCSR_REGOFS) 95827c7ca7eSbellard 95927c7ca7eSbellard #define SH7750_RTCSR_KEY 0xA500 /* RTCSR write key */ 960*22138965SBALATON Zoltan #define SH7750_RTCSR_CMF 0x0080 /* Compare-Match Flag (indicates a */ 961*22138965SBALATON Zoltan /* match between the refresh timer */ 962*22138965SBALATON Zoltan /* counter and refresh time constant) */ 96327c7ca7eSbellard #define SH7750_RTCSR_CMIE 0x0040 /* Compare-Match Interrupt Enable */ 96427c7ca7eSbellard #define SH7750_RTCSR_CKS 0x0038 /* Refresh Counter Clock Selects */ 96527c7ca7eSbellard #define SH7750_RTCSR_CKS_DIS 0x0000 /* Clock Input Disabled */ 96627c7ca7eSbellard #define SH7750_RTCSR_CKS_CKIO_DIV4 0x0008 /* Bus Clock / 4 */ 96727c7ca7eSbellard #define SH7750_RTCSR_CKS_CKIO_DIV16 0x0010 /* Bus Clock / 16 */ 96827c7ca7eSbellard #define SH7750_RTCSR_CKS_CKIO_DIV64 0x0018 /* Bus Clock / 64 */ 96927c7ca7eSbellard #define SH7750_RTCSR_CKS_CKIO_DIV256 0x0020 /* Bus Clock / 256 */ 97027c7ca7eSbellard #define SH7750_RTCSR_CKS_CKIO_DIV1024 0x0028 /* Bus Clock / 1024 */ 97127c7ca7eSbellard #define SH7750_RTCSR_CKS_CKIO_DIV2048 0x0030 /* Bus Clock / 2048 */ 97227c7ca7eSbellard #define SH7750_RTCSR_CKS_CKIO_DIV4096 0x0038 /* Bus Clock / 4096 */ 97327c7ca7eSbellard 97427c7ca7eSbellard #define SH7750_RTCSR_OVF 0x0004 /* Refresh Count Overflow Flag */ 975*22138965SBALATON Zoltan #define SH7750_RTCSR_OVIE 0x0002 /* Refresh Count Overflow Interrupt */ 976*22138965SBALATON Zoltan /* Enable */ 97727c7ca7eSbellard #define SH7750_RTCSR_LMTS 0x0001 /* Refresh Count Overflow Limit Select */ 97827c7ca7eSbellard #define SH7750_RTCSR_LMTS_1024 0x0000 /* Count Limit is 1024 */ 97927c7ca7eSbellard #define SH7750_RTCSR_LMTS_512 0x0001 /* Count Limit is 512 */ 98027c7ca7eSbellard 98127c7ca7eSbellard /* Refresh Timer Counter (half) - RTCNT */ 98227c7ca7eSbellard #define SH7750_RTCNT_REGOFS 0x800020 /* offset */ 98327c7ca7eSbellard #define SH7750_RTCNT SH7750_P4_REG32(SH7750_RTCNT_REGOFS) 98427c7ca7eSbellard #define SH7750_RTCNT_A7 SH7750_A7_REG32(SH7750_RTCNT_REGOFS) 98527c7ca7eSbellard 98627c7ca7eSbellard #define SH7750_RTCNT_KEY 0xA500 /* RTCNT write key */ 98727c7ca7eSbellard 98827c7ca7eSbellard /* Refresh Time Constant Register (half) - RTCOR */ 98927c7ca7eSbellard #define SH7750_RTCOR_REGOFS 0x800024 /* offset */ 99027c7ca7eSbellard #define SH7750_RTCOR SH7750_P4_REG32(SH7750_RTCOR_REGOFS) 99127c7ca7eSbellard #define SH7750_RTCOR_A7 SH7750_A7_REG32(SH7750_RTCOR_REGOFS) 99227c7ca7eSbellard 99327c7ca7eSbellard #define SH7750_RTCOR_KEY 0xA500 /* RTCOR write key */ 99427c7ca7eSbellard 99527c7ca7eSbellard /* Refresh Count Register (half) - RFCR */ 99627c7ca7eSbellard #define SH7750_RFCR_REGOFS 0x800028 /* offset */ 99727c7ca7eSbellard #define SH7750_RFCR SH7750_P4_REG32(SH7750_RFCR_REGOFS) 99827c7ca7eSbellard #define SH7750_RFCR_A7 SH7750_A7_REG32(SH7750_RFCR_REGOFS) 99927c7ca7eSbellard 100027c7ca7eSbellard #define SH7750_RFCR_KEY 0xA400 /* RFCR write key */ 100127c7ca7eSbellard 1002c2432a42Saurel32 /* Synchronous DRAM mode registers - SDMR */ 1003c2432a42Saurel32 #define SH7750_SDMR2_REGOFS 0x900000 /* base offset */ 1004c2432a42Saurel32 #define SH7750_SDMR2_REGNB 0x0FFC /* nb of register */ 1005c2432a42Saurel32 #define SH7750_SDMR2 SH7750_P4_REG32(SH7750_SDMR2_REGOFS) 1006c2432a42Saurel32 #define SH7750_SDMR2_A7 SH7750_A7_REG32(SH7750_SDMR2_REGOFS) 1007c2432a42Saurel32 1008c2432a42Saurel32 #define SH7750_SDMR3_REGOFS 0x940000 /* offset */ 1009c2432a42Saurel32 #define SH7750_SDMR3_REGNB 0x0FFC /* nb of register */ 1010c2432a42Saurel32 #define SH7750_SDMR3 SH7750_P4_REG32(SH7750_SDMR3_REGOFS) 1011c2432a42Saurel32 #define SH7750_SDMR3_A7 SH7750_A7_REG32(SH7750_SDMR3_REGOFS) 1012c2432a42Saurel32 101327c7ca7eSbellard /* 101427c7ca7eSbellard * Direct Memory Access Controller (DMAC) 101527c7ca7eSbellard */ 101627c7ca7eSbellard 101727c7ca7eSbellard /* DMA Source Address Register - SAR0, SAR1, SAR2, SAR3 */ 101827c7ca7eSbellard #define SH7750_SAR_REGOFS(n) (0xA00000 + ((n)*16)) /* offset */ 101927c7ca7eSbellard #define SH7750_SAR(n) SH7750_P4_REG32(SH7750_SAR_REGOFS(n)) 102027c7ca7eSbellard #define SH7750_SAR_A7(n) SH7750_A7_REG32(SH7750_SAR_REGOFS(n)) 102127c7ca7eSbellard #define SH7750_SAR0 SH7750_SAR(0) 102227c7ca7eSbellard #define SH7750_SAR1 SH7750_SAR(1) 102327c7ca7eSbellard #define SH7750_SAR2 SH7750_SAR(2) 102427c7ca7eSbellard #define SH7750_SAR3 SH7750_SAR(3) 102527c7ca7eSbellard #define SH7750_SAR0_A7 SH7750_SAR_A7(0) 102627c7ca7eSbellard #define SH7750_SAR1_A7 SH7750_SAR_A7(1) 102727c7ca7eSbellard #define SH7750_SAR2_A7 SH7750_SAR_A7(2) 102827c7ca7eSbellard #define SH7750_SAR3_A7 SH7750_SAR_A7(3) 102927c7ca7eSbellard 103027c7ca7eSbellard /* DMA Destination Address Register - DAR0, DAR1, DAR2, DAR3 */ 103127c7ca7eSbellard #define SH7750_DAR_REGOFS(n) (0xA00004 + ((n)*16)) /* offset */ 103227c7ca7eSbellard #define SH7750_DAR(n) SH7750_P4_REG32(SH7750_DAR_REGOFS(n)) 103327c7ca7eSbellard #define SH7750_DAR_A7(n) SH7750_A7_REG32(SH7750_DAR_REGOFS(n)) 103427c7ca7eSbellard #define SH7750_DAR0 SH7750_DAR(0) 103527c7ca7eSbellard #define SH7750_DAR1 SH7750_DAR(1) 103627c7ca7eSbellard #define SH7750_DAR2 SH7750_DAR(2) 103727c7ca7eSbellard #define SH7750_DAR3 SH7750_DAR(3) 103827c7ca7eSbellard #define SH7750_DAR0_A7 SH7750_DAR_A7(0) 103927c7ca7eSbellard #define SH7750_DAR1_A7 SH7750_DAR_A7(1) 104027c7ca7eSbellard #define SH7750_DAR2_A7 SH7750_DAR_A7(2) 104127c7ca7eSbellard #define SH7750_DAR3_A7 SH7750_DAR_A7(3) 104227c7ca7eSbellard 104327c7ca7eSbellard /* DMA Transfer Count Register - DMATCR0, DMATCR1, DMATCR2, DMATCR3 */ 104427c7ca7eSbellard #define SH7750_DMATCR_REGOFS(n) (0xA00008 + ((n)*16)) /* offset */ 104527c7ca7eSbellard #define SH7750_DMATCR(n) SH7750_P4_REG32(SH7750_DMATCR_REGOFS(n)) 104627c7ca7eSbellard #define SH7750_DMATCR_A7(n) SH7750_A7_REG32(SH7750_DMATCR_REGOFS(n)) 104727c7ca7eSbellard #define SH7750_DMATCR0_P4 SH7750_DMATCR(0) 104827c7ca7eSbellard #define SH7750_DMATCR1_P4 SH7750_DMATCR(1) 104927c7ca7eSbellard #define SH7750_DMATCR2_P4 SH7750_DMATCR(2) 105027c7ca7eSbellard #define SH7750_DMATCR3_P4 SH7750_DMATCR(3) 105127c7ca7eSbellard #define SH7750_DMATCR0_A7 SH7750_DMATCR_A7(0) 105227c7ca7eSbellard #define SH7750_DMATCR1_A7 SH7750_DMATCR_A7(1) 105327c7ca7eSbellard #define SH7750_DMATCR2_A7 SH7750_DMATCR_A7(2) 105427c7ca7eSbellard #define SH7750_DMATCR3_A7 SH7750_DMATCR_A7(3) 105527c7ca7eSbellard 105627c7ca7eSbellard /* DMA Channel Control Register - CHCR0, CHCR1, CHCR2, CHCR3 */ 105727c7ca7eSbellard #define SH7750_CHCR_REGOFS(n) (0xA0000C + ((n)*16)) /* offset */ 105827c7ca7eSbellard #define SH7750_CHCR(n) SH7750_P4_REG32(SH7750_CHCR_REGOFS(n)) 105927c7ca7eSbellard #define SH7750_CHCR_A7(n) SH7750_A7_REG32(SH7750_CHCR_REGOFS(n)) 106027c7ca7eSbellard #define SH7750_CHCR0 SH7750_CHCR(0) 106127c7ca7eSbellard #define SH7750_CHCR1 SH7750_CHCR(1) 106227c7ca7eSbellard #define SH7750_CHCR2 SH7750_CHCR(2) 106327c7ca7eSbellard #define SH7750_CHCR3 SH7750_CHCR(3) 106427c7ca7eSbellard #define SH7750_CHCR0_A7 SH7750_CHCR_A7(0) 106527c7ca7eSbellard #define SH7750_CHCR1_A7 SH7750_CHCR_A7(1) 106627c7ca7eSbellard #define SH7750_CHCR2_A7 SH7750_CHCR_A7(2) 106727c7ca7eSbellard #define SH7750_CHCR3_A7 SH7750_CHCR_A7(3) 106827c7ca7eSbellard 106927c7ca7eSbellard #define SH7750_CHCR_SSA 0xE0000000 /* Source Address Space Attribute */ 107027c7ca7eSbellard #define SH7750_CHCR_SSA_PCMCIA 0x00000000 /* Reserved in PCMCIA access */ 107127c7ca7eSbellard #define SH7750_CHCR_SSA_DYNBSZ 0x20000000 /* Dynamic Bus Sizing I/O space */ 107227c7ca7eSbellard #define SH7750_CHCR_SSA_IO8 0x40000000 /* 8-bit I/O space */ 107327c7ca7eSbellard #define SH7750_CHCR_SSA_IO16 0x60000000 /* 16-bit I/O space */ 107427c7ca7eSbellard #define SH7750_CHCR_SSA_CMEM8 0x80000000 /* 8-bit common memory space */ 107527c7ca7eSbellard #define SH7750_CHCR_SSA_CMEM16 0xA0000000 /* 16-bit common memory space */ 107627c7ca7eSbellard #define SH7750_CHCR_SSA_AMEM8 0xC0000000 /* 8-bit attribute memory space */ 107727c7ca7eSbellard #define SH7750_CHCR_SSA_AMEM16 0xE0000000 /* 16-bit attribute memory space */ 107827c7ca7eSbellard 1079*22138965SBALATON Zoltan #define SH7750_CHCR_STC 0x10000000 /* Source Addr Wait Control Select */ 1080*22138965SBALATON Zoltan /* specifies CS5 or CS6 space wait */ 1081*22138965SBALATON Zoltan /* control for PCMCIA access */ 108227c7ca7eSbellard 108327c7ca7eSbellard #define SH7750_CHCR_DSA 0x0E000000 /* Source Address Space Attribute */ 108427c7ca7eSbellard #define SH7750_CHCR_DSA_PCMCIA 0x00000000 /* Reserved in PCMCIA access */ 108527c7ca7eSbellard #define SH7750_CHCR_DSA_DYNBSZ 0x02000000 /* Dynamic Bus Sizing I/O space */ 108627c7ca7eSbellard #define SH7750_CHCR_DSA_IO8 0x04000000 /* 8-bit I/O space */ 108727c7ca7eSbellard #define SH7750_CHCR_DSA_IO16 0x06000000 /* 16-bit I/O space */ 108827c7ca7eSbellard #define SH7750_CHCR_DSA_CMEM8 0x08000000 /* 8-bit common memory space */ 108927c7ca7eSbellard #define SH7750_CHCR_DSA_CMEM16 0x0A000000 /* 16-bit common memory space */ 109027c7ca7eSbellard #define SH7750_CHCR_DSA_AMEM8 0x0C000000 /* 8-bit attribute memory space */ 109127c7ca7eSbellard #define SH7750_CHCR_DSA_AMEM16 0x0E000000 /* 16-bit attribute memory space */ 109227c7ca7eSbellard 1093*22138965SBALATON Zoltan #define SH7750_CHCR_DTC 0x01000000 /* Destination Address Wait Control */ 1094*22138965SBALATON Zoltan /* Select, specifies CS5 or CS6 */ 1095*22138965SBALATON Zoltan /* space wait control for PCMCIA */ 1096*22138965SBALATON Zoltan /* access */ 109727c7ca7eSbellard 109827c7ca7eSbellard #define SH7750_CHCR_DS 0x00080000 /* DREQ\ Select : */ 109927c7ca7eSbellard #define SH7750_CHCR_DS_LOWLVL 0x00000000 /* Low Level Detection */ 110027c7ca7eSbellard #define SH7750_CHCR_DS_FALL 0x00080000 /* Falling Edge Detection */ 110127c7ca7eSbellard 110227c7ca7eSbellard #define SH7750_CHCR_RL 0x00040000 /* Request Check Level: */ 110327c7ca7eSbellard #define SH7750_CHCR_RL_ACTH 0x00000000 /* DRAK is an active high out */ 110427c7ca7eSbellard #define SH7750_CHCR_RL_ACTL 0x00040000 /* DRAK is an active low out */ 110527c7ca7eSbellard 110627c7ca7eSbellard #define SH7750_CHCR_AM 0x00020000 /* Acknowledge Mode: */ 110727c7ca7eSbellard #define SH7750_CHCR_AM_RD 0x00000000 /* DACK is output in read cycle */ 110827c7ca7eSbellard #define SH7750_CHCR_AM_WR 0x00020000 /* DACK is output in write cycle */ 110927c7ca7eSbellard 111027c7ca7eSbellard #define SH7750_CHCR_AL 0x00010000 /* Acknowledge Level: */ 111127c7ca7eSbellard #define SH7750_CHCR_AL_ACTH 0x00000000 /* DACK is an active high out */ 111227c7ca7eSbellard #define SH7750_CHCR_AL_ACTL 0x00010000 /* DACK is an active low out */ 111327c7ca7eSbellard 111427c7ca7eSbellard #define SH7750_CHCR_DM 0x0000C000 /* Destination Address Mode: */ 111527c7ca7eSbellard #define SH7750_CHCR_DM_FIX 0x00000000 /* Destination Addr Fixed */ 111627c7ca7eSbellard #define SH7750_CHCR_DM_INC 0x00004000 /* Destination Addr Incremented */ 111727c7ca7eSbellard #define SH7750_CHCR_DM_DEC 0x00008000 /* Destination Addr Decremented */ 111827c7ca7eSbellard 111927c7ca7eSbellard #define SH7750_CHCR_SM 0x00003000 /* Source Address Mode: */ 112027c7ca7eSbellard #define SH7750_CHCR_SM_FIX 0x00000000 /* Source Addr Fixed */ 112127c7ca7eSbellard #define SH7750_CHCR_SM_INC 0x00001000 /* Source Addr Incremented */ 112227c7ca7eSbellard #define SH7750_CHCR_SM_DEC 0x00002000 /* Source Addr Decremented */ 112327c7ca7eSbellard 112427c7ca7eSbellard #define SH7750_CHCR_RS 0x00000F00 /* Request Source Select: */ 1125*22138965SBALATON Zoltan #define SH7750_CHCR_RS_ER_DA_EA_TO_EA 0x000 /* External Request, Dual Addr */ 1126*22138965SBALATON Zoltan /* Mode, External Addr Space */ 1127*22138965SBALATON Zoltan /* -> External Addr Space) */ 1128*22138965SBALATON Zoltan #define SH7750_CHCR_RS_ER_SA_EA_TO_ED 0x200 /* External Request, Single */ 1129*22138965SBALATON Zoltan /* Address Mode (Ext. Addr */ 1130*22138965SBALATON Zoltan /* Space -> External Device) */ 1131*22138965SBALATON Zoltan #define SH7750_CHCR_RS_ER_SA_ED_TO_EA 0x300 /* External Request, Single */ 1132*22138965SBALATON Zoltan /* Address Mode, (External */ 1133*22138965SBALATON Zoltan /* Device -> External Addr */ 1134*22138965SBALATON Zoltan /* Space) */ 1135*22138965SBALATON Zoltan #define SH7750_CHCR_RS_AR_EA_TO_EA 0x400 /* Auto-Request (External Addr */ 1136*22138965SBALATON Zoltan /* Space -> Ext. Addr Space) */ 113727c7ca7eSbellard 1138*22138965SBALATON Zoltan #define SH7750_CHCR_RS_AR_EA_TO_OCP 0x500 /* Auto-Request (External Addr */ 1139*22138965SBALATON Zoltan /* Space -> On-chip */ 1140*22138965SBALATON Zoltan /* Peripheral Module) */ 1141*22138965SBALATON Zoltan #define SH7750_CHCR_RS_AR_OCP_TO_EA 0x600 /* Auto-Request (On-chip */ 1142*22138965SBALATON Zoltan /* Peripheral Module -> */ 1143*22138965SBALATON Zoltan /* External Addr Space */ 1144*22138965SBALATON Zoltan #define SH7750_CHCR_RS_SCITX_EA_TO_SC 0x800 /* SCI Transmit-Data-Empty intr */ 1145*22138965SBALATON Zoltan /* transfer request (external */ 1146*22138965SBALATON Zoltan /* address space -> SCTDR1) */ 1147*22138965SBALATON Zoltan #define SH7750_CHCR_RS_SCIRX_SC_TO_EA 0x900 /* SCI Receive-Data-Full intr */ 1148*22138965SBALATON Zoltan /* transfer request (SCRDR1 */ 1149*22138965SBALATON Zoltan /* -> External Addr Space) */ 1150*22138965SBALATON Zoltan #define SH7750_CHCR_RS_SCIFTX_EA_TO_SC 0xA00 /* SCIF TX-Data-Empty intr */ 1151*22138965SBALATON Zoltan /* transfer request (external */ 1152*22138965SBALATON Zoltan /* address space -> SCFTDR1) */ 1153*22138965SBALATON Zoltan #define SH7750_CHCR_RS_SCIFRX_SC_TO_EA 0xB00 /* SCIF Receive-Data-Full intr */ 1154*22138965SBALATON Zoltan /* transfer request (SCFRDR2 */ 1155*22138965SBALATON Zoltan /* -> External Addr Space) */ 1156*22138965SBALATON Zoltan #define SH7750_CHCR_RS_TMU2_EA_TO_EA 0xC00 /* TMU Channel 2 (input capture */ 1157*22138965SBALATON Zoltan /* interrupt), (external */ 1158*22138965SBALATON Zoltan /* address space -> external */ 1159*22138965SBALATON Zoltan /* address space) */ 1160*22138965SBALATON Zoltan #define SH7750_CHCR_RS_TMU2_EA_TO_OCP 0xD00 /* TMU Channel 2 (input capture */ 1161*22138965SBALATON Zoltan /* interrupt), (external */ 1162*22138965SBALATON Zoltan /* address space -> on-chip */ 1163*22138965SBALATON Zoltan /* peripheral module) */ 1164*22138965SBALATON Zoltan #define SH7750_CHCR_RS_TMU2_OCP_TO_EA 0xE00 /* TMU Channel 2 (input capture */ 1165*22138965SBALATON Zoltan /* interrupt), (on-chip */ 1166*22138965SBALATON Zoltan /* peripheral module -> */ 1167*22138965SBALATON Zoltan /* external address space) */ 116827c7ca7eSbellard 116927c7ca7eSbellard #define SH7750_CHCR_TM 0x00000080 /* Transmit mode: */ 117027c7ca7eSbellard #define SH7750_CHCR_TM_CSTEAL 0x00000000 /* Cycle Steal Mode */ 117127c7ca7eSbellard #define SH7750_CHCR_TM_BURST 0x00000080 /* Burst Mode */ 117227c7ca7eSbellard 117327c7ca7eSbellard #define SH7750_CHCR_TS 0x00000070 /* Transmit Size: */ 117427c7ca7eSbellard #define SH7750_CHCR_TS_QUAD 0x00000000 /* Quadword Size (64 bits) */ 117527c7ca7eSbellard #define SH7750_CHCR_TS_BYTE 0x00000010 /* Byte Size (8 bit) */ 117627c7ca7eSbellard #define SH7750_CHCR_TS_WORD 0x00000020 /* Word Size (16 bit) */ 117727c7ca7eSbellard #define SH7750_CHCR_TS_LONG 0x00000030 /* Longword Size (32 bit) */ 117827c7ca7eSbellard #define SH7750_CHCR_TS_BLOCK 0x00000040 /* 32-byte block transfer */ 117927c7ca7eSbellard 118027c7ca7eSbellard #define SH7750_CHCR_IE 0x00000004 /* Interrupt Enable */ 118127c7ca7eSbellard #define SH7750_CHCR_TE 0x00000002 /* Transfer End */ 118227c7ca7eSbellard #define SH7750_CHCR_DE 0x00000001 /* DMAC Enable */ 118327c7ca7eSbellard 118427c7ca7eSbellard /* DMA Operation Register - DMAOR */ 118527c7ca7eSbellard #define SH7750_DMAOR_REGOFS 0xA00040 /* offset */ 118627c7ca7eSbellard #define SH7750_DMAOR SH7750_P4_REG32(SH7750_DMAOR_REGOFS) 118727c7ca7eSbellard #define SH7750_DMAOR_A7 SH7750_A7_REG32(SH7750_DMAOR_REGOFS) 118827c7ca7eSbellard 118927c7ca7eSbellard #define SH7750_DMAOR_DDT 0x00008000 /* On-Demand Data Transfer Mode */ 119027c7ca7eSbellard 119127c7ca7eSbellard #define SH7750_DMAOR_PR 0x00000300 /* Priority Mode: */ 119227c7ca7eSbellard #define SH7750_DMAOR_PR_0123 0x00000000 /* CH0 > CH1 > CH2 > CH3 */ 119327c7ca7eSbellard #define SH7750_DMAOR_PR_0231 0x00000100 /* CH0 > CH2 > CH3 > CH1 */ 119427c7ca7eSbellard #define SH7750_DMAOR_PR_2013 0x00000200 /* CH2 > CH0 > CH1 > CH3 */ 119527c7ca7eSbellard #define SH7750_DMAOR_PR_RR 0x00000300 /* Round-robin mode */ 119627c7ca7eSbellard 119727c7ca7eSbellard #define SH7750_DMAOR_COD 0x00000010 /* Check Overrun for DREQ\ */ 119827c7ca7eSbellard #define SH7750_DMAOR_AE 0x00000004 /* Address Error flag */ 119927c7ca7eSbellard #define SH7750_DMAOR_NMIF 0x00000002 /* NMI Flag */ 120027c7ca7eSbellard #define SH7750_DMAOR_DME 0x00000001 /* DMAC Master Enable */ 120127c7ca7eSbellard 120227c7ca7eSbellard /* 120327c7ca7eSbellard * I/O Ports 120427c7ca7eSbellard */ 120527c7ca7eSbellard /* Port Control Register A - PCTRA */ 120627c7ca7eSbellard #define SH7750_PCTRA_REGOFS 0x80002C /* offset */ 120727c7ca7eSbellard #define SH7750_PCTRA SH7750_P4_REG32(SH7750_PCTRA_REGOFS) 120827c7ca7eSbellard #define SH7750_PCTRA_A7 SH7750_A7_REG32(SH7750_PCTRA_REGOFS) 120927c7ca7eSbellard 121027c7ca7eSbellard #define SH7750_PCTRA_PBPUP(n) 0 /* Bit n is pulled up */ 121127c7ca7eSbellard #define SH7750_PCTRA_PBNPUP(n) (1 << ((n)*2+1)) /* Bit n is not pulled up */ 121227c7ca7eSbellard #define SH7750_PCTRA_PBINP(n) 0 /* Bit n is an input */ 121327c7ca7eSbellard #define SH7750_PCTRA_PBOUT(n) (1 << ((n)*2)) /* Bit n is an output */ 121427c7ca7eSbellard 121527c7ca7eSbellard /* Port Data Register A - PDTRA(half) */ 121627c7ca7eSbellard #define SH7750_PDTRA_REGOFS 0x800030 /* offset */ 121727c7ca7eSbellard #define SH7750_PDTRA SH7750_P4_REG32(SH7750_PDTRA_REGOFS) 121827c7ca7eSbellard #define SH7750_PDTRA_A7 SH7750_A7_REG32(SH7750_PDTRA_REGOFS) 121927c7ca7eSbellard 122027c7ca7eSbellard #define SH7750_PDTRA_BIT(n) (1 << (n)) 122127c7ca7eSbellard 122227c7ca7eSbellard /* Port Control Register B - PCTRB */ 122327c7ca7eSbellard #define SH7750_PCTRB_REGOFS 0x800040 /* offset */ 122427c7ca7eSbellard #define SH7750_PCTRB SH7750_P4_REG32(SH7750_PCTRB_REGOFS) 122527c7ca7eSbellard #define SH7750_PCTRB_A7 SH7750_A7_REG32(SH7750_PCTRB_REGOFS) 122627c7ca7eSbellard 122727c7ca7eSbellard #define SH7750_PCTRB_PBPUP(n) 0 /* Bit n is pulled up */ 122827c7ca7eSbellard #define SH7750_PCTRB_PBNPUP(n) (1 << ((n-16)*2+1)) /* Bit n is not pulled up */ 122927c7ca7eSbellard #define SH7750_PCTRB_PBINP(n) 0 /* Bit n is an input */ 123027c7ca7eSbellard #define SH7750_PCTRB_PBOUT(n) (1 << ((n-16)*2)) /* Bit n is an output */ 123127c7ca7eSbellard 123227c7ca7eSbellard /* Port Data Register B - PDTRB(half) */ 123327c7ca7eSbellard #define SH7750_PDTRB_REGOFS 0x800044 /* offset */ 123427c7ca7eSbellard #define SH7750_PDTRB SH7750_P4_REG32(SH7750_PDTRB_REGOFS) 123527c7ca7eSbellard #define SH7750_PDTRB_A7 SH7750_A7_REG32(SH7750_PDTRB_REGOFS) 123627c7ca7eSbellard 123727c7ca7eSbellard #define SH7750_PDTRB_BIT(n) (1 << ((n)-16)) 123827c7ca7eSbellard 123927c7ca7eSbellard /* GPIO Interrupt Control Register - GPIOIC(half) */ 124027c7ca7eSbellard #define SH7750_GPIOIC_REGOFS 0x800048 /* offset */ 124127c7ca7eSbellard #define SH7750_GPIOIC SH7750_P4_REG32(SH7750_GPIOIC_REGOFS) 124227c7ca7eSbellard #define SH7750_GPIOIC_A7 SH7750_A7_REG32(SH7750_GPIOIC_REGOFS) 124327c7ca7eSbellard 124427c7ca7eSbellard #define SH7750_GPIOIC_PTIREN(n) (1 << (n)) /* Port n is used as a GPIO int */ 124527c7ca7eSbellard 124627c7ca7eSbellard /* 124727c7ca7eSbellard * Interrupt Controller - INTC 124827c7ca7eSbellard */ 124927c7ca7eSbellard /* Interrupt Control Register - ICR (half) */ 125027c7ca7eSbellard #define SH7750_ICR_REGOFS 0xD00000 /* offset */ 125127c7ca7eSbellard #define SH7750_ICR SH7750_P4_REG32(SH7750_ICR_REGOFS) 125227c7ca7eSbellard #define SH7750_ICR_A7 SH7750_A7_REG32(SH7750_ICR_REGOFS) 125327c7ca7eSbellard 125427c7ca7eSbellard #define SH7750_ICR_NMIL 0x8000 /* NMI Input Level */ 125527c7ca7eSbellard #define SH7750_ICR_MAI 0x4000 /* NMI Interrupt Mask */ 125627c7ca7eSbellard 125727c7ca7eSbellard #define SH7750_ICR_NMIB 0x0200 /* NMI Block Mode: */ 1258*22138965SBALATON Zoltan #define SH7750_ICR_NMIB_BLK 0x0000 /* NMI requests held pending while */ 1259*22138965SBALATON Zoltan /* SR.BL bit is set to 1 */ 1260*22138965SBALATON Zoltan #define SH7750_ICR_NMIB_NBLK 0x0200 /* NMI requests detected when SR.BL */ 1261*22138965SBALATON Zoltan /* bit set to 1 */ 126227c7ca7eSbellard 126327c7ca7eSbellard #define SH7750_ICR_NMIE 0x0100 /* NMI Edge Select: */ 1264*22138965SBALATON Zoltan #define SH7750_ICR_NMIE_FALL 0x0000 /* Interrupt request detected on */ 1265*22138965SBALATON Zoltan /* falling edge of NMI input */ 1266*22138965SBALATON Zoltan #define SH7750_ICR_NMIE_RISE 0x0100 /* Interrupt request detected on */ 1267*22138965SBALATON Zoltan /* rising edge of NMI input */ 126827c7ca7eSbellard 126927c7ca7eSbellard #define SH7750_ICR_IRLM 0x0080 /* IRL Pin Mode: */ 1270*22138965SBALATON Zoltan #define SH7750_ICR_IRLM_ENC 0x0000 /* IRL\ pins used as a level-encoded */ 1271*22138965SBALATON Zoltan /* interrupt requests */ 1272*22138965SBALATON Zoltan #define SH7750_ICR_IRLM_RAW 0x0080 /* IRL\ pins used as a four */ 1273*22138965SBALATON Zoltan /* independent interrupt requests */ 127427c7ca7eSbellard 127527c7ca7eSbellard /* 127627c7ca7eSbellard * User Break Controller registers 127727c7ca7eSbellard */ 127827c7ca7eSbellard #define SH7750_BARA 0x200000 /* Break address regiser A */ 127927c7ca7eSbellard #define SH7750_BAMRA 0x200004 /* Break address mask regiser A */ 128027c7ca7eSbellard #define SH7750_BBRA 0x200008 /* Break bus cycle regiser A */ 128127c7ca7eSbellard #define SH7750_BARB 0x20000c /* Break address regiser B */ 128227c7ca7eSbellard #define SH7750_BAMRB 0x200010 /* Break address mask regiser B */ 128327c7ca7eSbellard #define SH7750_BBRB 0x200014 /* Break bus cycle regiser B */ 128427c7ca7eSbellard #define SH7750_BASRB 0x000018 /* Break ASID regiser B */ 128527c7ca7eSbellard #define SH7750_BDRB 0x200018 /* Break data regiser B */ 128627c7ca7eSbellard #define SH7750_BDMRB 0x20001c /* Break data mask regiser B */ 128727c7ca7eSbellard #define SH7750_BRCR 0x200020 /* Break control register */ 128827c7ca7eSbellard 128927c7ca7eSbellard #define SH7750_BRCR_UDBE 0x0001 /* User break debug enable bit */ 129027c7ca7eSbellard 129127c7ca7eSbellard /* 129227c7ca7eSbellard * Missing in RTEMS, added for QEMU 129327c7ca7eSbellard */ 129427c7ca7eSbellard #define SH7750_BCR3_A7 0x1f800050 129527c7ca7eSbellard #define SH7750_BCR4_A7 0x1e0a00f0 129627c7ca7eSbellard 129727c7ca7eSbellard #endif 1298