1 /* 2 * SH7750 device 3 * 4 * Copyright (c) 2007 Magnus Damm 5 * Copyright (c) 2005 Samuel Tardieu 6 * 7 * Permission is hereby granted, free of charge, to any person obtaining a copy 8 * of this software and associated documentation files (the "Software"), to deal 9 * in the Software without restriction, including without limitation the rights 10 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 11 * copies of the Software, and to permit persons to whom the Software is 12 * furnished to do so, subject to the following conditions: 13 * 14 * The above copyright notice and this permission notice shall be included in 15 * all copies or substantial portions of the Software. 16 * 17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 22 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 23 * THE SOFTWARE. 24 */ 25 26 #include "qemu/osdep.h" 27 #include "qapi/error.h" 28 #include "hw/sysbus.h" 29 #include "hw/irq.h" 30 #include "hw/sh4/sh.h" 31 #include "system/system.h" 32 #include "target/sh4/cpu.h" 33 #include "hw/qdev-properties.h" 34 #include "hw/qdev-properties-system.h" 35 #include "sh7750_regs.h" 36 #include "sh7750_regnames.h" 37 #include "hw/sh4/sh_intc.h" 38 #include "hw/timer/tmu012.h" 39 #include "exec/exec-all.h" 40 #include "exec/cputlb.h" 41 #include "trace.h" 42 43 typedef struct SH7750State { 44 MemoryRegion iomem; 45 MemoryRegion iomem_1f0; 46 MemoryRegion iomem_ff0; 47 MemoryRegion iomem_1f8; 48 MemoryRegion iomem_ff8; 49 MemoryRegion iomem_1fc; 50 MemoryRegion iomem_ffc; 51 MemoryRegion mmct_iomem; 52 /* CPU */ 53 SuperHCPU *cpu; 54 /* Peripheral frequency in Hz */ 55 uint32_t periph_freq; 56 /* SDRAM controller */ 57 uint32_t bcr1; 58 uint16_t bcr2; 59 uint16_t bcr3; 60 uint32_t bcr4; 61 uint16_t rfcr; 62 /* PCMCIA controller */ 63 uint16_t pcr; 64 /* IO ports */ 65 uint16_t gpioic; 66 uint32_t pctra; 67 uint32_t pctrb; 68 uint16_t portdira; /* Cached */ 69 uint16_t portpullupa; /* Cached */ 70 uint16_t portdirb; /* Cached */ 71 uint16_t portpullupb; /* Cached */ 72 uint16_t pdtra; 73 uint16_t pdtrb; 74 uint16_t periph_pdtra; /* Imposed by the peripherals */ 75 uint16_t periph_portdira; /* Direction seen from the peripherals */ 76 uint16_t periph_pdtrb; /* Imposed by the peripherals */ 77 uint16_t periph_portdirb; /* Direction seen from the peripherals */ 78 79 /* Cache */ 80 uint32_t ccr; 81 82 struct intc_desc intc; 83 } SH7750State; 84 85 static inline int has_bcr3_and_bcr4(SH7750State *s) 86 { 87 return s->cpu->env.features & SH_FEATURE_BCR3_AND_BCR4; 88 } 89 90 /* 91 * I/O ports 92 */ 93 94 static uint16_t portdir(uint32_t v) 95 { 96 #define EVENPORTMASK(n) ((v & (1 << ((n) << 1))) >> (n)) 97 return 98 EVENPORTMASK(15) | EVENPORTMASK(14) | EVENPORTMASK(13) | 99 EVENPORTMASK(12) | EVENPORTMASK(11) | EVENPORTMASK(10) | 100 EVENPORTMASK(9) | EVENPORTMASK(8) | EVENPORTMASK(7) | 101 EVENPORTMASK(6) | EVENPORTMASK(5) | EVENPORTMASK(4) | 102 EVENPORTMASK(3) | EVENPORTMASK(2) | EVENPORTMASK(1) | 103 EVENPORTMASK(0); 104 } 105 106 static uint16_t portpullup(uint32_t v) 107 { 108 #define ODDPORTMASK(n) ((v & (1 << (((n) << 1) + 1))) >> (n)) 109 return 110 ODDPORTMASK(15) | ODDPORTMASK(14) | ODDPORTMASK(13) | 111 ODDPORTMASK(12) | ODDPORTMASK(11) | ODDPORTMASK(10) | 112 ODDPORTMASK(9) | ODDPORTMASK(8) | ODDPORTMASK(7) | ODDPORTMASK(6) | 113 ODDPORTMASK(5) | ODDPORTMASK(4) | ODDPORTMASK(3) | ODDPORTMASK(2) | 114 ODDPORTMASK(1) | ODDPORTMASK(0); 115 } 116 117 static uint16_t porta_lines(SH7750State *s) 118 { 119 return (s->portdira & s->pdtra) | /* CPU */ 120 (s->periph_portdira & s->periph_pdtra) | /* Peripherals */ 121 (~(s->portdira | s->periph_portdira) & s->portpullupa); /* Pullups */ 122 } 123 124 static uint16_t portb_lines(SH7750State *s) 125 { 126 return (s->portdirb & s->pdtrb) | /* CPU */ 127 (s->periph_portdirb & s->periph_pdtrb) | /* Peripherals */ 128 (~(s->portdirb | s->periph_portdirb) & s->portpullupb); /* Pullups */ 129 } 130 131 static void porta_changed(SH7750State *s, uint16_t prev) 132 { 133 uint16_t currenta; 134 135 currenta = porta_lines(s); 136 if (currenta == prev) { 137 return; 138 } 139 trace_sh7750_porta(prev, currenta, s->pdtra, s->pctra); 140 } 141 142 static void portb_changed(SH7750State *s, uint16_t prev) 143 { 144 uint16_t currentb; 145 146 currentb = portb_lines(s); 147 if (currentb == prev) { 148 return; 149 } 150 trace_sh7750_portb(prev, currentb, s->pdtrb, s->pctrb); 151 } 152 153 /* 154 * Memory 155 */ 156 157 static void error_access(const char *kind, hwaddr addr) 158 { 159 fprintf(stderr, "%s to %s (0x" HWADDR_FMT_plx ") not supported\n", 160 kind, regname(addr), addr); 161 } 162 163 static void ignore_access(const char *kind, hwaddr addr) 164 { 165 fprintf(stderr, "%s to %s (0x" HWADDR_FMT_plx ") ignored\n", 166 kind, regname(addr), addr); 167 } 168 169 static uint32_t sh7750_mem_readb(void *opaque, hwaddr addr) 170 { 171 switch (addr) { 172 default: 173 error_access("byte read", addr); 174 abort(); 175 } 176 } 177 178 static uint32_t sh7750_mem_readw(void *opaque, hwaddr addr) 179 { 180 SH7750State *s = opaque; 181 182 switch (addr) { 183 case SH7750_BCR2_A7: 184 return s->bcr2; 185 case SH7750_BCR3_A7: 186 if (!has_bcr3_and_bcr4(s)) { 187 error_access("word read", addr); 188 } 189 return s->bcr3; 190 case SH7750_FRQCR_A7: 191 return 0; 192 case SH7750_PCR_A7: 193 return s->pcr; 194 case SH7750_RFCR_A7: 195 fprintf(stderr, 196 "Read access to refresh count register, incrementing\n"); 197 return s->rfcr++; 198 case SH7750_PDTRA_A7: 199 return porta_lines(s); 200 case SH7750_PDTRB_A7: 201 return portb_lines(s); 202 case SH7750_RTCOR_A7: 203 case SH7750_RTCNT_A7: 204 case SH7750_RTCSR_A7: 205 ignore_access("word read", addr); 206 return 0; 207 default: 208 error_access("word read", addr); 209 abort(); 210 } 211 } 212 213 static uint32_t sh7750_mem_readl(void *opaque, hwaddr addr) 214 { 215 SH7750State *s = opaque; 216 SuperHCPUClass *scc; 217 218 switch (addr) { 219 case SH7750_BCR1_A7: 220 return s->bcr1; 221 case SH7750_BCR4_A7: 222 if (!has_bcr3_and_bcr4(s)) { 223 error_access("long read", addr); 224 } 225 return s->bcr4; 226 case SH7750_WCR1_A7: 227 case SH7750_WCR2_A7: 228 case SH7750_WCR3_A7: 229 case SH7750_MCR_A7: 230 ignore_access("long read", addr); 231 return 0; 232 case SH7750_MMUCR_A7: 233 return s->cpu->env.mmucr; 234 case SH7750_PTEH_A7: 235 return s->cpu->env.pteh; 236 case SH7750_PTEL_A7: 237 return s->cpu->env.ptel; 238 case SH7750_TTB_A7: 239 return s->cpu->env.ttb; 240 case SH7750_TEA_A7: 241 return s->cpu->env.tea; 242 case SH7750_TRA_A7: 243 return s->cpu->env.tra; 244 case SH7750_EXPEVT_A7: 245 return s->cpu->env.expevt; 246 case SH7750_INTEVT_A7: 247 return s->cpu->env.intevt; 248 case SH7750_CCR_A7: 249 return s->ccr; 250 case 0x1f000030: /* Processor version */ 251 scc = SUPERH_CPU_GET_CLASS(s->cpu); 252 return scc->pvr; 253 case 0x1f000040: /* Cache version */ 254 scc = SUPERH_CPU_GET_CLASS(s->cpu); 255 return scc->cvr; 256 case 0x1f000044: /* Processor revision */ 257 scc = SUPERH_CPU_GET_CLASS(s->cpu); 258 return scc->prr; 259 default: 260 error_access("long read", addr); 261 abort(); 262 } 263 } 264 265 #define is_in_sdrmx(a, x) (a >= SH7750_SDMR ## x ## _A7 \ 266 && a <= (SH7750_SDMR ## x ## _A7 + SH7750_SDMR ## x ## _REGNB)) 267 static void sh7750_mem_writeb(void *opaque, hwaddr addr, 268 uint32_t mem_value) 269 { 270 271 if (is_in_sdrmx(addr, 2) || is_in_sdrmx(addr, 3)) { 272 ignore_access("byte write", addr); 273 return; 274 } 275 276 error_access("byte write", addr); 277 abort(); 278 } 279 280 static void sh7750_mem_writew(void *opaque, hwaddr addr, 281 uint32_t mem_value) 282 { 283 SH7750State *s = opaque; 284 uint16_t temp; 285 286 switch (addr) { 287 /* SDRAM controller */ 288 case SH7750_BCR2_A7: 289 s->bcr2 = mem_value; 290 return; 291 case SH7750_BCR3_A7: 292 if (!has_bcr3_and_bcr4(s)) { 293 error_access("word write", addr); 294 } 295 s->bcr3 = mem_value; 296 return; 297 case SH7750_PCR_A7: 298 s->pcr = mem_value; 299 return; 300 case SH7750_RTCNT_A7: 301 case SH7750_RTCOR_A7: 302 case SH7750_RTCSR_A7: 303 ignore_access("word write", addr); 304 return; 305 /* IO ports */ 306 case SH7750_PDTRA_A7: 307 temp = porta_lines(s); 308 s->pdtra = mem_value; 309 porta_changed(s, temp); 310 return; 311 case SH7750_PDTRB_A7: 312 temp = portb_lines(s); 313 s->pdtrb = mem_value; 314 portb_changed(s, temp); 315 return; 316 case SH7750_RFCR_A7: 317 fprintf(stderr, "Write access to refresh count register\n"); 318 s->rfcr = mem_value; 319 return; 320 case SH7750_GPIOIC_A7: 321 s->gpioic = mem_value; 322 if (mem_value != 0) { 323 fprintf(stderr, "I/O interrupts not implemented\n"); 324 abort(); 325 } 326 return; 327 default: 328 error_access("word write", addr); 329 abort(); 330 } 331 } 332 333 static void sh7750_mem_writel(void *opaque, hwaddr addr, 334 uint32_t mem_value) 335 { 336 SH7750State *s = opaque; 337 uint16_t temp; 338 339 switch (addr) { 340 /* SDRAM controller */ 341 case SH7750_BCR1_A7: 342 s->bcr1 = mem_value; 343 return; 344 case SH7750_BCR4_A7: 345 if (!has_bcr3_and_bcr4(s)) { 346 error_access("long write", addr); 347 } 348 s->bcr4 = mem_value; 349 return; 350 case SH7750_WCR1_A7: 351 case SH7750_WCR2_A7: 352 case SH7750_WCR3_A7: 353 case SH7750_MCR_A7: 354 ignore_access("long write", addr); 355 return; 356 /* IO ports */ 357 case SH7750_PCTRA_A7: 358 temp = porta_lines(s); 359 s->pctra = mem_value; 360 s->portdira = portdir(mem_value); 361 s->portpullupa = portpullup(mem_value); 362 porta_changed(s, temp); 363 return; 364 case SH7750_PCTRB_A7: 365 temp = portb_lines(s); 366 s->pctrb = mem_value; 367 s->portdirb = portdir(mem_value); 368 s->portpullupb = portpullup(mem_value); 369 portb_changed(s, temp); 370 return; 371 case SH7750_MMUCR_A7: 372 if (mem_value & MMUCR_TI) { 373 cpu_sh4_invalidate_tlb(&s->cpu->env); 374 } 375 s->cpu->env.mmucr = mem_value & ~MMUCR_TI; 376 return; 377 case SH7750_PTEH_A7: 378 /* If asid changes, clear all registered tlb entries. */ 379 if ((s->cpu->env.pteh & 0xff) != (mem_value & 0xff)) { 380 tlb_flush(CPU(s->cpu)); 381 } 382 s->cpu->env.pteh = mem_value; 383 return; 384 case SH7750_PTEL_A7: 385 s->cpu->env.ptel = mem_value; 386 return; 387 case SH7750_PTEA_A7: 388 s->cpu->env.ptea = mem_value & 0x0000000f; 389 return; 390 case SH7750_TTB_A7: 391 s->cpu->env.ttb = mem_value; 392 return; 393 case SH7750_TEA_A7: 394 s->cpu->env.tea = mem_value; 395 return; 396 case SH7750_TRA_A7: 397 s->cpu->env.tra = mem_value & 0x000007ff; 398 return; 399 case SH7750_EXPEVT_A7: 400 s->cpu->env.expevt = mem_value & 0x000007ff; 401 return; 402 case SH7750_INTEVT_A7: 403 s->cpu->env.intevt = mem_value & 0x000007ff; 404 return; 405 case SH7750_CCR_A7: 406 s->ccr = mem_value; 407 return; 408 default: 409 error_access("long write", addr); 410 abort(); 411 } 412 } 413 414 static uint64_t sh7750_mem_readfn(void *opaque, hwaddr addr, unsigned size) 415 { 416 switch (size) { 417 case 1: 418 return sh7750_mem_readb(opaque, addr); 419 case 2: 420 return sh7750_mem_readw(opaque, addr); 421 case 4: 422 return sh7750_mem_readl(opaque, addr); 423 default: 424 g_assert_not_reached(); 425 } 426 } 427 428 static void sh7750_mem_writefn(void *opaque, hwaddr addr, 429 uint64_t value, unsigned size) 430 { 431 switch (size) { 432 case 1: 433 sh7750_mem_writeb(opaque, addr, value); 434 break; 435 case 2: 436 sh7750_mem_writew(opaque, addr, value); 437 break; 438 case 4: 439 sh7750_mem_writel(opaque, addr, value); 440 break; 441 default: 442 g_assert_not_reached(); 443 } 444 } 445 446 static const MemoryRegionOps sh7750_mem_ops = { 447 .read = sh7750_mem_readfn, 448 .write = sh7750_mem_writefn, 449 .valid.min_access_size = 1, 450 .valid.max_access_size = 4, 451 .endianness = DEVICE_NATIVE_ENDIAN, 452 }; 453 454 /* 455 * sh775x interrupt controller tables for sh_intc.c 456 * stolen from linux/arch/sh/kernel/cpu/sh4/setup-sh7750.c 457 */ 458 459 enum { 460 UNUSED = 0, 461 462 /* interrupt sources */ 463 IRL_0, IRL_1, IRL_2, IRL_3, IRL_4, IRL_5, IRL_6, IRL_7, 464 IRL_8, IRL_9, IRL_A, IRL_B, IRL_C, IRL_D, IRL_E, 465 IRL0, IRL1, IRL2, IRL3, 466 HUDI, GPIOI, 467 DMAC_DMTE0, DMAC_DMTE1, DMAC_DMTE2, DMAC_DMTE3, 468 DMAC_DMTE4, DMAC_DMTE5, DMAC_DMTE6, DMAC_DMTE7, 469 DMAC_DMAE, 470 PCIC0_PCISERR, PCIC1_PCIERR, PCIC1_PCIPWDWN, PCIC1_PCIPWON, 471 PCIC1_PCIDMA0, PCIC1_PCIDMA1, PCIC1_PCIDMA2, PCIC1_PCIDMA3, 472 TMU3, TMU4, TMU0, TMU1, TMU2_TUNI, TMU2_TICPI, 473 RTC_ATI, RTC_PRI, RTC_CUI, 474 SCI1_ERI, SCI1_RXI, SCI1_TXI, SCI1_TEI, 475 SCIF_ERI, SCIF_RXI, SCIF_BRI, SCIF_TXI, 476 WDT, 477 REF_RCMI, REF_ROVI, 478 479 /* interrupt groups */ 480 DMAC, PCIC1, TMU2, RTC, SCI1, SCIF, REF, 481 /* irl bundle */ 482 IRL, 483 484 NR_SOURCES, 485 }; 486 487 static struct intc_vect vectors[] = { 488 INTC_VECT(HUDI, 0x600), INTC_VECT(GPIOI, 0x620), 489 INTC_VECT(TMU0, 0x400), INTC_VECT(TMU1, 0x420), 490 INTC_VECT(TMU2_TUNI, 0x440), INTC_VECT(TMU2_TICPI, 0x460), 491 INTC_VECT(RTC_ATI, 0x480), INTC_VECT(RTC_PRI, 0x4a0), 492 INTC_VECT(RTC_CUI, 0x4c0), 493 INTC_VECT(SCI1_ERI, 0x4e0), INTC_VECT(SCI1_RXI, 0x500), 494 INTC_VECT(SCI1_TXI, 0x520), INTC_VECT(SCI1_TEI, 0x540), 495 INTC_VECT(SCIF_ERI, 0x700), INTC_VECT(SCIF_RXI, 0x720), 496 INTC_VECT(SCIF_BRI, 0x740), INTC_VECT(SCIF_TXI, 0x760), 497 INTC_VECT(WDT, 0x560), 498 INTC_VECT(REF_RCMI, 0x580), INTC_VECT(REF_ROVI, 0x5a0), 499 }; 500 501 static struct intc_group groups[] = { 502 INTC_GROUP(TMU2, TMU2_TUNI, TMU2_TICPI), 503 INTC_GROUP(RTC, RTC_ATI, RTC_PRI, RTC_CUI), 504 INTC_GROUP(SCI1, SCI1_ERI, SCI1_RXI, SCI1_TXI, SCI1_TEI), 505 INTC_GROUP(SCIF, SCIF_ERI, SCIF_RXI, SCIF_BRI, SCIF_TXI), 506 INTC_GROUP(REF, REF_RCMI, REF_ROVI), 507 }; 508 509 static struct intc_prio_reg prio_registers[] = { 510 { 0xffd00004, 0, 16, 4, /* IPRA */ { TMU0, TMU1, TMU2, RTC } }, 511 { 0xffd00008, 0, 16, 4, /* IPRB */ { WDT, REF, SCI1, 0 } }, 512 { 0xffd0000c, 0, 16, 4, /* IPRC */ { GPIOI, DMAC, SCIF, HUDI } }, 513 { 0xffd00010, 0, 16, 4, /* IPRD */ { IRL0, IRL1, IRL2, IRL3 } }, 514 { 0xfe080000, 0, 32, 4, /* INTPRI00 */ { 0, 0, 0, 0, TMU4, TMU3, 515 PCIC1, PCIC0_PCISERR } }, 516 }; 517 518 /* SH7750, SH7750S, SH7751 and SH7091 all have 4-channel DMA controllers */ 519 520 static struct intc_vect vectors_dma4[] = { 521 INTC_VECT(DMAC_DMTE0, 0x640), INTC_VECT(DMAC_DMTE1, 0x660), 522 INTC_VECT(DMAC_DMTE2, 0x680), INTC_VECT(DMAC_DMTE3, 0x6a0), 523 INTC_VECT(DMAC_DMAE, 0x6c0), 524 }; 525 526 static struct intc_group groups_dma4[] = { 527 INTC_GROUP(DMAC, DMAC_DMTE0, DMAC_DMTE1, DMAC_DMTE2, 528 DMAC_DMTE3, DMAC_DMAE), 529 }; 530 531 /* SH7750R and SH7751R both have 8-channel DMA controllers */ 532 533 static struct intc_vect vectors_dma8[] = { 534 INTC_VECT(DMAC_DMTE0, 0x640), INTC_VECT(DMAC_DMTE1, 0x660), 535 INTC_VECT(DMAC_DMTE2, 0x680), INTC_VECT(DMAC_DMTE3, 0x6a0), 536 INTC_VECT(DMAC_DMTE4, 0x780), INTC_VECT(DMAC_DMTE5, 0x7a0), 537 INTC_VECT(DMAC_DMTE6, 0x7c0), INTC_VECT(DMAC_DMTE7, 0x7e0), 538 INTC_VECT(DMAC_DMAE, 0x6c0), 539 }; 540 541 static struct intc_group groups_dma8[] = { 542 INTC_GROUP(DMAC, DMAC_DMTE0, DMAC_DMTE1, DMAC_DMTE2, 543 DMAC_DMTE3, DMAC_DMTE4, DMAC_DMTE5, 544 DMAC_DMTE6, DMAC_DMTE7, DMAC_DMAE), 545 }; 546 547 /* SH7750R, SH7751 and SH7751R all have two extra timer channels */ 548 549 static struct intc_vect vectors_tmu34[] = { 550 INTC_VECT(TMU3, 0xb00), INTC_VECT(TMU4, 0xb80), 551 }; 552 553 static struct intc_mask_reg mask_registers[] = { 554 { 0xfe080040, 0xfe080060, 32, /* INTMSK00 / INTMSKCLR00 */ 555 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 556 0, 0, 0, 0, 0, 0, TMU4, TMU3, 557 PCIC1_PCIERR, PCIC1_PCIPWDWN, PCIC1_PCIPWON, 558 PCIC1_PCIDMA0, PCIC1_PCIDMA1, PCIC1_PCIDMA2, 559 PCIC1_PCIDMA3, PCIC0_PCISERR } }, 560 }; 561 562 /* SH7750S, SH7750R, SH7751 and SH7751R all have IRLM priority registers */ 563 564 static struct intc_vect vectors_irlm[] = { 565 INTC_VECT(IRL0, 0x240), INTC_VECT(IRL1, 0x2a0), 566 INTC_VECT(IRL2, 0x300), INTC_VECT(IRL3, 0x360), 567 }; 568 569 /* SH7751 and SH7751R both have PCI */ 570 571 static struct intc_vect vectors_pci[] = { 572 INTC_VECT(PCIC0_PCISERR, 0xa00), INTC_VECT(PCIC1_PCIERR, 0xae0), 573 INTC_VECT(PCIC1_PCIPWDWN, 0xac0), INTC_VECT(PCIC1_PCIPWON, 0xaa0), 574 INTC_VECT(PCIC1_PCIDMA0, 0xa80), INTC_VECT(PCIC1_PCIDMA1, 0xa60), 575 INTC_VECT(PCIC1_PCIDMA2, 0xa40), INTC_VECT(PCIC1_PCIDMA3, 0xa20), 576 }; 577 578 static struct intc_group groups_pci[] = { 579 INTC_GROUP(PCIC1, PCIC1_PCIERR, PCIC1_PCIPWDWN, PCIC1_PCIPWON, 580 PCIC1_PCIDMA0, PCIC1_PCIDMA1, PCIC1_PCIDMA2, PCIC1_PCIDMA3), 581 }; 582 583 static struct intc_vect vectors_irl[] = { 584 INTC_VECT(IRL_0, 0x200), 585 INTC_VECT(IRL_1, 0x220), 586 INTC_VECT(IRL_2, 0x240), 587 INTC_VECT(IRL_3, 0x260), 588 INTC_VECT(IRL_4, 0x280), 589 INTC_VECT(IRL_5, 0x2a0), 590 INTC_VECT(IRL_6, 0x2c0), 591 INTC_VECT(IRL_7, 0x2e0), 592 INTC_VECT(IRL_8, 0x300), 593 INTC_VECT(IRL_9, 0x320), 594 INTC_VECT(IRL_A, 0x340), 595 INTC_VECT(IRL_B, 0x360), 596 INTC_VECT(IRL_C, 0x380), 597 INTC_VECT(IRL_D, 0x3a0), 598 INTC_VECT(IRL_E, 0x3c0), 599 }; 600 601 static struct intc_group groups_irl[] = { 602 INTC_GROUP(IRL, IRL_0, IRL_1, IRL_2, IRL_3, IRL_4, IRL_5, IRL_6, 603 IRL_7, IRL_8, IRL_9, IRL_A, IRL_B, IRL_C, IRL_D, IRL_E), 604 }; 605 606 /* 607 * Memory mapped cache and TLB 608 */ 609 610 #define MM_REGION_MASK 0x07000000 611 #define MM_ICACHE_ADDR (0) 612 #define MM_ICACHE_DATA (1) 613 #define MM_ITLB_ADDR (2) 614 #define MM_ITLB_DATA (3) 615 #define MM_OCACHE_ADDR (4) 616 #define MM_OCACHE_DATA (5) 617 #define MM_UTLB_ADDR (6) 618 #define MM_UTLB_DATA (7) 619 #define MM_REGION_TYPE(addr) ((addr & MM_REGION_MASK) >> 24) 620 621 static uint64_t invalid_read(void *opaque, hwaddr addr) 622 { 623 abort(); 624 625 return 0; 626 } 627 628 static uint64_t sh7750_mmct_read(void *opaque, hwaddr addr, 629 unsigned size) 630 { 631 SH7750State *s = opaque; 632 uint32_t ret = 0; 633 634 if (size != 4) { 635 return invalid_read(opaque, addr); 636 } 637 638 switch (MM_REGION_TYPE(addr)) { 639 case MM_ICACHE_ADDR: 640 case MM_ICACHE_DATA: 641 /* do nothing */ 642 break; 643 case MM_ITLB_ADDR: 644 ret = cpu_sh4_read_mmaped_itlb_addr(&s->cpu->env, addr); 645 break; 646 case MM_ITLB_DATA: 647 ret = cpu_sh4_read_mmaped_itlb_data(&s->cpu->env, addr); 648 break; 649 case MM_OCACHE_ADDR: 650 case MM_OCACHE_DATA: 651 /* do nothing */ 652 break; 653 case MM_UTLB_ADDR: 654 ret = cpu_sh4_read_mmaped_utlb_addr(&s->cpu->env, addr); 655 break; 656 case MM_UTLB_DATA: 657 ret = cpu_sh4_read_mmaped_utlb_data(&s->cpu->env, addr); 658 break; 659 default: 660 abort(); 661 } 662 663 return ret; 664 } 665 666 static void invalid_write(void *opaque, hwaddr addr, 667 uint64_t mem_value) 668 { 669 abort(); 670 } 671 672 static void sh7750_mmct_write(void *opaque, hwaddr addr, 673 uint64_t mem_value, unsigned size) 674 { 675 SH7750State *s = opaque; 676 677 if (size != 4) { 678 invalid_write(opaque, addr, mem_value); 679 } 680 681 switch (MM_REGION_TYPE(addr)) { 682 case MM_ICACHE_ADDR: 683 case MM_ICACHE_DATA: 684 /* do nothing */ 685 break; 686 case MM_ITLB_ADDR: 687 cpu_sh4_write_mmaped_itlb_addr(&s->cpu->env, addr, mem_value); 688 break; 689 case MM_ITLB_DATA: 690 cpu_sh4_write_mmaped_itlb_data(&s->cpu->env, addr, mem_value); 691 abort(); 692 break; 693 case MM_OCACHE_ADDR: 694 case MM_OCACHE_DATA: 695 /* do nothing */ 696 break; 697 case MM_UTLB_ADDR: 698 cpu_sh4_write_mmaped_utlb_addr(&s->cpu->env, addr, mem_value); 699 break; 700 case MM_UTLB_DATA: 701 cpu_sh4_write_mmaped_utlb_data(&s->cpu->env, addr, mem_value); 702 break; 703 default: 704 abort(); 705 break; 706 } 707 } 708 709 static const MemoryRegionOps sh7750_mmct_ops = { 710 .read = sh7750_mmct_read, 711 .write = sh7750_mmct_write, 712 .endianness = DEVICE_NATIVE_ENDIAN, 713 }; 714 715 SH7750State *sh7750_init(SuperHCPU *cpu, MemoryRegion *sysmem) 716 { 717 SH7750State *s; 718 DeviceState *dev; 719 SysBusDevice *sb; 720 MemoryRegion *mr, *alias; 721 722 s = g_new0(SH7750State, 1); 723 s->cpu = cpu; 724 s->periph_freq = 60000000; /* 60MHz */ 725 memory_region_init_io(&s->iomem, NULL, &sh7750_mem_ops, s, 726 "memory", 0x1fc01000); 727 728 memory_region_init_alias(&s->iomem_1f0, NULL, "memory-1f0", 729 &s->iomem, 0x1f000000, 0x1000); 730 memory_region_add_subregion(sysmem, 0x1f000000, &s->iomem_1f0); 731 732 memory_region_init_alias(&s->iomem_ff0, NULL, "memory-ff0", 733 &s->iomem, 0x1f000000, 0x1000); 734 memory_region_add_subregion(sysmem, 0xff000000, &s->iomem_ff0); 735 736 memory_region_init_alias(&s->iomem_1f8, NULL, "memory-1f8", 737 &s->iomem, 0x1f800000, 0x1000); 738 memory_region_add_subregion(sysmem, 0x1f800000, &s->iomem_1f8); 739 740 memory_region_init_alias(&s->iomem_ff8, NULL, "memory-ff8", 741 &s->iomem, 0x1f800000, 0x1000); 742 memory_region_add_subregion(sysmem, 0xff800000, &s->iomem_ff8); 743 744 memory_region_init_alias(&s->iomem_1fc, NULL, "memory-1fc", 745 &s->iomem, 0x1fc00000, 0x1000); 746 memory_region_add_subregion(sysmem, 0x1fc00000, &s->iomem_1fc); 747 748 memory_region_init_alias(&s->iomem_ffc, NULL, "memory-ffc", 749 &s->iomem, 0x1fc00000, 0x1000); 750 memory_region_add_subregion(sysmem, 0xffc00000, &s->iomem_ffc); 751 752 memory_region_init_io(&s->mmct_iomem, NULL, &sh7750_mmct_ops, s, 753 "cache-and-tlb", 0x08000000); 754 memory_region_add_subregion(sysmem, 0xf0000000, &s->mmct_iomem); 755 756 sh_intc_init(sysmem, &s->intc, NR_SOURCES, 757 _INTC_ARRAY(mask_registers), 758 _INTC_ARRAY(prio_registers)); 759 760 sh_intc_register_sources(&s->intc, 761 _INTC_ARRAY(vectors), 762 _INTC_ARRAY(groups)); 763 764 cpu->env.intc_handle = &s->intc; 765 766 /* SCI */ 767 dev = qdev_new(TYPE_SH_SERIAL); 768 dev->id = g_strdup("sci"); 769 qdev_prop_set_chr(dev, "chardev", serial_hd(0)); 770 sb = SYS_BUS_DEVICE(dev); 771 sysbus_realize_and_unref(sb, &error_fatal); 772 sysbus_mmio_map(sb, 0, 0xffe00000); 773 alias = g_malloc(sizeof(*alias)); 774 mr = sysbus_mmio_get_region(sb, 0); 775 memory_region_init_alias(alias, OBJECT(dev), "sci-a7", mr, 776 0, memory_region_size(mr)); 777 memory_region_add_subregion(sysmem, A7ADDR(0xffe00000), alias); 778 qdev_connect_gpio_out_named(dev, "eri", 0, s->intc.irqs[SCI1_ERI]); 779 qdev_connect_gpio_out_named(dev, "rxi", 0, s->intc.irqs[SCI1_RXI]); 780 qdev_connect_gpio_out_named(dev, "txi", 0, s->intc.irqs[SCI1_TXI]); 781 qdev_connect_gpio_out_named(dev, "tei", 0, s->intc.irqs[SCI1_TEI]); 782 783 /* SCIF */ 784 dev = qdev_new(TYPE_SH_SERIAL); 785 dev->id = g_strdup("scif"); 786 qdev_prop_set_chr(dev, "chardev", serial_hd(1)); 787 qdev_prop_set_uint8(dev, "features", SH_SERIAL_FEAT_SCIF); 788 sb = SYS_BUS_DEVICE(dev); 789 sysbus_realize_and_unref(sb, &error_fatal); 790 sysbus_mmio_map(sb, 0, 0xffe80000); 791 alias = g_malloc(sizeof(*alias)); 792 mr = sysbus_mmio_get_region(sb, 0); 793 memory_region_init_alias(alias, OBJECT(dev), "scif-a7", mr, 794 0, memory_region_size(mr)); 795 memory_region_add_subregion(sysmem, A7ADDR(0xffe80000), alias); 796 qdev_connect_gpio_out_named(dev, "eri", 0, s->intc.irqs[SCIF_ERI]); 797 qdev_connect_gpio_out_named(dev, "rxi", 0, s->intc.irqs[SCIF_RXI]); 798 qdev_connect_gpio_out_named(dev, "txi", 0, s->intc.irqs[SCIF_TXI]); 799 qdev_connect_gpio_out_named(dev, "bri", 0, s->intc.irqs[SCIF_BRI]); 800 801 tmu012_init(sysmem, 0x1fd80000, 802 TMU012_FEAT_TOCR | TMU012_FEAT_3CHAN | TMU012_FEAT_EXTCLK, 803 s->periph_freq, 804 s->intc.irqs[TMU0], 805 s->intc.irqs[TMU1], 806 s->intc.irqs[TMU2_TUNI], 807 s->intc.irqs[TMU2_TICPI]); 808 809 if (cpu->env.id & (SH_CPU_SH7750 | SH_CPU_SH7750S | SH_CPU_SH7751)) { 810 sh_intc_register_sources(&s->intc, 811 _INTC_ARRAY(vectors_dma4), 812 _INTC_ARRAY(groups_dma4)); 813 } 814 815 if (cpu->env.id & (SH_CPU_SH7750R | SH_CPU_SH7751R)) { 816 sh_intc_register_sources(&s->intc, 817 _INTC_ARRAY(vectors_dma8), 818 _INTC_ARRAY(groups_dma8)); 819 } 820 821 if (cpu->env.id & (SH_CPU_SH7750R | SH_CPU_SH7751 | SH_CPU_SH7751R)) { 822 sh_intc_register_sources(&s->intc, 823 _INTC_ARRAY(vectors_tmu34), 824 NULL, 0); 825 tmu012_init(sysmem, 0x1e100000, 0, s->periph_freq, 826 s->intc.irqs[TMU3], 827 s->intc.irqs[TMU4], 828 NULL, NULL); 829 } 830 831 if (cpu->env.id & (SH_CPU_SH7751_ALL)) { 832 sh_intc_register_sources(&s->intc, 833 _INTC_ARRAY(vectors_pci), 834 _INTC_ARRAY(groups_pci)); 835 } 836 837 if (cpu->env.id & (SH_CPU_SH7750S | SH_CPU_SH7750R | SH_CPU_SH7751_ALL)) { 838 sh_intc_register_sources(&s->intc, 839 _INTC_ARRAY(vectors_irlm), 840 NULL, 0); 841 } 842 843 sh_intc_register_sources(&s->intc, 844 _INTC_ARRAY(vectors_irl), 845 _INTC_ARRAY(groups_irl)); 846 return s; 847 } 848 849 qemu_irq sh7750_irl(SH7750State *s) 850 { 851 sh_intc_toggle_source(&s->intc.sources[IRL], 1, 0); /* enable */ 852 return qemu_allocate_irq(sh_intc_set_irl, &s->intc.sources[IRL], 0); 853 } 854