1 /* 2 * SH7750 device 3 * 4 * Copyright (c) 2007 Magnus Damm 5 * Copyright (c) 2005 Samuel Tardieu 6 * 7 * Permission is hereby granted, free of charge, to any person obtaining a copy 8 * of this software and associated documentation files (the "Software"), to deal 9 * in the Software without restriction, including without limitation the rights 10 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 11 * copies of the Software, and to permit persons to whom the Software is 12 * furnished to do so, subject to the following conditions: 13 * 14 * The above copyright notice and this permission notice shall be included in 15 * all copies or substantial portions of the Software. 16 * 17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 22 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 23 * THE SOFTWARE. 24 */ 25 26 #include "qemu/osdep.h" 27 #include "qapi/error.h" 28 #include "hw/sysbus.h" 29 #include "hw/irq.h" 30 #include "hw/sh4/sh.h" 31 #include "system/system.h" 32 #include "hw/qdev-properties.h" 33 #include "hw/qdev-properties-system.h" 34 #include "sh7750_regs.h" 35 #include "sh7750_regnames.h" 36 #include "hw/sh4/sh_intc.h" 37 #include "hw/timer/tmu012.h" 38 #include "exec/exec-all.h" 39 #include "exec/cputlb.h" 40 #include "trace.h" 41 42 typedef struct SH7750State { 43 MemoryRegion iomem; 44 MemoryRegion iomem_1f0; 45 MemoryRegion iomem_ff0; 46 MemoryRegion iomem_1f8; 47 MemoryRegion iomem_ff8; 48 MemoryRegion iomem_1fc; 49 MemoryRegion iomem_ffc; 50 MemoryRegion mmct_iomem; 51 /* CPU */ 52 SuperHCPU *cpu; 53 /* Peripheral frequency in Hz */ 54 uint32_t periph_freq; 55 /* SDRAM controller */ 56 uint32_t bcr1; 57 uint16_t bcr2; 58 uint16_t bcr3; 59 uint32_t bcr4; 60 uint16_t rfcr; 61 /* PCMCIA controller */ 62 uint16_t pcr; 63 /* IO ports */ 64 uint16_t gpioic; 65 uint32_t pctra; 66 uint32_t pctrb; 67 uint16_t portdira; /* Cached */ 68 uint16_t portpullupa; /* Cached */ 69 uint16_t portdirb; /* Cached */ 70 uint16_t portpullupb; /* Cached */ 71 uint16_t pdtra; 72 uint16_t pdtrb; 73 uint16_t periph_pdtra; /* Imposed by the peripherals */ 74 uint16_t periph_portdira; /* Direction seen from the peripherals */ 75 uint16_t periph_pdtrb; /* Imposed by the peripherals */ 76 uint16_t periph_portdirb; /* Direction seen from the peripherals */ 77 78 /* Cache */ 79 uint32_t ccr; 80 81 struct intc_desc intc; 82 } SH7750State; 83 84 static inline int has_bcr3_and_bcr4(SH7750State *s) 85 { 86 return s->cpu->env.features & SH_FEATURE_BCR3_AND_BCR4; 87 } 88 89 /* 90 * I/O ports 91 */ 92 93 static uint16_t portdir(uint32_t v) 94 { 95 #define EVENPORTMASK(n) ((v & (1 << ((n) << 1))) >> (n)) 96 return 97 EVENPORTMASK(15) | EVENPORTMASK(14) | EVENPORTMASK(13) | 98 EVENPORTMASK(12) | EVENPORTMASK(11) | EVENPORTMASK(10) | 99 EVENPORTMASK(9) | EVENPORTMASK(8) | EVENPORTMASK(7) | 100 EVENPORTMASK(6) | EVENPORTMASK(5) | EVENPORTMASK(4) | 101 EVENPORTMASK(3) | EVENPORTMASK(2) | EVENPORTMASK(1) | 102 EVENPORTMASK(0); 103 } 104 105 static uint16_t portpullup(uint32_t v) 106 { 107 #define ODDPORTMASK(n) ((v & (1 << (((n) << 1) + 1))) >> (n)) 108 return 109 ODDPORTMASK(15) | ODDPORTMASK(14) | ODDPORTMASK(13) | 110 ODDPORTMASK(12) | ODDPORTMASK(11) | ODDPORTMASK(10) | 111 ODDPORTMASK(9) | ODDPORTMASK(8) | ODDPORTMASK(7) | ODDPORTMASK(6) | 112 ODDPORTMASK(5) | ODDPORTMASK(4) | ODDPORTMASK(3) | ODDPORTMASK(2) | 113 ODDPORTMASK(1) | ODDPORTMASK(0); 114 } 115 116 static uint16_t porta_lines(SH7750State *s) 117 { 118 return (s->portdira & s->pdtra) | /* CPU */ 119 (s->periph_portdira & s->periph_pdtra) | /* Peripherals */ 120 (~(s->portdira | s->periph_portdira) & s->portpullupa); /* Pullups */ 121 } 122 123 static uint16_t portb_lines(SH7750State *s) 124 { 125 return (s->portdirb & s->pdtrb) | /* CPU */ 126 (s->periph_portdirb & s->periph_pdtrb) | /* Peripherals */ 127 (~(s->portdirb | s->periph_portdirb) & s->portpullupb); /* Pullups */ 128 } 129 130 static void porta_changed(SH7750State *s, uint16_t prev) 131 { 132 uint16_t currenta; 133 134 currenta = porta_lines(s); 135 if (currenta == prev) { 136 return; 137 } 138 trace_sh7750_porta(prev, currenta, s->pdtra, s->pctra); 139 } 140 141 static void portb_changed(SH7750State *s, uint16_t prev) 142 { 143 uint16_t currentb; 144 145 currentb = portb_lines(s); 146 if (currentb == prev) { 147 return; 148 } 149 trace_sh7750_portb(prev, currentb, s->pdtrb, s->pctrb); 150 } 151 152 /* 153 * Memory 154 */ 155 156 static void error_access(const char *kind, hwaddr addr) 157 { 158 fprintf(stderr, "%s to %s (0x" HWADDR_FMT_plx ") not supported\n", 159 kind, regname(addr), addr); 160 } 161 162 static void ignore_access(const char *kind, hwaddr addr) 163 { 164 fprintf(stderr, "%s to %s (0x" HWADDR_FMT_plx ") ignored\n", 165 kind, regname(addr), addr); 166 } 167 168 static uint32_t sh7750_mem_readb(void *opaque, hwaddr addr) 169 { 170 switch (addr) { 171 default: 172 error_access("byte read", addr); 173 abort(); 174 } 175 } 176 177 static uint32_t sh7750_mem_readw(void *opaque, hwaddr addr) 178 { 179 SH7750State *s = opaque; 180 181 switch (addr) { 182 case SH7750_BCR2_A7: 183 return s->bcr2; 184 case SH7750_BCR3_A7: 185 if (!has_bcr3_and_bcr4(s)) { 186 error_access("word read", addr); 187 } 188 return s->bcr3; 189 case SH7750_FRQCR_A7: 190 return 0; 191 case SH7750_PCR_A7: 192 return s->pcr; 193 case SH7750_RFCR_A7: 194 fprintf(stderr, 195 "Read access to refresh count register, incrementing\n"); 196 return s->rfcr++; 197 case SH7750_PDTRA_A7: 198 return porta_lines(s); 199 case SH7750_PDTRB_A7: 200 return portb_lines(s); 201 case SH7750_RTCOR_A7: 202 case SH7750_RTCNT_A7: 203 case SH7750_RTCSR_A7: 204 ignore_access("word read", addr); 205 return 0; 206 default: 207 error_access("word read", addr); 208 abort(); 209 } 210 } 211 212 static uint32_t sh7750_mem_readl(void *opaque, hwaddr addr) 213 { 214 SH7750State *s = opaque; 215 SuperHCPUClass *scc; 216 217 switch (addr) { 218 case SH7750_BCR1_A7: 219 return s->bcr1; 220 case SH7750_BCR4_A7: 221 if (!has_bcr3_and_bcr4(s)) { 222 error_access("long read", addr); 223 } 224 return s->bcr4; 225 case SH7750_WCR1_A7: 226 case SH7750_WCR2_A7: 227 case SH7750_WCR3_A7: 228 case SH7750_MCR_A7: 229 ignore_access("long read", addr); 230 return 0; 231 case SH7750_MMUCR_A7: 232 return s->cpu->env.mmucr; 233 case SH7750_PTEH_A7: 234 return s->cpu->env.pteh; 235 case SH7750_PTEL_A7: 236 return s->cpu->env.ptel; 237 case SH7750_TTB_A7: 238 return s->cpu->env.ttb; 239 case SH7750_TEA_A7: 240 return s->cpu->env.tea; 241 case SH7750_TRA_A7: 242 return s->cpu->env.tra; 243 case SH7750_EXPEVT_A7: 244 return s->cpu->env.expevt; 245 case SH7750_INTEVT_A7: 246 return s->cpu->env.intevt; 247 case SH7750_CCR_A7: 248 return s->ccr; 249 case 0x1f000030: /* Processor version */ 250 scc = SUPERH_CPU_GET_CLASS(s->cpu); 251 return scc->pvr; 252 case 0x1f000040: /* Cache version */ 253 scc = SUPERH_CPU_GET_CLASS(s->cpu); 254 return scc->cvr; 255 case 0x1f000044: /* Processor revision */ 256 scc = SUPERH_CPU_GET_CLASS(s->cpu); 257 return scc->prr; 258 default: 259 error_access("long read", addr); 260 abort(); 261 } 262 } 263 264 #define is_in_sdrmx(a, x) (a >= SH7750_SDMR ## x ## _A7 \ 265 && a <= (SH7750_SDMR ## x ## _A7 + SH7750_SDMR ## x ## _REGNB)) 266 static void sh7750_mem_writeb(void *opaque, hwaddr addr, 267 uint32_t mem_value) 268 { 269 270 if (is_in_sdrmx(addr, 2) || is_in_sdrmx(addr, 3)) { 271 ignore_access("byte write", addr); 272 return; 273 } 274 275 error_access("byte write", addr); 276 abort(); 277 } 278 279 static void sh7750_mem_writew(void *opaque, hwaddr addr, 280 uint32_t mem_value) 281 { 282 SH7750State *s = opaque; 283 uint16_t temp; 284 285 switch (addr) { 286 /* SDRAM controller */ 287 case SH7750_BCR2_A7: 288 s->bcr2 = mem_value; 289 return; 290 case SH7750_BCR3_A7: 291 if (!has_bcr3_and_bcr4(s)) { 292 error_access("word write", addr); 293 } 294 s->bcr3 = mem_value; 295 return; 296 case SH7750_PCR_A7: 297 s->pcr = mem_value; 298 return; 299 case SH7750_RTCNT_A7: 300 case SH7750_RTCOR_A7: 301 case SH7750_RTCSR_A7: 302 ignore_access("word write", addr); 303 return; 304 /* IO ports */ 305 case SH7750_PDTRA_A7: 306 temp = porta_lines(s); 307 s->pdtra = mem_value; 308 porta_changed(s, temp); 309 return; 310 case SH7750_PDTRB_A7: 311 temp = portb_lines(s); 312 s->pdtrb = mem_value; 313 portb_changed(s, temp); 314 return; 315 case SH7750_RFCR_A7: 316 fprintf(stderr, "Write access to refresh count register\n"); 317 s->rfcr = mem_value; 318 return; 319 case SH7750_GPIOIC_A7: 320 s->gpioic = mem_value; 321 if (mem_value != 0) { 322 fprintf(stderr, "I/O interrupts not implemented\n"); 323 abort(); 324 } 325 return; 326 default: 327 error_access("word write", addr); 328 abort(); 329 } 330 } 331 332 static void sh7750_mem_writel(void *opaque, hwaddr addr, 333 uint32_t mem_value) 334 { 335 SH7750State *s = opaque; 336 uint16_t temp; 337 338 switch (addr) { 339 /* SDRAM controller */ 340 case SH7750_BCR1_A7: 341 s->bcr1 = mem_value; 342 return; 343 case SH7750_BCR4_A7: 344 if (!has_bcr3_and_bcr4(s)) { 345 error_access("long write", addr); 346 } 347 s->bcr4 = mem_value; 348 return; 349 case SH7750_WCR1_A7: 350 case SH7750_WCR2_A7: 351 case SH7750_WCR3_A7: 352 case SH7750_MCR_A7: 353 ignore_access("long write", addr); 354 return; 355 /* IO ports */ 356 case SH7750_PCTRA_A7: 357 temp = porta_lines(s); 358 s->pctra = mem_value; 359 s->portdira = portdir(mem_value); 360 s->portpullupa = portpullup(mem_value); 361 porta_changed(s, temp); 362 return; 363 case SH7750_PCTRB_A7: 364 temp = portb_lines(s); 365 s->pctrb = mem_value; 366 s->portdirb = portdir(mem_value); 367 s->portpullupb = portpullup(mem_value); 368 portb_changed(s, temp); 369 return; 370 case SH7750_MMUCR_A7: 371 if (mem_value & MMUCR_TI) { 372 cpu_sh4_invalidate_tlb(&s->cpu->env); 373 } 374 s->cpu->env.mmucr = mem_value & ~MMUCR_TI; 375 return; 376 case SH7750_PTEH_A7: 377 /* If asid changes, clear all registered tlb entries. */ 378 if ((s->cpu->env.pteh & 0xff) != (mem_value & 0xff)) { 379 tlb_flush(CPU(s->cpu)); 380 } 381 s->cpu->env.pteh = mem_value; 382 return; 383 case SH7750_PTEL_A7: 384 s->cpu->env.ptel = mem_value; 385 return; 386 case SH7750_PTEA_A7: 387 s->cpu->env.ptea = mem_value & 0x0000000f; 388 return; 389 case SH7750_TTB_A7: 390 s->cpu->env.ttb = mem_value; 391 return; 392 case SH7750_TEA_A7: 393 s->cpu->env.tea = mem_value; 394 return; 395 case SH7750_TRA_A7: 396 s->cpu->env.tra = mem_value & 0x000007ff; 397 return; 398 case SH7750_EXPEVT_A7: 399 s->cpu->env.expevt = mem_value & 0x000007ff; 400 return; 401 case SH7750_INTEVT_A7: 402 s->cpu->env.intevt = mem_value & 0x000007ff; 403 return; 404 case SH7750_CCR_A7: 405 s->ccr = mem_value; 406 return; 407 default: 408 error_access("long write", addr); 409 abort(); 410 } 411 } 412 413 static uint64_t sh7750_mem_readfn(void *opaque, hwaddr addr, unsigned size) 414 { 415 switch (size) { 416 case 1: 417 return sh7750_mem_readb(opaque, addr); 418 case 2: 419 return sh7750_mem_readw(opaque, addr); 420 case 4: 421 return sh7750_mem_readl(opaque, addr); 422 default: 423 g_assert_not_reached(); 424 } 425 } 426 427 static void sh7750_mem_writefn(void *opaque, hwaddr addr, 428 uint64_t value, unsigned size) 429 { 430 switch (size) { 431 case 1: 432 sh7750_mem_writeb(opaque, addr, value); 433 break; 434 case 2: 435 sh7750_mem_writew(opaque, addr, value); 436 break; 437 case 4: 438 sh7750_mem_writel(opaque, addr, value); 439 break; 440 default: 441 g_assert_not_reached(); 442 } 443 } 444 445 static const MemoryRegionOps sh7750_mem_ops = { 446 .read = sh7750_mem_readfn, 447 .write = sh7750_mem_writefn, 448 .valid.min_access_size = 1, 449 .valid.max_access_size = 4, 450 .endianness = DEVICE_NATIVE_ENDIAN, 451 }; 452 453 /* 454 * sh775x interrupt controller tables for sh_intc.c 455 * stolen from linux/arch/sh/kernel/cpu/sh4/setup-sh7750.c 456 */ 457 458 enum { 459 UNUSED = 0, 460 461 /* interrupt sources */ 462 IRL_0, IRL_1, IRL_2, IRL_3, IRL_4, IRL_5, IRL_6, IRL_7, 463 IRL_8, IRL_9, IRL_A, IRL_B, IRL_C, IRL_D, IRL_E, 464 IRL0, IRL1, IRL2, IRL3, 465 HUDI, GPIOI, 466 DMAC_DMTE0, DMAC_DMTE1, DMAC_DMTE2, DMAC_DMTE3, 467 DMAC_DMTE4, DMAC_DMTE5, DMAC_DMTE6, DMAC_DMTE7, 468 DMAC_DMAE, 469 PCIC0_PCISERR, PCIC1_PCIERR, PCIC1_PCIPWDWN, PCIC1_PCIPWON, 470 PCIC1_PCIDMA0, PCIC1_PCIDMA1, PCIC1_PCIDMA2, PCIC1_PCIDMA3, 471 TMU3, TMU4, TMU0, TMU1, TMU2_TUNI, TMU2_TICPI, 472 RTC_ATI, RTC_PRI, RTC_CUI, 473 SCI1_ERI, SCI1_RXI, SCI1_TXI, SCI1_TEI, 474 SCIF_ERI, SCIF_RXI, SCIF_BRI, SCIF_TXI, 475 WDT, 476 REF_RCMI, REF_ROVI, 477 478 /* interrupt groups */ 479 DMAC, PCIC1, TMU2, RTC, SCI1, SCIF, REF, 480 /* irl bundle */ 481 IRL, 482 483 NR_SOURCES, 484 }; 485 486 static struct intc_vect vectors[] = { 487 INTC_VECT(HUDI, 0x600), INTC_VECT(GPIOI, 0x620), 488 INTC_VECT(TMU0, 0x400), INTC_VECT(TMU1, 0x420), 489 INTC_VECT(TMU2_TUNI, 0x440), INTC_VECT(TMU2_TICPI, 0x460), 490 INTC_VECT(RTC_ATI, 0x480), INTC_VECT(RTC_PRI, 0x4a0), 491 INTC_VECT(RTC_CUI, 0x4c0), 492 INTC_VECT(SCI1_ERI, 0x4e0), INTC_VECT(SCI1_RXI, 0x500), 493 INTC_VECT(SCI1_TXI, 0x520), INTC_VECT(SCI1_TEI, 0x540), 494 INTC_VECT(SCIF_ERI, 0x700), INTC_VECT(SCIF_RXI, 0x720), 495 INTC_VECT(SCIF_BRI, 0x740), INTC_VECT(SCIF_TXI, 0x760), 496 INTC_VECT(WDT, 0x560), 497 INTC_VECT(REF_RCMI, 0x580), INTC_VECT(REF_ROVI, 0x5a0), 498 }; 499 500 static struct intc_group groups[] = { 501 INTC_GROUP(TMU2, TMU2_TUNI, TMU2_TICPI), 502 INTC_GROUP(RTC, RTC_ATI, RTC_PRI, RTC_CUI), 503 INTC_GROUP(SCI1, SCI1_ERI, SCI1_RXI, SCI1_TXI, SCI1_TEI), 504 INTC_GROUP(SCIF, SCIF_ERI, SCIF_RXI, SCIF_BRI, SCIF_TXI), 505 INTC_GROUP(REF, REF_RCMI, REF_ROVI), 506 }; 507 508 static struct intc_prio_reg prio_registers[] = { 509 { 0xffd00004, 0, 16, 4, /* IPRA */ { TMU0, TMU1, TMU2, RTC } }, 510 { 0xffd00008, 0, 16, 4, /* IPRB */ { WDT, REF, SCI1, 0 } }, 511 { 0xffd0000c, 0, 16, 4, /* IPRC */ { GPIOI, DMAC, SCIF, HUDI } }, 512 { 0xffd00010, 0, 16, 4, /* IPRD */ { IRL0, IRL1, IRL2, IRL3 } }, 513 { 0xfe080000, 0, 32, 4, /* INTPRI00 */ { 0, 0, 0, 0, TMU4, TMU3, 514 PCIC1, PCIC0_PCISERR } }, 515 }; 516 517 /* SH7750, SH7750S, SH7751 and SH7091 all have 4-channel DMA controllers */ 518 519 static struct intc_vect vectors_dma4[] = { 520 INTC_VECT(DMAC_DMTE0, 0x640), INTC_VECT(DMAC_DMTE1, 0x660), 521 INTC_VECT(DMAC_DMTE2, 0x680), INTC_VECT(DMAC_DMTE3, 0x6a0), 522 INTC_VECT(DMAC_DMAE, 0x6c0), 523 }; 524 525 static struct intc_group groups_dma4[] = { 526 INTC_GROUP(DMAC, DMAC_DMTE0, DMAC_DMTE1, DMAC_DMTE2, 527 DMAC_DMTE3, DMAC_DMAE), 528 }; 529 530 /* SH7750R and SH7751R both have 8-channel DMA controllers */ 531 532 static struct intc_vect vectors_dma8[] = { 533 INTC_VECT(DMAC_DMTE0, 0x640), INTC_VECT(DMAC_DMTE1, 0x660), 534 INTC_VECT(DMAC_DMTE2, 0x680), INTC_VECT(DMAC_DMTE3, 0x6a0), 535 INTC_VECT(DMAC_DMTE4, 0x780), INTC_VECT(DMAC_DMTE5, 0x7a0), 536 INTC_VECT(DMAC_DMTE6, 0x7c0), INTC_VECT(DMAC_DMTE7, 0x7e0), 537 INTC_VECT(DMAC_DMAE, 0x6c0), 538 }; 539 540 static struct intc_group groups_dma8[] = { 541 INTC_GROUP(DMAC, DMAC_DMTE0, DMAC_DMTE1, DMAC_DMTE2, 542 DMAC_DMTE3, DMAC_DMTE4, DMAC_DMTE5, 543 DMAC_DMTE6, DMAC_DMTE7, DMAC_DMAE), 544 }; 545 546 /* SH7750R, SH7751 and SH7751R all have two extra timer channels */ 547 548 static struct intc_vect vectors_tmu34[] = { 549 INTC_VECT(TMU3, 0xb00), INTC_VECT(TMU4, 0xb80), 550 }; 551 552 static struct intc_mask_reg mask_registers[] = { 553 { 0xfe080040, 0xfe080060, 32, /* INTMSK00 / INTMSKCLR00 */ 554 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 555 0, 0, 0, 0, 0, 0, TMU4, TMU3, 556 PCIC1_PCIERR, PCIC1_PCIPWDWN, PCIC1_PCIPWON, 557 PCIC1_PCIDMA0, PCIC1_PCIDMA1, PCIC1_PCIDMA2, 558 PCIC1_PCIDMA3, PCIC0_PCISERR } }, 559 }; 560 561 /* SH7750S, SH7750R, SH7751 and SH7751R all have IRLM priority registers */ 562 563 static struct intc_vect vectors_irlm[] = { 564 INTC_VECT(IRL0, 0x240), INTC_VECT(IRL1, 0x2a0), 565 INTC_VECT(IRL2, 0x300), INTC_VECT(IRL3, 0x360), 566 }; 567 568 /* SH7751 and SH7751R both have PCI */ 569 570 static struct intc_vect vectors_pci[] = { 571 INTC_VECT(PCIC0_PCISERR, 0xa00), INTC_VECT(PCIC1_PCIERR, 0xae0), 572 INTC_VECT(PCIC1_PCIPWDWN, 0xac0), INTC_VECT(PCIC1_PCIPWON, 0xaa0), 573 INTC_VECT(PCIC1_PCIDMA0, 0xa80), INTC_VECT(PCIC1_PCIDMA1, 0xa60), 574 INTC_VECT(PCIC1_PCIDMA2, 0xa40), INTC_VECT(PCIC1_PCIDMA3, 0xa20), 575 }; 576 577 static struct intc_group groups_pci[] = { 578 INTC_GROUP(PCIC1, PCIC1_PCIERR, PCIC1_PCIPWDWN, PCIC1_PCIPWON, 579 PCIC1_PCIDMA0, PCIC1_PCIDMA1, PCIC1_PCIDMA2, PCIC1_PCIDMA3), 580 }; 581 582 static struct intc_vect vectors_irl[] = { 583 INTC_VECT(IRL_0, 0x200), 584 INTC_VECT(IRL_1, 0x220), 585 INTC_VECT(IRL_2, 0x240), 586 INTC_VECT(IRL_3, 0x260), 587 INTC_VECT(IRL_4, 0x280), 588 INTC_VECT(IRL_5, 0x2a0), 589 INTC_VECT(IRL_6, 0x2c0), 590 INTC_VECT(IRL_7, 0x2e0), 591 INTC_VECT(IRL_8, 0x300), 592 INTC_VECT(IRL_9, 0x320), 593 INTC_VECT(IRL_A, 0x340), 594 INTC_VECT(IRL_B, 0x360), 595 INTC_VECT(IRL_C, 0x380), 596 INTC_VECT(IRL_D, 0x3a0), 597 INTC_VECT(IRL_E, 0x3c0), 598 }; 599 600 static struct intc_group groups_irl[] = { 601 INTC_GROUP(IRL, IRL_0, IRL_1, IRL_2, IRL_3, IRL_4, IRL_5, IRL_6, 602 IRL_7, IRL_8, IRL_9, IRL_A, IRL_B, IRL_C, IRL_D, IRL_E), 603 }; 604 605 /* 606 * Memory mapped cache and TLB 607 */ 608 609 #define MM_REGION_MASK 0x07000000 610 #define MM_ICACHE_ADDR (0) 611 #define MM_ICACHE_DATA (1) 612 #define MM_ITLB_ADDR (2) 613 #define MM_ITLB_DATA (3) 614 #define MM_OCACHE_ADDR (4) 615 #define MM_OCACHE_DATA (5) 616 #define MM_UTLB_ADDR (6) 617 #define MM_UTLB_DATA (7) 618 #define MM_REGION_TYPE(addr) ((addr & MM_REGION_MASK) >> 24) 619 620 static uint64_t invalid_read(void *opaque, hwaddr addr) 621 { 622 abort(); 623 624 return 0; 625 } 626 627 static uint64_t sh7750_mmct_read(void *opaque, hwaddr addr, 628 unsigned size) 629 { 630 SH7750State *s = opaque; 631 uint32_t ret = 0; 632 633 if (size != 4) { 634 return invalid_read(opaque, addr); 635 } 636 637 switch (MM_REGION_TYPE(addr)) { 638 case MM_ICACHE_ADDR: 639 case MM_ICACHE_DATA: 640 /* do nothing */ 641 break; 642 case MM_ITLB_ADDR: 643 ret = cpu_sh4_read_mmaped_itlb_addr(&s->cpu->env, addr); 644 break; 645 case MM_ITLB_DATA: 646 ret = cpu_sh4_read_mmaped_itlb_data(&s->cpu->env, addr); 647 break; 648 case MM_OCACHE_ADDR: 649 case MM_OCACHE_DATA: 650 /* do nothing */ 651 break; 652 case MM_UTLB_ADDR: 653 ret = cpu_sh4_read_mmaped_utlb_addr(&s->cpu->env, addr); 654 break; 655 case MM_UTLB_DATA: 656 ret = cpu_sh4_read_mmaped_utlb_data(&s->cpu->env, addr); 657 break; 658 default: 659 abort(); 660 } 661 662 return ret; 663 } 664 665 static void invalid_write(void *opaque, hwaddr addr, 666 uint64_t mem_value) 667 { 668 abort(); 669 } 670 671 static void sh7750_mmct_write(void *opaque, hwaddr addr, 672 uint64_t mem_value, unsigned size) 673 { 674 SH7750State *s = opaque; 675 676 if (size != 4) { 677 invalid_write(opaque, addr, mem_value); 678 } 679 680 switch (MM_REGION_TYPE(addr)) { 681 case MM_ICACHE_ADDR: 682 case MM_ICACHE_DATA: 683 /* do nothing */ 684 break; 685 case MM_ITLB_ADDR: 686 cpu_sh4_write_mmaped_itlb_addr(&s->cpu->env, addr, mem_value); 687 break; 688 case MM_ITLB_DATA: 689 cpu_sh4_write_mmaped_itlb_data(&s->cpu->env, addr, mem_value); 690 abort(); 691 break; 692 case MM_OCACHE_ADDR: 693 case MM_OCACHE_DATA: 694 /* do nothing */ 695 break; 696 case MM_UTLB_ADDR: 697 cpu_sh4_write_mmaped_utlb_addr(&s->cpu->env, addr, mem_value); 698 break; 699 case MM_UTLB_DATA: 700 cpu_sh4_write_mmaped_utlb_data(&s->cpu->env, addr, mem_value); 701 break; 702 default: 703 abort(); 704 break; 705 } 706 } 707 708 static const MemoryRegionOps sh7750_mmct_ops = { 709 .read = sh7750_mmct_read, 710 .write = sh7750_mmct_write, 711 .endianness = DEVICE_NATIVE_ENDIAN, 712 }; 713 714 SH7750State *sh7750_init(SuperHCPU *cpu, MemoryRegion *sysmem) 715 { 716 SH7750State *s; 717 DeviceState *dev; 718 SysBusDevice *sb; 719 MemoryRegion *mr, *alias; 720 721 s = g_new0(SH7750State, 1); 722 s->cpu = cpu; 723 s->periph_freq = 60000000; /* 60MHz */ 724 memory_region_init_io(&s->iomem, NULL, &sh7750_mem_ops, s, 725 "memory", 0x1fc01000); 726 727 memory_region_init_alias(&s->iomem_1f0, NULL, "memory-1f0", 728 &s->iomem, 0x1f000000, 0x1000); 729 memory_region_add_subregion(sysmem, 0x1f000000, &s->iomem_1f0); 730 731 memory_region_init_alias(&s->iomem_ff0, NULL, "memory-ff0", 732 &s->iomem, 0x1f000000, 0x1000); 733 memory_region_add_subregion(sysmem, 0xff000000, &s->iomem_ff0); 734 735 memory_region_init_alias(&s->iomem_1f8, NULL, "memory-1f8", 736 &s->iomem, 0x1f800000, 0x1000); 737 memory_region_add_subregion(sysmem, 0x1f800000, &s->iomem_1f8); 738 739 memory_region_init_alias(&s->iomem_ff8, NULL, "memory-ff8", 740 &s->iomem, 0x1f800000, 0x1000); 741 memory_region_add_subregion(sysmem, 0xff800000, &s->iomem_ff8); 742 743 memory_region_init_alias(&s->iomem_1fc, NULL, "memory-1fc", 744 &s->iomem, 0x1fc00000, 0x1000); 745 memory_region_add_subregion(sysmem, 0x1fc00000, &s->iomem_1fc); 746 747 memory_region_init_alias(&s->iomem_ffc, NULL, "memory-ffc", 748 &s->iomem, 0x1fc00000, 0x1000); 749 memory_region_add_subregion(sysmem, 0xffc00000, &s->iomem_ffc); 750 751 memory_region_init_io(&s->mmct_iomem, NULL, &sh7750_mmct_ops, s, 752 "cache-and-tlb", 0x08000000); 753 memory_region_add_subregion(sysmem, 0xf0000000, &s->mmct_iomem); 754 755 sh_intc_init(sysmem, &s->intc, NR_SOURCES, 756 _INTC_ARRAY(mask_registers), 757 _INTC_ARRAY(prio_registers)); 758 759 sh_intc_register_sources(&s->intc, 760 _INTC_ARRAY(vectors), 761 _INTC_ARRAY(groups)); 762 763 cpu->env.intc_handle = &s->intc; 764 765 /* SCI */ 766 dev = qdev_new(TYPE_SH_SERIAL); 767 dev->id = g_strdup("sci"); 768 qdev_prop_set_chr(dev, "chardev", serial_hd(0)); 769 sb = SYS_BUS_DEVICE(dev); 770 sysbus_realize_and_unref(sb, &error_fatal); 771 sysbus_mmio_map(sb, 0, 0xffe00000); 772 alias = g_malloc(sizeof(*alias)); 773 mr = sysbus_mmio_get_region(sb, 0); 774 memory_region_init_alias(alias, OBJECT(dev), "sci-a7", mr, 775 0, memory_region_size(mr)); 776 memory_region_add_subregion(sysmem, A7ADDR(0xffe00000), alias); 777 qdev_connect_gpio_out_named(dev, "eri", 0, s->intc.irqs[SCI1_ERI]); 778 qdev_connect_gpio_out_named(dev, "rxi", 0, s->intc.irqs[SCI1_RXI]); 779 qdev_connect_gpio_out_named(dev, "txi", 0, s->intc.irqs[SCI1_TXI]); 780 qdev_connect_gpio_out_named(dev, "tei", 0, s->intc.irqs[SCI1_TEI]); 781 782 /* SCIF */ 783 dev = qdev_new(TYPE_SH_SERIAL); 784 dev->id = g_strdup("scif"); 785 qdev_prop_set_chr(dev, "chardev", serial_hd(1)); 786 qdev_prop_set_uint8(dev, "features", SH_SERIAL_FEAT_SCIF); 787 sb = SYS_BUS_DEVICE(dev); 788 sysbus_realize_and_unref(sb, &error_fatal); 789 sysbus_mmio_map(sb, 0, 0xffe80000); 790 alias = g_malloc(sizeof(*alias)); 791 mr = sysbus_mmio_get_region(sb, 0); 792 memory_region_init_alias(alias, OBJECT(dev), "scif-a7", mr, 793 0, memory_region_size(mr)); 794 memory_region_add_subregion(sysmem, A7ADDR(0xffe80000), alias); 795 qdev_connect_gpio_out_named(dev, "eri", 0, s->intc.irqs[SCIF_ERI]); 796 qdev_connect_gpio_out_named(dev, "rxi", 0, s->intc.irqs[SCIF_RXI]); 797 qdev_connect_gpio_out_named(dev, "txi", 0, s->intc.irqs[SCIF_TXI]); 798 qdev_connect_gpio_out_named(dev, "bri", 0, s->intc.irqs[SCIF_BRI]); 799 800 tmu012_init(sysmem, 0x1fd80000, 801 TMU012_FEAT_TOCR | TMU012_FEAT_3CHAN | TMU012_FEAT_EXTCLK, 802 s->periph_freq, 803 s->intc.irqs[TMU0], 804 s->intc.irqs[TMU1], 805 s->intc.irqs[TMU2_TUNI], 806 s->intc.irqs[TMU2_TICPI]); 807 808 if (cpu->env.id & (SH_CPU_SH7750 | SH_CPU_SH7750S | SH_CPU_SH7751)) { 809 sh_intc_register_sources(&s->intc, 810 _INTC_ARRAY(vectors_dma4), 811 _INTC_ARRAY(groups_dma4)); 812 } 813 814 if (cpu->env.id & (SH_CPU_SH7750R | SH_CPU_SH7751R)) { 815 sh_intc_register_sources(&s->intc, 816 _INTC_ARRAY(vectors_dma8), 817 _INTC_ARRAY(groups_dma8)); 818 } 819 820 if (cpu->env.id & (SH_CPU_SH7750R | SH_CPU_SH7751 | SH_CPU_SH7751R)) { 821 sh_intc_register_sources(&s->intc, 822 _INTC_ARRAY(vectors_tmu34), 823 NULL, 0); 824 tmu012_init(sysmem, 0x1e100000, 0, s->periph_freq, 825 s->intc.irqs[TMU3], 826 s->intc.irqs[TMU4], 827 NULL, NULL); 828 } 829 830 if (cpu->env.id & (SH_CPU_SH7751_ALL)) { 831 sh_intc_register_sources(&s->intc, 832 _INTC_ARRAY(vectors_pci), 833 _INTC_ARRAY(groups_pci)); 834 } 835 836 if (cpu->env.id & (SH_CPU_SH7750S | SH_CPU_SH7750R | SH_CPU_SH7751_ALL)) { 837 sh_intc_register_sources(&s->intc, 838 _INTC_ARRAY(vectors_irlm), 839 NULL, 0); 840 } 841 842 sh_intc_register_sources(&s->intc, 843 _INTC_ARRAY(vectors_irl), 844 _INTC_ARRAY(groups_irl)); 845 return s; 846 } 847 848 qemu_irq sh7750_irl(SH7750State *s) 849 { 850 sh_intc_toggle_source(&s->intc.sources[IRL], 1, 0); /* enable */ 851 return qemu_allocate_irq(sh_intc_set_irl, &s->intc.sources[IRL], 0); 852 } 853