1 /* 2 * Renesas SH7751R R2D-PLUS emulation 3 * 4 * Copyright (c) 2007 Magnus Damm 5 * Copyright (c) 2008 Paul Mundt 6 * 7 * Permission is hereby granted, free of charge, to any person obtaining a copy 8 * of this software and associated documentation files (the "Software"), to deal 9 * in the Software without restriction, including without limitation the rights 10 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 11 * copies of the Software, and to permit persons to whom the Software is 12 * furnished to do so, subject to the following conditions: 13 * 14 * The above copyright notice and this permission notice shall be included in 15 * all copies or substantial portions of the Software. 16 * 17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 22 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 23 * THE SOFTWARE. 24 */ 25 26 #include "qemu/osdep.h" 27 #include "qemu/units.h" 28 #include "qapi/error.h" 29 #include "qemu/error-report.h" 30 #include "cpu.h" 31 #include "hw/sysbus.h" 32 #include "hw/sh4/sh.h" 33 #include "sysemu/reset.h" 34 #include "sysemu/runstate.h" 35 #include "sysemu/sysemu.h" 36 #include "hw/boards.h" 37 #include "hw/pci/pci.h" 38 #include "hw/qdev-properties.h" 39 #include "net/net.h" 40 #include "sh7750_regs.h" 41 #include "hw/ide/mmio.h" 42 #include "hw/irq.h" 43 #include "hw/loader.h" 44 #include "hw/usb.h" 45 #include "hw/block/flash.h" 46 #include "exec/tswap.h" 47 48 #define FLASH_BASE 0x00000000 49 #define FLASH_SIZE (16 * MiB) 50 51 #define SDRAM_BASE 0x0c000000 /* Physical location of SDRAM: Area 3 */ 52 #define SDRAM_SIZE 0x04000000 53 54 #define SM501_VRAM_SIZE 0x800000 55 56 #define BOOT_PARAMS_OFFSET 0x0010000 57 /* CONFIG_BOOT_LINK_OFFSET of Linux kernel */ 58 #define LINUX_LOAD_OFFSET 0x0800000 59 #define INITRD_LOAD_OFFSET 0x1800000 60 61 #define PA_IRLMSK 0x00 62 #define PA_POWOFF 0x30 63 #define PA_VERREG 0x32 64 #define PA_OUTPORT 0x36 65 66 typedef struct { 67 uint16_t bcr; 68 uint16_t irlmsk; 69 uint16_t irlmon; 70 uint16_t cfctl; 71 uint16_t cfpow; 72 uint16_t dispctl; 73 uint16_t sdmpow; 74 uint16_t rtcce; 75 uint16_t pcicd; 76 uint16_t voyagerrts; 77 uint16_t cfrst; 78 uint16_t admrts; 79 uint16_t extrst; 80 uint16_t cfcdintclr; 81 uint16_t keyctlclr; 82 uint16_t pad0; 83 uint16_t pad1; 84 uint16_t verreg; 85 uint16_t inport; 86 uint16_t outport; 87 uint16_t bverreg; 88 89 /* output pin */ 90 qemu_irq irl; 91 MemoryRegion iomem; 92 } r2d_fpga_t; 93 94 enum r2d_fpga_irq { 95 PCI_INTD, CF_IDE, CF_CD, PCI_INTC, SM501, KEY, RTC_A, RTC_T, 96 SDCARD, PCI_INTA, PCI_INTB, EXT, TP, 97 NR_IRQS 98 }; 99 100 static const struct { short irl; uint16_t msk; } irqtab[NR_IRQS] = { 101 [CF_IDE] = { 1, 1 << 9 }, 102 [CF_CD] = { 2, 1 << 8 }, 103 [PCI_INTA] = { 9, 1 << 14 }, 104 [PCI_INTB] = { 10, 1 << 13 }, 105 [PCI_INTC] = { 3, 1 << 12 }, 106 [PCI_INTD] = { 0, 1 << 11 }, 107 [SM501] = { 4, 1 << 10 }, 108 [KEY] = { 5, 1 << 6 }, 109 [RTC_A] = { 6, 1 << 5 }, 110 [RTC_T] = { 7, 1 << 4 }, 111 [SDCARD] = { 8, 1 << 7 }, 112 [EXT] = { 11, 1 << 0 }, 113 [TP] = { 12, 1 << 15 }, 114 }; 115 116 static void update_irl(r2d_fpga_t *fpga) 117 { 118 int i, irl = 15; 119 for (i = 0; i < NR_IRQS; i++) { 120 if ((fpga->irlmon & fpga->irlmsk & irqtab[i].msk) && 121 irqtab[i].irl < irl) { 122 irl = irqtab[i].irl; 123 } 124 } 125 qemu_set_irq(fpga->irl, irl ^ 15); 126 } 127 128 static void r2d_fpga_irq_set(void *opaque, int n, int level) 129 { 130 r2d_fpga_t *fpga = opaque; 131 if (level) { 132 fpga->irlmon |= irqtab[n].msk; 133 } else { 134 fpga->irlmon &= ~irqtab[n].msk; 135 } 136 update_irl(fpga); 137 } 138 139 static uint64_t r2d_fpga_read(void *opaque, hwaddr addr, unsigned int size) 140 { 141 r2d_fpga_t *s = opaque; 142 143 switch (addr) { 144 case PA_IRLMSK: 145 return s->irlmsk; 146 case PA_OUTPORT: 147 return s->outport; 148 case PA_POWOFF: 149 return 0x00; 150 case PA_VERREG: 151 return 0x10; 152 } 153 154 return 0; 155 } 156 157 static void 158 r2d_fpga_write(void *opaque, hwaddr addr, uint64_t value, unsigned int size) 159 { 160 r2d_fpga_t *s = opaque; 161 162 switch (addr) { 163 case PA_IRLMSK: 164 s->irlmsk = value; 165 update_irl(s); 166 break; 167 case PA_OUTPORT: 168 s->outport = value; 169 break; 170 case PA_POWOFF: 171 if (value & 1) { 172 qemu_system_shutdown_request(SHUTDOWN_CAUSE_GUEST_SHUTDOWN); 173 } 174 break; 175 case PA_VERREG: 176 /* Discard writes */ 177 break; 178 } 179 } 180 181 static const MemoryRegionOps r2d_fpga_ops = { 182 .read = r2d_fpga_read, 183 .write = r2d_fpga_write, 184 .impl.min_access_size = 2, 185 .impl.max_access_size = 2, 186 .endianness = DEVICE_NATIVE_ENDIAN, 187 }; 188 189 static qemu_irq *r2d_fpga_init(MemoryRegion *sysmem, 190 hwaddr base, qemu_irq irl) 191 { 192 r2d_fpga_t *s; 193 194 s = g_new0(r2d_fpga_t, 1); 195 196 s->irl = irl; 197 198 memory_region_init_io(&s->iomem, NULL, &r2d_fpga_ops, s, "r2d-fpga", 0x40); 199 memory_region_add_subregion(sysmem, base, &s->iomem); 200 return qemu_allocate_irqs(r2d_fpga_irq_set, s, NR_IRQS); 201 } 202 203 typedef struct ResetData { 204 SuperHCPU *cpu; 205 uint32_t vector; 206 } ResetData; 207 208 static void main_cpu_reset(void *opaque) 209 { 210 ResetData *s = (ResetData *)opaque; 211 CPUSH4State *env = &s->cpu->env; 212 213 cpu_reset(CPU(s->cpu)); 214 env->pc = s->vector; 215 } 216 217 static struct QEMU_PACKED 218 { 219 int mount_root_rdonly; 220 int ramdisk_flags; 221 int orig_root_dev; 222 int loader_type; 223 int initrd_start; 224 int initrd_size; 225 226 char pad[232]; 227 228 char kernel_cmdline[256] QEMU_NONSTRING; 229 } boot_params; 230 231 static void r2d_init(MachineState *machine) 232 { 233 const char *kernel_filename = machine->kernel_filename; 234 const char *kernel_cmdline = machine->kernel_cmdline; 235 const char *initrd_filename = machine->initrd_filename; 236 MachineClass *mc = MACHINE_GET_CLASS(machine); 237 SuperHCPU *cpu; 238 CPUSH4State *env; 239 ResetData *reset_info; 240 struct SH7750State *s; 241 MemoryRegion *sdram = g_new(MemoryRegion, 1); 242 qemu_irq *irq; 243 DriveInfo *dinfo; 244 DeviceState *dev; 245 SysBusDevice *busdev; 246 MemoryRegion *address_space_mem = get_system_memory(); 247 PCIBus *pci_bus; 248 USBBus *usb_bus; 249 250 cpu = SUPERH_CPU(cpu_create(machine->cpu_type)); 251 env = &cpu->env; 252 253 reset_info = g_new0(ResetData, 1); 254 reset_info->cpu = cpu; 255 reset_info->vector = env->pc; 256 qemu_register_reset(main_cpu_reset, reset_info); 257 258 /* Allocate memory space */ 259 memory_region_init_ram(sdram, NULL, "r2d.sdram", SDRAM_SIZE, &error_fatal); 260 memory_region_add_subregion(address_space_mem, SDRAM_BASE, sdram); 261 /* Register peripherals */ 262 s = sh7750_init(cpu, address_space_mem); 263 irq = r2d_fpga_init(address_space_mem, 0x04000000, sh7750_irl(s)); 264 265 dev = qdev_new("sh_pci"); 266 busdev = SYS_BUS_DEVICE(dev); 267 sysbus_realize_and_unref(busdev, &error_fatal); 268 pci_bus = PCI_BUS(qdev_get_child_bus(dev, "pci")); 269 sysbus_mmio_map(busdev, 0, P4ADDR(0x1e200000)); 270 sysbus_mmio_map(busdev, 1, A7ADDR(0x1e200000)); 271 sysbus_connect_irq(busdev, 0, irq[PCI_INTA]); 272 sysbus_connect_irq(busdev, 1, irq[PCI_INTB]); 273 sysbus_connect_irq(busdev, 2, irq[PCI_INTC]); 274 sysbus_connect_irq(busdev, 3, irq[PCI_INTD]); 275 276 dev = qdev_new("sysbus-sm501"); 277 busdev = SYS_BUS_DEVICE(dev); 278 qdev_prop_set_uint32(dev, "vram-size", SM501_VRAM_SIZE); 279 qdev_prop_set_uint64(dev, "dma-offset", 0x10000000); 280 qdev_prop_set_chr(dev, "chardev", serial_hd(2)); 281 sysbus_realize_and_unref(busdev, &error_fatal); 282 sysbus_mmio_map(busdev, 0, 0x10000000); 283 sysbus_mmio_map(busdev, 1, 0x13e00000); 284 sysbus_connect_irq(busdev, 0, irq[SM501]); 285 286 /* onboard CF (True IDE mode, Master only). */ 287 dinfo = drive_get(IF_IDE, 0, 0); 288 dev = qdev_new("mmio-ide"); 289 busdev = SYS_BUS_DEVICE(dev); 290 sysbus_connect_irq(busdev, 0, irq[CF_IDE]); 291 qdev_prop_set_uint32(dev, "shift", 1); 292 sysbus_realize_and_unref(busdev, &error_fatal); 293 sysbus_mmio_map(busdev, 0, 0x14001000); 294 sysbus_mmio_map(busdev, 1, 0x1400080c); 295 mmio_ide_init_drives(dev, dinfo, NULL); 296 297 /* 298 * Onboard flash memory 299 * According to the old board user document in Japanese (under 300 * NDA) what is referred to as FROM (Area0) is connected via a 301 * 32-bit bus and CS0 to CN8. The docs mention a Cypress 302 * S29PL127J60TFI130 chipsset. Per the 'S29PL-J 002-00615 303 * Rev. *E' datasheet, it is a 128Mbit NOR parallel flash 304 * addressable in words of 16bit. 305 */ 306 dinfo = drive_get(IF_PFLASH, 0, 0); 307 pflash_cfi02_register(0x0, "r2d.flash", FLASH_SIZE, 308 dinfo ? blk_by_legacy_dinfo(dinfo) : NULL, 309 64 * KiB, 1, 2, 0x0001, 0x227e, 0x2220, 0x2200, 310 0x555, 0x2aa, 0); 311 312 /* NIC: rtl8139 on-board, and 2 slots. */ 313 pci_init_nic_in_slot(pci_bus, mc->default_nic, NULL, "2"); 314 pci_init_nic_devices(pci_bus, mc->default_nic); 315 316 /* USB keyboard */ 317 usb_bus = USB_BUS(object_resolve_type_unambiguous(TYPE_USB_BUS, 318 &error_abort)); 319 usb_create_simple(usb_bus, "usb-kbd"); 320 321 /* Todo: register on board registers */ 322 memset(&boot_params, 0, sizeof(boot_params)); 323 324 if (kernel_filename) { 325 int kernel_size; 326 327 kernel_size = load_image_targphys(kernel_filename, 328 SDRAM_BASE + LINUX_LOAD_OFFSET, 329 INITRD_LOAD_OFFSET - LINUX_LOAD_OFFSET); 330 if (kernel_size < 0) { 331 error_report("qemu: could not load kernel '%s'", kernel_filename); 332 exit(1); 333 } 334 335 /* initialization which should be done by firmware */ 336 address_space_stl(&address_space_memory, SH7750_BCR1, 1 << 3, 337 MEMTXATTRS_UNSPECIFIED, NULL); /* cs3 SDRAM */ 338 address_space_stw(&address_space_memory, SH7750_BCR2, 3 << (3 * 2), 339 MEMTXATTRS_UNSPECIFIED, NULL); /* cs3 32bit */ 340 /* Start from P2 area */ 341 reset_info->vector = (SDRAM_BASE + LINUX_LOAD_OFFSET) | 0xa0000000; 342 } 343 344 if (initrd_filename) { 345 int initrd_size; 346 347 initrd_size = load_image_targphys(initrd_filename, 348 SDRAM_BASE + INITRD_LOAD_OFFSET, 349 SDRAM_SIZE - INITRD_LOAD_OFFSET); 350 351 if (initrd_size < 0) { 352 error_report("qemu: could not load initrd '%s'", initrd_filename); 353 exit(1); 354 } 355 356 /* initialization which should be done by firmware */ 357 boot_params.loader_type = tswap32(1); 358 boot_params.initrd_start = tswap32(INITRD_LOAD_OFFSET); 359 boot_params.initrd_size = tswap32(initrd_size); 360 } 361 362 if (kernel_cmdline) { 363 /* 364 * I see no evidence that this .kernel_cmdline buffer requires 365 * NUL-termination, so using strncpy should be ok. 366 */ 367 strncpy(boot_params.kernel_cmdline, kernel_cmdline, 368 sizeof(boot_params.kernel_cmdline)); 369 } 370 371 rom_add_blob_fixed("boot_params", &boot_params, sizeof(boot_params), 372 SDRAM_BASE + BOOT_PARAMS_OFFSET); 373 } 374 375 static void r2d_machine_init(MachineClass *mc) 376 { 377 mc->desc = "r2d-plus board"; 378 mc->init = r2d_init; 379 mc->block_default_type = IF_IDE; 380 mc->default_cpu_type = TYPE_SH7751R_CPU; 381 mc->default_nic = "rtl8139"; 382 } 383 384 DEFINE_MACHINE("r2d", r2d_machine_init) 385