1 /* 2 * SD Association Host Standard Specification v2.0 controller emulation 3 * 4 * Copyright (c) 2011 Samsung Electronics Co., Ltd. 5 * Mitsyanko Igor <i.mitsyanko@samsung.com> 6 * Peter A.G. Crosthwaite <peter.crosthwaite@petalogix.com> 7 * 8 * Based on MMC controller for Samsung S5PC1xx-based board emulation 9 * by Alexey Merkulov and Vladimir Monakhov. 10 * 11 * This program is free software; you can redistribute it and/or modify it 12 * under the terms of the GNU General Public License as published by the 13 * Free Software Foundation; either version 2 of the License, or (at your 14 * option) any later version. 15 * 16 * This program is distributed in the hope that it will be useful, 17 * but WITHOUT ANY WARRANTY; without even the implied warranty of 18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. 19 * See the GNU General Public License for more details. 20 * 21 * You should have received a copy of the GNU General Public License along 22 * with this program; if not, see <http://www.gnu.org/licenses/>. 23 */ 24 25 #include "qemu/osdep.h" 26 #include "qemu/error-report.h" 27 #include "qapi/error.h" 28 #include "hw/hw.h" 29 #include "sysemu/block-backend.h" 30 #include "sysemu/blockdev.h" 31 #include "sysemu/dma.h" 32 #include "qemu/timer.h" 33 #include "qemu/bitops.h" 34 #include "hw/sd/sdhci.h" 35 #include "sdhci-internal.h" 36 #include "qemu/log.h" 37 #include "qemu/cutils.h" 38 #include "trace.h" 39 40 #define TYPE_SDHCI_BUS "sdhci-bus" 41 #define SDHCI_BUS(obj) OBJECT_CHECK(SDBus, (obj), TYPE_SDHCI_BUS) 42 43 #define MASKED_WRITE(reg, mask, val) (reg = (reg & (mask)) | (val)) 44 45 /* Default SD/MMC host controller features information, which will be 46 * presented in CAPABILITIES register of generic SD host controller at reset. 47 * 48 * support: 49 * - 3.3v and 1.8v voltages 50 * - SDMA/ADMA1/ADMA2 51 * - high-speed 52 * max host controller R/W buffers size: 512B 53 * max clock frequency for SDclock: 52 MHz 54 * timeout clock frequency: 52 MHz 55 * 56 * does not support: 57 * - 3.0v voltage 58 * - 64-bit system bus 59 * - suspend/resume 60 */ 61 #define SDHC_CAPAB_REG_DEFAULT 0x057834b4 62 63 static inline unsigned int sdhci_get_fifolen(SDHCIState *s) 64 { 65 return 1 << (9 + FIELD_EX32(s->capareg, SDHC_CAPAB, MAXBLOCKLENGTH)); 66 } 67 68 /* return true on error */ 69 static bool sdhci_check_capab_freq_range(SDHCIState *s, const char *desc, 70 uint8_t freq, Error **errp) 71 { 72 if (s->sd_spec_version >= 3) { 73 return false; 74 } 75 switch (freq) { 76 case 0: 77 case 10 ... 63: 78 break; 79 default: 80 error_setg(errp, "SD %s clock frequency can have value" 81 "in range 0-63 only", desc); 82 return true; 83 } 84 return false; 85 } 86 87 static void sdhci_check_capareg(SDHCIState *s, Error **errp) 88 { 89 uint64_t msk = s->capareg; 90 uint32_t val; 91 bool y; 92 93 switch (s->sd_spec_version) { 94 case 3: 95 val = FIELD_EX64(s->capareg, SDHC_CAPAB, ASYNC_INT); 96 trace_sdhci_capareg("async interrupt", val); 97 msk = FIELD_DP64(msk, SDHC_CAPAB, ASYNC_INT, 0); 98 99 val = FIELD_EX64(s->capareg, SDHC_CAPAB, SLOT_TYPE); 100 if (val) { 101 error_setg(errp, "slot-type not supported"); 102 return; 103 } 104 trace_sdhci_capareg("slot type", val); 105 msk = FIELD_DP64(msk, SDHC_CAPAB, SLOT_TYPE, 0); 106 107 if (val != 2) { 108 val = FIELD_EX64(s->capareg, SDHC_CAPAB, EMBEDDED_8BIT); 109 trace_sdhci_capareg("8-bit bus", val); 110 } 111 msk = FIELD_DP64(msk, SDHC_CAPAB, EMBEDDED_8BIT, 0); 112 113 val = FIELD_EX64(s->capareg, SDHC_CAPAB, BUS_SPEED); 114 trace_sdhci_capareg("bus speed mask", val); 115 msk = FIELD_DP64(msk, SDHC_CAPAB, BUS_SPEED, 0); 116 117 val = FIELD_EX64(s->capareg, SDHC_CAPAB, DRIVER_STRENGTH); 118 trace_sdhci_capareg("driver strength mask", val); 119 msk = FIELD_DP64(msk, SDHC_CAPAB, DRIVER_STRENGTH, 0); 120 121 val = FIELD_EX64(s->capareg, SDHC_CAPAB, TIMER_RETUNING); 122 trace_sdhci_capareg("timer re-tuning", val); 123 msk = FIELD_DP64(msk, SDHC_CAPAB, TIMER_RETUNING, 0); 124 125 val = FIELD_EX64(s->capareg, SDHC_CAPAB, SDR50_TUNING); 126 trace_sdhci_capareg("use SDR50 tuning", val); 127 msk = FIELD_DP64(msk, SDHC_CAPAB, SDR50_TUNING, 0); 128 129 val = FIELD_EX64(s->capareg, SDHC_CAPAB, RETUNING_MODE); 130 trace_sdhci_capareg("re-tuning mode", val); 131 msk = FIELD_DP64(msk, SDHC_CAPAB, RETUNING_MODE, 0); 132 133 val = FIELD_EX64(s->capareg, SDHC_CAPAB, CLOCK_MULT); 134 trace_sdhci_capareg("clock multiplier", val); 135 msk = FIELD_DP64(msk, SDHC_CAPAB, CLOCK_MULT, 0); 136 137 /* fallthrough */ 138 case 2: /* default version */ 139 val = FIELD_EX64(s->capareg, SDHC_CAPAB, ADMA2); 140 trace_sdhci_capareg("ADMA2", val); 141 msk = FIELD_DP64(msk, SDHC_CAPAB, ADMA2, 0); 142 143 val = FIELD_EX64(s->capareg, SDHC_CAPAB, ADMA1); 144 trace_sdhci_capareg("ADMA1", val); 145 msk = FIELD_DP64(msk, SDHC_CAPAB, ADMA1, 0); 146 147 val = FIELD_EX64(s->capareg, SDHC_CAPAB, BUS64BIT); 148 trace_sdhci_capareg("64-bit system bus", val); 149 msk = FIELD_DP64(msk, SDHC_CAPAB, BUS64BIT, 0); 150 151 /* fallthrough */ 152 case 1: 153 y = FIELD_EX64(s->capareg, SDHC_CAPAB, TOUNIT); 154 msk = FIELD_DP64(msk, SDHC_CAPAB, TOUNIT, 0); 155 156 val = FIELD_EX64(s->capareg, SDHC_CAPAB, TOCLKFREQ); 157 trace_sdhci_capareg(y ? "timeout (MHz)" : "Timeout (KHz)", val); 158 if (sdhci_check_capab_freq_range(s, "timeout", val, errp)) { 159 return; 160 } 161 msk = FIELD_DP64(msk, SDHC_CAPAB, TOCLKFREQ, 0); 162 163 val = FIELD_EX64(s->capareg, SDHC_CAPAB, BASECLKFREQ); 164 trace_sdhci_capareg(y ? "base (MHz)" : "Base (KHz)", val); 165 if (sdhci_check_capab_freq_range(s, "base", val, errp)) { 166 return; 167 } 168 msk = FIELD_DP64(msk, SDHC_CAPAB, BASECLKFREQ, 0); 169 170 val = FIELD_EX64(s->capareg, SDHC_CAPAB, MAXBLOCKLENGTH); 171 if (val >= 3) { 172 error_setg(errp, "block size can be 512, 1024 or 2048 only"); 173 return; 174 } 175 trace_sdhci_capareg("max block length", sdhci_get_fifolen(s)); 176 msk = FIELD_DP64(msk, SDHC_CAPAB, MAXBLOCKLENGTH, 0); 177 178 val = FIELD_EX64(s->capareg, SDHC_CAPAB, HIGHSPEED); 179 trace_sdhci_capareg("high speed", val); 180 msk = FIELD_DP64(msk, SDHC_CAPAB, HIGHSPEED, 0); 181 182 val = FIELD_EX64(s->capareg, SDHC_CAPAB, SDMA); 183 trace_sdhci_capareg("SDMA", val); 184 msk = FIELD_DP64(msk, SDHC_CAPAB, SDMA, 0); 185 186 val = FIELD_EX64(s->capareg, SDHC_CAPAB, SUSPRESUME); 187 trace_sdhci_capareg("suspend/resume", val); 188 msk = FIELD_DP64(msk, SDHC_CAPAB, SUSPRESUME, 0); 189 190 val = FIELD_EX64(s->capareg, SDHC_CAPAB, V33); 191 trace_sdhci_capareg("3.3v", val); 192 msk = FIELD_DP64(msk, SDHC_CAPAB, V33, 0); 193 194 val = FIELD_EX64(s->capareg, SDHC_CAPAB, V30); 195 trace_sdhci_capareg("3.0v", val); 196 msk = FIELD_DP64(msk, SDHC_CAPAB, V30, 0); 197 198 val = FIELD_EX64(s->capareg, SDHC_CAPAB, V18); 199 trace_sdhci_capareg("1.8v", val); 200 msk = FIELD_DP64(msk, SDHC_CAPAB, V18, 0); 201 break; 202 203 default: 204 error_setg(errp, "Unsupported spec version: %u", s->sd_spec_version); 205 } 206 if (msk) { 207 qemu_log_mask(LOG_UNIMP, 208 "SDHCI: unknown CAPAB mask: 0x%016" PRIx64 "\n", msk); 209 } 210 } 211 212 static uint8_t sdhci_slotint(SDHCIState *s) 213 { 214 return (s->norintsts & s->norintsigen) || (s->errintsts & s->errintsigen) || 215 ((s->norintsts & SDHC_NIS_INSERT) && (s->wakcon & SDHC_WKUP_ON_INS)) || 216 ((s->norintsts & SDHC_NIS_REMOVE) && (s->wakcon & SDHC_WKUP_ON_RMV)); 217 } 218 219 static inline void sdhci_update_irq(SDHCIState *s) 220 { 221 qemu_set_irq(s->irq, sdhci_slotint(s)); 222 } 223 224 static void sdhci_raise_insertion_irq(void *opaque) 225 { 226 SDHCIState *s = (SDHCIState *)opaque; 227 228 if (s->norintsts & SDHC_NIS_REMOVE) { 229 timer_mod(s->insert_timer, 230 qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + SDHC_INSERTION_DELAY); 231 } else { 232 s->prnsts = 0x1ff0000; 233 if (s->norintstsen & SDHC_NISEN_INSERT) { 234 s->norintsts |= SDHC_NIS_INSERT; 235 } 236 sdhci_update_irq(s); 237 } 238 } 239 240 static void sdhci_set_inserted(DeviceState *dev, bool level) 241 { 242 SDHCIState *s = (SDHCIState *)dev; 243 244 trace_sdhci_set_inserted(level ? "insert" : "eject"); 245 if ((s->norintsts & SDHC_NIS_REMOVE) && level) { 246 /* Give target some time to notice card ejection */ 247 timer_mod(s->insert_timer, 248 qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + SDHC_INSERTION_DELAY); 249 } else { 250 if (level) { 251 s->prnsts = 0x1ff0000; 252 if (s->norintstsen & SDHC_NISEN_INSERT) { 253 s->norintsts |= SDHC_NIS_INSERT; 254 } 255 } else { 256 s->prnsts = 0x1fa0000; 257 s->pwrcon &= ~SDHC_POWER_ON; 258 s->clkcon &= ~SDHC_CLOCK_SDCLK_EN; 259 if (s->norintstsen & SDHC_NISEN_REMOVE) { 260 s->norintsts |= SDHC_NIS_REMOVE; 261 } 262 } 263 sdhci_update_irq(s); 264 } 265 } 266 267 static void sdhci_set_readonly(DeviceState *dev, bool level) 268 { 269 SDHCIState *s = (SDHCIState *)dev; 270 271 if (level) { 272 s->prnsts &= ~SDHC_WRITE_PROTECT; 273 } else { 274 /* Write enabled */ 275 s->prnsts |= SDHC_WRITE_PROTECT; 276 } 277 } 278 279 static void sdhci_reset(SDHCIState *s) 280 { 281 DeviceState *dev = DEVICE(s); 282 283 timer_del(s->insert_timer); 284 timer_del(s->transfer_timer); 285 286 /* Set all registers to 0. Capabilities/Version registers are not cleared 287 * and assumed to always preserve their value, given to them during 288 * initialization */ 289 memset(&s->sdmasysad, 0, (uintptr_t)&s->capareg - (uintptr_t)&s->sdmasysad); 290 291 /* Reset other state based on current card insertion/readonly status */ 292 sdhci_set_inserted(dev, sdbus_get_inserted(&s->sdbus)); 293 sdhci_set_readonly(dev, sdbus_get_readonly(&s->sdbus)); 294 295 s->data_count = 0; 296 s->stopped_state = sdhc_not_stopped; 297 s->pending_insert_state = false; 298 } 299 300 static void sdhci_poweron_reset(DeviceState *dev) 301 { 302 /* QOM (ie power-on) reset. This is identical to reset 303 * commanded via device register apart from handling of the 304 * 'pending insert on powerup' quirk. 305 */ 306 SDHCIState *s = (SDHCIState *)dev; 307 308 sdhci_reset(s); 309 310 if (s->pending_insert_quirk) { 311 s->pending_insert_state = true; 312 } 313 } 314 315 static void sdhci_data_transfer(void *opaque); 316 317 static void sdhci_send_command(SDHCIState *s) 318 { 319 SDRequest request; 320 uint8_t response[16]; 321 int rlen; 322 323 s->errintsts = 0; 324 s->acmd12errsts = 0; 325 request.cmd = s->cmdreg >> 8; 326 request.arg = s->argument; 327 328 trace_sdhci_send_command(request.cmd, request.arg); 329 rlen = sdbus_do_command(&s->sdbus, &request, response); 330 331 if (s->cmdreg & SDHC_CMD_RESPONSE) { 332 if (rlen == 4) { 333 s->rspreg[0] = (response[0] << 24) | (response[1] << 16) | 334 (response[2] << 8) | response[3]; 335 s->rspreg[1] = s->rspreg[2] = s->rspreg[3] = 0; 336 trace_sdhci_response4(s->rspreg[0]); 337 } else if (rlen == 16) { 338 s->rspreg[0] = (response[11] << 24) | (response[12] << 16) | 339 (response[13] << 8) | response[14]; 340 s->rspreg[1] = (response[7] << 24) | (response[8] << 16) | 341 (response[9] << 8) | response[10]; 342 s->rspreg[2] = (response[3] << 24) | (response[4] << 16) | 343 (response[5] << 8) | response[6]; 344 s->rspreg[3] = (response[0] << 16) | (response[1] << 8) | 345 response[2]; 346 trace_sdhci_response16(s->rspreg[3], s->rspreg[2], 347 s->rspreg[1], s->rspreg[0]); 348 } else { 349 trace_sdhci_error("timeout waiting for command response"); 350 if (s->errintstsen & SDHC_EISEN_CMDTIMEOUT) { 351 s->errintsts |= SDHC_EIS_CMDTIMEOUT; 352 s->norintsts |= SDHC_NIS_ERR; 353 } 354 } 355 356 if (!(s->quirks & SDHCI_QUIRK_NO_BUSY_IRQ) && 357 (s->norintstsen & SDHC_NISEN_TRSCMP) && 358 (s->cmdreg & SDHC_CMD_RESPONSE) == SDHC_CMD_RSP_WITH_BUSY) { 359 s->norintsts |= SDHC_NIS_TRSCMP; 360 } 361 } 362 363 if (s->norintstsen & SDHC_NISEN_CMDCMP) { 364 s->norintsts |= SDHC_NIS_CMDCMP; 365 } 366 367 sdhci_update_irq(s); 368 369 if (s->blksize && (s->cmdreg & SDHC_CMD_DATA_PRESENT)) { 370 s->data_count = 0; 371 sdhci_data_transfer(s); 372 } 373 } 374 375 static void sdhci_end_transfer(SDHCIState *s) 376 { 377 /* Automatically send CMD12 to stop transfer if AutoCMD12 enabled */ 378 if ((s->trnmod & SDHC_TRNS_ACMD12) != 0) { 379 SDRequest request; 380 uint8_t response[16]; 381 382 request.cmd = 0x0C; 383 request.arg = 0; 384 trace_sdhci_end_transfer(request.cmd, request.arg); 385 sdbus_do_command(&s->sdbus, &request, response); 386 /* Auto CMD12 response goes to the upper Response register */ 387 s->rspreg[3] = (response[0] << 24) | (response[1] << 16) | 388 (response[2] << 8) | response[3]; 389 } 390 391 s->prnsts &= ~(SDHC_DOING_READ | SDHC_DOING_WRITE | 392 SDHC_DAT_LINE_ACTIVE | SDHC_DATA_INHIBIT | 393 SDHC_SPACE_AVAILABLE | SDHC_DATA_AVAILABLE); 394 395 if (s->norintstsen & SDHC_NISEN_TRSCMP) { 396 s->norintsts |= SDHC_NIS_TRSCMP; 397 } 398 399 sdhci_update_irq(s); 400 } 401 402 /* 403 * Programmed i/o data transfer 404 */ 405 #define BLOCK_SIZE_MASK (4 * K_BYTE - 1) 406 407 /* Fill host controller's read buffer with BLKSIZE bytes of data from card */ 408 static void sdhci_read_block_from_card(SDHCIState *s) 409 { 410 int index = 0; 411 uint8_t data; 412 const uint16_t blk_size = s->blksize & BLOCK_SIZE_MASK; 413 414 if ((s->trnmod & SDHC_TRNS_MULTI) && 415 (s->trnmod & SDHC_TRNS_BLK_CNT_EN) && (s->blkcnt == 0)) { 416 return; 417 } 418 419 for (index = 0; index < blk_size; index++) { 420 data = sdbus_read_data(&s->sdbus); 421 if (!FIELD_EX32(s->hostctl2, SDHC_HOSTCTL2, EXECUTE_TUNING)) { 422 /* Device is not in tunning */ 423 s->fifo_buffer[index] = data; 424 } 425 } 426 427 if (FIELD_EX32(s->hostctl2, SDHC_HOSTCTL2, EXECUTE_TUNING)) { 428 /* Device is in tunning */ 429 s->hostctl2 &= ~R_SDHC_HOSTCTL2_EXECUTE_TUNING_MASK; 430 s->hostctl2 |= R_SDHC_HOSTCTL2_SAMPLING_CLKSEL_MASK; 431 s->prnsts &= ~(SDHC_DAT_LINE_ACTIVE | SDHC_DOING_READ | 432 SDHC_DATA_INHIBIT); 433 goto read_done; 434 } 435 436 /* New data now available for READ through Buffer Port Register */ 437 s->prnsts |= SDHC_DATA_AVAILABLE; 438 if (s->norintstsen & SDHC_NISEN_RBUFRDY) { 439 s->norintsts |= SDHC_NIS_RBUFRDY; 440 } 441 442 /* Clear DAT line active status if that was the last block */ 443 if ((s->trnmod & SDHC_TRNS_MULTI) == 0 || 444 ((s->trnmod & SDHC_TRNS_MULTI) && s->blkcnt == 1)) { 445 s->prnsts &= ~SDHC_DAT_LINE_ACTIVE; 446 } 447 448 /* If stop at block gap request was set and it's not the last block of 449 * data - generate Block Event interrupt */ 450 if (s->stopped_state == sdhc_gap_read && (s->trnmod & SDHC_TRNS_MULTI) && 451 s->blkcnt != 1) { 452 s->prnsts &= ~SDHC_DAT_LINE_ACTIVE; 453 if (s->norintstsen & SDHC_EISEN_BLKGAP) { 454 s->norintsts |= SDHC_EIS_BLKGAP; 455 } 456 } 457 458 read_done: 459 sdhci_update_irq(s); 460 } 461 462 /* Read @size byte of data from host controller @s BUFFER DATA PORT register */ 463 static uint32_t sdhci_read_dataport(SDHCIState *s, unsigned size) 464 { 465 uint32_t value = 0; 466 int i; 467 468 /* first check that a valid data exists in host controller input buffer */ 469 if ((s->prnsts & SDHC_DATA_AVAILABLE) == 0) { 470 trace_sdhci_error("read from empty buffer"); 471 return 0; 472 } 473 474 for (i = 0; i < size; i++) { 475 value |= s->fifo_buffer[s->data_count] << i * 8; 476 s->data_count++; 477 /* check if we've read all valid data (blksize bytes) from buffer */ 478 if ((s->data_count) >= (s->blksize & BLOCK_SIZE_MASK)) { 479 trace_sdhci_read_dataport(s->data_count); 480 s->prnsts &= ~SDHC_DATA_AVAILABLE; /* no more data in a buffer */ 481 s->data_count = 0; /* next buff read must start at position [0] */ 482 483 if (s->trnmod & SDHC_TRNS_BLK_CNT_EN) { 484 s->blkcnt--; 485 } 486 487 /* if that was the last block of data */ 488 if ((s->trnmod & SDHC_TRNS_MULTI) == 0 || 489 ((s->trnmod & SDHC_TRNS_BLK_CNT_EN) && (s->blkcnt == 0)) || 490 /* stop at gap request */ 491 (s->stopped_state == sdhc_gap_read && 492 !(s->prnsts & SDHC_DAT_LINE_ACTIVE))) { 493 sdhci_end_transfer(s); 494 } else { /* if there are more data, read next block from card */ 495 sdhci_read_block_from_card(s); 496 } 497 break; 498 } 499 } 500 501 return value; 502 } 503 504 /* Write data from host controller FIFO to card */ 505 static void sdhci_write_block_to_card(SDHCIState *s) 506 { 507 int index = 0; 508 509 if (s->prnsts & SDHC_SPACE_AVAILABLE) { 510 if (s->norintstsen & SDHC_NISEN_WBUFRDY) { 511 s->norintsts |= SDHC_NIS_WBUFRDY; 512 } 513 sdhci_update_irq(s); 514 return; 515 } 516 517 if (s->trnmod & SDHC_TRNS_BLK_CNT_EN) { 518 if (s->blkcnt == 0) { 519 return; 520 } else { 521 s->blkcnt--; 522 } 523 } 524 525 for (index = 0; index < (s->blksize & BLOCK_SIZE_MASK); index++) { 526 sdbus_write_data(&s->sdbus, s->fifo_buffer[index]); 527 } 528 529 /* Next data can be written through BUFFER DATORT register */ 530 s->prnsts |= SDHC_SPACE_AVAILABLE; 531 532 /* Finish transfer if that was the last block of data */ 533 if ((s->trnmod & SDHC_TRNS_MULTI) == 0 || 534 ((s->trnmod & SDHC_TRNS_MULTI) && 535 (s->trnmod & SDHC_TRNS_BLK_CNT_EN) && (s->blkcnt == 0))) { 536 sdhci_end_transfer(s); 537 } else if (s->norintstsen & SDHC_NISEN_WBUFRDY) { 538 s->norintsts |= SDHC_NIS_WBUFRDY; 539 } 540 541 /* Generate Block Gap Event if requested and if not the last block */ 542 if (s->stopped_state == sdhc_gap_write && (s->trnmod & SDHC_TRNS_MULTI) && 543 s->blkcnt > 0) { 544 s->prnsts &= ~SDHC_DOING_WRITE; 545 if (s->norintstsen & SDHC_EISEN_BLKGAP) { 546 s->norintsts |= SDHC_EIS_BLKGAP; 547 } 548 sdhci_end_transfer(s); 549 } 550 551 sdhci_update_irq(s); 552 } 553 554 /* Write @size bytes of @value data to host controller @s Buffer Data Port 555 * register */ 556 static void sdhci_write_dataport(SDHCIState *s, uint32_t value, unsigned size) 557 { 558 unsigned i; 559 560 /* Check that there is free space left in a buffer */ 561 if (!(s->prnsts & SDHC_SPACE_AVAILABLE)) { 562 trace_sdhci_error("Can't write to data buffer: buffer full"); 563 return; 564 } 565 566 for (i = 0; i < size; i++) { 567 s->fifo_buffer[s->data_count] = value & 0xFF; 568 s->data_count++; 569 value >>= 8; 570 if (s->data_count >= (s->blksize & BLOCK_SIZE_MASK)) { 571 trace_sdhci_write_dataport(s->data_count); 572 s->data_count = 0; 573 s->prnsts &= ~SDHC_SPACE_AVAILABLE; 574 if (s->prnsts & SDHC_DOING_WRITE) { 575 sdhci_write_block_to_card(s); 576 } 577 } 578 } 579 } 580 581 /* 582 * Single DMA data transfer 583 */ 584 585 /* Multi block SDMA transfer */ 586 static void sdhci_sdma_transfer_multi_blocks(SDHCIState *s) 587 { 588 bool page_aligned = false; 589 unsigned int n, begin; 590 const uint16_t block_size = s->blksize & BLOCK_SIZE_MASK; 591 uint32_t boundary_chk = 1 << (((s->blksize & ~BLOCK_SIZE_MASK) >> 12) + 12); 592 uint32_t boundary_count = boundary_chk - (s->sdmasysad % boundary_chk); 593 594 if (!(s->trnmod & SDHC_TRNS_BLK_CNT_EN) || !s->blkcnt) { 595 qemu_log_mask(LOG_UNIMP, "infinite transfer is not supported\n"); 596 return; 597 } 598 599 /* XXX: Some sd/mmc drivers (for example, u-boot-slp) do not account for 600 * possible stop at page boundary if initial address is not page aligned, 601 * allow them to work properly */ 602 if ((s->sdmasysad % boundary_chk) == 0) { 603 page_aligned = true; 604 } 605 606 if (s->trnmod & SDHC_TRNS_READ) { 607 s->prnsts |= SDHC_DOING_READ | SDHC_DATA_INHIBIT | 608 SDHC_DAT_LINE_ACTIVE; 609 while (s->blkcnt) { 610 if (s->data_count == 0) { 611 for (n = 0; n < block_size; n++) { 612 s->fifo_buffer[n] = sdbus_read_data(&s->sdbus); 613 } 614 } 615 begin = s->data_count; 616 if (((boundary_count + begin) < block_size) && page_aligned) { 617 s->data_count = boundary_count + begin; 618 boundary_count = 0; 619 } else { 620 s->data_count = block_size; 621 boundary_count -= block_size - begin; 622 if (s->trnmod & SDHC_TRNS_BLK_CNT_EN) { 623 s->blkcnt--; 624 } 625 } 626 dma_memory_write(s->dma_as, s->sdmasysad, 627 &s->fifo_buffer[begin], s->data_count - begin); 628 s->sdmasysad += s->data_count - begin; 629 if (s->data_count == block_size) { 630 s->data_count = 0; 631 } 632 if (page_aligned && boundary_count == 0) { 633 break; 634 } 635 } 636 } else { 637 s->prnsts |= SDHC_DOING_WRITE | SDHC_DATA_INHIBIT | 638 SDHC_DAT_LINE_ACTIVE; 639 while (s->blkcnt) { 640 begin = s->data_count; 641 if (((boundary_count + begin) < block_size) && page_aligned) { 642 s->data_count = boundary_count + begin; 643 boundary_count = 0; 644 } else { 645 s->data_count = block_size; 646 boundary_count -= block_size - begin; 647 } 648 dma_memory_read(s->dma_as, s->sdmasysad, 649 &s->fifo_buffer[begin], s->data_count - begin); 650 s->sdmasysad += s->data_count - begin; 651 if (s->data_count == block_size) { 652 for (n = 0; n < block_size; n++) { 653 sdbus_write_data(&s->sdbus, s->fifo_buffer[n]); 654 } 655 s->data_count = 0; 656 if (s->trnmod & SDHC_TRNS_BLK_CNT_EN) { 657 s->blkcnt--; 658 } 659 } 660 if (page_aligned && boundary_count == 0) { 661 break; 662 } 663 } 664 } 665 666 if (s->blkcnt == 0) { 667 sdhci_end_transfer(s); 668 } else { 669 if (s->norintstsen & SDHC_NISEN_DMA) { 670 s->norintsts |= SDHC_NIS_DMA; 671 } 672 sdhci_update_irq(s); 673 } 674 } 675 676 /* single block SDMA transfer */ 677 static void sdhci_sdma_transfer_single_block(SDHCIState *s) 678 { 679 int n; 680 uint32_t datacnt = s->blksize & BLOCK_SIZE_MASK; 681 682 if (s->trnmod & SDHC_TRNS_READ) { 683 for (n = 0; n < datacnt; n++) { 684 s->fifo_buffer[n] = sdbus_read_data(&s->sdbus); 685 } 686 dma_memory_write(s->dma_as, s->sdmasysad, s->fifo_buffer, datacnt); 687 } else { 688 dma_memory_read(s->dma_as, s->sdmasysad, s->fifo_buffer, datacnt); 689 for (n = 0; n < datacnt; n++) { 690 sdbus_write_data(&s->sdbus, s->fifo_buffer[n]); 691 } 692 } 693 s->blkcnt--; 694 695 sdhci_end_transfer(s); 696 } 697 698 typedef struct ADMADescr { 699 hwaddr addr; 700 uint16_t length; 701 uint8_t attr; 702 uint8_t incr; 703 } ADMADescr; 704 705 static void get_adma_description(SDHCIState *s, ADMADescr *dscr) 706 { 707 uint32_t adma1 = 0; 708 uint64_t adma2 = 0; 709 hwaddr entry_addr = (hwaddr)s->admasysaddr; 710 switch (SDHC_DMA_TYPE(s->hostctl1)) { 711 case SDHC_CTRL_ADMA2_32: 712 dma_memory_read(s->dma_as, entry_addr, (uint8_t *)&adma2, 713 sizeof(adma2)); 714 adma2 = le64_to_cpu(adma2); 715 /* The spec does not specify endianness of descriptor table. 716 * We currently assume that it is LE. 717 */ 718 dscr->addr = (hwaddr)extract64(adma2, 32, 32) & ~0x3ull; 719 dscr->length = (uint16_t)extract64(adma2, 16, 16); 720 dscr->attr = (uint8_t)extract64(adma2, 0, 7); 721 dscr->incr = 8; 722 break; 723 case SDHC_CTRL_ADMA1_32: 724 dma_memory_read(s->dma_as, entry_addr, (uint8_t *)&adma1, 725 sizeof(adma1)); 726 adma1 = le32_to_cpu(adma1); 727 dscr->addr = (hwaddr)(adma1 & 0xFFFFF000); 728 dscr->attr = (uint8_t)extract32(adma1, 0, 7); 729 dscr->incr = 4; 730 if ((dscr->attr & SDHC_ADMA_ATTR_ACT_MASK) == SDHC_ADMA_ATTR_SET_LEN) { 731 dscr->length = (uint16_t)extract32(adma1, 12, 16); 732 } else { 733 dscr->length = 4096; 734 } 735 break; 736 case SDHC_CTRL_ADMA2_64: 737 dma_memory_read(s->dma_as, entry_addr, 738 (uint8_t *)(&dscr->attr), 1); 739 dma_memory_read(s->dma_as, entry_addr + 2, 740 (uint8_t *)(&dscr->length), 2); 741 dscr->length = le16_to_cpu(dscr->length); 742 dma_memory_read(s->dma_as, entry_addr + 4, 743 (uint8_t *)(&dscr->addr), 8); 744 dscr->addr = le64_to_cpu(dscr->addr); 745 dscr->attr &= (uint8_t) ~0xC0; 746 dscr->incr = 12; 747 break; 748 } 749 } 750 751 /* Advanced DMA data transfer */ 752 753 static void sdhci_do_adma(SDHCIState *s) 754 { 755 unsigned int n, begin, length; 756 const uint16_t block_size = s->blksize & BLOCK_SIZE_MASK; 757 ADMADescr dscr = {}; 758 int i; 759 760 for (i = 0; i < SDHC_ADMA_DESCS_PER_DELAY; ++i) { 761 s->admaerr &= ~SDHC_ADMAERR_LENGTH_MISMATCH; 762 763 get_adma_description(s, &dscr); 764 trace_sdhci_adma_loop(dscr.addr, dscr.length, dscr.attr); 765 766 if ((dscr.attr & SDHC_ADMA_ATTR_VALID) == 0) { 767 /* Indicate that error occurred in ST_FDS state */ 768 s->admaerr &= ~SDHC_ADMAERR_STATE_MASK; 769 s->admaerr |= SDHC_ADMAERR_STATE_ST_FDS; 770 771 /* Generate ADMA error interrupt */ 772 if (s->errintstsen & SDHC_EISEN_ADMAERR) { 773 s->errintsts |= SDHC_EIS_ADMAERR; 774 s->norintsts |= SDHC_NIS_ERR; 775 } 776 777 sdhci_update_irq(s); 778 return; 779 } 780 781 length = dscr.length ? dscr.length : 65536; 782 783 switch (dscr.attr & SDHC_ADMA_ATTR_ACT_MASK) { 784 case SDHC_ADMA_ATTR_ACT_TRAN: /* data transfer */ 785 786 if (s->trnmod & SDHC_TRNS_READ) { 787 while (length) { 788 if (s->data_count == 0) { 789 for (n = 0; n < block_size; n++) { 790 s->fifo_buffer[n] = sdbus_read_data(&s->sdbus); 791 } 792 } 793 begin = s->data_count; 794 if ((length + begin) < block_size) { 795 s->data_count = length + begin; 796 length = 0; 797 } else { 798 s->data_count = block_size; 799 length -= block_size - begin; 800 } 801 dma_memory_write(s->dma_as, dscr.addr, 802 &s->fifo_buffer[begin], 803 s->data_count - begin); 804 dscr.addr += s->data_count - begin; 805 if (s->data_count == block_size) { 806 s->data_count = 0; 807 if (s->trnmod & SDHC_TRNS_BLK_CNT_EN) { 808 s->blkcnt--; 809 if (s->blkcnt == 0) { 810 break; 811 } 812 } 813 } 814 } 815 } else { 816 while (length) { 817 begin = s->data_count; 818 if ((length + begin) < block_size) { 819 s->data_count = length + begin; 820 length = 0; 821 } else { 822 s->data_count = block_size; 823 length -= block_size - begin; 824 } 825 dma_memory_read(s->dma_as, dscr.addr, 826 &s->fifo_buffer[begin], 827 s->data_count - begin); 828 dscr.addr += s->data_count - begin; 829 if (s->data_count == block_size) { 830 for (n = 0; n < block_size; n++) { 831 sdbus_write_data(&s->sdbus, s->fifo_buffer[n]); 832 } 833 s->data_count = 0; 834 if (s->trnmod & SDHC_TRNS_BLK_CNT_EN) { 835 s->blkcnt--; 836 if (s->blkcnt == 0) { 837 break; 838 } 839 } 840 } 841 } 842 } 843 s->admasysaddr += dscr.incr; 844 break; 845 case SDHC_ADMA_ATTR_ACT_LINK: /* link to next descriptor table */ 846 s->admasysaddr = dscr.addr; 847 trace_sdhci_adma("link", s->admasysaddr); 848 break; 849 default: 850 s->admasysaddr += dscr.incr; 851 break; 852 } 853 854 if (dscr.attr & SDHC_ADMA_ATTR_INT) { 855 trace_sdhci_adma("interrupt", s->admasysaddr); 856 if (s->norintstsen & SDHC_NISEN_DMA) { 857 s->norintsts |= SDHC_NIS_DMA; 858 } 859 860 sdhci_update_irq(s); 861 } 862 863 /* ADMA transfer terminates if blkcnt == 0 or by END attribute */ 864 if (((s->trnmod & SDHC_TRNS_BLK_CNT_EN) && 865 (s->blkcnt == 0)) || (dscr.attr & SDHC_ADMA_ATTR_END)) { 866 trace_sdhci_adma_transfer_completed(); 867 if (length || ((dscr.attr & SDHC_ADMA_ATTR_END) && 868 (s->trnmod & SDHC_TRNS_BLK_CNT_EN) && 869 s->blkcnt != 0)) { 870 trace_sdhci_error("SD/MMC host ADMA length mismatch"); 871 s->admaerr |= SDHC_ADMAERR_LENGTH_MISMATCH | 872 SDHC_ADMAERR_STATE_ST_TFR; 873 if (s->errintstsen & SDHC_EISEN_ADMAERR) { 874 trace_sdhci_error("Set ADMA error flag"); 875 s->errintsts |= SDHC_EIS_ADMAERR; 876 s->norintsts |= SDHC_NIS_ERR; 877 } 878 879 sdhci_update_irq(s); 880 } 881 sdhci_end_transfer(s); 882 return; 883 } 884 885 } 886 887 /* we have unfinished business - reschedule to continue ADMA */ 888 timer_mod(s->transfer_timer, 889 qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + SDHC_TRANSFER_DELAY); 890 } 891 892 /* Perform data transfer according to controller configuration */ 893 894 static void sdhci_data_transfer(void *opaque) 895 { 896 SDHCIState *s = (SDHCIState *)opaque; 897 898 if (s->trnmod & SDHC_TRNS_DMA) { 899 switch (SDHC_DMA_TYPE(s->hostctl1)) { 900 case SDHC_CTRL_SDMA: 901 if ((s->blkcnt == 1) || !(s->trnmod & SDHC_TRNS_MULTI)) { 902 sdhci_sdma_transfer_single_block(s); 903 } else { 904 sdhci_sdma_transfer_multi_blocks(s); 905 } 906 907 break; 908 case SDHC_CTRL_ADMA1_32: 909 if (!(s->capareg & R_SDHC_CAPAB_ADMA1_MASK)) { 910 trace_sdhci_error("ADMA1 not supported"); 911 break; 912 } 913 914 sdhci_do_adma(s); 915 break; 916 case SDHC_CTRL_ADMA2_32: 917 if (!(s->capareg & R_SDHC_CAPAB_ADMA2_MASK)) { 918 trace_sdhci_error("ADMA2 not supported"); 919 break; 920 } 921 922 sdhci_do_adma(s); 923 break; 924 case SDHC_CTRL_ADMA2_64: 925 if (!(s->capareg & R_SDHC_CAPAB_ADMA2_MASK) || 926 !(s->capareg & R_SDHC_CAPAB_BUS64BIT_MASK)) { 927 trace_sdhci_error("64 bit ADMA not supported"); 928 break; 929 } 930 931 sdhci_do_adma(s); 932 break; 933 default: 934 trace_sdhci_error("Unsupported DMA type"); 935 break; 936 } 937 } else { 938 if ((s->trnmod & SDHC_TRNS_READ) && sdbus_data_ready(&s->sdbus)) { 939 s->prnsts |= SDHC_DOING_READ | SDHC_DATA_INHIBIT | 940 SDHC_DAT_LINE_ACTIVE; 941 sdhci_read_block_from_card(s); 942 } else { 943 s->prnsts |= SDHC_DOING_WRITE | SDHC_DAT_LINE_ACTIVE | 944 SDHC_SPACE_AVAILABLE | SDHC_DATA_INHIBIT; 945 sdhci_write_block_to_card(s); 946 } 947 } 948 } 949 950 static bool sdhci_can_issue_command(SDHCIState *s) 951 { 952 if (!SDHC_CLOCK_IS_ON(s->clkcon) || 953 (((s->prnsts & SDHC_DATA_INHIBIT) || s->stopped_state) && 954 ((s->cmdreg & SDHC_CMD_DATA_PRESENT) || 955 ((s->cmdreg & SDHC_CMD_RESPONSE) == SDHC_CMD_RSP_WITH_BUSY && 956 !(SDHC_COMMAND_TYPE(s->cmdreg) == SDHC_CMD_ABORT))))) { 957 return false; 958 } 959 960 return true; 961 } 962 963 /* The Buffer Data Port register must be accessed in sequential and 964 * continuous manner */ 965 static inline bool 966 sdhci_buff_access_is_sequential(SDHCIState *s, unsigned byte_num) 967 { 968 if ((s->data_count & 0x3) != byte_num) { 969 trace_sdhci_error("Non-sequential access to Buffer Data Port register" 970 "is prohibited\n"); 971 return false; 972 } 973 return true; 974 } 975 976 static uint64_t sdhci_read(void *opaque, hwaddr offset, unsigned size) 977 { 978 SDHCIState *s = (SDHCIState *)opaque; 979 uint32_t ret = 0; 980 981 switch (offset & ~0x3) { 982 case SDHC_SYSAD: 983 ret = s->sdmasysad; 984 break; 985 case SDHC_BLKSIZE: 986 ret = s->blksize | (s->blkcnt << 16); 987 break; 988 case SDHC_ARGUMENT: 989 ret = s->argument; 990 break; 991 case SDHC_TRNMOD: 992 ret = s->trnmod | (s->cmdreg << 16); 993 break; 994 case SDHC_RSPREG0 ... SDHC_RSPREG3: 995 ret = s->rspreg[((offset & ~0x3) - SDHC_RSPREG0) >> 2]; 996 break; 997 case SDHC_BDATA: 998 if (sdhci_buff_access_is_sequential(s, offset - SDHC_BDATA)) { 999 ret = sdhci_read_dataport(s, size); 1000 trace_sdhci_access("rd", size << 3, offset, "->", ret, ret); 1001 return ret; 1002 } 1003 break; 1004 case SDHC_PRNSTS: 1005 ret = s->prnsts; 1006 ret = FIELD_DP32(ret, SDHC_PRNSTS, DAT_LVL, 1007 sdbus_get_dat_lines(&s->sdbus)); 1008 ret = FIELD_DP32(ret, SDHC_PRNSTS, CMD_LVL, 1009 sdbus_get_cmd_line(&s->sdbus)); 1010 break; 1011 case SDHC_HOSTCTL: 1012 ret = s->hostctl1 | (s->pwrcon << 8) | (s->blkgap << 16) | 1013 (s->wakcon << 24); 1014 break; 1015 case SDHC_CLKCON: 1016 ret = s->clkcon | (s->timeoutcon << 16); 1017 break; 1018 case SDHC_NORINTSTS: 1019 ret = s->norintsts | (s->errintsts << 16); 1020 break; 1021 case SDHC_NORINTSTSEN: 1022 ret = s->norintstsen | (s->errintstsen << 16); 1023 break; 1024 case SDHC_NORINTSIGEN: 1025 ret = s->norintsigen | (s->errintsigen << 16); 1026 break; 1027 case SDHC_ACMD12ERRSTS: 1028 ret = s->acmd12errsts | (s->hostctl2 << 16); 1029 break; 1030 case SDHC_CAPAB: 1031 ret = (uint32_t)s->capareg; 1032 break; 1033 case SDHC_CAPAB + 4: 1034 ret = (uint32_t)(s->capareg >> 32); 1035 break; 1036 case SDHC_MAXCURR: 1037 ret = (uint32_t)s->maxcurr; 1038 break; 1039 case SDHC_MAXCURR + 4: 1040 ret = (uint32_t)(s->maxcurr >> 32); 1041 break; 1042 case SDHC_ADMAERR: 1043 ret = s->admaerr; 1044 break; 1045 case SDHC_ADMASYSADDR: 1046 ret = (uint32_t)s->admasysaddr; 1047 break; 1048 case SDHC_ADMASYSADDR + 4: 1049 ret = (uint32_t)(s->admasysaddr >> 32); 1050 break; 1051 case SDHC_SLOT_INT_STATUS: 1052 ret = (s->version << 16) | sdhci_slotint(s); 1053 break; 1054 default: 1055 qemu_log_mask(LOG_UNIMP, "SDHC rd_%ub @0x%02" HWADDR_PRIx " " 1056 "not implemented\n", size, offset); 1057 break; 1058 } 1059 1060 ret >>= (offset & 0x3) * 8; 1061 ret &= (1ULL << (size * 8)) - 1; 1062 trace_sdhci_access("rd", size << 3, offset, "->", ret, ret); 1063 return ret; 1064 } 1065 1066 static inline void sdhci_blkgap_write(SDHCIState *s, uint8_t value) 1067 { 1068 if ((value & SDHC_STOP_AT_GAP_REQ) && (s->blkgap & SDHC_STOP_AT_GAP_REQ)) { 1069 return; 1070 } 1071 s->blkgap = value & SDHC_STOP_AT_GAP_REQ; 1072 1073 if ((value & SDHC_CONTINUE_REQ) && s->stopped_state && 1074 (s->blkgap & SDHC_STOP_AT_GAP_REQ) == 0) { 1075 if (s->stopped_state == sdhc_gap_read) { 1076 s->prnsts |= SDHC_DAT_LINE_ACTIVE | SDHC_DOING_READ; 1077 sdhci_read_block_from_card(s); 1078 } else { 1079 s->prnsts |= SDHC_DAT_LINE_ACTIVE | SDHC_DOING_WRITE; 1080 sdhci_write_block_to_card(s); 1081 } 1082 s->stopped_state = sdhc_not_stopped; 1083 } else if (!s->stopped_state && (value & SDHC_STOP_AT_GAP_REQ)) { 1084 if (s->prnsts & SDHC_DOING_READ) { 1085 s->stopped_state = sdhc_gap_read; 1086 } else if (s->prnsts & SDHC_DOING_WRITE) { 1087 s->stopped_state = sdhc_gap_write; 1088 } 1089 } 1090 } 1091 1092 static inline void sdhci_reset_write(SDHCIState *s, uint8_t value) 1093 { 1094 switch (value) { 1095 case SDHC_RESET_ALL: 1096 sdhci_reset(s); 1097 break; 1098 case SDHC_RESET_CMD: 1099 s->prnsts &= ~SDHC_CMD_INHIBIT; 1100 s->norintsts &= ~SDHC_NIS_CMDCMP; 1101 break; 1102 case SDHC_RESET_DATA: 1103 s->data_count = 0; 1104 s->prnsts &= ~(SDHC_SPACE_AVAILABLE | SDHC_DATA_AVAILABLE | 1105 SDHC_DOING_READ | SDHC_DOING_WRITE | 1106 SDHC_DATA_INHIBIT | SDHC_DAT_LINE_ACTIVE); 1107 s->blkgap &= ~(SDHC_STOP_AT_GAP_REQ | SDHC_CONTINUE_REQ); 1108 s->stopped_state = sdhc_not_stopped; 1109 s->norintsts &= ~(SDHC_NIS_WBUFRDY | SDHC_NIS_RBUFRDY | 1110 SDHC_NIS_DMA | SDHC_NIS_TRSCMP | SDHC_NIS_BLKGAP); 1111 break; 1112 } 1113 } 1114 1115 static void 1116 sdhci_write(void *opaque, hwaddr offset, uint64_t val, unsigned size) 1117 { 1118 SDHCIState *s = (SDHCIState *)opaque; 1119 unsigned shift = 8 * (offset & 0x3); 1120 uint32_t mask = ~(((1ULL << (size * 8)) - 1) << shift); 1121 uint32_t value = val; 1122 value <<= shift; 1123 1124 switch (offset & ~0x3) { 1125 case SDHC_SYSAD: 1126 s->sdmasysad = (s->sdmasysad & mask) | value; 1127 MASKED_WRITE(s->sdmasysad, mask, value); 1128 /* Writing to last byte of sdmasysad might trigger transfer */ 1129 if (!(mask & 0xFF000000) && TRANSFERRING_DATA(s->prnsts) && s->blkcnt && 1130 s->blksize && SDHC_DMA_TYPE(s->hostctl1) == SDHC_CTRL_SDMA) { 1131 if (s->trnmod & SDHC_TRNS_MULTI) { 1132 sdhci_sdma_transfer_multi_blocks(s); 1133 } else { 1134 sdhci_sdma_transfer_single_block(s); 1135 } 1136 } 1137 break; 1138 case SDHC_BLKSIZE: 1139 if (!TRANSFERRING_DATA(s->prnsts)) { 1140 MASKED_WRITE(s->blksize, mask, value); 1141 MASKED_WRITE(s->blkcnt, mask >> 16, value >> 16); 1142 } 1143 1144 /* Limit block size to the maximum buffer size */ 1145 if (extract32(s->blksize, 0, 12) > s->buf_maxsz) { 1146 qemu_log_mask(LOG_GUEST_ERROR, "%s: Size 0x%x is larger than " \ 1147 "the maximum buffer 0x%x", __func__, s->blksize, 1148 s->buf_maxsz); 1149 1150 s->blksize = deposit32(s->blksize, 0, 12, s->buf_maxsz); 1151 } 1152 1153 break; 1154 case SDHC_ARGUMENT: 1155 MASKED_WRITE(s->argument, mask, value); 1156 break; 1157 case SDHC_TRNMOD: 1158 /* DMA can be enabled only if it is supported as indicated by 1159 * capabilities register */ 1160 if (!(s->capareg & R_SDHC_CAPAB_SDMA_MASK)) { 1161 value &= ~SDHC_TRNS_DMA; 1162 } 1163 MASKED_WRITE(s->trnmod, mask, value & SDHC_TRNMOD_MASK); 1164 MASKED_WRITE(s->cmdreg, mask >> 16, value >> 16); 1165 1166 /* Writing to the upper byte of CMDREG triggers SD command generation */ 1167 if ((mask & 0xFF000000) || !sdhci_can_issue_command(s)) { 1168 break; 1169 } 1170 1171 sdhci_send_command(s); 1172 break; 1173 case SDHC_BDATA: 1174 if (sdhci_buff_access_is_sequential(s, offset - SDHC_BDATA)) { 1175 sdhci_write_dataport(s, value >> shift, size); 1176 } 1177 break; 1178 case SDHC_HOSTCTL: 1179 if (!(mask & 0xFF0000)) { 1180 sdhci_blkgap_write(s, value >> 16); 1181 } 1182 MASKED_WRITE(s->hostctl1, mask, value); 1183 MASKED_WRITE(s->pwrcon, mask >> 8, value >> 8); 1184 MASKED_WRITE(s->wakcon, mask >> 24, value >> 24); 1185 if (!(s->prnsts & SDHC_CARD_PRESENT) || ((s->pwrcon >> 1) & 0x7) < 5 || 1186 !(s->capareg & (1 << (31 - ((s->pwrcon >> 1) & 0x7))))) { 1187 s->pwrcon &= ~SDHC_POWER_ON; 1188 } 1189 break; 1190 case SDHC_CLKCON: 1191 if (!(mask & 0xFF000000)) { 1192 sdhci_reset_write(s, value >> 24); 1193 } 1194 MASKED_WRITE(s->clkcon, mask, value); 1195 MASKED_WRITE(s->timeoutcon, mask >> 16, value >> 16); 1196 if (s->clkcon & SDHC_CLOCK_INT_EN) { 1197 s->clkcon |= SDHC_CLOCK_INT_STABLE; 1198 } else { 1199 s->clkcon &= ~SDHC_CLOCK_INT_STABLE; 1200 } 1201 break; 1202 case SDHC_NORINTSTS: 1203 if (s->norintstsen & SDHC_NISEN_CARDINT) { 1204 value &= ~SDHC_NIS_CARDINT; 1205 } 1206 s->norintsts &= mask | ~value; 1207 s->errintsts &= (mask >> 16) | ~(value >> 16); 1208 if (s->errintsts) { 1209 s->norintsts |= SDHC_NIS_ERR; 1210 } else { 1211 s->norintsts &= ~SDHC_NIS_ERR; 1212 } 1213 sdhci_update_irq(s); 1214 break; 1215 case SDHC_NORINTSTSEN: 1216 MASKED_WRITE(s->norintstsen, mask, value); 1217 MASKED_WRITE(s->errintstsen, mask >> 16, value >> 16); 1218 s->norintsts &= s->norintstsen; 1219 s->errintsts &= s->errintstsen; 1220 if (s->errintsts) { 1221 s->norintsts |= SDHC_NIS_ERR; 1222 } else { 1223 s->norintsts &= ~SDHC_NIS_ERR; 1224 } 1225 /* Quirk for Raspberry Pi: pending card insert interrupt 1226 * appears when first enabled after power on */ 1227 if ((s->norintstsen & SDHC_NISEN_INSERT) && s->pending_insert_state) { 1228 assert(s->pending_insert_quirk); 1229 s->norintsts |= SDHC_NIS_INSERT; 1230 s->pending_insert_state = false; 1231 } 1232 sdhci_update_irq(s); 1233 break; 1234 case SDHC_NORINTSIGEN: 1235 MASKED_WRITE(s->norintsigen, mask, value); 1236 MASKED_WRITE(s->errintsigen, mask >> 16, value >> 16); 1237 sdhci_update_irq(s); 1238 break; 1239 case SDHC_ADMAERR: 1240 MASKED_WRITE(s->admaerr, mask, value); 1241 break; 1242 case SDHC_ADMASYSADDR: 1243 s->admasysaddr = (s->admasysaddr & (0xFFFFFFFF00000000ULL | 1244 (uint64_t)mask)) | (uint64_t)value; 1245 break; 1246 case SDHC_ADMASYSADDR + 4: 1247 s->admasysaddr = (s->admasysaddr & (0x00000000FFFFFFFFULL | 1248 ((uint64_t)mask << 32))) | ((uint64_t)value << 32); 1249 break; 1250 case SDHC_FEAER: 1251 s->acmd12errsts |= value; 1252 s->errintsts |= (value >> 16) & s->errintstsen; 1253 if (s->acmd12errsts) { 1254 s->errintsts |= SDHC_EIS_CMD12ERR; 1255 } 1256 if (s->errintsts) { 1257 s->norintsts |= SDHC_NIS_ERR; 1258 } 1259 sdhci_update_irq(s); 1260 break; 1261 case SDHC_ACMD12ERRSTS: 1262 MASKED_WRITE(s->acmd12errsts, mask, value & UINT16_MAX); 1263 if (s->uhs_mode >= UHS_I) { 1264 MASKED_WRITE(s->hostctl2, mask >> 16, value >> 16); 1265 1266 if (FIELD_EX32(s->hostctl2, SDHC_HOSTCTL2, V18_ENA)) { 1267 sdbus_set_voltage(&s->sdbus, SD_VOLTAGE_1_8V); 1268 } else { 1269 sdbus_set_voltage(&s->sdbus, SD_VOLTAGE_3_3V); 1270 } 1271 } 1272 break; 1273 1274 case SDHC_CAPAB: 1275 case SDHC_CAPAB + 4: 1276 case SDHC_MAXCURR: 1277 case SDHC_MAXCURR + 4: 1278 qemu_log_mask(LOG_GUEST_ERROR, "SDHC wr_%ub @0x%02" HWADDR_PRIx 1279 " <- 0x%08x read-only\n", size, offset, value >> shift); 1280 break; 1281 1282 default: 1283 qemu_log_mask(LOG_UNIMP, "SDHC wr_%ub @0x%02" HWADDR_PRIx " <- 0x%08x " 1284 "not implemented\n", size, offset, value >> shift); 1285 break; 1286 } 1287 trace_sdhci_access("wr", size << 3, offset, "<-", 1288 value >> shift, value >> shift); 1289 } 1290 1291 static const MemoryRegionOps sdhci_mmio_ops = { 1292 .read = sdhci_read, 1293 .write = sdhci_write, 1294 .valid = { 1295 .min_access_size = 1, 1296 .max_access_size = 4, 1297 .unaligned = false 1298 }, 1299 .endianness = DEVICE_LITTLE_ENDIAN, 1300 }; 1301 1302 static void sdhci_init_readonly_registers(SDHCIState *s, Error **errp) 1303 { 1304 Error *local_err = NULL; 1305 1306 switch (s->sd_spec_version) { 1307 case 2 ... 3: 1308 break; 1309 default: 1310 error_setg(errp, "Only Spec v2/v3 are supported"); 1311 return; 1312 } 1313 s->version = (SDHC_HCVER_VENDOR << 8) | (s->sd_spec_version - 1); 1314 1315 sdhci_check_capareg(s, &local_err); 1316 if (local_err) { 1317 error_propagate(errp, local_err); 1318 return; 1319 } 1320 } 1321 1322 /* --- qdev common --- */ 1323 1324 #define DEFINE_SDHCI_COMMON_PROPERTIES(_state) \ 1325 DEFINE_PROP_UINT8("sd-spec-version", _state, sd_spec_version, 2), \ 1326 DEFINE_PROP_UINT8("uhs", _state, uhs_mode, UHS_NOT_SUPPORTED), \ 1327 \ 1328 /* Capabilities registers provide information on supported 1329 * features of this specific host controller implementation */ \ 1330 DEFINE_PROP_UINT64("capareg", _state, capareg, SDHC_CAPAB_REG_DEFAULT), \ 1331 DEFINE_PROP_UINT64("maxcurr", _state, maxcurr, 0) 1332 1333 static void sdhci_initfn(SDHCIState *s) 1334 { 1335 qbus_create_inplace(&s->sdbus, sizeof(s->sdbus), 1336 TYPE_SDHCI_BUS, DEVICE(s), "sd-bus"); 1337 1338 s->insert_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, sdhci_raise_insertion_irq, s); 1339 s->transfer_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, sdhci_data_transfer, s); 1340 1341 s->io_ops = &sdhci_mmio_ops; 1342 } 1343 1344 static void sdhci_uninitfn(SDHCIState *s) 1345 { 1346 timer_del(s->insert_timer); 1347 timer_free(s->insert_timer); 1348 timer_del(s->transfer_timer); 1349 timer_free(s->transfer_timer); 1350 1351 g_free(s->fifo_buffer); 1352 s->fifo_buffer = NULL; 1353 } 1354 1355 static void sdhci_common_realize(SDHCIState *s, Error **errp) 1356 { 1357 Error *local_err = NULL; 1358 1359 sdhci_init_readonly_registers(s, &local_err); 1360 if (local_err) { 1361 error_propagate(errp, local_err); 1362 return; 1363 } 1364 s->buf_maxsz = sdhci_get_fifolen(s); 1365 s->fifo_buffer = g_malloc0(s->buf_maxsz); 1366 1367 memory_region_init_io(&s->iomem, OBJECT(s), &sdhci_mmio_ops, s, "sdhci", 1368 SDHC_REGISTERS_MAP_SIZE); 1369 } 1370 1371 static void sdhci_common_unrealize(SDHCIState *s, Error **errp) 1372 { 1373 /* This function is expected to be called only once for each class: 1374 * - SysBus: via DeviceClass->unrealize(), 1375 * - PCI: via PCIDeviceClass->exit(). 1376 * However to avoid double-free and/or use-after-free we still nullify 1377 * this variable (better safe than sorry!). */ 1378 g_free(s->fifo_buffer); 1379 s->fifo_buffer = NULL; 1380 } 1381 1382 static bool sdhci_pending_insert_vmstate_needed(void *opaque) 1383 { 1384 SDHCIState *s = opaque; 1385 1386 return s->pending_insert_state; 1387 } 1388 1389 static const VMStateDescription sdhci_pending_insert_vmstate = { 1390 .name = "sdhci/pending-insert", 1391 .version_id = 1, 1392 .minimum_version_id = 1, 1393 .needed = sdhci_pending_insert_vmstate_needed, 1394 .fields = (VMStateField[]) { 1395 VMSTATE_BOOL(pending_insert_state, SDHCIState), 1396 VMSTATE_END_OF_LIST() 1397 }, 1398 }; 1399 1400 const VMStateDescription sdhci_vmstate = { 1401 .name = "sdhci", 1402 .version_id = 1, 1403 .minimum_version_id = 1, 1404 .fields = (VMStateField[]) { 1405 VMSTATE_UINT32(sdmasysad, SDHCIState), 1406 VMSTATE_UINT16(blksize, SDHCIState), 1407 VMSTATE_UINT16(blkcnt, SDHCIState), 1408 VMSTATE_UINT32(argument, SDHCIState), 1409 VMSTATE_UINT16(trnmod, SDHCIState), 1410 VMSTATE_UINT16(cmdreg, SDHCIState), 1411 VMSTATE_UINT32_ARRAY(rspreg, SDHCIState, 4), 1412 VMSTATE_UINT32(prnsts, SDHCIState), 1413 VMSTATE_UINT8(hostctl1, SDHCIState), 1414 VMSTATE_UINT8(pwrcon, SDHCIState), 1415 VMSTATE_UINT8(blkgap, SDHCIState), 1416 VMSTATE_UINT8(wakcon, SDHCIState), 1417 VMSTATE_UINT16(clkcon, SDHCIState), 1418 VMSTATE_UINT8(timeoutcon, SDHCIState), 1419 VMSTATE_UINT8(admaerr, SDHCIState), 1420 VMSTATE_UINT16(norintsts, SDHCIState), 1421 VMSTATE_UINT16(errintsts, SDHCIState), 1422 VMSTATE_UINT16(norintstsen, SDHCIState), 1423 VMSTATE_UINT16(errintstsen, SDHCIState), 1424 VMSTATE_UINT16(norintsigen, SDHCIState), 1425 VMSTATE_UINT16(errintsigen, SDHCIState), 1426 VMSTATE_UINT16(acmd12errsts, SDHCIState), 1427 VMSTATE_UINT16(data_count, SDHCIState), 1428 VMSTATE_UINT64(admasysaddr, SDHCIState), 1429 VMSTATE_UINT8(stopped_state, SDHCIState), 1430 VMSTATE_VBUFFER_UINT32(fifo_buffer, SDHCIState, 1, NULL, buf_maxsz), 1431 VMSTATE_TIMER_PTR(insert_timer, SDHCIState), 1432 VMSTATE_TIMER_PTR(transfer_timer, SDHCIState), 1433 VMSTATE_END_OF_LIST() 1434 }, 1435 .subsections = (const VMStateDescription*[]) { 1436 &sdhci_pending_insert_vmstate, 1437 NULL 1438 }, 1439 }; 1440 1441 static void sdhci_common_class_init(ObjectClass *klass, void *data) 1442 { 1443 DeviceClass *dc = DEVICE_CLASS(klass); 1444 1445 set_bit(DEVICE_CATEGORY_STORAGE, dc->categories); 1446 dc->vmsd = &sdhci_vmstate; 1447 dc->reset = sdhci_poweron_reset; 1448 } 1449 1450 /* --- qdev PCI --- */ 1451 1452 static Property sdhci_pci_properties[] = { 1453 DEFINE_SDHCI_COMMON_PROPERTIES(SDHCIState), 1454 DEFINE_PROP_END_OF_LIST(), 1455 }; 1456 1457 static void sdhci_pci_realize(PCIDevice *dev, Error **errp) 1458 { 1459 SDHCIState *s = PCI_SDHCI(dev); 1460 Error *local_err = NULL; 1461 1462 sdhci_initfn(s); 1463 sdhci_common_realize(s, errp); 1464 if (local_err) { 1465 error_propagate(errp, local_err); 1466 return; 1467 } 1468 1469 dev->config[PCI_CLASS_PROG] = 0x01; /* Standard Host supported DMA */ 1470 dev->config[PCI_INTERRUPT_PIN] = 0x01; /* interrupt pin A */ 1471 s->irq = pci_allocate_irq(dev); 1472 s->dma_as = pci_get_address_space(dev); 1473 pci_register_bar(dev, 0, PCI_BASE_ADDRESS_SPACE_MEMORY, &s->iomem); 1474 } 1475 1476 static void sdhci_pci_exit(PCIDevice *dev) 1477 { 1478 SDHCIState *s = PCI_SDHCI(dev); 1479 1480 sdhci_common_unrealize(s, &error_abort); 1481 sdhci_uninitfn(s); 1482 } 1483 1484 static void sdhci_pci_class_init(ObjectClass *klass, void *data) 1485 { 1486 DeviceClass *dc = DEVICE_CLASS(klass); 1487 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); 1488 1489 k->realize = sdhci_pci_realize; 1490 k->exit = sdhci_pci_exit; 1491 k->vendor_id = PCI_VENDOR_ID_REDHAT; 1492 k->device_id = PCI_DEVICE_ID_REDHAT_SDHCI; 1493 k->class_id = PCI_CLASS_SYSTEM_SDHCI; 1494 dc->props = sdhci_pci_properties; 1495 1496 sdhci_common_class_init(klass, data); 1497 } 1498 1499 static const TypeInfo sdhci_pci_info = { 1500 .name = TYPE_PCI_SDHCI, 1501 .parent = TYPE_PCI_DEVICE, 1502 .instance_size = sizeof(SDHCIState), 1503 .class_init = sdhci_pci_class_init, 1504 .interfaces = (InterfaceInfo[]) { 1505 { INTERFACE_CONVENTIONAL_PCI_DEVICE }, 1506 { }, 1507 }, 1508 }; 1509 1510 /* --- qdev SysBus --- */ 1511 1512 static Property sdhci_sysbus_properties[] = { 1513 DEFINE_SDHCI_COMMON_PROPERTIES(SDHCIState), 1514 DEFINE_PROP_BOOL("pending-insert-quirk", SDHCIState, pending_insert_quirk, 1515 false), 1516 DEFINE_PROP_LINK("dma", SDHCIState, 1517 dma_mr, TYPE_MEMORY_REGION, MemoryRegion *), 1518 DEFINE_PROP_END_OF_LIST(), 1519 }; 1520 1521 static void sdhci_sysbus_init(Object *obj) 1522 { 1523 SDHCIState *s = SYSBUS_SDHCI(obj); 1524 1525 sdhci_initfn(s); 1526 } 1527 1528 static void sdhci_sysbus_finalize(Object *obj) 1529 { 1530 SDHCIState *s = SYSBUS_SDHCI(obj); 1531 1532 if (s->dma_mr) { 1533 object_unparent(OBJECT(s->dma_mr)); 1534 } 1535 1536 sdhci_uninitfn(s); 1537 } 1538 1539 static void sdhci_sysbus_realize(DeviceState *dev, Error ** errp) 1540 { 1541 SDHCIState *s = SYSBUS_SDHCI(dev); 1542 SysBusDevice *sbd = SYS_BUS_DEVICE(dev); 1543 Error *local_err = NULL; 1544 1545 sdhci_common_realize(s, errp); 1546 if (local_err) { 1547 error_propagate(errp, local_err); 1548 return; 1549 } 1550 1551 if (s->dma_mr) { 1552 s->dma_as = &s->sysbus_dma_as; 1553 address_space_init(s->dma_as, s->dma_mr, "sdhci-dma"); 1554 } else { 1555 /* use system_memory() if property "dma" not set */ 1556 s->dma_as = &address_space_memory; 1557 } 1558 1559 sysbus_init_irq(sbd, &s->irq); 1560 1561 memory_region_init_io(&s->iomem, OBJECT(s), s->io_ops, s, "sdhci", 1562 SDHC_REGISTERS_MAP_SIZE); 1563 1564 sysbus_init_mmio(sbd, &s->iomem); 1565 } 1566 1567 static void sdhci_sysbus_unrealize(DeviceState *dev, Error **errp) 1568 { 1569 SDHCIState *s = SYSBUS_SDHCI(dev); 1570 1571 sdhci_common_unrealize(s, &error_abort); 1572 1573 if (s->dma_mr) { 1574 address_space_destroy(s->dma_as); 1575 } 1576 } 1577 1578 static void sdhci_sysbus_class_init(ObjectClass *klass, void *data) 1579 { 1580 DeviceClass *dc = DEVICE_CLASS(klass); 1581 1582 dc->props = sdhci_sysbus_properties; 1583 dc->realize = sdhci_sysbus_realize; 1584 dc->unrealize = sdhci_sysbus_unrealize; 1585 1586 sdhci_common_class_init(klass, data); 1587 } 1588 1589 static const TypeInfo sdhci_sysbus_info = { 1590 .name = TYPE_SYSBUS_SDHCI, 1591 .parent = TYPE_SYS_BUS_DEVICE, 1592 .instance_size = sizeof(SDHCIState), 1593 .instance_init = sdhci_sysbus_init, 1594 .instance_finalize = sdhci_sysbus_finalize, 1595 .class_init = sdhci_sysbus_class_init, 1596 }; 1597 1598 /* --- qdev bus master --- */ 1599 1600 static void sdhci_bus_class_init(ObjectClass *klass, void *data) 1601 { 1602 SDBusClass *sbc = SD_BUS_CLASS(klass); 1603 1604 sbc->set_inserted = sdhci_set_inserted; 1605 sbc->set_readonly = sdhci_set_readonly; 1606 } 1607 1608 static const TypeInfo sdhci_bus_info = { 1609 .name = TYPE_SDHCI_BUS, 1610 .parent = TYPE_SD_BUS, 1611 .instance_size = sizeof(SDBus), 1612 .class_init = sdhci_bus_class_init, 1613 }; 1614 1615 static uint64_t usdhc_read(void *opaque, hwaddr offset, unsigned size) 1616 { 1617 SDHCIState *s = SYSBUS_SDHCI(opaque); 1618 uint32_t ret; 1619 uint16_t hostctl1; 1620 1621 switch (offset) { 1622 default: 1623 return sdhci_read(opaque, offset, size); 1624 1625 case SDHC_HOSTCTL: 1626 /* 1627 * For a detailed explanation on the following bit 1628 * manipulation code see comments in a similar part of 1629 * usdhc_write() 1630 */ 1631 hostctl1 = SDHC_DMA_TYPE(s->hostctl1) << (8 - 3); 1632 1633 if (s->hostctl1 & SDHC_CTRL_8BITBUS) { 1634 hostctl1 |= ESDHC_CTRL_8BITBUS; 1635 } 1636 1637 if (s->hostctl1 & SDHC_CTRL_4BITBUS) { 1638 hostctl1 |= ESDHC_CTRL_4BITBUS; 1639 } 1640 1641 ret = hostctl1; 1642 ret |= (uint32_t)s->blkgap << 16; 1643 ret |= (uint32_t)s->wakcon << 24; 1644 1645 break; 1646 1647 case ESDHC_DLL_CTRL: 1648 case ESDHC_TUNE_CTRL_STATUS: 1649 case ESDHC_UNDOCUMENTED_REG27: 1650 case ESDHC_TUNING_CTRL: 1651 case ESDHC_VENDOR_SPEC: 1652 case ESDHC_MIX_CTRL: 1653 case ESDHC_WTMK_LVL: 1654 ret = 0; 1655 break; 1656 } 1657 1658 return ret; 1659 } 1660 1661 static void 1662 usdhc_write(void *opaque, hwaddr offset, uint64_t val, unsigned size) 1663 { 1664 SDHCIState *s = SYSBUS_SDHCI(opaque); 1665 uint8_t hostctl1; 1666 uint32_t value = (uint32_t)val; 1667 1668 switch (offset) { 1669 case ESDHC_DLL_CTRL: 1670 case ESDHC_TUNE_CTRL_STATUS: 1671 case ESDHC_UNDOCUMENTED_REG27: 1672 case ESDHC_TUNING_CTRL: 1673 case ESDHC_WTMK_LVL: 1674 case ESDHC_VENDOR_SPEC: 1675 break; 1676 1677 case SDHC_HOSTCTL: 1678 /* 1679 * Here's What ESDHCI has at offset 0x28 (SDHC_HOSTCTL) 1680 * 1681 * 7 6 5 4 3 2 1 0 1682 * |-----------+--------+--------+-----------+----------+---------| 1683 * | Card | Card | Endian | DATA3 | Data | Led | 1684 * | Detect | Detect | Mode | as Card | Transfer | Control | 1685 * | Signal | Test | | Detection | Width | | 1686 * | Selection | Level | | Pin | | | 1687 * |-----------+--------+--------+-----------+----------+---------| 1688 * 1689 * and 0x29 1690 * 1691 * 15 10 9 8 1692 * |----------+------| 1693 * | Reserved | DMA | 1694 * | | Sel. | 1695 * | | | 1696 * |----------+------| 1697 * 1698 * and here's what SDCHI spec expects those offsets to be: 1699 * 1700 * 0x28 (Host Control Register) 1701 * 1702 * 7 6 5 4 3 2 1 0 1703 * |--------+--------+----------+------+--------+----------+---------| 1704 * | Card | Card | Extended | DMA | High | Data | LED | 1705 * | Detect | Detect | Data | Sel. | Speed | Transfer | Control | 1706 * | Signal | Test | Transfer | | Enable | Width | | 1707 * | Sel. | Level | Width | | | | | 1708 * |--------+--------+----------+------+--------+----------+---------| 1709 * 1710 * and 0x29 (Power Control Register) 1711 * 1712 * |----------------------------------| 1713 * | Power Control Register | 1714 * | | 1715 * | Description omitted, | 1716 * | since it has no analog in ESDHCI | 1717 * | | 1718 * |----------------------------------| 1719 * 1720 * Since offsets 0x2A and 0x2B should be compatible between 1721 * both IP specs we only need to reconcile least 16-bit of the 1722 * word we've been given. 1723 */ 1724 1725 /* 1726 * First, save bits 7 6 and 0 since they are identical 1727 */ 1728 hostctl1 = value & (SDHC_CTRL_LED | 1729 SDHC_CTRL_CDTEST_INS | 1730 SDHC_CTRL_CDTEST_EN); 1731 /* 1732 * Second, split "Data Transfer Width" from bits 2 and 1 in to 1733 * bits 5 and 1 1734 */ 1735 if (value & ESDHC_CTRL_8BITBUS) { 1736 hostctl1 |= SDHC_CTRL_8BITBUS; 1737 } 1738 1739 if (value & ESDHC_CTRL_4BITBUS) { 1740 hostctl1 |= ESDHC_CTRL_4BITBUS; 1741 } 1742 1743 /* 1744 * Third, move DMA select from bits 9 and 8 to bits 4 and 3 1745 */ 1746 hostctl1 |= SDHC_DMA_TYPE(value >> (8 - 3)); 1747 1748 /* 1749 * Now place the corrected value into low 16-bit of the value 1750 * we are going to give standard SDHCI write function 1751 * 1752 * NOTE: This transformation should be the inverse of what can 1753 * be found in drivers/mmc/host/sdhci-esdhc-imx.c in Linux 1754 * kernel 1755 */ 1756 value &= ~UINT16_MAX; 1757 value |= hostctl1; 1758 value |= (uint16_t)s->pwrcon << 8; 1759 1760 sdhci_write(opaque, offset, value, size); 1761 break; 1762 1763 case ESDHC_MIX_CTRL: 1764 /* 1765 * So, when SD/MMC stack in Linux tries to write to "Transfer 1766 * Mode Register", ESDHC i.MX quirk code will translate it 1767 * into a write to ESDHC_MIX_CTRL, so we do the opposite in 1768 * order to get where we started 1769 * 1770 * Note that Auto CMD23 Enable bit is located in a wrong place 1771 * on i.MX, but since it is not used by QEMU we do not care. 1772 * 1773 * We don't want to call sdhci_write(.., SDHC_TRNMOD, ...) 1774 * here becuase it will result in a call to 1775 * sdhci_send_command(s) which we don't want. 1776 * 1777 */ 1778 s->trnmod = value & UINT16_MAX; 1779 break; 1780 case SDHC_TRNMOD: 1781 /* 1782 * Similar to above, but this time a write to "Command 1783 * Register" will be translated into a 4-byte write to 1784 * "Transfer Mode register" where lower 16-bit of value would 1785 * be set to zero. So what we do is fill those bits with 1786 * cached value from s->trnmod and let the SDHCI 1787 * infrastructure handle the rest 1788 */ 1789 sdhci_write(opaque, offset, val | s->trnmod, size); 1790 break; 1791 case SDHC_BLKSIZE: 1792 /* 1793 * ESDHCI does not implement "Host SDMA Buffer Boundary", and 1794 * Linux driver will try to zero this field out which will 1795 * break the rest of SDHCI emulation. 1796 * 1797 * Linux defaults to maximum possible setting (512K boundary) 1798 * and it seems to be the only option that i.MX IP implements, 1799 * so we artificially set it to that value. 1800 */ 1801 val |= 0x7 << 12; 1802 /* FALLTHROUGH */ 1803 default: 1804 sdhci_write(opaque, offset, val, size); 1805 break; 1806 } 1807 } 1808 1809 1810 static const MemoryRegionOps usdhc_mmio_ops = { 1811 .read = usdhc_read, 1812 .write = usdhc_write, 1813 .valid = { 1814 .min_access_size = 1, 1815 .max_access_size = 4, 1816 .unaligned = false 1817 }, 1818 .endianness = DEVICE_LITTLE_ENDIAN, 1819 }; 1820 1821 static void imx_usdhc_init(Object *obj) 1822 { 1823 SDHCIState *s = SYSBUS_SDHCI(obj); 1824 1825 s->io_ops = &usdhc_mmio_ops; 1826 s->quirks = SDHCI_QUIRK_NO_BUSY_IRQ; 1827 } 1828 1829 static const TypeInfo imx_usdhc_info = { 1830 .name = TYPE_IMX_USDHC, 1831 .parent = TYPE_SYSBUS_SDHCI, 1832 .instance_init = imx_usdhc_init, 1833 }; 1834 1835 static void sdhci_register_types(void) 1836 { 1837 type_register_static(&sdhci_pci_info); 1838 type_register_static(&sdhci_sysbus_info); 1839 type_register_static(&sdhci_bus_info); 1840 type_register_static(&imx_usdhc_info); 1841 } 1842 1843 type_init(sdhci_register_types) 1844