1 /* 2 * SD Association Host Standard Specification v2.0 controller emulation 3 * 4 * Copyright (c) 2011 Samsung Electronics Co., Ltd. 5 * Mitsyanko Igor <i.mitsyanko@samsung.com> 6 * Peter A.G. Crosthwaite <peter.crosthwaite@petalogix.com> 7 * 8 * Based on MMC controller for Samsung S5PC1xx-based board emulation 9 * by Alexey Merkulov and Vladimir Monakhov. 10 * 11 * This program is free software; you can redistribute it and/or modify it 12 * under the terms of the GNU General Public License as published by the 13 * Free Software Foundation; either version 2 of the License, or (at your 14 * option) any later version. 15 * 16 * This program is distributed in the hope that it will be useful, 17 * but WITHOUT ANY WARRANTY; without even the implied warranty of 18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. 19 * See the GNU General Public License for more details. 20 * 21 * You should have received a copy of the GNU General Public License along 22 * with this program; if not, see <http://www.gnu.org/licenses/>. 23 */ 24 25 #include "qemu/osdep.h" 26 #include "qemu/error-report.h" 27 #include "qapi/error.h" 28 #include "hw/hw.h" 29 #include "sysemu/block-backend.h" 30 #include "sysemu/blockdev.h" 31 #include "sysemu/dma.h" 32 #include "qemu/timer.h" 33 #include "qemu/bitops.h" 34 #include "hw/sd/sdhci.h" 35 #include "sdhci-internal.h" 36 #include "qemu/log.h" 37 #include "qemu/cutils.h" 38 #include "trace.h" 39 40 #define TYPE_SDHCI_BUS "sdhci-bus" 41 #define SDHCI_BUS(obj) OBJECT_CHECK(SDBus, (obj), TYPE_SDHCI_BUS) 42 43 #define MASKED_WRITE(reg, mask, val) (reg = (reg & (mask)) | (val)) 44 45 /* Default SD/MMC host controller features information, which will be 46 * presented in CAPABILITIES register of generic SD host controller at reset. 47 * 48 * support: 49 * - 3.3v and 1.8v voltages 50 * - SDMA/ADMA1/ADMA2 51 * - high-speed 52 * max host controller R/W buffers size: 512B 53 * max clock frequency for SDclock: 52 MHz 54 * timeout clock frequency: 52 MHz 55 * 56 * does not support: 57 * - 3.0v voltage 58 * - 64-bit system bus 59 * - suspend/resume 60 */ 61 #define SDHC_CAPAB_REG_DEFAULT 0x057834b4 62 63 static inline unsigned int sdhci_get_fifolen(SDHCIState *s) 64 { 65 return 1 << (9 + FIELD_EX32(s->capareg, SDHC_CAPAB, MAXBLOCKLENGTH)); 66 } 67 68 /* return true on error */ 69 static bool sdhci_check_capab_freq_range(SDHCIState *s, const char *desc, 70 uint8_t freq, Error **errp) 71 { 72 switch (freq) { 73 case 0: 74 case 10 ... 63: 75 break; 76 default: 77 error_setg(errp, "SD %s clock frequency can have value" 78 "in range 0-63 only", desc); 79 return true; 80 } 81 return false; 82 } 83 84 static void sdhci_check_capareg(SDHCIState *s, Error **errp) 85 { 86 uint64_t msk = s->capareg; 87 uint32_t val; 88 bool y; 89 90 switch (s->sd_spec_version) { 91 case 2: /* default version */ 92 93 /* fallthrough */ 94 case 1: 95 y = FIELD_EX64(s->capareg, SDHC_CAPAB, TOUNIT); 96 msk = FIELD_DP64(msk, SDHC_CAPAB, TOUNIT, 0); 97 98 val = FIELD_EX64(s->capareg, SDHC_CAPAB, TOCLKFREQ); 99 trace_sdhci_capareg(y ? "timeout (MHz)" : "Timeout (KHz)", val); 100 if (sdhci_check_capab_freq_range(s, "timeout", val, errp)) { 101 return; 102 } 103 msk = FIELD_DP64(msk, SDHC_CAPAB, TOCLKFREQ, 0); 104 105 val = FIELD_EX64(s->capareg, SDHC_CAPAB, BASECLKFREQ); 106 trace_sdhci_capareg(y ? "base (MHz)" : "Base (KHz)", val); 107 if (sdhci_check_capab_freq_range(s, "base", val, errp)) { 108 return; 109 } 110 msk = FIELD_DP64(msk, SDHC_CAPAB, BASECLKFREQ, 0); 111 112 val = FIELD_EX64(s->capareg, SDHC_CAPAB, MAXBLOCKLENGTH); 113 if (val >= 3) { 114 error_setg(errp, "block size can be 512, 1024 or 2048 only"); 115 return; 116 } 117 trace_sdhci_capareg("max block length", sdhci_get_fifolen(s)); 118 msk = FIELD_DP64(msk, SDHC_CAPAB, MAXBLOCKLENGTH, 0); 119 120 val = FIELD_EX64(s->capareg, SDHC_CAPAB, HIGHSPEED); 121 trace_sdhci_capareg("high speed", val); 122 msk = FIELD_DP64(msk, SDHC_CAPAB, HIGHSPEED, 0); 123 124 val = FIELD_EX64(s->capareg, SDHC_CAPAB, SDMA); 125 trace_sdhci_capareg("SDMA", val); 126 msk = FIELD_DP64(msk, SDHC_CAPAB, SDMA, 0); 127 128 val = FIELD_EX64(s->capareg, SDHC_CAPAB, SUSPRESUME); 129 trace_sdhci_capareg("suspend/resume", val); 130 msk = FIELD_DP64(msk, SDHC_CAPAB, SUSPRESUME, 0); 131 132 val = FIELD_EX64(s->capareg, SDHC_CAPAB, V33); 133 trace_sdhci_capareg("3.3v", val); 134 msk = FIELD_DP64(msk, SDHC_CAPAB, V33, 0); 135 136 val = FIELD_EX64(s->capareg, SDHC_CAPAB, V30); 137 trace_sdhci_capareg("3.0v", val); 138 msk = FIELD_DP64(msk, SDHC_CAPAB, V30, 0); 139 140 val = FIELD_EX64(s->capareg, SDHC_CAPAB, V18); 141 trace_sdhci_capareg("1.8v", val); 142 msk = FIELD_DP64(msk, SDHC_CAPAB, V18, 0); 143 break; 144 145 default: 146 error_setg(errp, "Unsupported spec version: %u", s->sd_spec_version); 147 } 148 if (msk) { 149 qemu_log_mask(LOG_UNIMP, 150 "SDHCI: unknown CAPAB mask: 0x%016" PRIx64 "\n", msk); 151 } 152 } 153 154 static uint8_t sdhci_slotint(SDHCIState *s) 155 { 156 return (s->norintsts & s->norintsigen) || (s->errintsts & s->errintsigen) || 157 ((s->norintsts & SDHC_NIS_INSERT) && (s->wakcon & SDHC_WKUP_ON_INS)) || 158 ((s->norintsts & SDHC_NIS_REMOVE) && (s->wakcon & SDHC_WKUP_ON_RMV)); 159 } 160 161 static inline void sdhci_update_irq(SDHCIState *s) 162 { 163 qemu_set_irq(s->irq, sdhci_slotint(s)); 164 } 165 166 static void sdhci_raise_insertion_irq(void *opaque) 167 { 168 SDHCIState *s = (SDHCIState *)opaque; 169 170 if (s->norintsts & SDHC_NIS_REMOVE) { 171 timer_mod(s->insert_timer, 172 qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + SDHC_INSERTION_DELAY); 173 } else { 174 s->prnsts = 0x1ff0000; 175 if (s->norintstsen & SDHC_NISEN_INSERT) { 176 s->norintsts |= SDHC_NIS_INSERT; 177 } 178 sdhci_update_irq(s); 179 } 180 } 181 182 static void sdhci_set_inserted(DeviceState *dev, bool level) 183 { 184 SDHCIState *s = (SDHCIState *)dev; 185 186 trace_sdhci_set_inserted(level ? "insert" : "eject"); 187 if ((s->norintsts & SDHC_NIS_REMOVE) && level) { 188 /* Give target some time to notice card ejection */ 189 timer_mod(s->insert_timer, 190 qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + SDHC_INSERTION_DELAY); 191 } else { 192 if (level) { 193 s->prnsts = 0x1ff0000; 194 if (s->norintstsen & SDHC_NISEN_INSERT) { 195 s->norintsts |= SDHC_NIS_INSERT; 196 } 197 } else { 198 s->prnsts = 0x1fa0000; 199 s->pwrcon &= ~SDHC_POWER_ON; 200 s->clkcon &= ~SDHC_CLOCK_SDCLK_EN; 201 if (s->norintstsen & SDHC_NISEN_REMOVE) { 202 s->norintsts |= SDHC_NIS_REMOVE; 203 } 204 } 205 sdhci_update_irq(s); 206 } 207 } 208 209 static void sdhci_set_readonly(DeviceState *dev, bool level) 210 { 211 SDHCIState *s = (SDHCIState *)dev; 212 213 if (level) { 214 s->prnsts &= ~SDHC_WRITE_PROTECT; 215 } else { 216 /* Write enabled */ 217 s->prnsts |= SDHC_WRITE_PROTECT; 218 } 219 } 220 221 static void sdhci_reset(SDHCIState *s) 222 { 223 DeviceState *dev = DEVICE(s); 224 225 timer_del(s->insert_timer); 226 timer_del(s->transfer_timer); 227 228 /* Set all registers to 0. Capabilities/Version registers are not cleared 229 * and assumed to always preserve their value, given to them during 230 * initialization */ 231 memset(&s->sdmasysad, 0, (uintptr_t)&s->capareg - (uintptr_t)&s->sdmasysad); 232 233 /* Reset other state based on current card insertion/readonly status */ 234 sdhci_set_inserted(dev, sdbus_get_inserted(&s->sdbus)); 235 sdhci_set_readonly(dev, sdbus_get_readonly(&s->sdbus)); 236 237 s->data_count = 0; 238 s->stopped_state = sdhc_not_stopped; 239 s->pending_insert_state = false; 240 } 241 242 static void sdhci_poweron_reset(DeviceState *dev) 243 { 244 /* QOM (ie power-on) reset. This is identical to reset 245 * commanded via device register apart from handling of the 246 * 'pending insert on powerup' quirk. 247 */ 248 SDHCIState *s = (SDHCIState *)dev; 249 250 sdhci_reset(s); 251 252 if (s->pending_insert_quirk) { 253 s->pending_insert_state = true; 254 } 255 } 256 257 static void sdhci_data_transfer(void *opaque); 258 259 static void sdhci_send_command(SDHCIState *s) 260 { 261 SDRequest request; 262 uint8_t response[16]; 263 int rlen; 264 265 s->errintsts = 0; 266 s->acmd12errsts = 0; 267 request.cmd = s->cmdreg >> 8; 268 request.arg = s->argument; 269 270 trace_sdhci_send_command(request.cmd, request.arg); 271 rlen = sdbus_do_command(&s->sdbus, &request, response); 272 273 if (s->cmdreg & SDHC_CMD_RESPONSE) { 274 if (rlen == 4) { 275 s->rspreg[0] = (response[0] << 24) | (response[1] << 16) | 276 (response[2] << 8) | response[3]; 277 s->rspreg[1] = s->rspreg[2] = s->rspreg[3] = 0; 278 trace_sdhci_response4(s->rspreg[0]); 279 } else if (rlen == 16) { 280 s->rspreg[0] = (response[11] << 24) | (response[12] << 16) | 281 (response[13] << 8) | response[14]; 282 s->rspreg[1] = (response[7] << 24) | (response[8] << 16) | 283 (response[9] << 8) | response[10]; 284 s->rspreg[2] = (response[3] << 24) | (response[4] << 16) | 285 (response[5] << 8) | response[6]; 286 s->rspreg[3] = (response[0] << 16) | (response[1] << 8) | 287 response[2]; 288 trace_sdhci_response16(s->rspreg[3], s->rspreg[2], 289 s->rspreg[1], s->rspreg[0]); 290 } else { 291 trace_sdhci_error("timeout waiting for command response"); 292 if (s->errintstsen & SDHC_EISEN_CMDTIMEOUT) { 293 s->errintsts |= SDHC_EIS_CMDTIMEOUT; 294 s->norintsts |= SDHC_NIS_ERR; 295 } 296 } 297 298 if (!(s->quirks & SDHCI_QUIRK_NO_BUSY_IRQ) && 299 (s->norintstsen & SDHC_NISEN_TRSCMP) && 300 (s->cmdreg & SDHC_CMD_RESPONSE) == SDHC_CMD_RSP_WITH_BUSY) { 301 s->norintsts |= SDHC_NIS_TRSCMP; 302 } 303 } 304 305 if (s->norintstsen & SDHC_NISEN_CMDCMP) { 306 s->norintsts |= SDHC_NIS_CMDCMP; 307 } 308 309 sdhci_update_irq(s); 310 311 if (s->blksize && (s->cmdreg & SDHC_CMD_DATA_PRESENT)) { 312 s->data_count = 0; 313 sdhci_data_transfer(s); 314 } 315 } 316 317 static void sdhci_end_transfer(SDHCIState *s) 318 { 319 /* Automatically send CMD12 to stop transfer if AutoCMD12 enabled */ 320 if ((s->trnmod & SDHC_TRNS_ACMD12) != 0) { 321 SDRequest request; 322 uint8_t response[16]; 323 324 request.cmd = 0x0C; 325 request.arg = 0; 326 trace_sdhci_end_transfer(request.cmd, request.arg); 327 sdbus_do_command(&s->sdbus, &request, response); 328 /* Auto CMD12 response goes to the upper Response register */ 329 s->rspreg[3] = (response[0] << 24) | (response[1] << 16) | 330 (response[2] << 8) | response[3]; 331 } 332 333 s->prnsts &= ~(SDHC_DOING_READ | SDHC_DOING_WRITE | 334 SDHC_DAT_LINE_ACTIVE | SDHC_DATA_INHIBIT | 335 SDHC_SPACE_AVAILABLE | SDHC_DATA_AVAILABLE); 336 337 if (s->norintstsen & SDHC_NISEN_TRSCMP) { 338 s->norintsts |= SDHC_NIS_TRSCMP; 339 } 340 341 sdhci_update_irq(s); 342 } 343 344 /* 345 * Programmed i/o data transfer 346 */ 347 #define BLOCK_SIZE_MASK (4 * K_BYTE - 1) 348 349 /* Fill host controller's read buffer with BLKSIZE bytes of data from card */ 350 static void sdhci_read_block_from_card(SDHCIState *s) 351 { 352 int index = 0; 353 354 if ((s->trnmod & SDHC_TRNS_MULTI) && 355 (s->trnmod & SDHC_TRNS_BLK_CNT_EN) && (s->blkcnt == 0)) { 356 return; 357 } 358 359 for (index = 0; index < (s->blksize & BLOCK_SIZE_MASK); index++) { 360 s->fifo_buffer[index] = sdbus_read_data(&s->sdbus); 361 } 362 363 /* New data now available for READ through Buffer Port Register */ 364 s->prnsts |= SDHC_DATA_AVAILABLE; 365 if (s->norintstsen & SDHC_NISEN_RBUFRDY) { 366 s->norintsts |= SDHC_NIS_RBUFRDY; 367 } 368 369 /* Clear DAT line active status if that was the last block */ 370 if ((s->trnmod & SDHC_TRNS_MULTI) == 0 || 371 ((s->trnmod & SDHC_TRNS_MULTI) && s->blkcnt == 1)) { 372 s->prnsts &= ~SDHC_DAT_LINE_ACTIVE; 373 } 374 375 /* If stop at block gap request was set and it's not the last block of 376 * data - generate Block Event interrupt */ 377 if (s->stopped_state == sdhc_gap_read && (s->trnmod & SDHC_TRNS_MULTI) && 378 s->blkcnt != 1) { 379 s->prnsts &= ~SDHC_DAT_LINE_ACTIVE; 380 if (s->norintstsen & SDHC_EISEN_BLKGAP) { 381 s->norintsts |= SDHC_EIS_BLKGAP; 382 } 383 } 384 385 sdhci_update_irq(s); 386 } 387 388 /* Read @size byte of data from host controller @s BUFFER DATA PORT register */ 389 static uint32_t sdhci_read_dataport(SDHCIState *s, unsigned size) 390 { 391 uint32_t value = 0; 392 int i; 393 394 /* first check that a valid data exists in host controller input buffer */ 395 if ((s->prnsts & SDHC_DATA_AVAILABLE) == 0) { 396 trace_sdhci_error("read from empty buffer"); 397 return 0; 398 } 399 400 for (i = 0; i < size; i++) { 401 value |= s->fifo_buffer[s->data_count] << i * 8; 402 s->data_count++; 403 /* check if we've read all valid data (blksize bytes) from buffer */ 404 if ((s->data_count) >= (s->blksize & BLOCK_SIZE_MASK)) { 405 trace_sdhci_read_dataport(s->data_count); 406 s->prnsts &= ~SDHC_DATA_AVAILABLE; /* no more data in a buffer */ 407 s->data_count = 0; /* next buff read must start at position [0] */ 408 409 if (s->trnmod & SDHC_TRNS_BLK_CNT_EN) { 410 s->blkcnt--; 411 } 412 413 /* if that was the last block of data */ 414 if ((s->trnmod & SDHC_TRNS_MULTI) == 0 || 415 ((s->trnmod & SDHC_TRNS_BLK_CNT_EN) && (s->blkcnt == 0)) || 416 /* stop at gap request */ 417 (s->stopped_state == sdhc_gap_read && 418 !(s->prnsts & SDHC_DAT_LINE_ACTIVE))) { 419 sdhci_end_transfer(s); 420 } else { /* if there are more data, read next block from card */ 421 sdhci_read_block_from_card(s); 422 } 423 break; 424 } 425 } 426 427 return value; 428 } 429 430 /* Write data from host controller FIFO to card */ 431 static void sdhci_write_block_to_card(SDHCIState *s) 432 { 433 int index = 0; 434 435 if (s->prnsts & SDHC_SPACE_AVAILABLE) { 436 if (s->norintstsen & SDHC_NISEN_WBUFRDY) { 437 s->norintsts |= SDHC_NIS_WBUFRDY; 438 } 439 sdhci_update_irq(s); 440 return; 441 } 442 443 if (s->trnmod & SDHC_TRNS_BLK_CNT_EN) { 444 if (s->blkcnt == 0) { 445 return; 446 } else { 447 s->blkcnt--; 448 } 449 } 450 451 for (index = 0; index < (s->blksize & BLOCK_SIZE_MASK); index++) { 452 sdbus_write_data(&s->sdbus, s->fifo_buffer[index]); 453 } 454 455 /* Next data can be written through BUFFER DATORT register */ 456 s->prnsts |= SDHC_SPACE_AVAILABLE; 457 458 /* Finish transfer if that was the last block of data */ 459 if ((s->trnmod & SDHC_TRNS_MULTI) == 0 || 460 ((s->trnmod & SDHC_TRNS_MULTI) && 461 (s->trnmod & SDHC_TRNS_BLK_CNT_EN) && (s->blkcnt == 0))) { 462 sdhci_end_transfer(s); 463 } else if (s->norintstsen & SDHC_NISEN_WBUFRDY) { 464 s->norintsts |= SDHC_NIS_WBUFRDY; 465 } 466 467 /* Generate Block Gap Event if requested and if not the last block */ 468 if (s->stopped_state == sdhc_gap_write && (s->trnmod & SDHC_TRNS_MULTI) && 469 s->blkcnt > 0) { 470 s->prnsts &= ~SDHC_DOING_WRITE; 471 if (s->norintstsen & SDHC_EISEN_BLKGAP) { 472 s->norintsts |= SDHC_EIS_BLKGAP; 473 } 474 sdhci_end_transfer(s); 475 } 476 477 sdhci_update_irq(s); 478 } 479 480 /* Write @size bytes of @value data to host controller @s Buffer Data Port 481 * register */ 482 static void sdhci_write_dataport(SDHCIState *s, uint32_t value, unsigned size) 483 { 484 unsigned i; 485 486 /* Check that there is free space left in a buffer */ 487 if (!(s->prnsts & SDHC_SPACE_AVAILABLE)) { 488 trace_sdhci_error("Can't write to data buffer: buffer full"); 489 return; 490 } 491 492 for (i = 0; i < size; i++) { 493 s->fifo_buffer[s->data_count] = value & 0xFF; 494 s->data_count++; 495 value >>= 8; 496 if (s->data_count >= (s->blksize & BLOCK_SIZE_MASK)) { 497 trace_sdhci_write_dataport(s->data_count); 498 s->data_count = 0; 499 s->prnsts &= ~SDHC_SPACE_AVAILABLE; 500 if (s->prnsts & SDHC_DOING_WRITE) { 501 sdhci_write_block_to_card(s); 502 } 503 } 504 } 505 } 506 507 /* 508 * Single DMA data transfer 509 */ 510 511 /* Multi block SDMA transfer */ 512 static void sdhci_sdma_transfer_multi_blocks(SDHCIState *s) 513 { 514 bool page_aligned = false; 515 unsigned int n, begin; 516 const uint16_t block_size = s->blksize & BLOCK_SIZE_MASK; 517 uint32_t boundary_chk = 1 << (((s->blksize & ~BLOCK_SIZE_MASK) >> 12) + 12); 518 uint32_t boundary_count = boundary_chk - (s->sdmasysad % boundary_chk); 519 520 if (!(s->trnmod & SDHC_TRNS_BLK_CNT_EN) || !s->blkcnt) { 521 qemu_log_mask(LOG_UNIMP, "infinite transfer is not supported\n"); 522 return; 523 } 524 525 /* XXX: Some sd/mmc drivers (for example, u-boot-slp) do not account for 526 * possible stop at page boundary if initial address is not page aligned, 527 * allow them to work properly */ 528 if ((s->sdmasysad % boundary_chk) == 0) { 529 page_aligned = true; 530 } 531 532 if (s->trnmod & SDHC_TRNS_READ) { 533 s->prnsts |= SDHC_DOING_READ | SDHC_DATA_INHIBIT | 534 SDHC_DAT_LINE_ACTIVE; 535 while (s->blkcnt) { 536 if (s->data_count == 0) { 537 for (n = 0; n < block_size; n++) { 538 s->fifo_buffer[n] = sdbus_read_data(&s->sdbus); 539 } 540 } 541 begin = s->data_count; 542 if (((boundary_count + begin) < block_size) && page_aligned) { 543 s->data_count = boundary_count + begin; 544 boundary_count = 0; 545 } else { 546 s->data_count = block_size; 547 boundary_count -= block_size - begin; 548 if (s->trnmod & SDHC_TRNS_BLK_CNT_EN) { 549 s->blkcnt--; 550 } 551 } 552 dma_memory_write(s->dma_as, s->sdmasysad, 553 &s->fifo_buffer[begin], s->data_count - begin); 554 s->sdmasysad += s->data_count - begin; 555 if (s->data_count == block_size) { 556 s->data_count = 0; 557 } 558 if (page_aligned && boundary_count == 0) { 559 break; 560 } 561 } 562 } else { 563 s->prnsts |= SDHC_DOING_WRITE | SDHC_DATA_INHIBIT | 564 SDHC_DAT_LINE_ACTIVE; 565 while (s->blkcnt) { 566 begin = s->data_count; 567 if (((boundary_count + begin) < block_size) && page_aligned) { 568 s->data_count = boundary_count + begin; 569 boundary_count = 0; 570 } else { 571 s->data_count = block_size; 572 boundary_count -= block_size - begin; 573 } 574 dma_memory_read(s->dma_as, s->sdmasysad, 575 &s->fifo_buffer[begin], s->data_count - begin); 576 s->sdmasysad += s->data_count - begin; 577 if (s->data_count == block_size) { 578 for (n = 0; n < block_size; n++) { 579 sdbus_write_data(&s->sdbus, s->fifo_buffer[n]); 580 } 581 s->data_count = 0; 582 if (s->trnmod & SDHC_TRNS_BLK_CNT_EN) { 583 s->blkcnt--; 584 } 585 } 586 if (page_aligned && boundary_count == 0) { 587 break; 588 } 589 } 590 } 591 592 if (s->blkcnt == 0) { 593 sdhci_end_transfer(s); 594 } else { 595 if (s->norintstsen & SDHC_NISEN_DMA) { 596 s->norintsts |= SDHC_NIS_DMA; 597 } 598 sdhci_update_irq(s); 599 } 600 } 601 602 /* single block SDMA transfer */ 603 static void sdhci_sdma_transfer_single_block(SDHCIState *s) 604 { 605 int n; 606 uint32_t datacnt = s->blksize & BLOCK_SIZE_MASK; 607 608 if (s->trnmod & SDHC_TRNS_READ) { 609 for (n = 0; n < datacnt; n++) { 610 s->fifo_buffer[n] = sdbus_read_data(&s->sdbus); 611 } 612 dma_memory_write(s->dma_as, s->sdmasysad, s->fifo_buffer, datacnt); 613 } else { 614 dma_memory_read(s->dma_as, s->sdmasysad, s->fifo_buffer, datacnt); 615 for (n = 0; n < datacnt; n++) { 616 sdbus_write_data(&s->sdbus, s->fifo_buffer[n]); 617 } 618 } 619 s->blkcnt--; 620 621 sdhci_end_transfer(s); 622 } 623 624 typedef struct ADMADescr { 625 hwaddr addr; 626 uint16_t length; 627 uint8_t attr; 628 uint8_t incr; 629 } ADMADescr; 630 631 static void get_adma_description(SDHCIState *s, ADMADescr *dscr) 632 { 633 uint32_t adma1 = 0; 634 uint64_t adma2 = 0; 635 hwaddr entry_addr = (hwaddr)s->admasysaddr; 636 switch (SDHC_DMA_TYPE(s->hostctl)) { 637 case SDHC_CTRL_ADMA2_32: 638 dma_memory_read(s->dma_as, entry_addr, (uint8_t *)&adma2, 639 sizeof(adma2)); 640 adma2 = le64_to_cpu(adma2); 641 /* The spec does not specify endianness of descriptor table. 642 * We currently assume that it is LE. 643 */ 644 dscr->addr = (hwaddr)extract64(adma2, 32, 32) & ~0x3ull; 645 dscr->length = (uint16_t)extract64(adma2, 16, 16); 646 dscr->attr = (uint8_t)extract64(adma2, 0, 7); 647 dscr->incr = 8; 648 break; 649 case SDHC_CTRL_ADMA1_32: 650 dma_memory_read(s->dma_as, entry_addr, (uint8_t *)&adma1, 651 sizeof(adma1)); 652 adma1 = le32_to_cpu(adma1); 653 dscr->addr = (hwaddr)(adma1 & 0xFFFFF000); 654 dscr->attr = (uint8_t)extract32(adma1, 0, 7); 655 dscr->incr = 4; 656 if ((dscr->attr & SDHC_ADMA_ATTR_ACT_MASK) == SDHC_ADMA_ATTR_SET_LEN) { 657 dscr->length = (uint16_t)extract32(adma1, 12, 16); 658 } else { 659 dscr->length = 4096; 660 } 661 break; 662 case SDHC_CTRL_ADMA2_64: 663 dma_memory_read(s->dma_as, entry_addr, 664 (uint8_t *)(&dscr->attr), 1); 665 dma_memory_read(s->dma_as, entry_addr + 2, 666 (uint8_t *)(&dscr->length), 2); 667 dscr->length = le16_to_cpu(dscr->length); 668 dma_memory_read(s->dma_as, entry_addr + 4, 669 (uint8_t *)(&dscr->addr), 8); 670 dscr->attr = le64_to_cpu(dscr->attr); 671 dscr->attr &= 0xfffffff8; 672 dscr->incr = 12; 673 break; 674 } 675 } 676 677 /* Advanced DMA data transfer */ 678 679 static void sdhci_do_adma(SDHCIState *s) 680 { 681 unsigned int n, begin, length; 682 const uint16_t block_size = s->blksize & BLOCK_SIZE_MASK; 683 ADMADescr dscr = {}; 684 int i; 685 686 for (i = 0; i < SDHC_ADMA_DESCS_PER_DELAY; ++i) { 687 s->admaerr &= ~SDHC_ADMAERR_LENGTH_MISMATCH; 688 689 get_adma_description(s, &dscr); 690 trace_sdhci_adma_loop(dscr.addr, dscr.length, dscr.attr); 691 692 if ((dscr.attr & SDHC_ADMA_ATTR_VALID) == 0) { 693 /* Indicate that error occurred in ST_FDS state */ 694 s->admaerr &= ~SDHC_ADMAERR_STATE_MASK; 695 s->admaerr |= SDHC_ADMAERR_STATE_ST_FDS; 696 697 /* Generate ADMA error interrupt */ 698 if (s->errintstsen & SDHC_EISEN_ADMAERR) { 699 s->errintsts |= SDHC_EIS_ADMAERR; 700 s->norintsts |= SDHC_NIS_ERR; 701 } 702 703 sdhci_update_irq(s); 704 return; 705 } 706 707 length = dscr.length ? dscr.length : 65536; 708 709 switch (dscr.attr & SDHC_ADMA_ATTR_ACT_MASK) { 710 case SDHC_ADMA_ATTR_ACT_TRAN: /* data transfer */ 711 712 if (s->trnmod & SDHC_TRNS_READ) { 713 while (length) { 714 if (s->data_count == 0) { 715 for (n = 0; n < block_size; n++) { 716 s->fifo_buffer[n] = sdbus_read_data(&s->sdbus); 717 } 718 } 719 begin = s->data_count; 720 if ((length + begin) < block_size) { 721 s->data_count = length + begin; 722 length = 0; 723 } else { 724 s->data_count = block_size; 725 length -= block_size - begin; 726 } 727 dma_memory_write(s->dma_as, dscr.addr, 728 &s->fifo_buffer[begin], 729 s->data_count - begin); 730 dscr.addr += s->data_count - begin; 731 if (s->data_count == block_size) { 732 s->data_count = 0; 733 if (s->trnmod & SDHC_TRNS_BLK_CNT_EN) { 734 s->blkcnt--; 735 if (s->blkcnt == 0) { 736 break; 737 } 738 } 739 } 740 } 741 } else { 742 while (length) { 743 begin = s->data_count; 744 if ((length + begin) < block_size) { 745 s->data_count = length + begin; 746 length = 0; 747 } else { 748 s->data_count = block_size; 749 length -= block_size - begin; 750 } 751 dma_memory_read(s->dma_as, dscr.addr, 752 &s->fifo_buffer[begin], 753 s->data_count - begin); 754 dscr.addr += s->data_count - begin; 755 if (s->data_count == block_size) { 756 for (n = 0; n < block_size; n++) { 757 sdbus_write_data(&s->sdbus, s->fifo_buffer[n]); 758 } 759 s->data_count = 0; 760 if (s->trnmod & SDHC_TRNS_BLK_CNT_EN) { 761 s->blkcnt--; 762 if (s->blkcnt == 0) { 763 break; 764 } 765 } 766 } 767 } 768 } 769 s->admasysaddr += dscr.incr; 770 break; 771 case SDHC_ADMA_ATTR_ACT_LINK: /* link to next descriptor table */ 772 s->admasysaddr = dscr.addr; 773 trace_sdhci_adma("link", s->admasysaddr); 774 break; 775 default: 776 s->admasysaddr += dscr.incr; 777 break; 778 } 779 780 if (dscr.attr & SDHC_ADMA_ATTR_INT) { 781 trace_sdhci_adma("interrupt", s->admasysaddr); 782 if (s->norintstsen & SDHC_NISEN_DMA) { 783 s->norintsts |= SDHC_NIS_DMA; 784 } 785 786 sdhci_update_irq(s); 787 } 788 789 /* ADMA transfer terminates if blkcnt == 0 or by END attribute */ 790 if (((s->trnmod & SDHC_TRNS_BLK_CNT_EN) && 791 (s->blkcnt == 0)) || (dscr.attr & SDHC_ADMA_ATTR_END)) { 792 trace_sdhci_adma_transfer_completed(); 793 if (length || ((dscr.attr & SDHC_ADMA_ATTR_END) && 794 (s->trnmod & SDHC_TRNS_BLK_CNT_EN) && 795 s->blkcnt != 0)) { 796 trace_sdhci_error("SD/MMC host ADMA length mismatch"); 797 s->admaerr |= SDHC_ADMAERR_LENGTH_MISMATCH | 798 SDHC_ADMAERR_STATE_ST_TFR; 799 if (s->errintstsen & SDHC_EISEN_ADMAERR) { 800 trace_sdhci_error("Set ADMA error flag"); 801 s->errintsts |= SDHC_EIS_ADMAERR; 802 s->norintsts |= SDHC_NIS_ERR; 803 } 804 805 sdhci_update_irq(s); 806 } 807 sdhci_end_transfer(s); 808 return; 809 } 810 811 } 812 813 /* we have unfinished business - reschedule to continue ADMA */ 814 timer_mod(s->transfer_timer, 815 qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + SDHC_TRANSFER_DELAY); 816 } 817 818 /* Perform data transfer according to controller configuration */ 819 820 static void sdhci_data_transfer(void *opaque) 821 { 822 SDHCIState *s = (SDHCIState *)opaque; 823 824 if (s->trnmod & SDHC_TRNS_DMA) { 825 switch (SDHC_DMA_TYPE(s->hostctl)) { 826 case SDHC_CTRL_SDMA: 827 if ((s->blkcnt == 1) || !(s->trnmod & SDHC_TRNS_MULTI)) { 828 sdhci_sdma_transfer_single_block(s); 829 } else { 830 sdhci_sdma_transfer_multi_blocks(s); 831 } 832 833 break; 834 case SDHC_CTRL_ADMA1_32: 835 if (!(s->capareg & SDHC_CAN_DO_ADMA1)) { 836 trace_sdhci_error("ADMA1 not supported"); 837 break; 838 } 839 840 sdhci_do_adma(s); 841 break; 842 case SDHC_CTRL_ADMA2_32: 843 if (!(s->capareg & SDHC_CAN_DO_ADMA2)) { 844 trace_sdhci_error("ADMA2 not supported"); 845 break; 846 } 847 848 sdhci_do_adma(s); 849 break; 850 case SDHC_CTRL_ADMA2_64: 851 if (!(s->capareg & SDHC_CAN_DO_ADMA2) || 852 !(s->capareg & SDHC_64_BIT_BUS_SUPPORT)) { 853 trace_sdhci_error("64 bit ADMA not supported"); 854 break; 855 } 856 857 sdhci_do_adma(s); 858 break; 859 default: 860 trace_sdhci_error("Unsupported DMA type"); 861 break; 862 } 863 } else { 864 if ((s->trnmod & SDHC_TRNS_READ) && sdbus_data_ready(&s->sdbus)) { 865 s->prnsts |= SDHC_DOING_READ | SDHC_DATA_INHIBIT | 866 SDHC_DAT_LINE_ACTIVE; 867 sdhci_read_block_from_card(s); 868 } else { 869 s->prnsts |= SDHC_DOING_WRITE | SDHC_DAT_LINE_ACTIVE | 870 SDHC_SPACE_AVAILABLE | SDHC_DATA_INHIBIT; 871 sdhci_write_block_to_card(s); 872 } 873 } 874 } 875 876 static bool sdhci_can_issue_command(SDHCIState *s) 877 { 878 if (!SDHC_CLOCK_IS_ON(s->clkcon) || 879 (((s->prnsts & SDHC_DATA_INHIBIT) || s->stopped_state) && 880 ((s->cmdreg & SDHC_CMD_DATA_PRESENT) || 881 ((s->cmdreg & SDHC_CMD_RESPONSE) == SDHC_CMD_RSP_WITH_BUSY && 882 !(SDHC_COMMAND_TYPE(s->cmdreg) == SDHC_CMD_ABORT))))) { 883 return false; 884 } 885 886 return true; 887 } 888 889 /* The Buffer Data Port register must be accessed in sequential and 890 * continuous manner */ 891 static inline bool 892 sdhci_buff_access_is_sequential(SDHCIState *s, unsigned byte_num) 893 { 894 if ((s->data_count & 0x3) != byte_num) { 895 trace_sdhci_error("Non-sequential access to Buffer Data Port register" 896 "is prohibited\n"); 897 return false; 898 } 899 return true; 900 } 901 902 static uint64_t sdhci_read(void *opaque, hwaddr offset, unsigned size) 903 { 904 SDHCIState *s = (SDHCIState *)opaque; 905 uint32_t ret = 0; 906 907 switch (offset & ~0x3) { 908 case SDHC_SYSAD: 909 ret = s->sdmasysad; 910 break; 911 case SDHC_BLKSIZE: 912 ret = s->blksize | (s->blkcnt << 16); 913 break; 914 case SDHC_ARGUMENT: 915 ret = s->argument; 916 break; 917 case SDHC_TRNMOD: 918 ret = s->trnmod | (s->cmdreg << 16); 919 break; 920 case SDHC_RSPREG0 ... SDHC_RSPREG3: 921 ret = s->rspreg[((offset & ~0x3) - SDHC_RSPREG0) >> 2]; 922 break; 923 case SDHC_BDATA: 924 if (sdhci_buff_access_is_sequential(s, offset - SDHC_BDATA)) { 925 ret = sdhci_read_dataport(s, size); 926 trace_sdhci_access("rd", size << 3, offset, "->", ret, ret); 927 return ret; 928 } 929 break; 930 case SDHC_PRNSTS: 931 ret = s->prnsts; 932 break; 933 case SDHC_HOSTCTL: 934 ret = s->hostctl | (s->pwrcon << 8) | (s->blkgap << 16) | 935 (s->wakcon << 24); 936 break; 937 case SDHC_CLKCON: 938 ret = s->clkcon | (s->timeoutcon << 16); 939 break; 940 case SDHC_NORINTSTS: 941 ret = s->norintsts | (s->errintsts << 16); 942 break; 943 case SDHC_NORINTSTSEN: 944 ret = s->norintstsen | (s->errintstsen << 16); 945 break; 946 case SDHC_NORINTSIGEN: 947 ret = s->norintsigen | (s->errintsigen << 16); 948 break; 949 case SDHC_ACMD12ERRSTS: 950 ret = s->acmd12errsts; 951 break; 952 case SDHC_CAPAB: 953 ret = (uint32_t)s->capareg; 954 break; 955 case SDHC_CAPAB + 4: 956 ret = (uint32_t)(s->capareg >> 32); 957 break; 958 case SDHC_MAXCURR: 959 ret = (uint32_t)s->maxcurr; 960 break; 961 case SDHC_MAXCURR + 4: 962 ret = (uint32_t)(s->maxcurr >> 32); 963 break; 964 case SDHC_ADMAERR: 965 ret = s->admaerr; 966 break; 967 case SDHC_ADMASYSADDR: 968 ret = (uint32_t)s->admasysaddr; 969 break; 970 case SDHC_ADMASYSADDR + 4: 971 ret = (uint32_t)(s->admasysaddr >> 32); 972 break; 973 case SDHC_SLOT_INT_STATUS: 974 ret = (s->version << 16) | sdhci_slotint(s); 975 break; 976 default: 977 qemu_log_mask(LOG_UNIMP, "SDHC rd_%ub @0x%02" HWADDR_PRIx " " 978 "not implemented\n", size, offset); 979 break; 980 } 981 982 ret >>= (offset & 0x3) * 8; 983 ret &= (1ULL << (size * 8)) - 1; 984 trace_sdhci_access("rd", size << 3, offset, "->", ret, ret); 985 return ret; 986 } 987 988 static inline void sdhci_blkgap_write(SDHCIState *s, uint8_t value) 989 { 990 if ((value & SDHC_STOP_AT_GAP_REQ) && (s->blkgap & SDHC_STOP_AT_GAP_REQ)) { 991 return; 992 } 993 s->blkgap = value & SDHC_STOP_AT_GAP_REQ; 994 995 if ((value & SDHC_CONTINUE_REQ) && s->stopped_state && 996 (s->blkgap & SDHC_STOP_AT_GAP_REQ) == 0) { 997 if (s->stopped_state == sdhc_gap_read) { 998 s->prnsts |= SDHC_DAT_LINE_ACTIVE | SDHC_DOING_READ; 999 sdhci_read_block_from_card(s); 1000 } else { 1001 s->prnsts |= SDHC_DAT_LINE_ACTIVE | SDHC_DOING_WRITE; 1002 sdhci_write_block_to_card(s); 1003 } 1004 s->stopped_state = sdhc_not_stopped; 1005 } else if (!s->stopped_state && (value & SDHC_STOP_AT_GAP_REQ)) { 1006 if (s->prnsts & SDHC_DOING_READ) { 1007 s->stopped_state = sdhc_gap_read; 1008 } else if (s->prnsts & SDHC_DOING_WRITE) { 1009 s->stopped_state = sdhc_gap_write; 1010 } 1011 } 1012 } 1013 1014 static inline void sdhci_reset_write(SDHCIState *s, uint8_t value) 1015 { 1016 switch (value) { 1017 case SDHC_RESET_ALL: 1018 sdhci_reset(s); 1019 break; 1020 case SDHC_RESET_CMD: 1021 s->prnsts &= ~SDHC_CMD_INHIBIT; 1022 s->norintsts &= ~SDHC_NIS_CMDCMP; 1023 break; 1024 case SDHC_RESET_DATA: 1025 s->data_count = 0; 1026 s->prnsts &= ~(SDHC_SPACE_AVAILABLE | SDHC_DATA_AVAILABLE | 1027 SDHC_DOING_READ | SDHC_DOING_WRITE | 1028 SDHC_DATA_INHIBIT | SDHC_DAT_LINE_ACTIVE); 1029 s->blkgap &= ~(SDHC_STOP_AT_GAP_REQ | SDHC_CONTINUE_REQ); 1030 s->stopped_state = sdhc_not_stopped; 1031 s->norintsts &= ~(SDHC_NIS_WBUFRDY | SDHC_NIS_RBUFRDY | 1032 SDHC_NIS_DMA | SDHC_NIS_TRSCMP | SDHC_NIS_BLKGAP); 1033 break; 1034 } 1035 } 1036 1037 static void 1038 sdhci_write(void *opaque, hwaddr offset, uint64_t val, unsigned size) 1039 { 1040 SDHCIState *s = (SDHCIState *)opaque; 1041 unsigned shift = 8 * (offset & 0x3); 1042 uint32_t mask = ~(((1ULL << (size * 8)) - 1) << shift); 1043 uint32_t value = val; 1044 value <<= shift; 1045 1046 switch (offset & ~0x3) { 1047 case SDHC_SYSAD: 1048 s->sdmasysad = (s->sdmasysad & mask) | value; 1049 MASKED_WRITE(s->sdmasysad, mask, value); 1050 /* Writing to last byte of sdmasysad might trigger transfer */ 1051 if (!(mask & 0xFF000000) && TRANSFERRING_DATA(s->prnsts) && s->blkcnt && 1052 s->blksize && SDHC_DMA_TYPE(s->hostctl) == SDHC_CTRL_SDMA) { 1053 if (s->trnmod & SDHC_TRNS_MULTI) { 1054 sdhci_sdma_transfer_multi_blocks(s); 1055 } else { 1056 sdhci_sdma_transfer_single_block(s); 1057 } 1058 } 1059 break; 1060 case SDHC_BLKSIZE: 1061 if (!TRANSFERRING_DATA(s->prnsts)) { 1062 MASKED_WRITE(s->blksize, mask, value); 1063 MASKED_WRITE(s->blkcnt, mask >> 16, value >> 16); 1064 } 1065 1066 /* Limit block size to the maximum buffer size */ 1067 if (extract32(s->blksize, 0, 12) > s->buf_maxsz) { 1068 qemu_log_mask(LOG_GUEST_ERROR, "%s: Size 0x%x is larger than " \ 1069 "the maximum buffer 0x%x", __func__, s->blksize, 1070 s->buf_maxsz); 1071 1072 s->blksize = deposit32(s->blksize, 0, 12, s->buf_maxsz); 1073 } 1074 1075 break; 1076 case SDHC_ARGUMENT: 1077 MASKED_WRITE(s->argument, mask, value); 1078 break; 1079 case SDHC_TRNMOD: 1080 /* DMA can be enabled only if it is supported as indicated by 1081 * capabilities register */ 1082 if (!(s->capareg & R_SDHC_CAPAB_SDMA_MASK)) { 1083 value &= ~SDHC_TRNS_DMA; 1084 } 1085 MASKED_WRITE(s->trnmod, mask, value & SDHC_TRNMOD_MASK); 1086 MASKED_WRITE(s->cmdreg, mask >> 16, value >> 16); 1087 1088 /* Writing to the upper byte of CMDREG triggers SD command generation */ 1089 if ((mask & 0xFF000000) || !sdhci_can_issue_command(s)) { 1090 break; 1091 } 1092 1093 sdhci_send_command(s); 1094 break; 1095 case SDHC_BDATA: 1096 if (sdhci_buff_access_is_sequential(s, offset - SDHC_BDATA)) { 1097 sdhci_write_dataport(s, value >> shift, size); 1098 } 1099 break; 1100 case SDHC_HOSTCTL: 1101 if (!(mask & 0xFF0000)) { 1102 sdhci_blkgap_write(s, value >> 16); 1103 } 1104 MASKED_WRITE(s->hostctl, mask, value); 1105 MASKED_WRITE(s->pwrcon, mask >> 8, value >> 8); 1106 MASKED_WRITE(s->wakcon, mask >> 24, value >> 24); 1107 if (!(s->prnsts & SDHC_CARD_PRESENT) || ((s->pwrcon >> 1) & 0x7) < 5 || 1108 !(s->capareg & (1 << (31 - ((s->pwrcon >> 1) & 0x7))))) { 1109 s->pwrcon &= ~SDHC_POWER_ON; 1110 } 1111 break; 1112 case SDHC_CLKCON: 1113 if (!(mask & 0xFF000000)) { 1114 sdhci_reset_write(s, value >> 24); 1115 } 1116 MASKED_WRITE(s->clkcon, mask, value); 1117 MASKED_WRITE(s->timeoutcon, mask >> 16, value >> 16); 1118 if (s->clkcon & SDHC_CLOCK_INT_EN) { 1119 s->clkcon |= SDHC_CLOCK_INT_STABLE; 1120 } else { 1121 s->clkcon &= ~SDHC_CLOCK_INT_STABLE; 1122 } 1123 break; 1124 case SDHC_NORINTSTS: 1125 if (s->norintstsen & SDHC_NISEN_CARDINT) { 1126 value &= ~SDHC_NIS_CARDINT; 1127 } 1128 s->norintsts &= mask | ~value; 1129 s->errintsts &= (mask >> 16) | ~(value >> 16); 1130 if (s->errintsts) { 1131 s->norintsts |= SDHC_NIS_ERR; 1132 } else { 1133 s->norintsts &= ~SDHC_NIS_ERR; 1134 } 1135 sdhci_update_irq(s); 1136 break; 1137 case SDHC_NORINTSTSEN: 1138 MASKED_WRITE(s->norintstsen, mask, value); 1139 MASKED_WRITE(s->errintstsen, mask >> 16, value >> 16); 1140 s->norintsts &= s->norintstsen; 1141 s->errintsts &= s->errintstsen; 1142 if (s->errintsts) { 1143 s->norintsts |= SDHC_NIS_ERR; 1144 } else { 1145 s->norintsts &= ~SDHC_NIS_ERR; 1146 } 1147 /* Quirk for Raspberry Pi: pending card insert interrupt 1148 * appears when first enabled after power on */ 1149 if ((s->norintstsen & SDHC_NISEN_INSERT) && s->pending_insert_state) { 1150 assert(s->pending_insert_quirk); 1151 s->norintsts |= SDHC_NIS_INSERT; 1152 s->pending_insert_state = false; 1153 } 1154 sdhci_update_irq(s); 1155 break; 1156 case SDHC_NORINTSIGEN: 1157 MASKED_WRITE(s->norintsigen, mask, value); 1158 MASKED_WRITE(s->errintsigen, mask >> 16, value >> 16); 1159 sdhci_update_irq(s); 1160 break; 1161 case SDHC_ADMAERR: 1162 MASKED_WRITE(s->admaerr, mask, value); 1163 break; 1164 case SDHC_ADMASYSADDR: 1165 s->admasysaddr = (s->admasysaddr & (0xFFFFFFFF00000000ULL | 1166 (uint64_t)mask)) | (uint64_t)value; 1167 break; 1168 case SDHC_ADMASYSADDR + 4: 1169 s->admasysaddr = (s->admasysaddr & (0x00000000FFFFFFFFULL | 1170 ((uint64_t)mask << 32))) | ((uint64_t)value << 32); 1171 break; 1172 case SDHC_FEAER: 1173 s->acmd12errsts |= value; 1174 s->errintsts |= (value >> 16) & s->errintstsen; 1175 if (s->acmd12errsts) { 1176 s->errintsts |= SDHC_EIS_CMD12ERR; 1177 } 1178 if (s->errintsts) { 1179 s->norintsts |= SDHC_NIS_ERR; 1180 } 1181 sdhci_update_irq(s); 1182 break; 1183 case SDHC_ACMD12ERRSTS: 1184 MASKED_WRITE(s->acmd12errsts, mask, value); 1185 break; 1186 1187 case SDHC_CAPAB: 1188 case SDHC_CAPAB + 4: 1189 case SDHC_MAXCURR: 1190 case SDHC_MAXCURR + 4: 1191 qemu_log_mask(LOG_GUEST_ERROR, "SDHC wr_%ub @0x%02" HWADDR_PRIx 1192 " <- 0x%08x read-only\n", size, offset, value >> shift); 1193 break; 1194 1195 default: 1196 qemu_log_mask(LOG_UNIMP, "SDHC wr_%ub @0x%02" HWADDR_PRIx " <- 0x%08x " 1197 "not implemented\n", size, offset, value >> shift); 1198 break; 1199 } 1200 trace_sdhci_access("wr", size << 3, offset, "<-", 1201 value >> shift, value >> shift); 1202 } 1203 1204 static const MemoryRegionOps sdhci_mmio_ops = { 1205 .read = sdhci_read, 1206 .write = sdhci_write, 1207 .valid = { 1208 .min_access_size = 1, 1209 .max_access_size = 4, 1210 .unaligned = false 1211 }, 1212 .endianness = DEVICE_LITTLE_ENDIAN, 1213 }; 1214 1215 static void sdhci_init_readonly_registers(SDHCIState *s, Error **errp) 1216 { 1217 Error *local_err = NULL; 1218 1219 if (s->sd_spec_version != 2) { 1220 error_setg(errp, "Only Spec v2 is supported"); 1221 return; 1222 } 1223 s->version = (SDHC_HCVER_VENDOR << 8) | (s->sd_spec_version - 1); 1224 1225 sdhci_check_capareg(s, &local_err); 1226 if (local_err) { 1227 error_propagate(errp, local_err); 1228 return; 1229 } 1230 } 1231 1232 /* --- qdev common --- */ 1233 1234 #define DEFINE_SDHCI_COMMON_PROPERTIES(_state) \ 1235 DEFINE_PROP_UINT8("sd-spec-version", _state, sd_spec_version, 2), \ 1236 \ 1237 /* Capabilities registers provide information on supported 1238 * features of this specific host controller implementation */ \ 1239 DEFINE_PROP_UINT64("capareg", _state, capareg, SDHC_CAPAB_REG_DEFAULT), \ 1240 DEFINE_PROP_UINT64("maxcurr", _state, maxcurr, 0) 1241 1242 static void sdhci_initfn(SDHCIState *s) 1243 { 1244 qbus_create_inplace(&s->sdbus, sizeof(s->sdbus), 1245 TYPE_SDHCI_BUS, DEVICE(s), "sd-bus"); 1246 1247 s->insert_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, sdhci_raise_insertion_irq, s); 1248 s->transfer_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, sdhci_data_transfer, s); 1249 1250 s->io_ops = &sdhci_mmio_ops; 1251 } 1252 1253 static void sdhci_uninitfn(SDHCIState *s) 1254 { 1255 timer_del(s->insert_timer); 1256 timer_free(s->insert_timer); 1257 timer_del(s->transfer_timer); 1258 timer_free(s->transfer_timer); 1259 1260 g_free(s->fifo_buffer); 1261 s->fifo_buffer = NULL; 1262 } 1263 1264 static void sdhci_common_realize(SDHCIState *s, Error **errp) 1265 { 1266 Error *local_err = NULL; 1267 1268 sdhci_init_readonly_registers(s, &local_err); 1269 if (local_err) { 1270 error_propagate(errp, local_err); 1271 return; 1272 } 1273 s->buf_maxsz = sdhci_get_fifolen(s); 1274 s->fifo_buffer = g_malloc0(s->buf_maxsz); 1275 1276 memory_region_init_io(&s->iomem, OBJECT(s), &sdhci_mmio_ops, s, "sdhci", 1277 SDHC_REGISTERS_MAP_SIZE); 1278 } 1279 1280 static void sdhci_common_unrealize(SDHCIState *s, Error **errp) 1281 { 1282 /* This function is expected to be called only once for each class: 1283 * - SysBus: via DeviceClass->unrealize(), 1284 * - PCI: via PCIDeviceClass->exit(). 1285 * However to avoid double-free and/or use-after-free we still nullify 1286 * this variable (better safe than sorry!). */ 1287 g_free(s->fifo_buffer); 1288 s->fifo_buffer = NULL; 1289 } 1290 1291 static bool sdhci_pending_insert_vmstate_needed(void *opaque) 1292 { 1293 SDHCIState *s = opaque; 1294 1295 return s->pending_insert_state; 1296 } 1297 1298 static const VMStateDescription sdhci_pending_insert_vmstate = { 1299 .name = "sdhci/pending-insert", 1300 .version_id = 1, 1301 .minimum_version_id = 1, 1302 .needed = sdhci_pending_insert_vmstate_needed, 1303 .fields = (VMStateField[]) { 1304 VMSTATE_BOOL(pending_insert_state, SDHCIState), 1305 VMSTATE_END_OF_LIST() 1306 }, 1307 }; 1308 1309 const VMStateDescription sdhci_vmstate = { 1310 .name = "sdhci", 1311 .version_id = 1, 1312 .minimum_version_id = 1, 1313 .fields = (VMStateField[]) { 1314 VMSTATE_UINT32(sdmasysad, SDHCIState), 1315 VMSTATE_UINT16(blksize, SDHCIState), 1316 VMSTATE_UINT16(blkcnt, SDHCIState), 1317 VMSTATE_UINT32(argument, SDHCIState), 1318 VMSTATE_UINT16(trnmod, SDHCIState), 1319 VMSTATE_UINT16(cmdreg, SDHCIState), 1320 VMSTATE_UINT32_ARRAY(rspreg, SDHCIState, 4), 1321 VMSTATE_UINT32(prnsts, SDHCIState), 1322 VMSTATE_UINT8(hostctl, SDHCIState), 1323 VMSTATE_UINT8(pwrcon, SDHCIState), 1324 VMSTATE_UINT8(blkgap, SDHCIState), 1325 VMSTATE_UINT8(wakcon, SDHCIState), 1326 VMSTATE_UINT16(clkcon, SDHCIState), 1327 VMSTATE_UINT8(timeoutcon, SDHCIState), 1328 VMSTATE_UINT8(admaerr, SDHCIState), 1329 VMSTATE_UINT16(norintsts, SDHCIState), 1330 VMSTATE_UINT16(errintsts, SDHCIState), 1331 VMSTATE_UINT16(norintstsen, SDHCIState), 1332 VMSTATE_UINT16(errintstsen, SDHCIState), 1333 VMSTATE_UINT16(norintsigen, SDHCIState), 1334 VMSTATE_UINT16(errintsigen, SDHCIState), 1335 VMSTATE_UINT16(acmd12errsts, SDHCIState), 1336 VMSTATE_UINT16(data_count, SDHCIState), 1337 VMSTATE_UINT64(admasysaddr, SDHCIState), 1338 VMSTATE_UINT8(stopped_state, SDHCIState), 1339 VMSTATE_VBUFFER_UINT32(fifo_buffer, SDHCIState, 1, NULL, buf_maxsz), 1340 VMSTATE_TIMER_PTR(insert_timer, SDHCIState), 1341 VMSTATE_TIMER_PTR(transfer_timer, SDHCIState), 1342 VMSTATE_END_OF_LIST() 1343 }, 1344 .subsections = (const VMStateDescription*[]) { 1345 &sdhci_pending_insert_vmstate, 1346 NULL 1347 }, 1348 }; 1349 1350 static void sdhci_common_class_init(ObjectClass *klass, void *data) 1351 { 1352 DeviceClass *dc = DEVICE_CLASS(klass); 1353 1354 set_bit(DEVICE_CATEGORY_STORAGE, dc->categories); 1355 dc->vmsd = &sdhci_vmstate; 1356 dc->reset = sdhci_poweron_reset; 1357 } 1358 1359 /* --- qdev PCI --- */ 1360 1361 static Property sdhci_pci_properties[] = { 1362 DEFINE_SDHCI_COMMON_PROPERTIES(SDHCIState), 1363 DEFINE_PROP_END_OF_LIST(), 1364 }; 1365 1366 static void sdhci_pci_realize(PCIDevice *dev, Error **errp) 1367 { 1368 SDHCIState *s = PCI_SDHCI(dev); 1369 Error *local_err = NULL; 1370 1371 sdhci_initfn(s); 1372 sdhci_common_realize(s, errp); 1373 if (local_err) { 1374 error_propagate(errp, local_err); 1375 return; 1376 } 1377 1378 dev->config[PCI_CLASS_PROG] = 0x01; /* Standard Host supported DMA */ 1379 dev->config[PCI_INTERRUPT_PIN] = 0x01; /* interrupt pin A */ 1380 s->irq = pci_allocate_irq(dev); 1381 s->dma_as = pci_get_address_space(dev); 1382 pci_register_bar(dev, 0, PCI_BASE_ADDRESS_SPACE_MEMORY, &s->iomem); 1383 } 1384 1385 static void sdhci_pci_exit(PCIDevice *dev) 1386 { 1387 SDHCIState *s = PCI_SDHCI(dev); 1388 1389 sdhci_common_unrealize(s, &error_abort); 1390 sdhci_uninitfn(s); 1391 } 1392 1393 static void sdhci_pci_class_init(ObjectClass *klass, void *data) 1394 { 1395 DeviceClass *dc = DEVICE_CLASS(klass); 1396 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); 1397 1398 k->realize = sdhci_pci_realize; 1399 k->exit = sdhci_pci_exit; 1400 k->vendor_id = PCI_VENDOR_ID_REDHAT; 1401 k->device_id = PCI_DEVICE_ID_REDHAT_SDHCI; 1402 k->class_id = PCI_CLASS_SYSTEM_SDHCI; 1403 dc->props = sdhci_pci_properties; 1404 1405 sdhci_common_class_init(klass, data); 1406 } 1407 1408 static const TypeInfo sdhci_pci_info = { 1409 .name = TYPE_PCI_SDHCI, 1410 .parent = TYPE_PCI_DEVICE, 1411 .instance_size = sizeof(SDHCIState), 1412 .class_init = sdhci_pci_class_init, 1413 .interfaces = (InterfaceInfo[]) { 1414 { INTERFACE_CONVENTIONAL_PCI_DEVICE }, 1415 { }, 1416 }, 1417 }; 1418 1419 /* --- qdev SysBus --- */ 1420 1421 static Property sdhci_sysbus_properties[] = { 1422 DEFINE_SDHCI_COMMON_PROPERTIES(SDHCIState), 1423 DEFINE_PROP_BOOL("pending-insert-quirk", SDHCIState, pending_insert_quirk, 1424 false), 1425 DEFINE_PROP_LINK("dma", SDHCIState, 1426 dma_mr, TYPE_MEMORY_REGION, MemoryRegion *), 1427 DEFINE_PROP_END_OF_LIST(), 1428 }; 1429 1430 static void sdhci_sysbus_init(Object *obj) 1431 { 1432 SDHCIState *s = SYSBUS_SDHCI(obj); 1433 1434 sdhci_initfn(s); 1435 } 1436 1437 static void sdhci_sysbus_finalize(Object *obj) 1438 { 1439 SDHCIState *s = SYSBUS_SDHCI(obj); 1440 1441 if (s->dma_mr) { 1442 object_unparent(OBJECT(s->dma_mr)); 1443 } 1444 1445 sdhci_uninitfn(s); 1446 } 1447 1448 static void sdhci_sysbus_realize(DeviceState *dev, Error ** errp) 1449 { 1450 SDHCIState *s = SYSBUS_SDHCI(dev); 1451 SysBusDevice *sbd = SYS_BUS_DEVICE(dev); 1452 Error *local_err = NULL; 1453 1454 sdhci_common_realize(s, errp); 1455 if (local_err) { 1456 error_propagate(errp, local_err); 1457 return; 1458 } 1459 1460 if (s->dma_mr) { 1461 s->dma_as = &s->sysbus_dma_as; 1462 address_space_init(s->dma_as, s->dma_mr, "sdhci-dma"); 1463 } else { 1464 /* use system_memory() if property "dma" not set */ 1465 s->dma_as = &address_space_memory; 1466 } 1467 1468 sysbus_init_irq(sbd, &s->irq); 1469 1470 memory_region_init_io(&s->iomem, OBJECT(s), s->io_ops, s, "sdhci", 1471 SDHC_REGISTERS_MAP_SIZE); 1472 1473 sysbus_init_mmio(sbd, &s->iomem); 1474 } 1475 1476 static void sdhci_sysbus_unrealize(DeviceState *dev, Error **errp) 1477 { 1478 SDHCIState *s = SYSBUS_SDHCI(dev); 1479 1480 sdhci_common_unrealize(s, &error_abort); 1481 1482 if (s->dma_mr) { 1483 address_space_destroy(s->dma_as); 1484 } 1485 } 1486 1487 static void sdhci_sysbus_class_init(ObjectClass *klass, void *data) 1488 { 1489 DeviceClass *dc = DEVICE_CLASS(klass); 1490 1491 dc->props = sdhci_sysbus_properties; 1492 dc->realize = sdhci_sysbus_realize; 1493 dc->unrealize = sdhci_sysbus_unrealize; 1494 1495 sdhci_common_class_init(klass, data); 1496 } 1497 1498 static const TypeInfo sdhci_sysbus_info = { 1499 .name = TYPE_SYSBUS_SDHCI, 1500 .parent = TYPE_SYS_BUS_DEVICE, 1501 .instance_size = sizeof(SDHCIState), 1502 .instance_init = sdhci_sysbus_init, 1503 .instance_finalize = sdhci_sysbus_finalize, 1504 .class_init = sdhci_sysbus_class_init, 1505 }; 1506 1507 /* --- qdev bus master --- */ 1508 1509 static void sdhci_bus_class_init(ObjectClass *klass, void *data) 1510 { 1511 SDBusClass *sbc = SD_BUS_CLASS(klass); 1512 1513 sbc->set_inserted = sdhci_set_inserted; 1514 sbc->set_readonly = sdhci_set_readonly; 1515 } 1516 1517 static const TypeInfo sdhci_bus_info = { 1518 .name = TYPE_SDHCI_BUS, 1519 .parent = TYPE_SD_BUS, 1520 .instance_size = sizeof(SDBus), 1521 .class_init = sdhci_bus_class_init, 1522 }; 1523 1524 static uint64_t usdhc_read(void *opaque, hwaddr offset, unsigned size) 1525 { 1526 SDHCIState *s = SYSBUS_SDHCI(opaque); 1527 uint32_t ret; 1528 uint16_t hostctl; 1529 1530 switch (offset) { 1531 default: 1532 return sdhci_read(opaque, offset, size); 1533 1534 case SDHC_HOSTCTL: 1535 /* 1536 * For a detailed explanation on the following bit 1537 * manipulation code see comments in a similar part of 1538 * usdhc_write() 1539 */ 1540 hostctl = SDHC_DMA_TYPE(s->hostctl) << (8 - 3); 1541 1542 if (s->hostctl & SDHC_CTRL_8BITBUS) { 1543 hostctl |= ESDHC_CTRL_8BITBUS; 1544 } 1545 1546 if (s->hostctl & SDHC_CTRL_4BITBUS) { 1547 hostctl |= ESDHC_CTRL_4BITBUS; 1548 } 1549 1550 ret = hostctl; 1551 ret |= (uint32_t)s->blkgap << 16; 1552 ret |= (uint32_t)s->wakcon << 24; 1553 1554 break; 1555 1556 case ESDHC_DLL_CTRL: 1557 case ESDHC_TUNE_CTRL_STATUS: 1558 case ESDHC_UNDOCUMENTED_REG27: 1559 case ESDHC_TUNING_CTRL: 1560 case ESDHC_VENDOR_SPEC: 1561 case ESDHC_MIX_CTRL: 1562 case ESDHC_WTMK_LVL: 1563 ret = 0; 1564 break; 1565 } 1566 1567 return ret; 1568 } 1569 1570 static void 1571 usdhc_write(void *opaque, hwaddr offset, uint64_t val, unsigned size) 1572 { 1573 SDHCIState *s = SYSBUS_SDHCI(opaque); 1574 uint8_t hostctl; 1575 uint32_t value = (uint32_t)val; 1576 1577 switch (offset) { 1578 case ESDHC_DLL_CTRL: 1579 case ESDHC_TUNE_CTRL_STATUS: 1580 case ESDHC_UNDOCUMENTED_REG27: 1581 case ESDHC_TUNING_CTRL: 1582 case ESDHC_WTMK_LVL: 1583 case ESDHC_VENDOR_SPEC: 1584 break; 1585 1586 case SDHC_HOSTCTL: 1587 /* 1588 * Here's What ESDHCI has at offset 0x28 (SDHC_HOSTCTL) 1589 * 1590 * 7 6 5 4 3 2 1 0 1591 * |-----------+--------+--------+-----------+----------+---------| 1592 * | Card | Card | Endian | DATA3 | Data | Led | 1593 * | Detect | Detect | Mode | as Card | Transfer | Control | 1594 * | Signal | Test | | Detection | Width | | 1595 * | Selection | Level | | Pin | | | 1596 * |-----------+--------+--------+-----------+----------+---------| 1597 * 1598 * and 0x29 1599 * 1600 * 15 10 9 8 1601 * |----------+------| 1602 * | Reserved | DMA | 1603 * | | Sel. | 1604 * | | | 1605 * |----------+------| 1606 * 1607 * and here's what SDCHI spec expects those offsets to be: 1608 * 1609 * 0x28 (Host Control Register) 1610 * 1611 * 7 6 5 4 3 2 1 0 1612 * |--------+--------+----------+------+--------+----------+---------| 1613 * | Card | Card | Extended | DMA | High | Data | LED | 1614 * | Detect | Detect | Data | Sel. | Speed | Transfer | Control | 1615 * | Signal | Test | Transfer | | Enable | Width | | 1616 * | Sel. | Level | Width | | | | | 1617 * |--------+--------+----------+------+--------+----------+---------| 1618 * 1619 * and 0x29 (Power Control Register) 1620 * 1621 * |----------------------------------| 1622 * | Power Control Register | 1623 * | | 1624 * | Description omitted, | 1625 * | since it has no analog in ESDHCI | 1626 * | | 1627 * |----------------------------------| 1628 * 1629 * Since offsets 0x2A and 0x2B should be compatible between 1630 * both IP specs we only need to reconcile least 16-bit of the 1631 * word we've been given. 1632 */ 1633 1634 /* 1635 * First, save bits 7 6 and 0 since they are identical 1636 */ 1637 hostctl = value & (SDHC_CTRL_LED | 1638 SDHC_CTRL_CDTEST_INS | 1639 SDHC_CTRL_CDTEST_EN); 1640 /* 1641 * Second, split "Data Transfer Width" from bits 2 and 1 in to 1642 * bits 5 and 1 1643 */ 1644 if (value & ESDHC_CTRL_8BITBUS) { 1645 hostctl |= SDHC_CTRL_8BITBUS; 1646 } 1647 1648 if (value & ESDHC_CTRL_4BITBUS) { 1649 hostctl |= ESDHC_CTRL_4BITBUS; 1650 } 1651 1652 /* 1653 * Third, move DMA select from bits 9 and 8 to bits 4 and 3 1654 */ 1655 hostctl |= SDHC_DMA_TYPE(value >> (8 - 3)); 1656 1657 /* 1658 * Now place the corrected value into low 16-bit of the value 1659 * we are going to give standard SDHCI write function 1660 * 1661 * NOTE: This transformation should be the inverse of what can 1662 * be found in drivers/mmc/host/sdhci-esdhc-imx.c in Linux 1663 * kernel 1664 */ 1665 value &= ~UINT16_MAX; 1666 value |= hostctl; 1667 value |= (uint16_t)s->pwrcon << 8; 1668 1669 sdhci_write(opaque, offset, value, size); 1670 break; 1671 1672 case ESDHC_MIX_CTRL: 1673 /* 1674 * So, when SD/MMC stack in Linux tries to write to "Transfer 1675 * Mode Register", ESDHC i.MX quirk code will translate it 1676 * into a write to ESDHC_MIX_CTRL, so we do the opposite in 1677 * order to get where we started 1678 * 1679 * Note that Auto CMD23 Enable bit is located in a wrong place 1680 * on i.MX, but since it is not used by QEMU we do not care. 1681 * 1682 * We don't want to call sdhci_write(.., SDHC_TRNMOD, ...) 1683 * here becuase it will result in a call to 1684 * sdhci_send_command(s) which we don't want. 1685 * 1686 */ 1687 s->trnmod = value & UINT16_MAX; 1688 break; 1689 case SDHC_TRNMOD: 1690 /* 1691 * Similar to above, but this time a write to "Command 1692 * Register" will be translated into a 4-byte write to 1693 * "Transfer Mode register" where lower 16-bit of value would 1694 * be set to zero. So what we do is fill those bits with 1695 * cached value from s->trnmod and let the SDHCI 1696 * infrastructure handle the rest 1697 */ 1698 sdhci_write(opaque, offset, val | s->trnmod, size); 1699 break; 1700 case SDHC_BLKSIZE: 1701 /* 1702 * ESDHCI does not implement "Host SDMA Buffer Boundary", and 1703 * Linux driver will try to zero this field out which will 1704 * break the rest of SDHCI emulation. 1705 * 1706 * Linux defaults to maximum possible setting (512K boundary) 1707 * and it seems to be the only option that i.MX IP implements, 1708 * so we artificially set it to that value. 1709 */ 1710 val |= 0x7 << 12; 1711 /* FALLTHROUGH */ 1712 default: 1713 sdhci_write(opaque, offset, val, size); 1714 break; 1715 } 1716 } 1717 1718 1719 static const MemoryRegionOps usdhc_mmio_ops = { 1720 .read = usdhc_read, 1721 .write = usdhc_write, 1722 .valid = { 1723 .min_access_size = 1, 1724 .max_access_size = 4, 1725 .unaligned = false 1726 }, 1727 .endianness = DEVICE_LITTLE_ENDIAN, 1728 }; 1729 1730 static void imx_usdhc_init(Object *obj) 1731 { 1732 SDHCIState *s = SYSBUS_SDHCI(obj); 1733 1734 s->io_ops = &usdhc_mmio_ops; 1735 s->quirks = SDHCI_QUIRK_NO_BUSY_IRQ; 1736 } 1737 1738 static const TypeInfo imx_usdhc_info = { 1739 .name = TYPE_IMX_USDHC, 1740 .parent = TYPE_SYSBUS_SDHCI, 1741 .instance_init = imx_usdhc_init, 1742 }; 1743 1744 static void sdhci_register_types(void) 1745 { 1746 type_register_static(&sdhci_pci_info); 1747 type_register_static(&sdhci_sysbus_info); 1748 type_register_static(&sdhci_bus_info); 1749 type_register_static(&imx_usdhc_info); 1750 } 1751 1752 type_init(sdhci_register_types) 1753