1 /* 2 * SD Association Host Standard Specification v2.0 controller emulation 3 * 4 * Datasheet: PartA2_SD_Host_Controller_Simplified_Specification_Ver2.00.pdf 5 * 6 * Copyright (c) 2011 Samsung Electronics Co., Ltd. 7 * Mitsyanko Igor <i.mitsyanko@samsung.com> 8 * Peter A.G. Crosthwaite <peter.crosthwaite@petalogix.com> 9 * 10 * Based on MMC controller for Samsung S5PC1xx-based board emulation 11 * by Alexey Merkulov and Vladimir Monakhov. 12 * 13 * This program is free software; you can redistribute it and/or modify it 14 * under the terms of the GNU General Public License as published by the 15 * Free Software Foundation; either version 2 of the License, or (at your 16 * option) any later version. 17 * 18 * This program is distributed in the hope that it will be useful, 19 * but WITHOUT ANY WARRANTY; without even the implied warranty of 20 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. 21 * See the GNU General Public License for more details. 22 * 23 * You should have received a copy of the GNU General Public License along 24 * with this program; if not, see <http://www.gnu.org/licenses/>. 25 */ 26 27 #include "qemu/osdep.h" 28 #include "qemu/units.h" 29 #include "qemu/error-report.h" 30 #include "qapi/error.h" 31 #include "hw/irq.h" 32 #include "hw/qdev-properties.h" 33 #include "sysemu/dma.h" 34 #include "qemu/timer.h" 35 #include "qemu/bitops.h" 36 #include "hw/sd/sdhci.h" 37 #include "migration/vmstate.h" 38 #include "sdhci-internal.h" 39 #include "qemu/log.h" 40 #include "qemu/module.h" 41 #include "trace.h" 42 #include "qom/object.h" 43 44 #define TYPE_SDHCI_BUS "sdhci-bus" 45 /* This is reusing the SDBus typedef from SD_BUS */ 46 DECLARE_INSTANCE_CHECKER(SDBus, SDHCI_BUS, 47 TYPE_SDHCI_BUS) 48 49 #define MASKED_WRITE(reg, mask, val) (reg = (reg & (mask)) | (val)) 50 51 static inline unsigned int sdhci_get_fifolen(SDHCIState *s) 52 { 53 return 1 << (9 + FIELD_EX32(s->capareg, SDHC_CAPAB, MAXBLOCKLENGTH)); 54 } 55 56 /* return true on error */ 57 static bool sdhci_check_capab_freq_range(SDHCIState *s, const char *desc, 58 uint8_t freq, Error **errp) 59 { 60 if (s->sd_spec_version >= 3) { 61 return false; 62 } 63 switch (freq) { 64 case 0: 65 case 10 ... 63: 66 break; 67 default: 68 error_setg(errp, "SD %s clock frequency can have value" 69 "in range 0-63 only", desc); 70 return true; 71 } 72 return false; 73 } 74 75 static void sdhci_check_capareg(SDHCIState *s, Error **errp) 76 { 77 uint64_t msk = s->capareg; 78 uint32_t val; 79 bool y; 80 81 switch (s->sd_spec_version) { 82 case 4: 83 val = FIELD_EX64(s->capareg, SDHC_CAPAB, BUS64BIT_V4); 84 trace_sdhci_capareg("64-bit system bus (v4)", val); 85 msk = FIELD_DP64(msk, SDHC_CAPAB, BUS64BIT_V4, 0); 86 87 val = FIELD_EX64(s->capareg, SDHC_CAPAB, UHS_II); 88 trace_sdhci_capareg("UHS-II", val); 89 msk = FIELD_DP64(msk, SDHC_CAPAB, UHS_II, 0); 90 91 val = FIELD_EX64(s->capareg, SDHC_CAPAB, ADMA3); 92 trace_sdhci_capareg("ADMA3", val); 93 msk = FIELD_DP64(msk, SDHC_CAPAB, ADMA3, 0); 94 95 /* fallthrough */ 96 case 3: 97 val = FIELD_EX64(s->capareg, SDHC_CAPAB, ASYNC_INT); 98 trace_sdhci_capareg("async interrupt", val); 99 msk = FIELD_DP64(msk, SDHC_CAPAB, ASYNC_INT, 0); 100 101 val = FIELD_EX64(s->capareg, SDHC_CAPAB, SLOT_TYPE); 102 if (val) { 103 error_setg(errp, "slot-type not supported"); 104 return; 105 } 106 trace_sdhci_capareg("slot type", val); 107 msk = FIELD_DP64(msk, SDHC_CAPAB, SLOT_TYPE, 0); 108 109 if (val != 2) { 110 val = FIELD_EX64(s->capareg, SDHC_CAPAB, EMBEDDED_8BIT); 111 trace_sdhci_capareg("8-bit bus", val); 112 } 113 msk = FIELD_DP64(msk, SDHC_CAPAB, EMBEDDED_8BIT, 0); 114 115 val = FIELD_EX64(s->capareg, SDHC_CAPAB, BUS_SPEED); 116 trace_sdhci_capareg("bus speed mask", val); 117 msk = FIELD_DP64(msk, SDHC_CAPAB, BUS_SPEED, 0); 118 119 val = FIELD_EX64(s->capareg, SDHC_CAPAB, DRIVER_STRENGTH); 120 trace_sdhci_capareg("driver strength mask", val); 121 msk = FIELD_DP64(msk, SDHC_CAPAB, DRIVER_STRENGTH, 0); 122 123 val = FIELD_EX64(s->capareg, SDHC_CAPAB, TIMER_RETUNING); 124 trace_sdhci_capareg("timer re-tuning", val); 125 msk = FIELD_DP64(msk, SDHC_CAPAB, TIMER_RETUNING, 0); 126 127 val = FIELD_EX64(s->capareg, SDHC_CAPAB, SDR50_TUNING); 128 trace_sdhci_capareg("use SDR50 tuning", val); 129 msk = FIELD_DP64(msk, SDHC_CAPAB, SDR50_TUNING, 0); 130 131 val = FIELD_EX64(s->capareg, SDHC_CAPAB, RETUNING_MODE); 132 trace_sdhci_capareg("re-tuning mode", val); 133 msk = FIELD_DP64(msk, SDHC_CAPAB, RETUNING_MODE, 0); 134 135 val = FIELD_EX64(s->capareg, SDHC_CAPAB, CLOCK_MULT); 136 trace_sdhci_capareg("clock multiplier", val); 137 msk = FIELD_DP64(msk, SDHC_CAPAB, CLOCK_MULT, 0); 138 139 /* fallthrough */ 140 case 2: /* default version */ 141 val = FIELD_EX64(s->capareg, SDHC_CAPAB, ADMA2); 142 trace_sdhci_capareg("ADMA2", val); 143 msk = FIELD_DP64(msk, SDHC_CAPAB, ADMA2, 0); 144 145 val = FIELD_EX64(s->capareg, SDHC_CAPAB, ADMA1); 146 trace_sdhci_capareg("ADMA1", val); 147 msk = FIELD_DP64(msk, SDHC_CAPAB, ADMA1, 0); 148 149 val = FIELD_EX64(s->capareg, SDHC_CAPAB, BUS64BIT); 150 trace_sdhci_capareg("64-bit system bus (v3)", val); 151 msk = FIELD_DP64(msk, SDHC_CAPAB, BUS64BIT, 0); 152 153 /* fallthrough */ 154 case 1: 155 y = FIELD_EX64(s->capareg, SDHC_CAPAB, TOUNIT); 156 msk = FIELD_DP64(msk, SDHC_CAPAB, TOUNIT, 0); 157 158 val = FIELD_EX64(s->capareg, SDHC_CAPAB, TOCLKFREQ); 159 trace_sdhci_capareg(y ? "timeout (MHz)" : "Timeout (KHz)", val); 160 if (sdhci_check_capab_freq_range(s, "timeout", val, errp)) { 161 return; 162 } 163 msk = FIELD_DP64(msk, SDHC_CAPAB, TOCLKFREQ, 0); 164 165 val = FIELD_EX64(s->capareg, SDHC_CAPAB, BASECLKFREQ); 166 trace_sdhci_capareg(y ? "base (MHz)" : "Base (KHz)", val); 167 if (sdhci_check_capab_freq_range(s, "base", val, errp)) { 168 return; 169 } 170 msk = FIELD_DP64(msk, SDHC_CAPAB, BASECLKFREQ, 0); 171 172 val = FIELD_EX64(s->capareg, SDHC_CAPAB, MAXBLOCKLENGTH); 173 if (val >= 3) { 174 error_setg(errp, "block size can be 512, 1024 or 2048 only"); 175 return; 176 } 177 trace_sdhci_capareg("max block length", sdhci_get_fifolen(s)); 178 msk = FIELD_DP64(msk, SDHC_CAPAB, MAXBLOCKLENGTH, 0); 179 180 val = FIELD_EX64(s->capareg, SDHC_CAPAB, HIGHSPEED); 181 trace_sdhci_capareg("high speed", val); 182 msk = FIELD_DP64(msk, SDHC_CAPAB, HIGHSPEED, 0); 183 184 val = FIELD_EX64(s->capareg, SDHC_CAPAB, SDMA); 185 trace_sdhci_capareg("SDMA", val); 186 msk = FIELD_DP64(msk, SDHC_CAPAB, SDMA, 0); 187 188 val = FIELD_EX64(s->capareg, SDHC_CAPAB, SUSPRESUME); 189 trace_sdhci_capareg("suspend/resume", val); 190 msk = FIELD_DP64(msk, SDHC_CAPAB, SUSPRESUME, 0); 191 192 val = FIELD_EX64(s->capareg, SDHC_CAPAB, V33); 193 trace_sdhci_capareg("3.3v", val); 194 msk = FIELD_DP64(msk, SDHC_CAPAB, V33, 0); 195 196 val = FIELD_EX64(s->capareg, SDHC_CAPAB, V30); 197 trace_sdhci_capareg("3.0v", val); 198 msk = FIELD_DP64(msk, SDHC_CAPAB, V30, 0); 199 200 val = FIELD_EX64(s->capareg, SDHC_CAPAB, V18); 201 trace_sdhci_capareg("1.8v", val); 202 msk = FIELD_DP64(msk, SDHC_CAPAB, V18, 0); 203 break; 204 205 default: 206 error_setg(errp, "Unsupported spec version: %u", s->sd_spec_version); 207 } 208 if (msk) { 209 qemu_log_mask(LOG_UNIMP, 210 "SDHCI: unknown CAPAB mask: 0x%016" PRIx64 "\n", msk); 211 } 212 } 213 214 static uint8_t sdhci_slotint(SDHCIState *s) 215 { 216 return (s->norintsts & s->norintsigen) || (s->errintsts & s->errintsigen) || 217 ((s->norintsts & SDHC_NIS_INSERT) && (s->wakcon & SDHC_WKUP_ON_INS)) || 218 ((s->norintsts & SDHC_NIS_REMOVE) && (s->wakcon & SDHC_WKUP_ON_RMV)); 219 } 220 221 static inline void sdhci_update_irq(SDHCIState *s) 222 { 223 qemu_set_irq(s->irq, sdhci_slotint(s)); 224 } 225 226 static void sdhci_raise_insertion_irq(void *opaque) 227 { 228 SDHCIState *s = (SDHCIState *)opaque; 229 230 if (s->norintsts & SDHC_NIS_REMOVE) { 231 timer_mod(s->insert_timer, 232 qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + SDHC_INSERTION_DELAY); 233 } else { 234 s->prnsts = 0x1ff0000; 235 if (s->norintstsen & SDHC_NISEN_INSERT) { 236 s->norintsts |= SDHC_NIS_INSERT; 237 } 238 sdhci_update_irq(s); 239 } 240 } 241 242 static void sdhci_set_inserted(DeviceState *dev, bool level) 243 { 244 SDHCIState *s = (SDHCIState *)dev; 245 246 trace_sdhci_set_inserted(level ? "insert" : "eject"); 247 if ((s->norintsts & SDHC_NIS_REMOVE) && level) { 248 /* Give target some time to notice card ejection */ 249 timer_mod(s->insert_timer, 250 qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + SDHC_INSERTION_DELAY); 251 } else { 252 if (level) { 253 s->prnsts = 0x1ff0000; 254 if (s->norintstsen & SDHC_NISEN_INSERT) { 255 s->norintsts |= SDHC_NIS_INSERT; 256 } 257 } else { 258 s->prnsts = 0x1fa0000; 259 s->pwrcon &= ~SDHC_POWER_ON; 260 s->clkcon &= ~SDHC_CLOCK_SDCLK_EN; 261 if (s->norintstsen & SDHC_NISEN_REMOVE) { 262 s->norintsts |= SDHC_NIS_REMOVE; 263 } 264 } 265 sdhci_update_irq(s); 266 } 267 } 268 269 static void sdhci_set_readonly(DeviceState *dev, bool level) 270 { 271 SDHCIState *s = (SDHCIState *)dev; 272 273 if (level) { 274 s->prnsts &= ~SDHC_WRITE_PROTECT; 275 } else { 276 /* Write enabled */ 277 s->prnsts |= SDHC_WRITE_PROTECT; 278 } 279 } 280 281 static void sdhci_reset(SDHCIState *s) 282 { 283 DeviceState *dev = DEVICE(s); 284 285 timer_del(s->insert_timer); 286 timer_del(s->transfer_timer); 287 288 /* Set all registers to 0. Capabilities/Version registers are not cleared 289 * and assumed to always preserve their value, given to them during 290 * initialization */ 291 memset(&s->sdmasysad, 0, (uintptr_t)&s->capareg - (uintptr_t)&s->sdmasysad); 292 293 /* Reset other state based on current card insertion/readonly status */ 294 sdhci_set_inserted(dev, sdbus_get_inserted(&s->sdbus)); 295 sdhci_set_readonly(dev, sdbus_get_readonly(&s->sdbus)); 296 297 s->data_count = 0; 298 s->stopped_state = sdhc_not_stopped; 299 s->pending_insert_state = false; 300 } 301 302 static void sdhci_poweron_reset(DeviceState *dev) 303 { 304 /* QOM (ie power-on) reset. This is identical to reset 305 * commanded via device register apart from handling of the 306 * 'pending insert on powerup' quirk. 307 */ 308 SDHCIState *s = (SDHCIState *)dev; 309 310 sdhci_reset(s); 311 312 if (s->pending_insert_quirk) { 313 s->pending_insert_state = true; 314 } 315 } 316 317 static void sdhci_data_transfer(void *opaque); 318 319 static void sdhci_send_command(SDHCIState *s) 320 { 321 SDRequest request; 322 uint8_t response[16]; 323 int rlen; 324 325 s->errintsts = 0; 326 s->acmd12errsts = 0; 327 request.cmd = s->cmdreg >> 8; 328 request.arg = s->argument; 329 330 trace_sdhci_send_command(request.cmd, request.arg); 331 rlen = sdbus_do_command(&s->sdbus, &request, response); 332 333 if (s->cmdreg & SDHC_CMD_RESPONSE) { 334 if (rlen == 4) { 335 s->rspreg[0] = ldl_be_p(response); 336 s->rspreg[1] = s->rspreg[2] = s->rspreg[3] = 0; 337 trace_sdhci_response4(s->rspreg[0]); 338 } else if (rlen == 16) { 339 s->rspreg[0] = ldl_be_p(&response[11]); 340 s->rspreg[1] = ldl_be_p(&response[7]); 341 s->rspreg[2] = ldl_be_p(&response[3]); 342 s->rspreg[3] = (response[0] << 16) | (response[1] << 8) | 343 response[2]; 344 trace_sdhci_response16(s->rspreg[3], s->rspreg[2], 345 s->rspreg[1], s->rspreg[0]); 346 } else { 347 trace_sdhci_error("timeout waiting for command response"); 348 if (s->errintstsen & SDHC_EISEN_CMDTIMEOUT) { 349 s->errintsts |= SDHC_EIS_CMDTIMEOUT; 350 s->norintsts |= SDHC_NIS_ERR; 351 } 352 } 353 354 if (!(s->quirks & SDHCI_QUIRK_NO_BUSY_IRQ) && 355 (s->norintstsen & SDHC_NISEN_TRSCMP) && 356 (s->cmdreg & SDHC_CMD_RESPONSE) == SDHC_CMD_RSP_WITH_BUSY) { 357 s->norintsts |= SDHC_NIS_TRSCMP; 358 } 359 } 360 361 if (s->norintstsen & SDHC_NISEN_CMDCMP) { 362 s->norintsts |= SDHC_NIS_CMDCMP; 363 } 364 365 sdhci_update_irq(s); 366 367 if (s->blksize && (s->cmdreg & SDHC_CMD_DATA_PRESENT)) { 368 s->data_count = 0; 369 sdhci_data_transfer(s); 370 } 371 } 372 373 static void sdhci_end_transfer(SDHCIState *s) 374 { 375 /* Automatically send CMD12 to stop transfer if AutoCMD12 enabled */ 376 if ((s->trnmod & SDHC_TRNS_ACMD12) != 0) { 377 SDRequest request; 378 uint8_t response[16]; 379 380 request.cmd = 0x0C; 381 request.arg = 0; 382 trace_sdhci_end_transfer(request.cmd, request.arg); 383 sdbus_do_command(&s->sdbus, &request, response); 384 /* Auto CMD12 response goes to the upper Response register */ 385 s->rspreg[3] = ldl_be_p(response); 386 } 387 388 s->prnsts &= ~(SDHC_DOING_READ | SDHC_DOING_WRITE | 389 SDHC_DAT_LINE_ACTIVE | SDHC_DATA_INHIBIT | 390 SDHC_SPACE_AVAILABLE | SDHC_DATA_AVAILABLE); 391 392 if (s->norintstsen & SDHC_NISEN_TRSCMP) { 393 s->norintsts |= SDHC_NIS_TRSCMP; 394 } 395 396 sdhci_update_irq(s); 397 } 398 399 /* 400 * Programmed i/o data transfer 401 */ 402 #define BLOCK_SIZE_MASK (4 * KiB - 1) 403 404 /* Fill host controller's read buffer with BLKSIZE bytes of data from card */ 405 static void sdhci_read_block_from_card(SDHCIState *s) 406 { 407 const uint16_t blk_size = s->blksize & BLOCK_SIZE_MASK; 408 409 if ((s->trnmod & SDHC_TRNS_MULTI) && 410 (s->trnmod & SDHC_TRNS_BLK_CNT_EN) && (s->blkcnt == 0)) { 411 return; 412 } 413 414 if (!FIELD_EX32(s->hostctl2, SDHC_HOSTCTL2, EXECUTE_TUNING)) { 415 /* Device is not in tuning */ 416 sdbus_read_data(&s->sdbus, s->fifo_buffer, blk_size); 417 } 418 419 if (FIELD_EX32(s->hostctl2, SDHC_HOSTCTL2, EXECUTE_TUNING)) { 420 /* Device is in tuning */ 421 s->hostctl2 &= ~R_SDHC_HOSTCTL2_EXECUTE_TUNING_MASK; 422 s->hostctl2 |= R_SDHC_HOSTCTL2_SAMPLING_CLKSEL_MASK; 423 s->prnsts &= ~(SDHC_DAT_LINE_ACTIVE | SDHC_DOING_READ | 424 SDHC_DATA_INHIBIT); 425 goto read_done; 426 } 427 428 /* New data now available for READ through Buffer Port Register */ 429 s->prnsts |= SDHC_DATA_AVAILABLE; 430 if (s->norintstsen & SDHC_NISEN_RBUFRDY) { 431 s->norintsts |= SDHC_NIS_RBUFRDY; 432 } 433 434 /* Clear DAT line active status if that was the last block */ 435 if ((s->trnmod & SDHC_TRNS_MULTI) == 0 || 436 ((s->trnmod & SDHC_TRNS_MULTI) && s->blkcnt == 1)) { 437 s->prnsts &= ~SDHC_DAT_LINE_ACTIVE; 438 } 439 440 /* If stop at block gap request was set and it's not the last block of 441 * data - generate Block Event interrupt */ 442 if (s->stopped_state == sdhc_gap_read && (s->trnmod & SDHC_TRNS_MULTI) && 443 s->blkcnt != 1) { 444 s->prnsts &= ~SDHC_DAT_LINE_ACTIVE; 445 if (s->norintstsen & SDHC_EISEN_BLKGAP) { 446 s->norintsts |= SDHC_EIS_BLKGAP; 447 } 448 } 449 450 read_done: 451 sdhci_update_irq(s); 452 } 453 454 /* Read @size byte of data from host controller @s BUFFER DATA PORT register */ 455 static uint32_t sdhci_read_dataport(SDHCIState *s, unsigned size) 456 { 457 uint32_t value = 0; 458 int i; 459 460 /* first check that a valid data exists in host controller input buffer */ 461 if ((s->prnsts & SDHC_DATA_AVAILABLE) == 0) { 462 trace_sdhci_error("read from empty buffer"); 463 return 0; 464 } 465 466 for (i = 0; i < size; i++) { 467 value |= s->fifo_buffer[s->data_count] << i * 8; 468 s->data_count++; 469 /* check if we've read all valid data (blksize bytes) from buffer */ 470 if ((s->data_count) >= (s->blksize & BLOCK_SIZE_MASK)) { 471 trace_sdhci_read_dataport(s->data_count); 472 s->prnsts &= ~SDHC_DATA_AVAILABLE; /* no more data in a buffer */ 473 s->data_count = 0; /* next buff read must start at position [0] */ 474 475 if (s->trnmod & SDHC_TRNS_BLK_CNT_EN) { 476 s->blkcnt--; 477 } 478 479 /* if that was the last block of data */ 480 if ((s->trnmod & SDHC_TRNS_MULTI) == 0 || 481 ((s->trnmod & SDHC_TRNS_BLK_CNT_EN) && (s->blkcnt == 0)) || 482 /* stop at gap request */ 483 (s->stopped_state == sdhc_gap_read && 484 !(s->prnsts & SDHC_DAT_LINE_ACTIVE))) { 485 sdhci_end_transfer(s); 486 } else { /* if there are more data, read next block from card */ 487 sdhci_read_block_from_card(s); 488 } 489 break; 490 } 491 } 492 493 return value; 494 } 495 496 /* Write data from host controller FIFO to card */ 497 static void sdhci_write_block_to_card(SDHCIState *s) 498 { 499 if (s->prnsts & SDHC_SPACE_AVAILABLE) { 500 if (s->norintstsen & SDHC_NISEN_WBUFRDY) { 501 s->norintsts |= SDHC_NIS_WBUFRDY; 502 } 503 sdhci_update_irq(s); 504 return; 505 } 506 507 if (s->trnmod & SDHC_TRNS_BLK_CNT_EN) { 508 if (s->blkcnt == 0) { 509 return; 510 } else { 511 s->blkcnt--; 512 } 513 } 514 515 sdbus_write_data(&s->sdbus, s->fifo_buffer, s->blksize & BLOCK_SIZE_MASK); 516 517 /* Next data can be written through BUFFER DATORT register */ 518 s->prnsts |= SDHC_SPACE_AVAILABLE; 519 520 /* Finish transfer if that was the last block of data */ 521 if ((s->trnmod & SDHC_TRNS_MULTI) == 0 || 522 ((s->trnmod & SDHC_TRNS_MULTI) && 523 (s->trnmod & SDHC_TRNS_BLK_CNT_EN) && (s->blkcnt == 0))) { 524 sdhci_end_transfer(s); 525 } else if (s->norintstsen & SDHC_NISEN_WBUFRDY) { 526 s->norintsts |= SDHC_NIS_WBUFRDY; 527 } 528 529 /* Generate Block Gap Event if requested and if not the last block */ 530 if (s->stopped_state == sdhc_gap_write && (s->trnmod & SDHC_TRNS_MULTI) && 531 s->blkcnt > 0) { 532 s->prnsts &= ~SDHC_DOING_WRITE; 533 if (s->norintstsen & SDHC_EISEN_BLKGAP) { 534 s->norintsts |= SDHC_EIS_BLKGAP; 535 } 536 sdhci_end_transfer(s); 537 } 538 539 sdhci_update_irq(s); 540 } 541 542 /* Write @size bytes of @value data to host controller @s Buffer Data Port 543 * register */ 544 static void sdhci_write_dataport(SDHCIState *s, uint32_t value, unsigned size) 545 { 546 unsigned i; 547 548 /* Check that there is free space left in a buffer */ 549 if (!(s->prnsts & SDHC_SPACE_AVAILABLE)) { 550 trace_sdhci_error("Can't write to data buffer: buffer full"); 551 return; 552 } 553 554 for (i = 0; i < size; i++) { 555 s->fifo_buffer[s->data_count] = value & 0xFF; 556 s->data_count++; 557 value >>= 8; 558 if (s->data_count >= (s->blksize & BLOCK_SIZE_MASK)) { 559 trace_sdhci_write_dataport(s->data_count); 560 s->data_count = 0; 561 s->prnsts &= ~SDHC_SPACE_AVAILABLE; 562 if (s->prnsts & SDHC_DOING_WRITE) { 563 sdhci_write_block_to_card(s); 564 } 565 } 566 } 567 } 568 569 /* 570 * Single DMA data transfer 571 */ 572 573 /* Multi block SDMA transfer */ 574 static void sdhci_sdma_transfer_multi_blocks(SDHCIState *s) 575 { 576 bool page_aligned = false; 577 unsigned int begin; 578 const uint16_t block_size = s->blksize & BLOCK_SIZE_MASK; 579 uint32_t boundary_chk = 1 << (((s->blksize & ~BLOCK_SIZE_MASK) >> 12) + 12); 580 uint32_t boundary_count = boundary_chk - (s->sdmasysad % boundary_chk); 581 582 if (!(s->trnmod & SDHC_TRNS_BLK_CNT_EN) || !s->blkcnt) { 583 qemu_log_mask(LOG_UNIMP, "infinite transfer is not supported\n"); 584 return; 585 } 586 587 /* XXX: Some sd/mmc drivers (for example, u-boot-slp) do not account for 588 * possible stop at page boundary if initial address is not page aligned, 589 * allow them to work properly */ 590 if ((s->sdmasysad % boundary_chk) == 0) { 591 page_aligned = true; 592 } 593 594 if (s->trnmod & SDHC_TRNS_READ) { 595 s->prnsts |= SDHC_DOING_READ | SDHC_DATA_INHIBIT | 596 SDHC_DAT_LINE_ACTIVE; 597 while (s->blkcnt) { 598 if (s->data_count == 0) { 599 sdbus_read_data(&s->sdbus, s->fifo_buffer, block_size); 600 } 601 begin = s->data_count; 602 if (((boundary_count + begin) < block_size) && page_aligned) { 603 s->data_count = boundary_count + begin; 604 boundary_count = 0; 605 } else { 606 s->data_count = block_size; 607 boundary_count -= block_size - begin; 608 if (s->trnmod & SDHC_TRNS_BLK_CNT_EN) { 609 s->blkcnt--; 610 } 611 } 612 dma_memory_write(s->dma_as, s->sdmasysad, 613 &s->fifo_buffer[begin], s->data_count - begin); 614 s->sdmasysad += s->data_count - begin; 615 if (s->data_count == block_size) { 616 s->data_count = 0; 617 } 618 if (page_aligned && boundary_count == 0) { 619 break; 620 } 621 } 622 } else { 623 s->prnsts |= SDHC_DOING_WRITE | SDHC_DATA_INHIBIT | 624 SDHC_DAT_LINE_ACTIVE; 625 while (s->blkcnt) { 626 begin = s->data_count; 627 if (((boundary_count + begin) < block_size) && page_aligned) { 628 s->data_count = boundary_count + begin; 629 boundary_count = 0; 630 } else { 631 s->data_count = block_size; 632 boundary_count -= block_size - begin; 633 } 634 dma_memory_read(s->dma_as, s->sdmasysad, 635 &s->fifo_buffer[begin], s->data_count - begin); 636 s->sdmasysad += s->data_count - begin; 637 if (s->data_count == block_size) { 638 sdbus_write_data(&s->sdbus, s->fifo_buffer, block_size); 639 s->data_count = 0; 640 if (s->trnmod & SDHC_TRNS_BLK_CNT_EN) { 641 s->blkcnt--; 642 } 643 } 644 if (page_aligned && boundary_count == 0) { 645 break; 646 } 647 } 648 } 649 650 if (s->blkcnt == 0) { 651 sdhci_end_transfer(s); 652 } else { 653 if (s->norintstsen & SDHC_NISEN_DMA) { 654 s->norintsts |= SDHC_NIS_DMA; 655 } 656 sdhci_update_irq(s); 657 } 658 } 659 660 /* single block SDMA transfer */ 661 static void sdhci_sdma_transfer_single_block(SDHCIState *s) 662 { 663 uint32_t datacnt = s->blksize & BLOCK_SIZE_MASK; 664 665 if (s->trnmod & SDHC_TRNS_READ) { 666 sdbus_read_data(&s->sdbus, s->fifo_buffer, datacnt); 667 dma_memory_write(s->dma_as, s->sdmasysad, s->fifo_buffer, datacnt); 668 } else { 669 dma_memory_read(s->dma_as, s->sdmasysad, s->fifo_buffer, datacnt); 670 sdbus_write_data(&s->sdbus, s->fifo_buffer, datacnt); 671 } 672 s->blkcnt--; 673 674 sdhci_end_transfer(s); 675 } 676 677 typedef struct ADMADescr { 678 hwaddr addr; 679 uint16_t length; 680 uint8_t attr; 681 uint8_t incr; 682 } ADMADescr; 683 684 static void get_adma_description(SDHCIState *s, ADMADescr *dscr) 685 { 686 uint32_t adma1 = 0; 687 uint64_t adma2 = 0; 688 hwaddr entry_addr = (hwaddr)s->admasysaddr; 689 switch (SDHC_DMA_TYPE(s->hostctl1)) { 690 case SDHC_CTRL_ADMA2_32: 691 dma_memory_read(s->dma_as, entry_addr, &adma2, sizeof(adma2)); 692 adma2 = le64_to_cpu(adma2); 693 /* The spec does not specify endianness of descriptor table. 694 * We currently assume that it is LE. 695 */ 696 dscr->addr = (hwaddr)extract64(adma2, 32, 32) & ~0x3ull; 697 dscr->length = (uint16_t)extract64(adma2, 16, 16); 698 dscr->attr = (uint8_t)extract64(adma2, 0, 7); 699 dscr->incr = 8; 700 break; 701 case SDHC_CTRL_ADMA1_32: 702 dma_memory_read(s->dma_as, entry_addr, &adma1, sizeof(adma1)); 703 adma1 = le32_to_cpu(adma1); 704 dscr->addr = (hwaddr)(adma1 & 0xFFFFF000); 705 dscr->attr = (uint8_t)extract32(adma1, 0, 7); 706 dscr->incr = 4; 707 if ((dscr->attr & SDHC_ADMA_ATTR_ACT_MASK) == SDHC_ADMA_ATTR_SET_LEN) { 708 dscr->length = (uint16_t)extract32(adma1, 12, 16); 709 } else { 710 dscr->length = 4 * KiB; 711 } 712 break; 713 case SDHC_CTRL_ADMA2_64: 714 dma_memory_read(s->dma_as, entry_addr, &dscr->attr, 1); 715 dma_memory_read(s->dma_as, entry_addr + 2, &dscr->length, 2); 716 dscr->length = le16_to_cpu(dscr->length); 717 dma_memory_read(s->dma_as, entry_addr + 4, &dscr->addr, 8); 718 dscr->addr = le64_to_cpu(dscr->addr); 719 dscr->attr &= (uint8_t) ~0xC0; 720 dscr->incr = 12; 721 break; 722 } 723 } 724 725 /* Advanced DMA data transfer */ 726 727 static void sdhci_do_adma(SDHCIState *s) 728 { 729 unsigned int begin, length; 730 const uint16_t block_size = s->blksize & BLOCK_SIZE_MASK; 731 ADMADescr dscr = {}; 732 int i; 733 734 if (s->trnmod & SDHC_TRNS_BLK_CNT_EN && !s->blkcnt) { 735 /* Stop Multiple Transfer */ 736 sdhci_end_transfer(s); 737 return; 738 } 739 740 for (i = 0; i < SDHC_ADMA_DESCS_PER_DELAY; ++i) { 741 s->admaerr &= ~SDHC_ADMAERR_LENGTH_MISMATCH; 742 743 get_adma_description(s, &dscr); 744 trace_sdhci_adma_loop(dscr.addr, dscr.length, dscr.attr); 745 746 if ((dscr.attr & SDHC_ADMA_ATTR_VALID) == 0) { 747 /* Indicate that error occurred in ST_FDS state */ 748 s->admaerr &= ~SDHC_ADMAERR_STATE_MASK; 749 s->admaerr |= SDHC_ADMAERR_STATE_ST_FDS; 750 751 /* Generate ADMA error interrupt */ 752 if (s->errintstsen & SDHC_EISEN_ADMAERR) { 753 s->errintsts |= SDHC_EIS_ADMAERR; 754 s->norintsts |= SDHC_NIS_ERR; 755 } 756 757 sdhci_update_irq(s); 758 return; 759 } 760 761 length = dscr.length ? dscr.length : 64 * KiB; 762 763 switch (dscr.attr & SDHC_ADMA_ATTR_ACT_MASK) { 764 case SDHC_ADMA_ATTR_ACT_TRAN: /* data transfer */ 765 if (s->trnmod & SDHC_TRNS_READ) { 766 while (length) { 767 if (s->data_count == 0) { 768 sdbus_read_data(&s->sdbus, s->fifo_buffer, block_size); 769 } 770 begin = s->data_count; 771 if ((length + begin) < block_size) { 772 s->data_count = length + begin; 773 length = 0; 774 } else { 775 s->data_count = block_size; 776 length -= block_size - begin; 777 } 778 dma_memory_write(s->dma_as, dscr.addr, 779 &s->fifo_buffer[begin], 780 s->data_count - begin); 781 dscr.addr += s->data_count - begin; 782 if (s->data_count == block_size) { 783 s->data_count = 0; 784 if (s->trnmod & SDHC_TRNS_BLK_CNT_EN) { 785 s->blkcnt--; 786 if (s->blkcnt == 0) { 787 break; 788 } 789 } 790 } 791 } 792 } else { 793 while (length) { 794 begin = s->data_count; 795 if ((length + begin) < block_size) { 796 s->data_count = length + begin; 797 length = 0; 798 } else { 799 s->data_count = block_size; 800 length -= block_size - begin; 801 } 802 dma_memory_read(s->dma_as, dscr.addr, 803 &s->fifo_buffer[begin], 804 s->data_count - begin); 805 dscr.addr += s->data_count - begin; 806 if (s->data_count == block_size) { 807 sdbus_write_data(&s->sdbus, s->fifo_buffer, block_size); 808 s->data_count = 0; 809 if (s->trnmod & SDHC_TRNS_BLK_CNT_EN) { 810 s->blkcnt--; 811 if (s->blkcnt == 0) { 812 break; 813 } 814 } 815 } 816 } 817 } 818 s->admasysaddr += dscr.incr; 819 break; 820 case SDHC_ADMA_ATTR_ACT_LINK: /* link to next descriptor table */ 821 s->admasysaddr = dscr.addr; 822 trace_sdhci_adma("link", s->admasysaddr); 823 break; 824 default: 825 s->admasysaddr += dscr.incr; 826 break; 827 } 828 829 if (dscr.attr & SDHC_ADMA_ATTR_INT) { 830 trace_sdhci_adma("interrupt", s->admasysaddr); 831 if (s->norintstsen & SDHC_NISEN_DMA) { 832 s->norintsts |= SDHC_NIS_DMA; 833 } 834 835 sdhci_update_irq(s); 836 } 837 838 /* ADMA transfer terminates if blkcnt == 0 or by END attribute */ 839 if (((s->trnmod & SDHC_TRNS_BLK_CNT_EN) && 840 (s->blkcnt == 0)) || (dscr.attr & SDHC_ADMA_ATTR_END)) { 841 trace_sdhci_adma_transfer_completed(); 842 if (length || ((dscr.attr & SDHC_ADMA_ATTR_END) && 843 (s->trnmod & SDHC_TRNS_BLK_CNT_EN) && 844 s->blkcnt != 0)) { 845 trace_sdhci_error("SD/MMC host ADMA length mismatch"); 846 s->admaerr |= SDHC_ADMAERR_LENGTH_MISMATCH | 847 SDHC_ADMAERR_STATE_ST_TFR; 848 if (s->errintstsen & SDHC_EISEN_ADMAERR) { 849 trace_sdhci_error("Set ADMA error flag"); 850 s->errintsts |= SDHC_EIS_ADMAERR; 851 s->norintsts |= SDHC_NIS_ERR; 852 } 853 854 sdhci_update_irq(s); 855 } 856 sdhci_end_transfer(s); 857 return; 858 } 859 860 } 861 862 /* we have unfinished business - reschedule to continue ADMA */ 863 timer_mod(s->transfer_timer, 864 qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + SDHC_TRANSFER_DELAY); 865 } 866 867 /* Perform data transfer according to controller configuration */ 868 869 static void sdhci_data_transfer(void *opaque) 870 { 871 SDHCIState *s = (SDHCIState *)opaque; 872 873 if (s->trnmod & SDHC_TRNS_DMA) { 874 switch (SDHC_DMA_TYPE(s->hostctl1)) { 875 case SDHC_CTRL_SDMA: 876 if ((s->blkcnt == 1) || !(s->trnmod & SDHC_TRNS_MULTI)) { 877 sdhci_sdma_transfer_single_block(s); 878 } else { 879 sdhci_sdma_transfer_multi_blocks(s); 880 } 881 882 break; 883 case SDHC_CTRL_ADMA1_32: 884 if (!(s->capareg & R_SDHC_CAPAB_ADMA1_MASK)) { 885 trace_sdhci_error("ADMA1 not supported"); 886 break; 887 } 888 889 sdhci_do_adma(s); 890 break; 891 case SDHC_CTRL_ADMA2_32: 892 if (!(s->capareg & R_SDHC_CAPAB_ADMA2_MASK)) { 893 trace_sdhci_error("ADMA2 not supported"); 894 break; 895 } 896 897 sdhci_do_adma(s); 898 break; 899 case SDHC_CTRL_ADMA2_64: 900 if (!(s->capareg & R_SDHC_CAPAB_ADMA2_MASK) || 901 !(s->capareg & R_SDHC_CAPAB_BUS64BIT_MASK)) { 902 trace_sdhci_error("64 bit ADMA not supported"); 903 break; 904 } 905 906 sdhci_do_adma(s); 907 break; 908 default: 909 trace_sdhci_error("Unsupported DMA type"); 910 break; 911 } 912 } else { 913 if ((s->trnmod & SDHC_TRNS_READ) && sdbus_data_ready(&s->sdbus)) { 914 s->prnsts |= SDHC_DOING_READ | SDHC_DATA_INHIBIT | 915 SDHC_DAT_LINE_ACTIVE; 916 sdhci_read_block_from_card(s); 917 } else { 918 s->prnsts |= SDHC_DOING_WRITE | SDHC_DAT_LINE_ACTIVE | 919 SDHC_SPACE_AVAILABLE | SDHC_DATA_INHIBIT; 920 sdhci_write_block_to_card(s); 921 } 922 } 923 } 924 925 static bool sdhci_can_issue_command(SDHCIState *s) 926 { 927 if (!SDHC_CLOCK_IS_ON(s->clkcon) || 928 (((s->prnsts & SDHC_DATA_INHIBIT) || s->stopped_state) && 929 ((s->cmdreg & SDHC_CMD_DATA_PRESENT) || 930 ((s->cmdreg & SDHC_CMD_RESPONSE) == SDHC_CMD_RSP_WITH_BUSY && 931 !(SDHC_COMMAND_TYPE(s->cmdreg) == SDHC_CMD_ABORT))))) { 932 return false; 933 } 934 935 return true; 936 } 937 938 /* The Buffer Data Port register must be accessed in sequential and 939 * continuous manner */ 940 static inline bool 941 sdhci_buff_access_is_sequential(SDHCIState *s, unsigned byte_num) 942 { 943 if ((s->data_count & 0x3) != byte_num) { 944 trace_sdhci_error("Non-sequential access to Buffer Data Port register" 945 "is prohibited\n"); 946 return false; 947 } 948 return true; 949 } 950 951 static uint64_t sdhci_read(void *opaque, hwaddr offset, unsigned size) 952 { 953 SDHCIState *s = (SDHCIState *)opaque; 954 uint32_t ret = 0; 955 956 switch (offset & ~0x3) { 957 case SDHC_SYSAD: 958 ret = s->sdmasysad; 959 break; 960 case SDHC_BLKSIZE: 961 ret = s->blksize | (s->blkcnt << 16); 962 break; 963 case SDHC_ARGUMENT: 964 ret = s->argument; 965 break; 966 case SDHC_TRNMOD: 967 ret = s->trnmod | (s->cmdreg << 16); 968 break; 969 case SDHC_RSPREG0 ... SDHC_RSPREG3: 970 ret = s->rspreg[((offset & ~0x3) - SDHC_RSPREG0) >> 2]; 971 break; 972 case SDHC_BDATA: 973 if (sdhci_buff_access_is_sequential(s, offset - SDHC_BDATA)) { 974 ret = sdhci_read_dataport(s, size); 975 trace_sdhci_access("rd", size << 3, offset, "->", ret, ret); 976 return ret; 977 } 978 break; 979 case SDHC_PRNSTS: 980 ret = s->prnsts; 981 ret = FIELD_DP32(ret, SDHC_PRNSTS, DAT_LVL, 982 sdbus_get_dat_lines(&s->sdbus)); 983 ret = FIELD_DP32(ret, SDHC_PRNSTS, CMD_LVL, 984 sdbus_get_cmd_line(&s->sdbus)); 985 break; 986 case SDHC_HOSTCTL: 987 ret = s->hostctl1 | (s->pwrcon << 8) | (s->blkgap << 16) | 988 (s->wakcon << 24); 989 break; 990 case SDHC_CLKCON: 991 ret = s->clkcon | (s->timeoutcon << 16); 992 break; 993 case SDHC_NORINTSTS: 994 ret = s->norintsts | (s->errintsts << 16); 995 break; 996 case SDHC_NORINTSTSEN: 997 ret = s->norintstsen | (s->errintstsen << 16); 998 break; 999 case SDHC_NORINTSIGEN: 1000 ret = s->norintsigen | (s->errintsigen << 16); 1001 break; 1002 case SDHC_ACMD12ERRSTS: 1003 ret = s->acmd12errsts | (s->hostctl2 << 16); 1004 break; 1005 case SDHC_CAPAB: 1006 ret = (uint32_t)s->capareg; 1007 break; 1008 case SDHC_CAPAB + 4: 1009 ret = (uint32_t)(s->capareg >> 32); 1010 break; 1011 case SDHC_MAXCURR: 1012 ret = (uint32_t)s->maxcurr; 1013 break; 1014 case SDHC_MAXCURR + 4: 1015 ret = (uint32_t)(s->maxcurr >> 32); 1016 break; 1017 case SDHC_ADMAERR: 1018 ret = s->admaerr; 1019 break; 1020 case SDHC_ADMASYSADDR: 1021 ret = (uint32_t)s->admasysaddr; 1022 break; 1023 case SDHC_ADMASYSADDR + 4: 1024 ret = (uint32_t)(s->admasysaddr >> 32); 1025 break; 1026 case SDHC_SLOT_INT_STATUS: 1027 ret = (s->version << 16) | sdhci_slotint(s); 1028 break; 1029 default: 1030 qemu_log_mask(LOG_UNIMP, "SDHC rd_%ub @0x%02" HWADDR_PRIx " " 1031 "not implemented\n", size, offset); 1032 break; 1033 } 1034 1035 ret >>= (offset & 0x3) * 8; 1036 ret &= (1ULL << (size * 8)) - 1; 1037 trace_sdhci_access("rd", size << 3, offset, "->", ret, ret); 1038 return ret; 1039 } 1040 1041 static inline void sdhci_blkgap_write(SDHCIState *s, uint8_t value) 1042 { 1043 if ((value & SDHC_STOP_AT_GAP_REQ) && (s->blkgap & SDHC_STOP_AT_GAP_REQ)) { 1044 return; 1045 } 1046 s->blkgap = value & SDHC_STOP_AT_GAP_REQ; 1047 1048 if ((value & SDHC_CONTINUE_REQ) && s->stopped_state && 1049 (s->blkgap & SDHC_STOP_AT_GAP_REQ) == 0) { 1050 if (s->stopped_state == sdhc_gap_read) { 1051 s->prnsts |= SDHC_DAT_LINE_ACTIVE | SDHC_DOING_READ; 1052 sdhci_read_block_from_card(s); 1053 } else { 1054 s->prnsts |= SDHC_DAT_LINE_ACTIVE | SDHC_DOING_WRITE; 1055 sdhci_write_block_to_card(s); 1056 } 1057 s->stopped_state = sdhc_not_stopped; 1058 } else if (!s->stopped_state && (value & SDHC_STOP_AT_GAP_REQ)) { 1059 if (s->prnsts & SDHC_DOING_READ) { 1060 s->stopped_state = sdhc_gap_read; 1061 } else if (s->prnsts & SDHC_DOING_WRITE) { 1062 s->stopped_state = sdhc_gap_write; 1063 } 1064 } 1065 } 1066 1067 static inline void sdhci_reset_write(SDHCIState *s, uint8_t value) 1068 { 1069 switch (value) { 1070 case SDHC_RESET_ALL: 1071 sdhci_reset(s); 1072 break; 1073 case SDHC_RESET_CMD: 1074 s->prnsts &= ~SDHC_CMD_INHIBIT; 1075 s->norintsts &= ~SDHC_NIS_CMDCMP; 1076 break; 1077 case SDHC_RESET_DATA: 1078 s->data_count = 0; 1079 s->prnsts &= ~(SDHC_SPACE_AVAILABLE | SDHC_DATA_AVAILABLE | 1080 SDHC_DOING_READ | SDHC_DOING_WRITE | 1081 SDHC_DATA_INHIBIT | SDHC_DAT_LINE_ACTIVE); 1082 s->blkgap &= ~(SDHC_STOP_AT_GAP_REQ | SDHC_CONTINUE_REQ); 1083 s->stopped_state = sdhc_not_stopped; 1084 s->norintsts &= ~(SDHC_NIS_WBUFRDY | SDHC_NIS_RBUFRDY | 1085 SDHC_NIS_DMA | SDHC_NIS_TRSCMP | SDHC_NIS_BLKGAP); 1086 break; 1087 } 1088 } 1089 1090 static void 1091 sdhci_write(void *opaque, hwaddr offset, uint64_t val, unsigned size) 1092 { 1093 SDHCIState *s = (SDHCIState *)opaque; 1094 unsigned shift = 8 * (offset & 0x3); 1095 uint32_t mask = ~(((1ULL << (size * 8)) - 1) << shift); 1096 uint32_t value = val; 1097 value <<= shift; 1098 1099 switch (offset & ~0x3) { 1100 case SDHC_SYSAD: 1101 s->sdmasysad = (s->sdmasysad & mask) | value; 1102 MASKED_WRITE(s->sdmasysad, mask, value); 1103 /* Writing to last byte of sdmasysad might trigger transfer */ 1104 if (!(mask & 0xFF000000) && TRANSFERRING_DATA(s->prnsts) && s->blkcnt && 1105 s->blksize && SDHC_DMA_TYPE(s->hostctl1) == SDHC_CTRL_SDMA) { 1106 if (s->trnmod & SDHC_TRNS_MULTI) { 1107 sdhci_sdma_transfer_multi_blocks(s); 1108 } else { 1109 sdhci_sdma_transfer_single_block(s); 1110 } 1111 } 1112 break; 1113 case SDHC_BLKSIZE: 1114 if (!TRANSFERRING_DATA(s->prnsts)) { 1115 MASKED_WRITE(s->blksize, mask, extract32(value, 0, 12)); 1116 MASKED_WRITE(s->blkcnt, mask >> 16, value >> 16); 1117 } 1118 1119 /* Limit block size to the maximum buffer size */ 1120 if (extract32(s->blksize, 0, 12) > s->buf_maxsz) { 1121 qemu_log_mask(LOG_GUEST_ERROR, "%s: Size 0x%x is larger than " 1122 "the maximum buffer 0x%x\n", __func__, s->blksize, 1123 s->buf_maxsz); 1124 1125 s->blksize = deposit32(s->blksize, 0, 12, s->buf_maxsz); 1126 } 1127 1128 break; 1129 case SDHC_ARGUMENT: 1130 MASKED_WRITE(s->argument, mask, value); 1131 break; 1132 case SDHC_TRNMOD: 1133 /* DMA can be enabled only if it is supported as indicated by 1134 * capabilities register */ 1135 if (!(s->capareg & R_SDHC_CAPAB_SDMA_MASK)) { 1136 value &= ~SDHC_TRNS_DMA; 1137 } 1138 MASKED_WRITE(s->trnmod, mask, value & SDHC_TRNMOD_MASK); 1139 MASKED_WRITE(s->cmdreg, mask >> 16, value >> 16); 1140 1141 /* Writing to the upper byte of CMDREG triggers SD command generation */ 1142 if ((mask & 0xFF000000) || !sdhci_can_issue_command(s)) { 1143 break; 1144 } 1145 1146 sdhci_send_command(s); 1147 break; 1148 case SDHC_BDATA: 1149 if (sdhci_buff_access_is_sequential(s, offset - SDHC_BDATA)) { 1150 sdhci_write_dataport(s, value >> shift, size); 1151 } 1152 break; 1153 case SDHC_HOSTCTL: 1154 if (!(mask & 0xFF0000)) { 1155 sdhci_blkgap_write(s, value >> 16); 1156 } 1157 MASKED_WRITE(s->hostctl1, mask, value); 1158 MASKED_WRITE(s->pwrcon, mask >> 8, value >> 8); 1159 MASKED_WRITE(s->wakcon, mask >> 24, value >> 24); 1160 if (!(s->prnsts & SDHC_CARD_PRESENT) || ((s->pwrcon >> 1) & 0x7) < 5 || 1161 !(s->capareg & (1 << (31 - ((s->pwrcon >> 1) & 0x7))))) { 1162 s->pwrcon &= ~SDHC_POWER_ON; 1163 } 1164 break; 1165 case SDHC_CLKCON: 1166 if (!(mask & 0xFF000000)) { 1167 sdhci_reset_write(s, value >> 24); 1168 } 1169 MASKED_WRITE(s->clkcon, mask, value); 1170 MASKED_WRITE(s->timeoutcon, mask >> 16, value >> 16); 1171 if (s->clkcon & SDHC_CLOCK_INT_EN) { 1172 s->clkcon |= SDHC_CLOCK_INT_STABLE; 1173 } else { 1174 s->clkcon &= ~SDHC_CLOCK_INT_STABLE; 1175 } 1176 break; 1177 case SDHC_NORINTSTS: 1178 if (s->norintstsen & SDHC_NISEN_CARDINT) { 1179 value &= ~SDHC_NIS_CARDINT; 1180 } 1181 s->norintsts &= mask | ~value; 1182 s->errintsts &= (mask >> 16) | ~(value >> 16); 1183 if (s->errintsts) { 1184 s->norintsts |= SDHC_NIS_ERR; 1185 } else { 1186 s->norintsts &= ~SDHC_NIS_ERR; 1187 } 1188 sdhci_update_irq(s); 1189 break; 1190 case SDHC_NORINTSTSEN: 1191 MASKED_WRITE(s->norintstsen, mask, value); 1192 MASKED_WRITE(s->errintstsen, mask >> 16, value >> 16); 1193 s->norintsts &= s->norintstsen; 1194 s->errintsts &= s->errintstsen; 1195 if (s->errintsts) { 1196 s->norintsts |= SDHC_NIS_ERR; 1197 } else { 1198 s->norintsts &= ~SDHC_NIS_ERR; 1199 } 1200 /* Quirk for Raspberry Pi: pending card insert interrupt 1201 * appears when first enabled after power on */ 1202 if ((s->norintstsen & SDHC_NISEN_INSERT) && s->pending_insert_state) { 1203 assert(s->pending_insert_quirk); 1204 s->norintsts |= SDHC_NIS_INSERT; 1205 s->pending_insert_state = false; 1206 } 1207 sdhci_update_irq(s); 1208 break; 1209 case SDHC_NORINTSIGEN: 1210 MASKED_WRITE(s->norintsigen, mask, value); 1211 MASKED_WRITE(s->errintsigen, mask >> 16, value >> 16); 1212 sdhci_update_irq(s); 1213 break; 1214 case SDHC_ADMAERR: 1215 MASKED_WRITE(s->admaerr, mask, value); 1216 break; 1217 case SDHC_ADMASYSADDR: 1218 s->admasysaddr = (s->admasysaddr & (0xFFFFFFFF00000000ULL | 1219 (uint64_t)mask)) | (uint64_t)value; 1220 break; 1221 case SDHC_ADMASYSADDR + 4: 1222 s->admasysaddr = (s->admasysaddr & (0x00000000FFFFFFFFULL | 1223 ((uint64_t)mask << 32))) | ((uint64_t)value << 32); 1224 break; 1225 case SDHC_FEAER: 1226 s->acmd12errsts |= value; 1227 s->errintsts |= (value >> 16) & s->errintstsen; 1228 if (s->acmd12errsts) { 1229 s->errintsts |= SDHC_EIS_CMD12ERR; 1230 } 1231 if (s->errintsts) { 1232 s->norintsts |= SDHC_NIS_ERR; 1233 } 1234 sdhci_update_irq(s); 1235 break; 1236 case SDHC_ACMD12ERRSTS: 1237 MASKED_WRITE(s->acmd12errsts, mask, value & UINT16_MAX); 1238 if (s->uhs_mode >= UHS_I) { 1239 MASKED_WRITE(s->hostctl2, mask >> 16, value >> 16); 1240 1241 if (FIELD_EX32(s->hostctl2, SDHC_HOSTCTL2, V18_ENA)) { 1242 sdbus_set_voltage(&s->sdbus, SD_VOLTAGE_1_8V); 1243 } else { 1244 sdbus_set_voltage(&s->sdbus, SD_VOLTAGE_3_3V); 1245 } 1246 } 1247 break; 1248 1249 case SDHC_CAPAB: 1250 case SDHC_CAPAB + 4: 1251 case SDHC_MAXCURR: 1252 case SDHC_MAXCURR + 4: 1253 qemu_log_mask(LOG_GUEST_ERROR, "SDHC wr_%ub @0x%02" HWADDR_PRIx 1254 " <- 0x%08x read-only\n", size, offset, value >> shift); 1255 break; 1256 1257 default: 1258 qemu_log_mask(LOG_UNIMP, "SDHC wr_%ub @0x%02" HWADDR_PRIx " <- 0x%08x " 1259 "not implemented\n", size, offset, value >> shift); 1260 break; 1261 } 1262 trace_sdhci_access("wr", size << 3, offset, "<-", 1263 value >> shift, value >> shift); 1264 } 1265 1266 static const MemoryRegionOps sdhci_mmio_ops = { 1267 .read = sdhci_read, 1268 .write = sdhci_write, 1269 .valid = { 1270 .min_access_size = 1, 1271 .max_access_size = 4, 1272 .unaligned = false 1273 }, 1274 .endianness = DEVICE_LITTLE_ENDIAN, 1275 }; 1276 1277 static void sdhci_init_readonly_registers(SDHCIState *s, Error **errp) 1278 { 1279 ERRP_GUARD(); 1280 1281 switch (s->sd_spec_version) { 1282 case 2 ... 3: 1283 break; 1284 default: 1285 error_setg(errp, "Only Spec v2/v3 are supported"); 1286 return; 1287 } 1288 s->version = (SDHC_HCVER_VENDOR << 8) | (s->sd_spec_version - 1); 1289 1290 sdhci_check_capareg(s, errp); 1291 if (*errp) { 1292 return; 1293 } 1294 } 1295 1296 /* --- qdev common --- */ 1297 1298 void sdhci_initfn(SDHCIState *s) 1299 { 1300 qbus_create_inplace(&s->sdbus, sizeof(s->sdbus), 1301 TYPE_SDHCI_BUS, DEVICE(s), "sd-bus"); 1302 1303 s->insert_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, sdhci_raise_insertion_irq, s); 1304 s->transfer_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, sdhci_data_transfer, s); 1305 1306 s->io_ops = &sdhci_mmio_ops; 1307 } 1308 1309 void sdhci_uninitfn(SDHCIState *s) 1310 { 1311 timer_del(s->insert_timer); 1312 timer_free(s->insert_timer); 1313 timer_del(s->transfer_timer); 1314 timer_free(s->transfer_timer); 1315 1316 g_free(s->fifo_buffer); 1317 s->fifo_buffer = NULL; 1318 } 1319 1320 void sdhci_common_realize(SDHCIState *s, Error **errp) 1321 { 1322 ERRP_GUARD(); 1323 1324 sdhci_init_readonly_registers(s, errp); 1325 if (*errp) { 1326 return; 1327 } 1328 s->buf_maxsz = sdhci_get_fifolen(s); 1329 s->fifo_buffer = g_malloc0(s->buf_maxsz); 1330 1331 memory_region_init_io(&s->iomem, OBJECT(s), s->io_ops, s, "sdhci", 1332 SDHC_REGISTERS_MAP_SIZE); 1333 } 1334 1335 void sdhci_common_unrealize(SDHCIState *s) 1336 { 1337 /* This function is expected to be called only once for each class: 1338 * - SysBus: via DeviceClass->unrealize(), 1339 * - PCI: via PCIDeviceClass->exit(). 1340 * However to avoid double-free and/or use-after-free we still nullify 1341 * this variable (better safe than sorry!). */ 1342 g_free(s->fifo_buffer); 1343 s->fifo_buffer = NULL; 1344 } 1345 1346 static bool sdhci_pending_insert_vmstate_needed(void *opaque) 1347 { 1348 SDHCIState *s = opaque; 1349 1350 return s->pending_insert_state; 1351 } 1352 1353 static const VMStateDescription sdhci_pending_insert_vmstate = { 1354 .name = "sdhci/pending-insert", 1355 .version_id = 1, 1356 .minimum_version_id = 1, 1357 .needed = sdhci_pending_insert_vmstate_needed, 1358 .fields = (VMStateField[]) { 1359 VMSTATE_BOOL(pending_insert_state, SDHCIState), 1360 VMSTATE_END_OF_LIST() 1361 }, 1362 }; 1363 1364 const VMStateDescription sdhci_vmstate = { 1365 .name = "sdhci", 1366 .version_id = 1, 1367 .minimum_version_id = 1, 1368 .fields = (VMStateField[]) { 1369 VMSTATE_UINT32(sdmasysad, SDHCIState), 1370 VMSTATE_UINT16(blksize, SDHCIState), 1371 VMSTATE_UINT16(blkcnt, SDHCIState), 1372 VMSTATE_UINT32(argument, SDHCIState), 1373 VMSTATE_UINT16(trnmod, SDHCIState), 1374 VMSTATE_UINT16(cmdreg, SDHCIState), 1375 VMSTATE_UINT32_ARRAY(rspreg, SDHCIState, 4), 1376 VMSTATE_UINT32(prnsts, SDHCIState), 1377 VMSTATE_UINT8(hostctl1, SDHCIState), 1378 VMSTATE_UINT8(pwrcon, SDHCIState), 1379 VMSTATE_UINT8(blkgap, SDHCIState), 1380 VMSTATE_UINT8(wakcon, SDHCIState), 1381 VMSTATE_UINT16(clkcon, SDHCIState), 1382 VMSTATE_UINT8(timeoutcon, SDHCIState), 1383 VMSTATE_UINT8(admaerr, SDHCIState), 1384 VMSTATE_UINT16(norintsts, SDHCIState), 1385 VMSTATE_UINT16(errintsts, SDHCIState), 1386 VMSTATE_UINT16(norintstsen, SDHCIState), 1387 VMSTATE_UINT16(errintstsen, SDHCIState), 1388 VMSTATE_UINT16(norintsigen, SDHCIState), 1389 VMSTATE_UINT16(errintsigen, SDHCIState), 1390 VMSTATE_UINT16(acmd12errsts, SDHCIState), 1391 VMSTATE_UINT16(data_count, SDHCIState), 1392 VMSTATE_UINT64(admasysaddr, SDHCIState), 1393 VMSTATE_UINT8(stopped_state, SDHCIState), 1394 VMSTATE_VBUFFER_UINT32(fifo_buffer, SDHCIState, 1, NULL, buf_maxsz), 1395 VMSTATE_TIMER_PTR(insert_timer, SDHCIState), 1396 VMSTATE_TIMER_PTR(transfer_timer, SDHCIState), 1397 VMSTATE_END_OF_LIST() 1398 }, 1399 .subsections = (const VMStateDescription*[]) { 1400 &sdhci_pending_insert_vmstate, 1401 NULL 1402 }, 1403 }; 1404 1405 void sdhci_common_class_init(ObjectClass *klass, void *data) 1406 { 1407 DeviceClass *dc = DEVICE_CLASS(klass); 1408 1409 set_bit(DEVICE_CATEGORY_STORAGE, dc->categories); 1410 dc->vmsd = &sdhci_vmstate; 1411 dc->reset = sdhci_poweron_reset; 1412 } 1413 1414 /* --- qdev SysBus --- */ 1415 1416 static Property sdhci_sysbus_properties[] = { 1417 DEFINE_SDHCI_COMMON_PROPERTIES(SDHCIState), 1418 DEFINE_PROP_BOOL("pending-insert-quirk", SDHCIState, pending_insert_quirk, 1419 false), 1420 DEFINE_PROP_LINK("dma", SDHCIState, 1421 dma_mr, TYPE_MEMORY_REGION, MemoryRegion *), 1422 DEFINE_PROP_END_OF_LIST(), 1423 }; 1424 1425 static void sdhci_sysbus_init(Object *obj) 1426 { 1427 SDHCIState *s = SYSBUS_SDHCI(obj); 1428 1429 sdhci_initfn(s); 1430 } 1431 1432 static void sdhci_sysbus_finalize(Object *obj) 1433 { 1434 SDHCIState *s = SYSBUS_SDHCI(obj); 1435 1436 if (s->dma_mr) { 1437 object_unparent(OBJECT(s->dma_mr)); 1438 } 1439 1440 sdhci_uninitfn(s); 1441 } 1442 1443 static void sdhci_sysbus_realize(DeviceState *dev, Error **errp) 1444 { 1445 ERRP_GUARD(); 1446 SDHCIState *s = SYSBUS_SDHCI(dev); 1447 SysBusDevice *sbd = SYS_BUS_DEVICE(dev); 1448 1449 sdhci_common_realize(s, errp); 1450 if (*errp) { 1451 return; 1452 } 1453 1454 if (s->dma_mr) { 1455 s->dma_as = &s->sysbus_dma_as; 1456 address_space_init(s->dma_as, s->dma_mr, "sdhci-dma"); 1457 } else { 1458 /* use system_memory() if property "dma" not set */ 1459 s->dma_as = &address_space_memory; 1460 } 1461 1462 sysbus_init_irq(sbd, &s->irq); 1463 1464 sysbus_init_mmio(sbd, &s->iomem); 1465 } 1466 1467 static void sdhci_sysbus_unrealize(DeviceState *dev) 1468 { 1469 SDHCIState *s = SYSBUS_SDHCI(dev); 1470 1471 sdhci_common_unrealize(s); 1472 1473 if (s->dma_mr) { 1474 address_space_destroy(s->dma_as); 1475 } 1476 } 1477 1478 static void sdhci_sysbus_class_init(ObjectClass *klass, void *data) 1479 { 1480 DeviceClass *dc = DEVICE_CLASS(klass); 1481 1482 device_class_set_props(dc, sdhci_sysbus_properties); 1483 dc->realize = sdhci_sysbus_realize; 1484 dc->unrealize = sdhci_sysbus_unrealize; 1485 1486 sdhci_common_class_init(klass, data); 1487 } 1488 1489 static const TypeInfo sdhci_sysbus_info = { 1490 .name = TYPE_SYSBUS_SDHCI, 1491 .parent = TYPE_SYS_BUS_DEVICE, 1492 .instance_size = sizeof(SDHCIState), 1493 .instance_init = sdhci_sysbus_init, 1494 .instance_finalize = sdhci_sysbus_finalize, 1495 .class_init = sdhci_sysbus_class_init, 1496 }; 1497 1498 /* --- qdev bus master --- */ 1499 1500 static void sdhci_bus_class_init(ObjectClass *klass, void *data) 1501 { 1502 SDBusClass *sbc = SD_BUS_CLASS(klass); 1503 1504 sbc->set_inserted = sdhci_set_inserted; 1505 sbc->set_readonly = sdhci_set_readonly; 1506 } 1507 1508 static const TypeInfo sdhci_bus_info = { 1509 .name = TYPE_SDHCI_BUS, 1510 .parent = TYPE_SD_BUS, 1511 .instance_size = sizeof(SDBus), 1512 .class_init = sdhci_bus_class_init, 1513 }; 1514 1515 /* --- qdev i.MX eSDHC --- */ 1516 1517 static uint64_t usdhc_read(void *opaque, hwaddr offset, unsigned size) 1518 { 1519 SDHCIState *s = SYSBUS_SDHCI(opaque); 1520 uint32_t ret; 1521 uint16_t hostctl1; 1522 1523 switch (offset) { 1524 default: 1525 return sdhci_read(opaque, offset, size); 1526 1527 case SDHC_HOSTCTL: 1528 /* 1529 * For a detailed explanation on the following bit 1530 * manipulation code see comments in a similar part of 1531 * usdhc_write() 1532 */ 1533 hostctl1 = SDHC_DMA_TYPE(s->hostctl1) << (8 - 3); 1534 1535 if (s->hostctl1 & SDHC_CTRL_8BITBUS) { 1536 hostctl1 |= ESDHC_CTRL_8BITBUS; 1537 } 1538 1539 if (s->hostctl1 & SDHC_CTRL_4BITBUS) { 1540 hostctl1 |= ESDHC_CTRL_4BITBUS; 1541 } 1542 1543 ret = hostctl1; 1544 ret |= (uint32_t)s->blkgap << 16; 1545 ret |= (uint32_t)s->wakcon << 24; 1546 1547 break; 1548 1549 case SDHC_PRNSTS: 1550 /* Add SDSTB (SD Clock Stable) bit to PRNSTS */ 1551 ret = sdhci_read(opaque, offset, size) & ~ESDHC_PRNSTS_SDSTB; 1552 if (s->clkcon & SDHC_CLOCK_INT_STABLE) { 1553 ret |= ESDHC_PRNSTS_SDSTB; 1554 } 1555 break; 1556 1557 case ESDHC_VENDOR_SPEC: 1558 ret = s->vendor_spec; 1559 break; 1560 case ESDHC_DLL_CTRL: 1561 case ESDHC_TUNE_CTRL_STATUS: 1562 case ESDHC_UNDOCUMENTED_REG27: 1563 case ESDHC_TUNING_CTRL: 1564 case ESDHC_MIX_CTRL: 1565 case ESDHC_WTMK_LVL: 1566 ret = 0; 1567 break; 1568 } 1569 1570 return ret; 1571 } 1572 1573 static void 1574 usdhc_write(void *opaque, hwaddr offset, uint64_t val, unsigned size) 1575 { 1576 SDHCIState *s = SYSBUS_SDHCI(opaque); 1577 uint8_t hostctl1; 1578 uint32_t value = (uint32_t)val; 1579 1580 switch (offset) { 1581 case ESDHC_DLL_CTRL: 1582 case ESDHC_TUNE_CTRL_STATUS: 1583 case ESDHC_UNDOCUMENTED_REG27: 1584 case ESDHC_TUNING_CTRL: 1585 case ESDHC_WTMK_LVL: 1586 break; 1587 1588 case ESDHC_VENDOR_SPEC: 1589 s->vendor_spec = value; 1590 switch (s->vendor) { 1591 case SDHCI_VENDOR_IMX: 1592 if (value & ESDHC_IMX_FRC_SDCLK_ON) { 1593 s->prnsts &= ~SDHC_IMX_CLOCK_GATE_OFF; 1594 } else { 1595 s->prnsts |= SDHC_IMX_CLOCK_GATE_OFF; 1596 } 1597 break; 1598 default: 1599 break; 1600 } 1601 break; 1602 1603 case SDHC_HOSTCTL: 1604 /* 1605 * Here's What ESDHCI has at offset 0x28 (SDHC_HOSTCTL) 1606 * 1607 * 7 6 5 4 3 2 1 0 1608 * |-----------+--------+--------+-----------+----------+---------| 1609 * | Card | Card | Endian | DATA3 | Data | Led | 1610 * | Detect | Detect | Mode | as Card | Transfer | Control | 1611 * | Signal | Test | | Detection | Width | | 1612 * | Selection | Level | | Pin | | | 1613 * |-----------+--------+--------+-----------+----------+---------| 1614 * 1615 * and 0x29 1616 * 1617 * 15 10 9 8 1618 * |----------+------| 1619 * | Reserved | DMA | 1620 * | | Sel. | 1621 * | | | 1622 * |----------+------| 1623 * 1624 * and here's what SDCHI spec expects those offsets to be: 1625 * 1626 * 0x28 (Host Control Register) 1627 * 1628 * 7 6 5 4 3 2 1 0 1629 * |--------+--------+----------+------+--------+----------+---------| 1630 * | Card | Card | Extended | DMA | High | Data | LED | 1631 * | Detect | Detect | Data | Sel. | Speed | Transfer | Control | 1632 * | Signal | Test | Transfer | | Enable | Width | | 1633 * | Sel. | Level | Width | | | | | 1634 * |--------+--------+----------+------+--------+----------+---------| 1635 * 1636 * and 0x29 (Power Control Register) 1637 * 1638 * |----------------------------------| 1639 * | Power Control Register | 1640 * | | 1641 * | Description omitted, | 1642 * | since it has no analog in ESDHCI | 1643 * | | 1644 * |----------------------------------| 1645 * 1646 * Since offsets 0x2A and 0x2B should be compatible between 1647 * both IP specs we only need to reconcile least 16-bit of the 1648 * word we've been given. 1649 */ 1650 1651 /* 1652 * First, save bits 7 6 and 0 since they are identical 1653 */ 1654 hostctl1 = value & (SDHC_CTRL_LED | 1655 SDHC_CTRL_CDTEST_INS | 1656 SDHC_CTRL_CDTEST_EN); 1657 /* 1658 * Second, split "Data Transfer Width" from bits 2 and 1 in to 1659 * bits 5 and 1 1660 */ 1661 if (value & ESDHC_CTRL_8BITBUS) { 1662 hostctl1 |= SDHC_CTRL_8BITBUS; 1663 } 1664 1665 if (value & ESDHC_CTRL_4BITBUS) { 1666 hostctl1 |= ESDHC_CTRL_4BITBUS; 1667 } 1668 1669 /* 1670 * Third, move DMA select from bits 9 and 8 to bits 4 and 3 1671 */ 1672 hostctl1 |= SDHC_DMA_TYPE(value >> (8 - 3)); 1673 1674 /* 1675 * Now place the corrected value into low 16-bit of the value 1676 * we are going to give standard SDHCI write function 1677 * 1678 * NOTE: This transformation should be the inverse of what can 1679 * be found in drivers/mmc/host/sdhci-esdhc-imx.c in Linux 1680 * kernel 1681 */ 1682 value &= ~UINT16_MAX; 1683 value |= hostctl1; 1684 value |= (uint16_t)s->pwrcon << 8; 1685 1686 sdhci_write(opaque, offset, value, size); 1687 break; 1688 1689 case ESDHC_MIX_CTRL: 1690 /* 1691 * So, when SD/MMC stack in Linux tries to write to "Transfer 1692 * Mode Register", ESDHC i.MX quirk code will translate it 1693 * into a write to ESDHC_MIX_CTRL, so we do the opposite in 1694 * order to get where we started 1695 * 1696 * Note that Auto CMD23 Enable bit is located in a wrong place 1697 * on i.MX, but since it is not used by QEMU we do not care. 1698 * 1699 * We don't want to call sdhci_write(.., SDHC_TRNMOD, ...) 1700 * here becuase it will result in a call to 1701 * sdhci_send_command(s) which we don't want. 1702 * 1703 */ 1704 s->trnmod = value & UINT16_MAX; 1705 break; 1706 case SDHC_TRNMOD: 1707 /* 1708 * Similar to above, but this time a write to "Command 1709 * Register" will be translated into a 4-byte write to 1710 * "Transfer Mode register" where lower 16-bit of value would 1711 * be set to zero. So what we do is fill those bits with 1712 * cached value from s->trnmod and let the SDHCI 1713 * infrastructure handle the rest 1714 */ 1715 sdhci_write(opaque, offset, val | s->trnmod, size); 1716 break; 1717 case SDHC_BLKSIZE: 1718 /* 1719 * ESDHCI does not implement "Host SDMA Buffer Boundary", and 1720 * Linux driver will try to zero this field out which will 1721 * break the rest of SDHCI emulation. 1722 * 1723 * Linux defaults to maximum possible setting (512K boundary) 1724 * and it seems to be the only option that i.MX IP implements, 1725 * so we artificially set it to that value. 1726 */ 1727 val |= 0x7 << 12; 1728 /* FALLTHROUGH */ 1729 default: 1730 sdhci_write(opaque, offset, val, size); 1731 break; 1732 } 1733 } 1734 1735 static const MemoryRegionOps usdhc_mmio_ops = { 1736 .read = usdhc_read, 1737 .write = usdhc_write, 1738 .valid = { 1739 .min_access_size = 1, 1740 .max_access_size = 4, 1741 .unaligned = false 1742 }, 1743 .endianness = DEVICE_LITTLE_ENDIAN, 1744 }; 1745 1746 static void imx_usdhc_init(Object *obj) 1747 { 1748 SDHCIState *s = SYSBUS_SDHCI(obj); 1749 1750 s->io_ops = &usdhc_mmio_ops; 1751 s->quirks = SDHCI_QUIRK_NO_BUSY_IRQ; 1752 } 1753 1754 static const TypeInfo imx_usdhc_info = { 1755 .name = TYPE_IMX_USDHC, 1756 .parent = TYPE_SYSBUS_SDHCI, 1757 .instance_init = imx_usdhc_init, 1758 }; 1759 1760 /* --- qdev Samsung s3c --- */ 1761 1762 #define S3C_SDHCI_CONTROL2 0x80 1763 #define S3C_SDHCI_CONTROL3 0x84 1764 #define S3C_SDHCI_CONTROL4 0x8c 1765 1766 static uint64_t sdhci_s3c_read(void *opaque, hwaddr offset, unsigned size) 1767 { 1768 uint64_t ret; 1769 1770 switch (offset) { 1771 case S3C_SDHCI_CONTROL2: 1772 case S3C_SDHCI_CONTROL3: 1773 case S3C_SDHCI_CONTROL4: 1774 /* ignore */ 1775 ret = 0; 1776 break; 1777 default: 1778 ret = sdhci_read(opaque, offset, size); 1779 break; 1780 } 1781 1782 return ret; 1783 } 1784 1785 static void sdhci_s3c_write(void *opaque, hwaddr offset, uint64_t val, 1786 unsigned size) 1787 { 1788 switch (offset) { 1789 case S3C_SDHCI_CONTROL2: 1790 case S3C_SDHCI_CONTROL3: 1791 case S3C_SDHCI_CONTROL4: 1792 /* ignore */ 1793 break; 1794 default: 1795 sdhci_write(opaque, offset, val, size); 1796 break; 1797 } 1798 } 1799 1800 static const MemoryRegionOps sdhci_s3c_mmio_ops = { 1801 .read = sdhci_s3c_read, 1802 .write = sdhci_s3c_write, 1803 .valid = { 1804 .min_access_size = 1, 1805 .max_access_size = 4, 1806 .unaligned = false 1807 }, 1808 .endianness = DEVICE_LITTLE_ENDIAN, 1809 }; 1810 1811 static void sdhci_s3c_init(Object *obj) 1812 { 1813 SDHCIState *s = SYSBUS_SDHCI(obj); 1814 1815 s->io_ops = &sdhci_s3c_mmio_ops; 1816 } 1817 1818 static const TypeInfo sdhci_s3c_info = { 1819 .name = TYPE_S3C_SDHCI , 1820 .parent = TYPE_SYSBUS_SDHCI, 1821 .instance_init = sdhci_s3c_init, 1822 }; 1823 1824 static void sdhci_register_types(void) 1825 { 1826 type_register_static(&sdhci_sysbus_info); 1827 type_register_static(&sdhci_bus_info); 1828 type_register_static(&imx_usdhc_info); 1829 type_register_static(&sdhci_s3c_info); 1830 } 1831 1832 type_init(sdhci_register_types) 1833