1 /* 2 * SD Association Host Standard Specification v2.0 controller emulation 3 * 4 * Datasheet: PartA2_SD_Host_Controller_Simplified_Specification_Ver2.00.pdf 5 * 6 * Copyright (c) 2011 Samsung Electronics Co., Ltd. 7 * Mitsyanko Igor <i.mitsyanko@samsung.com> 8 * Peter A.G. Crosthwaite <peter.crosthwaite@petalogix.com> 9 * 10 * Based on MMC controller for Samsung S5PC1xx-based board emulation 11 * by Alexey Merkulov and Vladimir Monakhov. 12 * 13 * This program is free software; you can redistribute it and/or modify it 14 * under the terms of the GNU General Public License as published by the 15 * Free Software Foundation; either version 2 of the License, or (at your 16 * option) any later version. 17 * 18 * This program is distributed in the hope that it will be useful, 19 * but WITHOUT ANY WARRANTY; without even the implied warranty of 20 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. 21 * See the GNU General Public License for more details. 22 * 23 * You should have received a copy of the GNU General Public License along 24 * with this program; if not, see <http://www.gnu.org/licenses/>. 25 */ 26 27 #include "qemu/osdep.h" 28 #include "qemu/units.h" 29 #include "qemu/error-report.h" 30 #include "qapi/error.h" 31 #include "hw/irq.h" 32 #include "hw/qdev-properties.h" 33 #include "system/dma.h" 34 #include "qemu/timer.h" 35 #include "qemu/bitops.h" 36 #include "hw/sd/sdhci.h" 37 #include "migration/vmstate.h" 38 #include "sdhci-internal.h" 39 #include "qemu/log.h" 40 #include "trace.h" 41 #include "qom/object.h" 42 43 #define TYPE_SDHCI_BUS "sdhci-bus" 44 /* This is reusing the SDBus typedef from SD_BUS */ 45 DECLARE_INSTANCE_CHECKER(SDBus, SDHCI_BUS, 46 TYPE_SDHCI_BUS) 47 48 #define MASKED_WRITE(reg, mask, val) (reg = (reg & (mask)) | (val)) 49 50 static inline unsigned int sdhci_get_fifolen(SDHCIState *s) 51 { 52 return 1 << (9 + FIELD_EX32(s->capareg, SDHC_CAPAB, MAXBLOCKLENGTH)); 53 } 54 55 /* return true on error */ 56 static bool sdhci_check_capab_freq_range(SDHCIState *s, const char *desc, 57 uint8_t freq, Error **errp) 58 { 59 if (s->sd_spec_version >= 3) { 60 return false; 61 } 62 switch (freq) { 63 case 0: 64 case 10 ... 63: 65 break; 66 default: 67 error_setg(errp, "SD %s clock frequency can have value" 68 "in range 0-63 only", desc); 69 return true; 70 } 71 return false; 72 } 73 74 static void sdhci_check_capareg(SDHCIState *s, Error **errp) 75 { 76 uint64_t msk = s->capareg; 77 uint32_t val; 78 bool y; 79 80 switch (s->sd_spec_version) { 81 case 4: 82 val = FIELD_EX64(s->capareg, SDHC_CAPAB, BUS64BIT_V4); 83 trace_sdhci_capareg("64-bit system bus (v4)", val); 84 msk = FIELD_DP64(msk, SDHC_CAPAB, BUS64BIT_V4, 0); 85 86 val = FIELD_EX64(s->capareg, SDHC_CAPAB, UHS_II); 87 trace_sdhci_capareg("UHS-II", val); 88 msk = FIELD_DP64(msk, SDHC_CAPAB, UHS_II, 0); 89 90 val = FIELD_EX64(s->capareg, SDHC_CAPAB, ADMA3); 91 trace_sdhci_capareg("ADMA3", val); 92 msk = FIELD_DP64(msk, SDHC_CAPAB, ADMA3, 0); 93 94 /* fallthrough */ 95 case 3: 96 val = FIELD_EX64(s->capareg, SDHC_CAPAB, ASYNC_INT); 97 trace_sdhci_capareg("async interrupt", val); 98 msk = FIELD_DP64(msk, SDHC_CAPAB, ASYNC_INT, 0); 99 100 val = FIELD_EX64(s->capareg, SDHC_CAPAB, SLOT_TYPE); 101 if (val) { 102 error_setg(errp, "slot-type not supported"); 103 return; 104 } 105 trace_sdhci_capareg("slot type", val); 106 msk = FIELD_DP64(msk, SDHC_CAPAB, SLOT_TYPE, 0); 107 108 if (val != 2) { 109 val = FIELD_EX64(s->capareg, SDHC_CAPAB, EMBEDDED_8BIT); 110 trace_sdhci_capareg("8-bit bus", val); 111 } 112 msk = FIELD_DP64(msk, SDHC_CAPAB, EMBEDDED_8BIT, 0); 113 114 val = FIELD_EX64(s->capareg, SDHC_CAPAB, BUS_SPEED); 115 trace_sdhci_capareg("bus speed mask", val); 116 msk = FIELD_DP64(msk, SDHC_CAPAB, BUS_SPEED, 0); 117 118 val = FIELD_EX64(s->capareg, SDHC_CAPAB, DRIVER_STRENGTH); 119 trace_sdhci_capareg("driver strength mask", val); 120 msk = FIELD_DP64(msk, SDHC_CAPAB, DRIVER_STRENGTH, 0); 121 122 val = FIELD_EX64(s->capareg, SDHC_CAPAB, TIMER_RETUNING); 123 trace_sdhci_capareg("timer re-tuning", val); 124 msk = FIELD_DP64(msk, SDHC_CAPAB, TIMER_RETUNING, 0); 125 126 val = FIELD_EX64(s->capareg, SDHC_CAPAB, SDR50_TUNING); 127 trace_sdhci_capareg("use SDR50 tuning", val); 128 msk = FIELD_DP64(msk, SDHC_CAPAB, SDR50_TUNING, 0); 129 130 val = FIELD_EX64(s->capareg, SDHC_CAPAB, RETUNING_MODE); 131 trace_sdhci_capareg("re-tuning mode", val); 132 msk = FIELD_DP64(msk, SDHC_CAPAB, RETUNING_MODE, 0); 133 134 val = FIELD_EX64(s->capareg, SDHC_CAPAB, CLOCK_MULT); 135 trace_sdhci_capareg("clock multiplier", val); 136 msk = FIELD_DP64(msk, SDHC_CAPAB, CLOCK_MULT, 0); 137 138 /* fallthrough */ 139 case 2: /* default version */ 140 val = FIELD_EX64(s->capareg, SDHC_CAPAB, ADMA2); 141 trace_sdhci_capareg("ADMA2", val); 142 msk = FIELD_DP64(msk, SDHC_CAPAB, ADMA2, 0); 143 144 val = FIELD_EX64(s->capareg, SDHC_CAPAB, ADMA1); 145 trace_sdhci_capareg("ADMA1", val); 146 msk = FIELD_DP64(msk, SDHC_CAPAB, ADMA1, 0); 147 148 val = FIELD_EX64(s->capareg, SDHC_CAPAB, BUS64BIT); 149 trace_sdhci_capareg("64-bit system bus (v3)", val); 150 msk = FIELD_DP64(msk, SDHC_CAPAB, BUS64BIT, 0); 151 152 /* fallthrough */ 153 case 1: 154 y = FIELD_EX64(s->capareg, SDHC_CAPAB, TOUNIT); 155 msk = FIELD_DP64(msk, SDHC_CAPAB, TOUNIT, 0); 156 157 val = FIELD_EX64(s->capareg, SDHC_CAPAB, TOCLKFREQ); 158 trace_sdhci_capareg(y ? "timeout (MHz)" : "Timeout (KHz)", val); 159 if (sdhci_check_capab_freq_range(s, "timeout", val, errp)) { 160 return; 161 } 162 msk = FIELD_DP64(msk, SDHC_CAPAB, TOCLKFREQ, 0); 163 164 val = FIELD_EX64(s->capareg, SDHC_CAPAB, BASECLKFREQ); 165 trace_sdhci_capareg(y ? "base (MHz)" : "Base (KHz)", val); 166 if (sdhci_check_capab_freq_range(s, "base", val, errp)) { 167 return; 168 } 169 msk = FIELD_DP64(msk, SDHC_CAPAB, BASECLKFREQ, 0); 170 171 val = FIELD_EX64(s->capareg, SDHC_CAPAB, MAXBLOCKLENGTH); 172 if (val >= 3) { 173 error_setg(errp, "block size can be 512, 1024 or 2048 only"); 174 return; 175 } 176 trace_sdhci_capareg("max block length", sdhci_get_fifolen(s)); 177 msk = FIELD_DP64(msk, SDHC_CAPAB, MAXBLOCKLENGTH, 0); 178 179 val = FIELD_EX64(s->capareg, SDHC_CAPAB, HIGHSPEED); 180 trace_sdhci_capareg("high speed", val); 181 msk = FIELD_DP64(msk, SDHC_CAPAB, HIGHSPEED, 0); 182 183 val = FIELD_EX64(s->capareg, SDHC_CAPAB, SDMA); 184 trace_sdhci_capareg("SDMA", val); 185 msk = FIELD_DP64(msk, SDHC_CAPAB, SDMA, 0); 186 187 val = FIELD_EX64(s->capareg, SDHC_CAPAB, SUSPRESUME); 188 trace_sdhci_capareg("suspend/resume", val); 189 msk = FIELD_DP64(msk, SDHC_CAPAB, SUSPRESUME, 0); 190 191 val = FIELD_EX64(s->capareg, SDHC_CAPAB, V33); 192 trace_sdhci_capareg("3.3v", val); 193 msk = FIELD_DP64(msk, SDHC_CAPAB, V33, 0); 194 195 val = FIELD_EX64(s->capareg, SDHC_CAPAB, V30); 196 trace_sdhci_capareg("3.0v", val); 197 msk = FIELD_DP64(msk, SDHC_CAPAB, V30, 0); 198 199 val = FIELD_EX64(s->capareg, SDHC_CAPAB, V18); 200 trace_sdhci_capareg("1.8v", val); 201 msk = FIELD_DP64(msk, SDHC_CAPAB, V18, 0); 202 break; 203 204 default: 205 error_setg(errp, "Unsupported spec version: %u", s->sd_spec_version); 206 } 207 if (msk) { 208 qemu_log_mask(LOG_UNIMP, 209 "SDHCI: unknown CAPAB mask: 0x%016" PRIx64 "\n", msk); 210 } 211 } 212 213 static uint8_t sdhci_slotint(SDHCIState *s) 214 { 215 return (s->norintsts & s->norintsigen) || (s->errintsts & s->errintsigen) || 216 ((s->norintsts & SDHC_NIS_INSERT) && (s->wakcon & SDHC_WKUP_ON_INS)) || 217 ((s->norintsts & SDHC_NIS_REMOVE) && (s->wakcon & SDHC_WKUP_ON_RMV)); 218 } 219 220 /* Return true if IRQ was pending and delivered */ 221 static bool sdhci_update_irq(SDHCIState *s) 222 { 223 bool pending = sdhci_slotint(s); 224 225 qemu_set_irq(s->irq, pending); 226 227 return pending; 228 } 229 230 static void sdhci_raise_insertion_irq(void *opaque) 231 { 232 SDHCIState *s = (SDHCIState *)opaque; 233 234 if (s->norintsts & SDHC_NIS_REMOVE) { 235 timer_mod(s->insert_timer, 236 qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + SDHC_INSERTION_DELAY); 237 } else { 238 s->prnsts = 0x1ff0000; 239 if (s->norintstsen & SDHC_NISEN_INSERT) { 240 s->norintsts |= SDHC_NIS_INSERT; 241 } 242 sdhci_update_irq(s); 243 } 244 } 245 246 static void sdhci_set_inserted(DeviceState *dev, bool level) 247 { 248 SDHCIState *s = (SDHCIState *)dev; 249 250 trace_sdhci_set_inserted(level ? "insert" : "eject"); 251 if ((s->norintsts & SDHC_NIS_REMOVE) && level) { 252 /* Give target some time to notice card ejection */ 253 timer_mod(s->insert_timer, 254 qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + SDHC_INSERTION_DELAY); 255 } else { 256 if (level) { 257 s->prnsts = 0x1ff0000; 258 if (s->norintstsen & SDHC_NISEN_INSERT) { 259 s->norintsts |= SDHC_NIS_INSERT; 260 } 261 } else { 262 s->prnsts = 0x1fa0000; 263 s->pwrcon &= ~SDHC_POWER_ON; 264 s->clkcon &= ~SDHC_CLOCK_SDCLK_EN; 265 if (s->norintstsen & SDHC_NISEN_REMOVE) { 266 s->norintsts |= SDHC_NIS_REMOVE; 267 } 268 } 269 sdhci_update_irq(s); 270 } 271 } 272 273 static void sdhci_set_readonly(DeviceState *dev, bool level) 274 { 275 SDHCIState *s = (SDHCIState *)dev; 276 277 if (level) { 278 s->prnsts &= ~SDHC_WRITE_PROTECT; 279 } else { 280 /* Write enabled */ 281 s->prnsts |= SDHC_WRITE_PROTECT; 282 } 283 } 284 285 static void sdhci_reset(SDHCIState *s) 286 { 287 DeviceState *dev = DEVICE(s); 288 289 timer_del(s->insert_timer); 290 timer_del(s->transfer_timer); 291 292 /* 293 * Set all registers to 0. Capabilities/Version registers are not cleared 294 * and assumed to always preserve their value, given to them during 295 * initialization 296 */ 297 memset(&s->sdmasysad, 0, (uintptr_t)&s->capareg - (uintptr_t)&s->sdmasysad); 298 299 /* Reset other state based on current card insertion/readonly status */ 300 sdhci_set_inserted(dev, sdbus_get_inserted(&s->sdbus)); 301 sdhci_set_readonly(dev, sdbus_get_readonly(&s->sdbus)); 302 303 s->data_count = 0; 304 s->stopped_state = sdhc_not_stopped; 305 s->pending_insert_state = false; 306 } 307 308 static void sdhci_poweron_reset(DeviceState *dev) 309 { 310 /* 311 * QOM (ie power-on) reset. This is identical to reset 312 * commanded via device register apart from handling of the 313 * 'pending insert on powerup' quirk. 314 */ 315 SDHCIState *s = (SDHCIState *)dev; 316 317 sdhci_reset(s); 318 319 if (s->pending_insert_quirk) { 320 s->pending_insert_state = true; 321 } 322 } 323 324 static void sdhci_data_transfer(void *opaque); 325 326 #define BLOCK_SIZE_MASK (4 * KiB - 1) 327 328 static void sdhci_send_command(SDHCIState *s) 329 { 330 SDRequest request; 331 uint8_t response[16]; 332 int rlen; 333 bool timeout = false; 334 335 s->errintsts = 0; 336 s->acmd12errsts = 0; 337 request.cmd = s->cmdreg >> 8; 338 request.arg = s->argument; 339 340 trace_sdhci_send_command(request.cmd, request.arg); 341 rlen = sdbus_do_command(&s->sdbus, &request, response); 342 343 if (s->cmdreg & SDHC_CMD_RESPONSE) { 344 if (rlen == 4) { 345 s->rspreg[0] = ldl_be_p(response); 346 s->rspreg[1] = s->rspreg[2] = s->rspreg[3] = 0; 347 trace_sdhci_response4(s->rspreg[0]); 348 } else if (rlen == 16) { 349 s->rspreg[0] = ldl_be_p(&response[11]); 350 s->rspreg[1] = ldl_be_p(&response[7]); 351 s->rspreg[2] = ldl_be_p(&response[3]); 352 s->rspreg[3] = (response[0] << 16) | (response[1] << 8) | 353 response[2]; 354 trace_sdhci_response16(s->rspreg[3], s->rspreg[2], 355 s->rspreg[1], s->rspreg[0]); 356 } else { 357 timeout = true; 358 trace_sdhci_error("timeout waiting for command response"); 359 if (s->errintstsen & SDHC_EISEN_CMDTIMEOUT) { 360 s->errintsts |= SDHC_EIS_CMDTIMEOUT; 361 s->norintsts |= SDHC_NIS_ERR; 362 } 363 } 364 365 if (!(s->quirks & SDHCI_QUIRK_NO_BUSY_IRQ) && 366 (s->norintstsen & SDHC_NISEN_TRSCMP) && 367 (s->cmdreg & SDHC_CMD_RESPONSE) == SDHC_CMD_RSP_WITH_BUSY) { 368 s->norintsts |= SDHC_NIS_TRSCMP; 369 } 370 } 371 372 if (s->norintstsen & SDHC_NISEN_CMDCMP) { 373 s->norintsts |= SDHC_NIS_CMDCMP; 374 } 375 376 sdhci_update_irq(s); 377 378 if (!timeout && (s->blksize & BLOCK_SIZE_MASK) && 379 (s->cmdreg & SDHC_CMD_DATA_PRESENT)) { 380 s->data_count = 0; 381 sdhci_data_transfer(s); 382 } 383 } 384 385 static void sdhci_end_transfer(SDHCIState *s) 386 { 387 /* Automatically send CMD12 to stop transfer if AutoCMD12 enabled */ 388 if ((s->trnmod & SDHC_TRNS_ACMD12) != 0) { 389 SDRequest request; 390 uint8_t response[16]; 391 392 request.cmd = 0x0C; 393 request.arg = 0; 394 trace_sdhci_end_transfer(request.cmd, request.arg); 395 sdbus_do_command(&s->sdbus, &request, response); 396 /* Auto CMD12 response goes to the upper Response register */ 397 s->rspreg[3] = ldl_be_p(response); 398 } 399 400 s->prnsts &= ~(SDHC_DOING_READ | SDHC_DOING_WRITE | 401 SDHC_DAT_LINE_ACTIVE | SDHC_DATA_INHIBIT | 402 SDHC_SPACE_AVAILABLE | SDHC_DATA_AVAILABLE); 403 404 if (s->norintstsen & SDHC_NISEN_TRSCMP) { 405 s->norintsts |= SDHC_NIS_TRSCMP; 406 } 407 408 sdhci_update_irq(s); 409 } 410 411 /* 412 * Programmed i/o data transfer 413 */ 414 415 /* Fill host controller's read buffer with BLKSIZE bytes of data from card */ 416 static void sdhci_read_block_from_card(SDHCIState *s) 417 { 418 const uint16_t blk_size = s->blksize & BLOCK_SIZE_MASK; 419 420 if ((s->trnmod & SDHC_TRNS_MULTI) && 421 (s->trnmod & SDHC_TRNS_BLK_CNT_EN) && (s->blkcnt == 0)) { 422 return; 423 } 424 425 if (!FIELD_EX32(s->hostctl2, SDHC_HOSTCTL2, EXECUTE_TUNING)) { 426 /* Device is not in tuning */ 427 sdbus_read_data(&s->sdbus, s->fifo_buffer, blk_size); 428 } 429 430 if (FIELD_EX32(s->hostctl2, SDHC_HOSTCTL2, EXECUTE_TUNING)) { 431 /* Device is in tuning */ 432 s->hostctl2 &= ~R_SDHC_HOSTCTL2_EXECUTE_TUNING_MASK; 433 s->hostctl2 |= R_SDHC_HOSTCTL2_SAMPLING_CLKSEL_MASK; 434 s->prnsts &= ~(SDHC_DAT_LINE_ACTIVE | SDHC_DOING_READ | 435 SDHC_DATA_INHIBIT); 436 goto read_done; 437 } 438 439 /* New data now available for READ through Buffer Port Register */ 440 s->prnsts |= SDHC_DATA_AVAILABLE; 441 if (s->norintstsen & SDHC_NISEN_RBUFRDY) { 442 s->norintsts |= SDHC_NIS_RBUFRDY; 443 } 444 445 /* Clear DAT line active status if that was the last block */ 446 if ((s->trnmod & SDHC_TRNS_MULTI) == 0 || 447 ((s->trnmod & SDHC_TRNS_MULTI) && s->blkcnt == 1)) { 448 s->prnsts &= ~SDHC_DAT_LINE_ACTIVE; 449 } 450 451 /* 452 * If stop at block gap request was set and it's not the last block of 453 * data - generate Block Event interrupt 454 */ 455 if (s->stopped_state == sdhc_gap_read && (s->trnmod & SDHC_TRNS_MULTI) && 456 s->blkcnt != 1) { 457 s->prnsts &= ~SDHC_DAT_LINE_ACTIVE; 458 if (s->norintstsen & SDHC_EISEN_BLKGAP) { 459 s->norintsts |= SDHC_EIS_BLKGAP; 460 } 461 } 462 463 read_done: 464 sdhci_update_irq(s); 465 } 466 467 /* Read @size byte of data from host controller @s BUFFER DATA PORT register */ 468 static uint32_t sdhci_read_dataport(SDHCIState *s, unsigned size) 469 { 470 uint32_t value = 0; 471 int i; 472 473 /* first check that a valid data exists in host controller input buffer */ 474 if ((s->prnsts & SDHC_DATA_AVAILABLE) == 0) { 475 trace_sdhci_error("read from empty buffer"); 476 return 0; 477 } 478 479 for (i = 0; i < size; i++) { 480 assert(s->data_count < s->buf_maxsz); 481 value |= s->fifo_buffer[s->data_count] << i * 8; 482 s->data_count++; 483 /* check if we've read all valid data (blksize bytes) from buffer */ 484 if ((s->data_count) >= (s->blksize & BLOCK_SIZE_MASK)) { 485 trace_sdhci_read_dataport(s->data_count); 486 s->prnsts &= ~SDHC_DATA_AVAILABLE; /* no more data in a buffer */ 487 s->data_count = 0; /* next buff read must start at position [0] */ 488 489 if (s->trnmod & SDHC_TRNS_BLK_CNT_EN) { 490 s->blkcnt--; 491 } 492 493 /* if that was the last block of data */ 494 if ((s->trnmod & SDHC_TRNS_MULTI) == 0 || 495 ((s->trnmod & SDHC_TRNS_BLK_CNT_EN) && (s->blkcnt == 0)) || 496 /* stop at gap request */ 497 (s->stopped_state == sdhc_gap_read && 498 !(s->prnsts & SDHC_DAT_LINE_ACTIVE))) { 499 sdhci_end_transfer(s); 500 } else { /* if there are more data, read next block from card */ 501 sdhci_read_block_from_card(s); 502 } 503 break; 504 } 505 } 506 507 return value; 508 } 509 510 /* Write data from host controller FIFO to card */ 511 static void sdhci_write_block_to_card(SDHCIState *s) 512 { 513 if (s->prnsts & SDHC_SPACE_AVAILABLE) { 514 if (s->norintstsen & SDHC_NISEN_WBUFRDY) { 515 s->norintsts |= SDHC_NIS_WBUFRDY; 516 } 517 sdhci_update_irq(s); 518 return; 519 } 520 521 if (s->trnmod & SDHC_TRNS_BLK_CNT_EN) { 522 if (s->blkcnt == 0) { 523 return; 524 } else { 525 s->blkcnt--; 526 } 527 } 528 529 sdbus_write_data(&s->sdbus, s->fifo_buffer, s->blksize & BLOCK_SIZE_MASK); 530 531 /* Next data can be written through BUFFER DATORT register */ 532 s->prnsts |= SDHC_SPACE_AVAILABLE; 533 534 /* Finish transfer if that was the last block of data */ 535 if ((s->trnmod & SDHC_TRNS_MULTI) == 0 || 536 ((s->trnmod & SDHC_TRNS_MULTI) && 537 (s->trnmod & SDHC_TRNS_BLK_CNT_EN) && (s->blkcnt == 0))) { 538 sdhci_end_transfer(s); 539 } else if (s->norintstsen & SDHC_NISEN_WBUFRDY) { 540 s->norintsts |= SDHC_NIS_WBUFRDY; 541 } 542 543 /* Generate Block Gap Event if requested and if not the last block */ 544 if (s->stopped_state == sdhc_gap_write && (s->trnmod & SDHC_TRNS_MULTI) && 545 s->blkcnt > 0) { 546 s->prnsts &= ~SDHC_DOING_WRITE; 547 if (s->norintstsen & SDHC_EISEN_BLKGAP) { 548 s->norintsts |= SDHC_EIS_BLKGAP; 549 } 550 sdhci_end_transfer(s); 551 } 552 553 sdhci_update_irq(s); 554 } 555 556 /* 557 * Write @size bytes of @value data to host controller @s Buffer Data Port 558 * register 559 */ 560 static void sdhci_write_dataport(SDHCIState *s, uint32_t value, unsigned size) 561 { 562 unsigned i; 563 564 /* Check that there is free space left in a buffer */ 565 if (!(s->prnsts & SDHC_SPACE_AVAILABLE)) { 566 trace_sdhci_error("Can't write to data buffer: buffer full"); 567 return; 568 } 569 570 for (i = 0; i < size; i++) { 571 assert(s->data_count < s->buf_maxsz); 572 s->fifo_buffer[s->data_count] = value & 0xFF; 573 s->data_count++; 574 value >>= 8; 575 if (s->data_count >= (s->blksize & BLOCK_SIZE_MASK)) { 576 trace_sdhci_write_dataport(s->data_count); 577 s->data_count = 0; 578 s->prnsts &= ~SDHC_SPACE_AVAILABLE; 579 if (s->prnsts & SDHC_DOING_WRITE) { 580 sdhci_write_block_to_card(s); 581 } 582 } 583 } 584 } 585 586 /* 587 * Single DMA data transfer 588 */ 589 590 /* Multi block SDMA transfer */ 591 static void sdhci_sdma_transfer_multi_blocks(SDHCIState *s) 592 { 593 bool page_aligned = false; 594 unsigned int begin; 595 const uint16_t block_size = s->blksize & BLOCK_SIZE_MASK; 596 uint32_t boundary_chk = 1 << (((s->blksize & ~BLOCK_SIZE_MASK) >> 12) + 12); 597 uint32_t boundary_count = boundary_chk - (s->sdmasysad % boundary_chk); 598 599 if (!(s->trnmod & SDHC_TRNS_BLK_CNT_EN) || !s->blkcnt) { 600 qemu_log_mask(LOG_UNIMP, "infinite transfer is not supported\n"); 601 return; 602 } 603 604 /* 605 * XXX: Some sd/mmc drivers (for example, u-boot-slp) do not account for 606 * possible stop at page boundary if initial address is not page aligned, 607 * allow them to work properly 608 */ 609 if ((s->sdmasysad % boundary_chk) == 0) { 610 page_aligned = true; 611 } 612 613 s->prnsts |= SDHC_DATA_INHIBIT | SDHC_DAT_LINE_ACTIVE; 614 if (s->trnmod & SDHC_TRNS_READ) { 615 s->prnsts |= SDHC_DOING_READ; 616 while (s->blkcnt) { 617 if (s->data_count == 0) { 618 sdbus_read_data(&s->sdbus, s->fifo_buffer, block_size); 619 } 620 begin = s->data_count; 621 if (((boundary_count + begin) < block_size) && page_aligned) { 622 s->data_count = boundary_count + begin; 623 boundary_count = 0; 624 } else { 625 s->data_count = block_size; 626 boundary_count -= block_size - begin; 627 if (s->trnmod & SDHC_TRNS_BLK_CNT_EN) { 628 s->blkcnt--; 629 } 630 } 631 dma_memory_write(s->dma_as, s->sdmasysad, &s->fifo_buffer[begin], 632 s->data_count - begin, MEMTXATTRS_UNSPECIFIED); 633 s->sdmasysad += s->data_count - begin; 634 if (s->data_count == block_size) { 635 s->data_count = 0; 636 } 637 if (page_aligned && boundary_count == 0) { 638 break; 639 } 640 } 641 } else { 642 s->prnsts |= SDHC_DOING_WRITE; 643 while (s->blkcnt) { 644 begin = s->data_count; 645 if (((boundary_count + begin) < block_size) && page_aligned) { 646 s->data_count = boundary_count + begin; 647 boundary_count = 0; 648 } else { 649 s->data_count = block_size; 650 boundary_count -= block_size - begin; 651 } 652 dma_memory_read(s->dma_as, s->sdmasysad, &s->fifo_buffer[begin], 653 s->data_count - begin, MEMTXATTRS_UNSPECIFIED); 654 s->sdmasysad += s->data_count - begin; 655 if (s->data_count == block_size) { 656 sdbus_write_data(&s->sdbus, s->fifo_buffer, block_size); 657 s->data_count = 0; 658 if (s->trnmod & SDHC_TRNS_BLK_CNT_EN) { 659 s->blkcnt--; 660 } 661 } 662 if (page_aligned && boundary_count == 0) { 663 break; 664 } 665 } 666 } 667 668 if (s->norintstsen & SDHC_NISEN_DMA) { 669 s->norintsts |= SDHC_NIS_DMA; 670 } 671 672 if (s->blkcnt == 0) { 673 sdhci_end_transfer(s); 674 } else { 675 sdhci_update_irq(s); 676 } 677 } 678 679 /* single block SDMA transfer */ 680 static void sdhci_sdma_transfer_single_block(SDHCIState *s) 681 { 682 uint32_t datacnt = s->blksize & BLOCK_SIZE_MASK; 683 684 if (s->trnmod & SDHC_TRNS_READ) { 685 sdbus_read_data(&s->sdbus, s->fifo_buffer, datacnt); 686 dma_memory_write(s->dma_as, s->sdmasysad, s->fifo_buffer, datacnt, 687 MEMTXATTRS_UNSPECIFIED); 688 } else { 689 dma_memory_read(s->dma_as, s->sdmasysad, s->fifo_buffer, datacnt, 690 MEMTXATTRS_UNSPECIFIED); 691 sdbus_write_data(&s->sdbus, s->fifo_buffer, datacnt); 692 } 693 s->blkcnt--; 694 695 if (s->norintstsen & SDHC_NISEN_DMA) { 696 s->norintsts |= SDHC_NIS_DMA; 697 } 698 699 sdhci_end_transfer(s); 700 } 701 702 typedef struct ADMADescr { 703 hwaddr addr; 704 uint16_t length; 705 uint8_t attr; 706 uint8_t incr; 707 } ADMADescr; 708 709 static void get_adma_description(SDHCIState *s, ADMADescr *dscr) 710 { 711 uint32_t adma1 = 0; 712 uint64_t adma2 = 0; 713 hwaddr entry_addr = (hwaddr)s->admasysaddr; 714 switch (SDHC_DMA_TYPE(s->hostctl1)) { 715 case SDHC_CTRL_ADMA2_32: 716 dma_memory_read(s->dma_as, entry_addr, &adma2, sizeof(adma2), 717 MEMTXATTRS_UNSPECIFIED); 718 adma2 = le64_to_cpu(adma2); 719 /* 720 * The spec does not specify endianness of descriptor table. 721 * We currently assume that it is LE. 722 */ 723 dscr->addr = (hwaddr)extract64(adma2, 32, 32) & ~0x3ull; 724 dscr->length = (uint16_t)extract64(adma2, 16, 16); 725 dscr->attr = (uint8_t)extract64(adma2, 0, 7); 726 dscr->incr = 8; 727 break; 728 case SDHC_CTRL_ADMA1_32: 729 dma_memory_read(s->dma_as, entry_addr, &adma1, sizeof(adma1), 730 MEMTXATTRS_UNSPECIFIED); 731 adma1 = le32_to_cpu(adma1); 732 dscr->addr = (hwaddr)(adma1 & 0xFFFFF000); 733 dscr->attr = (uint8_t)extract32(adma1, 0, 7); 734 dscr->incr = 4; 735 if ((dscr->attr & SDHC_ADMA_ATTR_ACT_MASK) == SDHC_ADMA_ATTR_SET_LEN) { 736 dscr->length = (uint16_t)extract32(adma1, 12, 16); 737 } else { 738 dscr->length = 4 * KiB; 739 } 740 break; 741 case SDHC_CTRL_ADMA2_64: 742 dma_memory_read(s->dma_as, entry_addr, &dscr->attr, 1, 743 MEMTXATTRS_UNSPECIFIED); 744 dma_memory_read(s->dma_as, entry_addr + 2, &dscr->length, 2, 745 MEMTXATTRS_UNSPECIFIED); 746 dscr->length = le16_to_cpu(dscr->length); 747 dma_memory_read(s->dma_as, entry_addr + 4, &dscr->addr, 8, 748 MEMTXATTRS_UNSPECIFIED); 749 dscr->addr = le64_to_cpu(dscr->addr); 750 dscr->attr &= (uint8_t) ~0xC0; 751 dscr->incr = 12; 752 break; 753 } 754 } 755 756 /* Advanced DMA data transfer */ 757 758 static void sdhci_do_adma(SDHCIState *s) 759 { 760 unsigned int begin, length; 761 const uint16_t block_size = s->blksize & BLOCK_SIZE_MASK; 762 const MemTxAttrs attrs = { .memory = true }; 763 ADMADescr dscr = {}; 764 MemTxResult res = MEMTX_ERROR; 765 int i; 766 767 if (s->trnmod & SDHC_TRNS_BLK_CNT_EN && !s->blkcnt) { 768 /* Stop Multiple Transfer */ 769 sdhci_end_transfer(s); 770 return; 771 } 772 773 for (i = 0; i < SDHC_ADMA_DESCS_PER_DELAY; ++i) { 774 s->admaerr &= ~SDHC_ADMAERR_LENGTH_MISMATCH; 775 776 get_adma_description(s, &dscr); 777 trace_sdhci_adma_loop(dscr.addr, dscr.length, dscr.attr); 778 779 if ((dscr.attr & SDHC_ADMA_ATTR_VALID) == 0) { 780 /* Indicate that error occurred in ST_FDS state */ 781 s->admaerr &= ~SDHC_ADMAERR_STATE_MASK; 782 s->admaerr |= SDHC_ADMAERR_STATE_ST_FDS; 783 784 /* Generate ADMA error interrupt */ 785 if (s->errintstsen & SDHC_EISEN_ADMAERR) { 786 s->errintsts |= SDHC_EIS_ADMAERR; 787 s->norintsts |= SDHC_NIS_ERR; 788 } 789 790 sdhci_update_irq(s); 791 return; 792 } 793 794 length = dscr.length ? dscr.length : 64 * KiB; 795 796 switch (dscr.attr & SDHC_ADMA_ATTR_ACT_MASK) { 797 case SDHC_ADMA_ATTR_ACT_TRAN: /* data transfer */ 798 s->prnsts |= SDHC_DATA_INHIBIT | SDHC_DAT_LINE_ACTIVE; 799 if (s->trnmod & SDHC_TRNS_READ) { 800 s->prnsts |= SDHC_DOING_READ; 801 while (length) { 802 if (s->data_count == 0) { 803 sdbus_read_data(&s->sdbus, s->fifo_buffer, block_size); 804 } 805 begin = s->data_count; 806 if ((length + begin) < block_size) { 807 s->data_count = length + begin; 808 length = 0; 809 } else { 810 s->data_count = block_size; 811 length -= block_size - begin; 812 } 813 res = dma_memory_write(s->dma_as, dscr.addr, 814 &s->fifo_buffer[begin], 815 s->data_count - begin, 816 attrs); 817 if (res != MEMTX_OK) { 818 break; 819 } 820 dscr.addr += s->data_count - begin; 821 if (s->data_count == block_size) { 822 s->data_count = 0; 823 if (s->trnmod & SDHC_TRNS_BLK_CNT_EN) { 824 s->blkcnt--; 825 if (s->blkcnt == 0) { 826 break; 827 } 828 } 829 } 830 } 831 } else { 832 s->prnsts |= SDHC_DOING_WRITE; 833 while (length) { 834 begin = s->data_count; 835 if ((length + begin) < block_size) { 836 s->data_count = length + begin; 837 length = 0; 838 } else { 839 s->data_count = block_size; 840 length -= block_size - begin; 841 } 842 res = dma_memory_read(s->dma_as, dscr.addr, 843 &s->fifo_buffer[begin], 844 s->data_count - begin, 845 attrs); 846 if (res != MEMTX_OK) { 847 break; 848 } 849 dscr.addr += s->data_count - begin; 850 if (s->data_count == block_size) { 851 sdbus_write_data(&s->sdbus, s->fifo_buffer, block_size); 852 s->data_count = 0; 853 if (s->trnmod & SDHC_TRNS_BLK_CNT_EN) { 854 s->blkcnt--; 855 if (s->blkcnt == 0) { 856 break; 857 } 858 } 859 } 860 } 861 } 862 if (res != MEMTX_OK) { 863 s->data_count = 0; 864 if (s->errintstsen & SDHC_EISEN_ADMAERR) { 865 trace_sdhci_error("Set ADMA error flag"); 866 s->errintsts |= SDHC_EIS_ADMAERR; 867 s->norintsts |= SDHC_NIS_ERR; 868 } 869 sdhci_update_irq(s); 870 } else { 871 s->admasysaddr += dscr.incr; 872 } 873 break; 874 case SDHC_ADMA_ATTR_ACT_LINK: /* link to next descriptor table */ 875 s->admasysaddr = dscr.addr; 876 trace_sdhci_adma("link", s->admasysaddr); 877 break; 878 default: 879 s->admasysaddr += dscr.incr; 880 break; 881 } 882 883 if (dscr.attr & SDHC_ADMA_ATTR_INT) { 884 trace_sdhci_adma("interrupt", s->admasysaddr); 885 if (s->norintstsen & SDHC_NISEN_DMA) { 886 s->norintsts |= SDHC_NIS_DMA; 887 } 888 889 if (sdhci_update_irq(s) && !(dscr.attr & SDHC_ADMA_ATTR_END)) { 890 /* IRQ delivered, reschedule current transfer */ 891 break; 892 } 893 } 894 895 /* ADMA transfer terminates if blkcnt == 0 or by END attribute */ 896 if (((s->trnmod & SDHC_TRNS_BLK_CNT_EN) && 897 (s->blkcnt == 0)) || (dscr.attr & SDHC_ADMA_ATTR_END)) { 898 trace_sdhci_adma_transfer_completed(); 899 if (length || ((dscr.attr & SDHC_ADMA_ATTR_END) && 900 (s->trnmod & SDHC_TRNS_BLK_CNT_EN) && 901 s->blkcnt != 0)) { 902 trace_sdhci_error("SD/MMC host ADMA length mismatch"); 903 s->admaerr |= SDHC_ADMAERR_LENGTH_MISMATCH | 904 SDHC_ADMAERR_STATE_ST_TFR; 905 if (s->errintstsen & SDHC_EISEN_ADMAERR) { 906 trace_sdhci_error("Set ADMA error flag"); 907 s->errintsts |= SDHC_EIS_ADMAERR; 908 s->norintsts |= SDHC_NIS_ERR; 909 } 910 911 sdhci_update_irq(s); 912 } 913 sdhci_end_transfer(s); 914 return; 915 } 916 917 } 918 919 /* we have unfinished business - reschedule to continue ADMA */ 920 timer_mod(s->transfer_timer, 921 qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + SDHC_TRANSFER_DELAY); 922 } 923 924 /* Perform data transfer according to controller configuration */ 925 926 static void sdhci_data_transfer(void *opaque) 927 { 928 SDHCIState *s = (SDHCIState *)opaque; 929 930 if (s->trnmod & SDHC_TRNS_DMA) { 931 switch (SDHC_DMA_TYPE(s->hostctl1)) { 932 case SDHC_CTRL_SDMA: 933 if ((s->blkcnt == 1) || !(s->trnmod & SDHC_TRNS_MULTI)) { 934 sdhci_sdma_transfer_single_block(s); 935 } else { 936 sdhci_sdma_transfer_multi_blocks(s); 937 } 938 939 break; 940 case SDHC_CTRL_ADMA1_32: 941 if (!(s->capareg & R_SDHC_CAPAB_ADMA1_MASK)) { 942 trace_sdhci_error("ADMA1 not supported"); 943 break; 944 } 945 946 sdhci_do_adma(s); 947 break; 948 case SDHC_CTRL_ADMA2_32: 949 if (!(s->capareg & R_SDHC_CAPAB_ADMA2_MASK)) { 950 trace_sdhci_error("ADMA2 not supported"); 951 break; 952 } 953 954 sdhci_do_adma(s); 955 break; 956 case SDHC_CTRL_ADMA2_64: 957 if (!(s->capareg & R_SDHC_CAPAB_ADMA2_MASK) || 958 !(s->capareg & R_SDHC_CAPAB_BUS64BIT_MASK)) { 959 trace_sdhci_error("64 bit ADMA not supported"); 960 break; 961 } 962 963 sdhci_do_adma(s); 964 break; 965 default: 966 trace_sdhci_error("Unsupported DMA type"); 967 break; 968 } 969 } else { 970 if ((s->trnmod & SDHC_TRNS_READ) && sdbus_data_ready(&s->sdbus)) { 971 s->prnsts |= SDHC_DOING_READ | SDHC_DATA_INHIBIT | 972 SDHC_DAT_LINE_ACTIVE; 973 sdhci_read_block_from_card(s); 974 } else { 975 s->prnsts |= SDHC_DOING_WRITE | SDHC_DAT_LINE_ACTIVE | 976 SDHC_SPACE_AVAILABLE | SDHC_DATA_INHIBIT; 977 sdhci_write_block_to_card(s); 978 } 979 } 980 } 981 982 static bool sdhci_can_issue_command(SDHCIState *s) 983 { 984 if (!SDHC_CLOCK_IS_ON(s->clkcon) || 985 (((s->prnsts & SDHC_DATA_INHIBIT) || s->stopped_state) && 986 ((s->cmdreg & SDHC_CMD_DATA_PRESENT) || 987 ((s->cmdreg & SDHC_CMD_RESPONSE) == SDHC_CMD_RSP_WITH_BUSY && 988 !(SDHC_COMMAND_TYPE(s->cmdreg) == SDHC_CMD_ABORT))))) { 989 return false; 990 } 991 992 return true; 993 } 994 995 /* 996 * The Buffer Data Port register must be accessed in sequential and 997 * continuous manner 998 */ 999 static inline bool 1000 sdhci_buff_access_is_sequential(SDHCIState *s, unsigned byte_num) 1001 { 1002 if ((s->data_count & 0x3) != byte_num) { 1003 qemu_log_mask(LOG_GUEST_ERROR, 1004 "SDHCI: Non-sequential access to Buffer Data Port" 1005 " register is prohibited\n"); 1006 return false; 1007 } 1008 return true; 1009 } 1010 1011 static void sdhci_resume_pending_transfer(SDHCIState *s) 1012 { 1013 timer_del(s->transfer_timer); 1014 sdhci_data_transfer(s); 1015 } 1016 1017 static uint64_t sdhci_read(void *opaque, hwaddr offset, unsigned size) 1018 { 1019 SDHCIState *s = (SDHCIState *)opaque; 1020 uint32_t ret = 0; 1021 1022 if (timer_pending(s->transfer_timer)) { 1023 sdhci_resume_pending_transfer(s); 1024 } 1025 1026 switch (offset & ~0x3) { 1027 case SDHC_SYSAD: 1028 ret = s->sdmasysad; 1029 break; 1030 case SDHC_BLKSIZE: 1031 ret = s->blksize | (s->blkcnt << 16); 1032 break; 1033 case SDHC_ARGUMENT: 1034 ret = s->argument; 1035 break; 1036 case SDHC_TRNMOD: 1037 ret = s->trnmod | (s->cmdreg << 16); 1038 break; 1039 case SDHC_RSPREG0 ... SDHC_RSPREG3: 1040 ret = s->rspreg[((offset & ~0x3) - SDHC_RSPREG0) >> 2]; 1041 break; 1042 case SDHC_BDATA: 1043 if (sdhci_buff_access_is_sequential(s, offset - SDHC_BDATA)) { 1044 ret = sdhci_read_dataport(s, size); 1045 trace_sdhci_access("rd", size << 3, offset, "->", ret, ret); 1046 return ret; 1047 } 1048 break; 1049 case SDHC_PRNSTS: 1050 ret = s->prnsts; 1051 ret = FIELD_DP32(ret, SDHC_PRNSTS, DAT_LVL, 1052 sdbus_get_dat_lines(&s->sdbus)); 1053 ret = FIELD_DP32(ret, SDHC_PRNSTS, CMD_LVL, 1054 sdbus_get_cmd_line(&s->sdbus)); 1055 break; 1056 case SDHC_HOSTCTL: 1057 ret = s->hostctl1 | (s->pwrcon << 8) | (s->blkgap << 16) | 1058 (s->wakcon << 24); 1059 break; 1060 case SDHC_CLKCON: 1061 ret = s->clkcon | (s->timeoutcon << 16); 1062 break; 1063 case SDHC_NORINTSTS: 1064 ret = s->norintsts | (s->errintsts << 16); 1065 break; 1066 case SDHC_NORINTSTSEN: 1067 ret = s->norintstsen | (s->errintstsen << 16); 1068 break; 1069 case SDHC_NORINTSIGEN: 1070 ret = s->norintsigen | (s->errintsigen << 16); 1071 break; 1072 case SDHC_ACMD12ERRSTS: 1073 ret = s->acmd12errsts | (s->hostctl2 << 16); 1074 break; 1075 case SDHC_CAPAB: 1076 ret = (uint32_t)s->capareg; 1077 break; 1078 case SDHC_CAPAB + 4: 1079 ret = (uint32_t)(s->capareg >> 32); 1080 break; 1081 case SDHC_MAXCURR: 1082 ret = (uint32_t)s->maxcurr; 1083 break; 1084 case SDHC_MAXCURR + 4: 1085 ret = (uint32_t)(s->maxcurr >> 32); 1086 break; 1087 case SDHC_ADMAERR: 1088 ret = s->admaerr; 1089 break; 1090 case SDHC_ADMASYSADDR: 1091 ret = (uint32_t)s->admasysaddr; 1092 break; 1093 case SDHC_ADMASYSADDR + 4: 1094 ret = (uint32_t)(s->admasysaddr >> 32); 1095 break; 1096 case SDHC_SLOT_INT_STATUS: 1097 ret = (s->version << 16) | sdhci_slotint(s); 1098 break; 1099 default: 1100 qemu_log_mask(LOG_UNIMP, "SDHC rd_%ub @0x%02" HWADDR_PRIx " " 1101 "not implemented\n", size, offset); 1102 break; 1103 } 1104 1105 ret >>= (offset & 0x3) * 8; 1106 ret &= (1ULL << (size * 8)) - 1; 1107 trace_sdhci_access("rd", size << 3, offset, "->", ret, ret); 1108 return ret; 1109 } 1110 1111 static inline void sdhci_blkgap_write(SDHCIState *s, uint8_t value) 1112 { 1113 if ((value & SDHC_STOP_AT_GAP_REQ) && (s->blkgap & SDHC_STOP_AT_GAP_REQ)) { 1114 return; 1115 } 1116 s->blkgap = value & SDHC_STOP_AT_GAP_REQ; 1117 1118 if ((value & SDHC_CONTINUE_REQ) && s->stopped_state && 1119 (s->blkgap & SDHC_STOP_AT_GAP_REQ) == 0) { 1120 if (s->stopped_state == sdhc_gap_read) { 1121 s->prnsts |= SDHC_DAT_LINE_ACTIVE | SDHC_DOING_READ; 1122 sdhci_read_block_from_card(s); 1123 } else { 1124 s->prnsts |= SDHC_DAT_LINE_ACTIVE | SDHC_DOING_WRITE; 1125 sdhci_write_block_to_card(s); 1126 } 1127 s->stopped_state = sdhc_not_stopped; 1128 } else if (!s->stopped_state && (value & SDHC_STOP_AT_GAP_REQ)) { 1129 if (s->prnsts & SDHC_DOING_READ) { 1130 s->stopped_state = sdhc_gap_read; 1131 } else if (s->prnsts & SDHC_DOING_WRITE) { 1132 s->stopped_state = sdhc_gap_write; 1133 } 1134 } 1135 } 1136 1137 static inline void sdhci_reset_write(SDHCIState *s, uint8_t value) 1138 { 1139 switch (value) { 1140 case SDHC_RESET_ALL: 1141 sdhci_reset(s); 1142 break; 1143 case SDHC_RESET_CMD: 1144 s->prnsts &= ~SDHC_CMD_INHIBIT; 1145 s->norintsts &= ~SDHC_NIS_CMDCMP; 1146 break; 1147 case SDHC_RESET_DATA: 1148 s->data_count = 0; 1149 s->prnsts &= ~(SDHC_SPACE_AVAILABLE | SDHC_DATA_AVAILABLE | 1150 SDHC_DOING_READ | SDHC_DOING_WRITE | 1151 SDHC_DATA_INHIBIT | SDHC_DAT_LINE_ACTIVE); 1152 s->blkgap &= ~(SDHC_STOP_AT_GAP_REQ | SDHC_CONTINUE_REQ); 1153 s->stopped_state = sdhc_not_stopped; 1154 s->norintsts &= ~(SDHC_NIS_WBUFRDY | SDHC_NIS_RBUFRDY | 1155 SDHC_NIS_DMA | SDHC_NIS_TRSCMP | SDHC_NIS_BLKGAP); 1156 break; 1157 } 1158 } 1159 1160 static void 1161 sdhci_write(void *opaque, hwaddr offset, uint64_t val, unsigned size) 1162 { 1163 SDHCIState *s = (SDHCIState *)opaque; 1164 unsigned shift = 8 * (offset & 0x3); 1165 uint32_t mask = ~(((1ULL << (size * 8)) - 1) << shift); 1166 uint32_t value = val; 1167 value <<= shift; 1168 1169 if (timer_pending(s->transfer_timer)) { 1170 sdhci_resume_pending_transfer(s); 1171 } 1172 1173 switch (offset & ~0x3) { 1174 case SDHC_SYSAD: 1175 if (!TRANSFERRING_DATA(s->prnsts)) { 1176 s->sdmasysad = (s->sdmasysad & mask) | value; 1177 MASKED_WRITE(s->sdmasysad, mask, value); 1178 /* Writing to last byte of sdmasysad might trigger transfer */ 1179 if (!(mask & 0xFF000000) && s->blkcnt && 1180 (s->blksize & BLOCK_SIZE_MASK) && 1181 SDHC_DMA_TYPE(s->hostctl1) == SDHC_CTRL_SDMA) { 1182 if (s->trnmod & SDHC_TRNS_MULTI) { 1183 sdhci_sdma_transfer_multi_blocks(s); 1184 } else { 1185 sdhci_sdma_transfer_single_block(s); 1186 } 1187 } 1188 } 1189 break; 1190 case SDHC_BLKSIZE: 1191 if (!TRANSFERRING_DATA(s->prnsts)) { 1192 uint16_t blksize = s->blksize; 1193 1194 /* 1195 * [14:12] SDMA Buffer Boundary 1196 * [11:00] Transfer Block Size 1197 */ 1198 MASKED_WRITE(s->blksize, mask, extract32(value, 0, 15)); 1199 MASKED_WRITE(s->blkcnt, mask >> 16, value >> 16); 1200 1201 /* Limit block size to the maximum buffer size */ 1202 if (extract32(s->blksize, 0, 12) > s->buf_maxsz) { 1203 qemu_log_mask(LOG_GUEST_ERROR, "%s: Size 0x%x is larger than " 1204 "the maximum buffer 0x%x\n", __func__, s->blksize, 1205 s->buf_maxsz); 1206 1207 s->blksize = deposit32(s->blksize, 0, 12, s->buf_maxsz); 1208 } 1209 1210 /* 1211 * If the block size is programmed to a different value from 1212 * the previous one, reset the data pointer of s->fifo_buffer[] 1213 * so that s->fifo_buffer[] can be filled in using the new block 1214 * size in the next transfer. 1215 */ 1216 if (blksize != s->blksize) { 1217 s->data_count = 0; 1218 } 1219 } 1220 1221 break; 1222 case SDHC_ARGUMENT: 1223 MASKED_WRITE(s->argument, mask, value); 1224 break; 1225 case SDHC_TRNMOD: 1226 /* 1227 * DMA can be enabled only if it is supported as indicated by 1228 * capabilities register 1229 */ 1230 if (!(s->capareg & R_SDHC_CAPAB_SDMA_MASK)) { 1231 value &= ~SDHC_TRNS_DMA; 1232 } 1233 1234 /* TRNMOD writes are inhibited while Command Inhibit (DAT) is true */ 1235 if (s->prnsts & SDHC_DATA_INHIBIT) { 1236 mask |= 0xffff; 1237 } 1238 1239 MASKED_WRITE(s->trnmod, mask, value & SDHC_TRNMOD_MASK); 1240 MASKED_WRITE(s->cmdreg, mask >> 16, value >> 16); 1241 1242 /* Writing to the upper byte of CMDREG triggers SD command generation */ 1243 if ((mask & 0xFF000000) || !sdhci_can_issue_command(s)) { 1244 break; 1245 } 1246 1247 sdhci_send_command(s); 1248 break; 1249 case SDHC_BDATA: 1250 if (sdhci_buff_access_is_sequential(s, offset - SDHC_BDATA)) { 1251 sdhci_write_dataport(s, value >> shift, size); 1252 } 1253 break; 1254 case SDHC_HOSTCTL: 1255 if (!(mask & 0xFF0000)) { 1256 sdhci_blkgap_write(s, value >> 16); 1257 } 1258 MASKED_WRITE(s->hostctl1, mask, value); 1259 MASKED_WRITE(s->pwrcon, mask >> 8, value >> 8); 1260 MASKED_WRITE(s->wakcon, mask >> 24, value >> 24); 1261 if (!(s->prnsts & SDHC_CARD_PRESENT) || ((s->pwrcon >> 1) & 0x7) < 5 || 1262 !(s->capareg & (1 << (31 - ((s->pwrcon >> 1) & 0x7))))) { 1263 s->pwrcon &= ~SDHC_POWER_ON; 1264 } 1265 break; 1266 case SDHC_CLKCON: 1267 if (!(mask & 0xFF000000)) { 1268 sdhci_reset_write(s, value >> 24); 1269 } 1270 MASKED_WRITE(s->clkcon, mask, value); 1271 MASKED_WRITE(s->timeoutcon, mask >> 16, value >> 16); 1272 if (s->clkcon & SDHC_CLOCK_INT_EN) { 1273 s->clkcon |= SDHC_CLOCK_INT_STABLE; 1274 } else { 1275 s->clkcon &= ~SDHC_CLOCK_INT_STABLE; 1276 } 1277 break; 1278 case SDHC_NORINTSTS: 1279 if (s->norintstsen & SDHC_NISEN_CARDINT) { 1280 value &= ~SDHC_NIS_CARDINT; 1281 } 1282 s->norintsts &= mask | ~value; 1283 s->errintsts &= (mask >> 16) | ~(value >> 16); 1284 if (s->errintsts) { 1285 s->norintsts |= SDHC_NIS_ERR; 1286 } else { 1287 s->norintsts &= ~SDHC_NIS_ERR; 1288 } 1289 sdhci_update_irq(s); 1290 break; 1291 case SDHC_NORINTSTSEN: 1292 MASKED_WRITE(s->norintstsen, mask, value); 1293 MASKED_WRITE(s->errintstsen, mask >> 16, value >> 16); 1294 s->norintsts &= s->norintstsen; 1295 s->errintsts &= s->errintstsen; 1296 if (s->errintsts) { 1297 s->norintsts |= SDHC_NIS_ERR; 1298 } else { 1299 s->norintsts &= ~SDHC_NIS_ERR; 1300 } 1301 /* 1302 * Quirk for Raspberry Pi: pending card insert interrupt 1303 * appears when first enabled after power on 1304 */ 1305 if ((s->norintstsen & SDHC_NISEN_INSERT) && s->pending_insert_state) { 1306 assert(s->pending_insert_quirk); 1307 s->norintsts |= SDHC_NIS_INSERT; 1308 s->pending_insert_state = false; 1309 } 1310 sdhci_update_irq(s); 1311 break; 1312 case SDHC_NORINTSIGEN: 1313 MASKED_WRITE(s->norintsigen, mask, value); 1314 MASKED_WRITE(s->errintsigen, mask >> 16, value >> 16); 1315 sdhci_update_irq(s); 1316 break; 1317 case SDHC_ADMAERR: 1318 MASKED_WRITE(s->admaerr, mask, value); 1319 break; 1320 case SDHC_ADMASYSADDR: 1321 s->admasysaddr = (s->admasysaddr & (0xFFFFFFFF00000000ULL | 1322 (uint64_t)mask)) | (uint64_t)value; 1323 break; 1324 case SDHC_ADMASYSADDR + 4: 1325 s->admasysaddr = (s->admasysaddr & (0x00000000FFFFFFFFULL | 1326 ((uint64_t)mask << 32))) | ((uint64_t)value << 32); 1327 break; 1328 case SDHC_FEAER: 1329 s->acmd12errsts |= value; 1330 s->errintsts |= (value >> 16) & s->errintstsen; 1331 if (s->acmd12errsts) { 1332 s->errintsts |= SDHC_EIS_CMD12ERR; 1333 } 1334 if (s->errintsts) { 1335 s->norintsts |= SDHC_NIS_ERR; 1336 } 1337 sdhci_update_irq(s); 1338 break; 1339 case SDHC_ACMD12ERRSTS: 1340 MASKED_WRITE(s->acmd12errsts, mask, value & UINT16_MAX); 1341 if (s->uhs_mode >= UHS_I) { 1342 MASKED_WRITE(s->hostctl2, mask >> 16, value >> 16); 1343 1344 if (FIELD_EX32(s->hostctl2, SDHC_HOSTCTL2, V18_ENA)) { 1345 sdbus_set_voltage(&s->sdbus, SD_VOLTAGE_1_8V); 1346 } else { 1347 sdbus_set_voltage(&s->sdbus, SD_VOLTAGE_3_3V); 1348 } 1349 } 1350 break; 1351 1352 case SDHC_CAPAB: 1353 case SDHC_CAPAB + 4: 1354 case SDHC_MAXCURR: 1355 case SDHC_MAXCURR + 4: 1356 qemu_log_mask(LOG_GUEST_ERROR, "SDHC wr_%ub @0x%02" HWADDR_PRIx 1357 " <- 0x%08x read-only\n", size, offset, value >> shift); 1358 break; 1359 1360 default: 1361 qemu_log_mask(LOG_UNIMP, "SDHC wr_%ub @0x%02" HWADDR_PRIx " <- 0x%08x " 1362 "not implemented\n", size, offset, value >> shift); 1363 break; 1364 } 1365 trace_sdhci_access("wr", size << 3, offset, "<-", 1366 value >> shift, value >> shift); 1367 } 1368 1369 static const MemoryRegionOps sdhci_mmio_le_ops = { 1370 .read = sdhci_read, 1371 .write = sdhci_write, 1372 .valid = { 1373 .min_access_size = 1, 1374 .max_access_size = 4, 1375 .unaligned = false 1376 }, 1377 .endianness = DEVICE_LITTLE_ENDIAN, 1378 }; 1379 1380 static const MemoryRegionOps sdhci_mmio_be_ops = { 1381 .read = sdhci_read, 1382 .write = sdhci_write, 1383 .impl = { 1384 .min_access_size = 4, 1385 .max_access_size = 4, 1386 }, 1387 .valid = { 1388 .min_access_size = 1, 1389 .max_access_size = 4, 1390 .unaligned = false 1391 }, 1392 .endianness = DEVICE_BIG_ENDIAN, 1393 }; 1394 1395 static void sdhci_init_readonly_registers(SDHCIState *s, Error **errp) 1396 { 1397 ERRP_GUARD(); 1398 1399 switch (s->sd_spec_version) { 1400 case 2 ... 3: 1401 break; 1402 default: 1403 error_setg(errp, "Only Spec v2/v3 are supported"); 1404 return; 1405 } 1406 s->version = (SDHC_HCVER_VENDOR << 8) | (s->sd_spec_version - 1); 1407 1408 sdhci_check_capareg(s, errp); 1409 if (*errp) { 1410 return; 1411 } 1412 } 1413 1414 /* --- qdev common --- */ 1415 1416 void sdhci_initfn(SDHCIState *s) 1417 { 1418 qbus_init(&s->sdbus, sizeof(s->sdbus), TYPE_SDHCI_BUS, DEVICE(s), "sd-bus"); 1419 1420 s->insert_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, 1421 sdhci_raise_insertion_irq, s); 1422 s->transfer_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, 1423 sdhci_data_transfer, s); 1424 1425 s->io_ops = &sdhci_mmio_le_ops; 1426 } 1427 1428 void sdhci_uninitfn(SDHCIState *s) 1429 { 1430 timer_free(s->insert_timer); 1431 timer_free(s->transfer_timer); 1432 1433 g_free(s->fifo_buffer); 1434 s->fifo_buffer = NULL; 1435 } 1436 1437 void sdhci_common_realize(SDHCIState *s, Error **errp) 1438 { 1439 ERRP_GUARD(); 1440 1441 switch (s->endianness) { 1442 case DEVICE_LITTLE_ENDIAN: 1443 /* s->io_ops is little endian by default */ 1444 break; 1445 case DEVICE_BIG_ENDIAN: 1446 if (s->io_ops != &sdhci_mmio_le_ops) { 1447 error_setg(errp, "SD controller doesn't support big endianness"); 1448 return; 1449 } 1450 s->io_ops = &sdhci_mmio_be_ops; 1451 break; 1452 default: 1453 error_setg(errp, "Incorrect endianness"); 1454 return; 1455 } 1456 1457 sdhci_init_readonly_registers(s, errp); 1458 if (*errp) { 1459 return; 1460 } 1461 1462 s->buf_maxsz = sdhci_get_fifolen(s); 1463 s->fifo_buffer = g_malloc0(s->buf_maxsz); 1464 1465 memory_region_init_io(&s->iomem, OBJECT(s), s->io_ops, s, "sdhci", 1466 SDHC_REGISTERS_MAP_SIZE); 1467 } 1468 1469 void sdhci_common_unrealize(SDHCIState *s) 1470 { 1471 /* 1472 * This function is expected to be called only once for each class: 1473 * - SysBus: via DeviceClass->unrealize(), 1474 * - PCI: via PCIDeviceClass->exit(). 1475 * However to avoid double-free and/or use-after-free we still nullify 1476 * this variable (better safe than sorry!). 1477 */ 1478 g_free(s->fifo_buffer); 1479 s->fifo_buffer = NULL; 1480 } 1481 1482 static bool sdhci_pending_insert_vmstate_needed(void *opaque) 1483 { 1484 SDHCIState *s = opaque; 1485 1486 return s->pending_insert_state; 1487 } 1488 1489 static const VMStateDescription sdhci_pending_insert_vmstate = { 1490 .name = "sdhci/pending-insert", 1491 .version_id = 1, 1492 .minimum_version_id = 1, 1493 .needed = sdhci_pending_insert_vmstate_needed, 1494 .fields = (const VMStateField[]) { 1495 VMSTATE_BOOL(pending_insert_state, SDHCIState), 1496 VMSTATE_END_OF_LIST() 1497 }, 1498 }; 1499 1500 const VMStateDescription sdhci_vmstate = { 1501 .name = "sdhci", 1502 .version_id = 1, 1503 .minimum_version_id = 1, 1504 .fields = (const VMStateField[]) { 1505 VMSTATE_UINT32(sdmasysad, SDHCIState), 1506 VMSTATE_UINT16(blksize, SDHCIState), 1507 VMSTATE_UINT16(blkcnt, SDHCIState), 1508 VMSTATE_UINT32(argument, SDHCIState), 1509 VMSTATE_UINT16(trnmod, SDHCIState), 1510 VMSTATE_UINT16(cmdreg, SDHCIState), 1511 VMSTATE_UINT32_ARRAY(rspreg, SDHCIState, 4), 1512 VMSTATE_UINT32(prnsts, SDHCIState), 1513 VMSTATE_UINT8(hostctl1, SDHCIState), 1514 VMSTATE_UINT8(pwrcon, SDHCIState), 1515 VMSTATE_UINT8(blkgap, SDHCIState), 1516 VMSTATE_UINT8(wakcon, SDHCIState), 1517 VMSTATE_UINT16(clkcon, SDHCIState), 1518 VMSTATE_UINT8(timeoutcon, SDHCIState), 1519 VMSTATE_UINT8(admaerr, SDHCIState), 1520 VMSTATE_UINT16(norintsts, SDHCIState), 1521 VMSTATE_UINT16(errintsts, SDHCIState), 1522 VMSTATE_UINT16(norintstsen, SDHCIState), 1523 VMSTATE_UINT16(errintstsen, SDHCIState), 1524 VMSTATE_UINT16(norintsigen, SDHCIState), 1525 VMSTATE_UINT16(errintsigen, SDHCIState), 1526 VMSTATE_UINT16(acmd12errsts, SDHCIState), 1527 VMSTATE_UINT16(data_count, SDHCIState), 1528 VMSTATE_UINT64(admasysaddr, SDHCIState), 1529 VMSTATE_UINT8(stopped_state, SDHCIState), 1530 VMSTATE_VBUFFER_UINT32(fifo_buffer, SDHCIState, 1, NULL, buf_maxsz), 1531 VMSTATE_TIMER_PTR(insert_timer, SDHCIState), 1532 VMSTATE_TIMER_PTR(transfer_timer, SDHCIState), 1533 VMSTATE_END_OF_LIST() 1534 }, 1535 .subsections = (const VMStateDescription * const []) { 1536 &sdhci_pending_insert_vmstate, 1537 NULL 1538 }, 1539 }; 1540 1541 void sdhci_common_class_init(ObjectClass *klass, void *data) 1542 { 1543 DeviceClass *dc = DEVICE_CLASS(klass); 1544 1545 set_bit(DEVICE_CATEGORY_STORAGE, dc->categories); 1546 dc->vmsd = &sdhci_vmstate; 1547 device_class_set_legacy_reset(dc, sdhci_poweron_reset); 1548 } 1549 1550 /* --- qdev SysBus --- */ 1551 1552 static const Property sdhci_sysbus_properties[] = { 1553 DEFINE_SDHCI_COMMON_PROPERTIES(SDHCIState), 1554 DEFINE_PROP_BOOL("pending-insert-quirk", SDHCIState, pending_insert_quirk, 1555 false), 1556 DEFINE_PROP_LINK("dma", SDHCIState, 1557 dma_mr, TYPE_MEMORY_REGION, MemoryRegion *), 1558 }; 1559 1560 static void sdhci_sysbus_init(Object *obj) 1561 { 1562 SDHCIState *s = SYSBUS_SDHCI(obj); 1563 1564 sdhci_initfn(s); 1565 } 1566 1567 static void sdhci_sysbus_finalize(Object *obj) 1568 { 1569 SDHCIState *s = SYSBUS_SDHCI(obj); 1570 1571 if (s->dma_mr) { 1572 object_unparent(OBJECT(s->dma_mr)); 1573 } 1574 1575 sdhci_uninitfn(s); 1576 } 1577 1578 static void sdhci_sysbus_realize(DeviceState *dev, Error **errp) 1579 { 1580 ERRP_GUARD(); 1581 SDHCIState *s = SYSBUS_SDHCI(dev); 1582 SysBusDevice *sbd = SYS_BUS_DEVICE(dev); 1583 1584 sdhci_common_realize(s, errp); 1585 if (*errp) { 1586 return; 1587 } 1588 1589 if (s->dma_mr) { 1590 s->dma_as = &s->sysbus_dma_as; 1591 address_space_init(s->dma_as, s->dma_mr, "sdhci-dma"); 1592 } else { 1593 /* use system_memory() if property "dma" not set */ 1594 s->dma_as = &address_space_memory; 1595 } 1596 1597 sysbus_init_irq(sbd, &s->irq); 1598 1599 sysbus_init_mmio(sbd, &s->iomem); 1600 } 1601 1602 static void sdhci_sysbus_unrealize(DeviceState *dev) 1603 { 1604 SDHCIState *s = SYSBUS_SDHCI(dev); 1605 1606 sdhci_common_unrealize(s); 1607 1608 if (s->dma_mr) { 1609 address_space_destroy(s->dma_as); 1610 } 1611 } 1612 1613 static void sdhci_sysbus_class_init(ObjectClass *klass, void *data) 1614 { 1615 DeviceClass *dc = DEVICE_CLASS(klass); 1616 1617 device_class_set_props(dc, sdhci_sysbus_properties); 1618 dc->realize = sdhci_sysbus_realize; 1619 dc->unrealize = sdhci_sysbus_unrealize; 1620 1621 sdhci_common_class_init(klass, data); 1622 } 1623 1624 /* --- qdev bus master --- */ 1625 1626 static void sdhci_bus_class_init(ObjectClass *klass, void *data) 1627 { 1628 SDBusClass *sbc = SD_BUS_CLASS(klass); 1629 1630 sbc->set_inserted = sdhci_set_inserted; 1631 sbc->set_readonly = sdhci_set_readonly; 1632 } 1633 1634 /* --- qdev i.MX eSDHC --- */ 1635 1636 #define USDHC_MIX_CTRL 0x48 1637 1638 #define USDHC_VENDOR_SPEC 0xc0 1639 #define USDHC_IMX_FRC_SDCLK_ON (1 << 8) 1640 1641 #define USDHC_DLL_CTRL 0x60 1642 1643 #define USDHC_TUNING_CTRL 0xcc 1644 #define USDHC_TUNE_CTRL_STATUS 0x68 1645 #define USDHC_WTMK_LVL 0x44 1646 1647 /* Undocumented register used by guests working around erratum ERR004536 */ 1648 #define USDHC_UNDOCUMENTED_REG27 0x6c 1649 1650 #define USDHC_CTRL_4BITBUS (0x1 << 1) 1651 #define USDHC_CTRL_8BITBUS (0x2 << 1) 1652 1653 #define USDHC_PRNSTS_SDSTB (1 << 3) 1654 1655 static uint64_t usdhc_read(void *opaque, hwaddr offset, unsigned size) 1656 { 1657 SDHCIState *s = SYSBUS_SDHCI(opaque); 1658 uint32_t ret; 1659 uint16_t hostctl1; 1660 1661 switch (offset) { 1662 default: 1663 return sdhci_read(opaque, offset, size); 1664 1665 case SDHC_HOSTCTL: 1666 /* 1667 * For a detailed explanation on the following bit 1668 * manipulation code see comments in a similar part of 1669 * usdhc_write() 1670 */ 1671 hostctl1 = SDHC_DMA_TYPE(s->hostctl1) << (8 - 3); 1672 1673 if (s->hostctl1 & SDHC_CTRL_8BITBUS) { 1674 hostctl1 |= USDHC_CTRL_8BITBUS; 1675 } 1676 1677 if (s->hostctl1 & SDHC_CTRL_4BITBUS) { 1678 hostctl1 |= USDHC_CTRL_4BITBUS; 1679 } 1680 1681 ret = hostctl1; 1682 ret |= (uint32_t)s->blkgap << 16; 1683 ret |= (uint32_t)s->wakcon << 24; 1684 1685 break; 1686 1687 case SDHC_PRNSTS: 1688 /* Add SDSTB (SD Clock Stable) bit to PRNSTS */ 1689 ret = sdhci_read(opaque, offset, size) & ~USDHC_PRNSTS_SDSTB; 1690 if (s->clkcon & SDHC_CLOCK_INT_STABLE) { 1691 ret |= USDHC_PRNSTS_SDSTB; 1692 } 1693 break; 1694 1695 case USDHC_VENDOR_SPEC: 1696 ret = s->vendor_spec; 1697 break; 1698 case USDHC_DLL_CTRL: 1699 case USDHC_TUNE_CTRL_STATUS: 1700 case USDHC_UNDOCUMENTED_REG27: 1701 case USDHC_TUNING_CTRL: 1702 case USDHC_MIX_CTRL: 1703 case USDHC_WTMK_LVL: 1704 ret = 0; 1705 break; 1706 } 1707 1708 return ret; 1709 } 1710 1711 static void 1712 usdhc_write(void *opaque, hwaddr offset, uint64_t val, unsigned size) 1713 { 1714 SDHCIState *s = SYSBUS_SDHCI(opaque); 1715 uint8_t hostctl1; 1716 uint32_t value = (uint32_t)val; 1717 1718 switch (offset) { 1719 case USDHC_DLL_CTRL: 1720 case USDHC_TUNE_CTRL_STATUS: 1721 case USDHC_UNDOCUMENTED_REG27: 1722 case USDHC_TUNING_CTRL: 1723 case USDHC_WTMK_LVL: 1724 break; 1725 1726 case USDHC_VENDOR_SPEC: 1727 s->vendor_spec = value; 1728 switch (s->vendor) { 1729 case SDHCI_VENDOR_IMX: 1730 if (value & USDHC_IMX_FRC_SDCLK_ON) { 1731 s->prnsts &= ~SDHC_IMX_CLOCK_GATE_OFF; 1732 } else { 1733 s->prnsts |= SDHC_IMX_CLOCK_GATE_OFF; 1734 } 1735 break; 1736 default: 1737 break; 1738 } 1739 break; 1740 1741 case SDHC_HOSTCTL: 1742 /* 1743 * Here's What ESDHCI has at offset 0x28 (SDHC_HOSTCTL) 1744 * 1745 * 7 6 5 4 3 2 1 0 1746 * |-----------+--------+--------+-----------+----------+---------| 1747 * | Card | Card | Endian | DATA3 | Data | Led | 1748 * | Detect | Detect | Mode | as Card | Transfer | Control | 1749 * | Signal | Test | | Detection | Width | | 1750 * | Selection | Level | | Pin | | | 1751 * |-----------+--------+--------+-----------+----------+---------| 1752 * 1753 * and 0x29 1754 * 1755 * 15 10 9 8 1756 * |----------+------| 1757 * | Reserved | DMA | 1758 * | | Sel. | 1759 * | | | 1760 * |----------+------| 1761 * 1762 * and here's what SDCHI spec expects those offsets to be: 1763 * 1764 * 0x28 (Host Control Register) 1765 * 1766 * 7 6 5 4 3 2 1 0 1767 * |--------+--------+----------+------+--------+----------+---------| 1768 * | Card | Card | Extended | DMA | High | Data | LED | 1769 * | Detect | Detect | Data | Sel. | Speed | Transfer | Control | 1770 * | Signal | Test | Transfer | | Enable | Width | | 1771 * | Sel. | Level | Width | | | | | 1772 * |--------+--------+----------+------+--------+----------+---------| 1773 * 1774 * and 0x29 (Power Control Register) 1775 * 1776 * |----------------------------------| 1777 * | Power Control Register | 1778 * | | 1779 * | Description omitted, | 1780 * | since it has no analog in ESDHCI | 1781 * | | 1782 * |----------------------------------| 1783 * 1784 * Since offsets 0x2A and 0x2B should be compatible between 1785 * both IP specs we only need to reconcile least 16-bit of the 1786 * word we've been given. 1787 */ 1788 1789 /* 1790 * First, save bits 7 6 and 0 since they are identical 1791 */ 1792 hostctl1 = value & (SDHC_CTRL_LED | 1793 SDHC_CTRL_CDTEST_INS | 1794 SDHC_CTRL_CDTEST_EN); 1795 /* 1796 * Second, split "Data Transfer Width" from bits 2 and 1 in to 1797 * bits 5 and 1 1798 */ 1799 if (value & USDHC_CTRL_8BITBUS) { 1800 hostctl1 |= SDHC_CTRL_8BITBUS; 1801 } 1802 1803 if (value & USDHC_CTRL_4BITBUS) { 1804 hostctl1 |= USDHC_CTRL_4BITBUS; 1805 } 1806 1807 /* 1808 * Third, move DMA select from bits 9 and 8 to bits 4 and 3 1809 */ 1810 hostctl1 |= SDHC_DMA_TYPE(value >> (8 - 3)); 1811 1812 /* 1813 * Now place the corrected value into low 16-bit of the value 1814 * we are going to give standard SDHCI write function 1815 * 1816 * NOTE: This transformation should be the inverse of what can 1817 * be found in drivers/mmc/host/sdhci-esdhc-imx.c in Linux 1818 * kernel 1819 */ 1820 value &= ~UINT16_MAX; 1821 value |= hostctl1; 1822 value |= (uint16_t)s->pwrcon << 8; 1823 1824 sdhci_write(opaque, offset, value, size); 1825 break; 1826 1827 case USDHC_MIX_CTRL: 1828 /* 1829 * So, when SD/MMC stack in Linux tries to write to "Transfer 1830 * Mode Register", ESDHC i.MX quirk code will translate it 1831 * into a write to ESDHC_MIX_CTRL, so we do the opposite in 1832 * order to get where we started 1833 * 1834 * Note that Auto CMD23 Enable bit is located in a wrong place 1835 * on i.MX, but since it is not used by QEMU we do not care. 1836 * 1837 * We don't want to call sdhci_write(.., SDHC_TRNMOD, ...) 1838 * here because it will result in a call to 1839 * sdhci_send_command(s) which we don't want. 1840 * 1841 */ 1842 s->trnmod = value & UINT16_MAX; 1843 break; 1844 case SDHC_TRNMOD: 1845 /* 1846 * Similar to above, but this time a write to "Command 1847 * Register" will be translated into a 4-byte write to 1848 * "Transfer Mode register" where lower 16-bit of value would 1849 * be set to zero. So what we do is fill those bits with 1850 * cached value from s->trnmod and let the SDHCI 1851 * infrastructure handle the rest 1852 */ 1853 sdhci_write(opaque, offset, val | s->trnmod, size); 1854 break; 1855 case SDHC_BLKSIZE: 1856 /* 1857 * ESDHCI does not implement "Host SDMA Buffer Boundary", and 1858 * Linux driver will try to zero this field out which will 1859 * break the rest of SDHCI emulation. 1860 * 1861 * Linux defaults to maximum possible setting (512K boundary) 1862 * and it seems to be the only option that i.MX IP implements, 1863 * so we artificially set it to that value. 1864 */ 1865 val |= 0x7 << 12; 1866 /* FALLTHROUGH */ 1867 default: 1868 sdhci_write(opaque, offset, val, size); 1869 break; 1870 } 1871 } 1872 1873 static const MemoryRegionOps usdhc_mmio_ops = { 1874 .read = usdhc_read, 1875 .write = usdhc_write, 1876 .valid = { 1877 .min_access_size = 1, 1878 .max_access_size = 4, 1879 .unaligned = false 1880 }, 1881 .endianness = DEVICE_LITTLE_ENDIAN, 1882 }; 1883 1884 static void imx_usdhc_init(Object *obj) 1885 { 1886 SDHCIState *s = SYSBUS_SDHCI(obj); 1887 1888 s->io_ops = &usdhc_mmio_ops; 1889 s->quirks = SDHCI_QUIRK_NO_BUSY_IRQ; 1890 } 1891 1892 /* --- qdev Samsung s3c --- */ 1893 1894 #define S3C_SDHCI_CONTROL2 0x80 1895 #define S3C_SDHCI_CONTROL3 0x84 1896 #define S3C_SDHCI_CONTROL4 0x8c 1897 1898 static uint64_t sdhci_s3c_read(void *opaque, hwaddr offset, unsigned size) 1899 { 1900 uint64_t ret; 1901 1902 switch (offset) { 1903 case S3C_SDHCI_CONTROL2: 1904 case S3C_SDHCI_CONTROL3: 1905 case S3C_SDHCI_CONTROL4: 1906 /* ignore */ 1907 ret = 0; 1908 break; 1909 default: 1910 ret = sdhci_read(opaque, offset, size); 1911 break; 1912 } 1913 1914 return ret; 1915 } 1916 1917 static void sdhci_s3c_write(void *opaque, hwaddr offset, uint64_t val, 1918 unsigned size) 1919 { 1920 switch (offset) { 1921 case S3C_SDHCI_CONTROL2: 1922 case S3C_SDHCI_CONTROL3: 1923 case S3C_SDHCI_CONTROL4: 1924 /* ignore */ 1925 break; 1926 default: 1927 sdhci_write(opaque, offset, val, size); 1928 break; 1929 } 1930 } 1931 1932 static const MemoryRegionOps sdhci_s3c_mmio_ops = { 1933 .read = sdhci_s3c_read, 1934 .write = sdhci_s3c_write, 1935 .valid = { 1936 .min_access_size = 1, 1937 .max_access_size = 4, 1938 .unaligned = false 1939 }, 1940 .endianness = DEVICE_LITTLE_ENDIAN, 1941 }; 1942 1943 static void sdhci_s3c_init(Object *obj) 1944 { 1945 SDHCIState *s = SYSBUS_SDHCI(obj); 1946 1947 s->io_ops = &sdhci_s3c_mmio_ops; 1948 } 1949 1950 static const TypeInfo sdhci_types[] = { 1951 { 1952 .name = TYPE_SDHCI_BUS, 1953 .parent = TYPE_SD_BUS, 1954 .instance_size = sizeof(SDBus), 1955 .class_init = sdhci_bus_class_init, 1956 }, 1957 { 1958 .name = TYPE_SYSBUS_SDHCI, 1959 .parent = TYPE_SYS_BUS_DEVICE, 1960 .instance_size = sizeof(SDHCIState), 1961 .instance_init = sdhci_sysbus_init, 1962 .instance_finalize = sdhci_sysbus_finalize, 1963 .class_init = sdhci_sysbus_class_init, 1964 }, 1965 { 1966 .name = TYPE_IMX_USDHC, 1967 .parent = TYPE_SYSBUS_SDHCI, 1968 .instance_init = imx_usdhc_init, 1969 }, 1970 { 1971 .name = TYPE_S3C_SDHCI, 1972 .parent = TYPE_SYSBUS_SDHCI, 1973 .instance_init = sdhci_s3c_init, 1974 }, 1975 }; 1976 1977 DEFINE_TYPES(sdhci_types) 1978