1 /* 2 * SD Association Host Standard Specification v2.0 controller emulation 3 * 4 * Datasheet: PartA2_SD_Host_Controller_Simplified_Specification_Ver2.00.pdf 5 * 6 * Copyright (c) 2011 Samsung Electronics Co., Ltd. 7 * Mitsyanko Igor <i.mitsyanko@samsung.com> 8 * Peter A.G. Crosthwaite <peter.crosthwaite@petalogix.com> 9 * 10 * Based on MMC controller for Samsung S5PC1xx-based board emulation 11 * by Alexey Merkulov and Vladimir Monakhov. 12 * 13 * This program is free software; you can redistribute it and/or modify it 14 * under the terms of the GNU General Public License as published by the 15 * Free Software Foundation; either version 2 of the License, or (at your 16 * option) any later version. 17 * 18 * This program is distributed in the hope that it will be useful, 19 * but WITHOUT ANY WARRANTY; without even the implied warranty of 20 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. 21 * See the GNU General Public License for more details. 22 * 23 * You should have received a copy of the GNU General Public License along 24 * with this program; if not, see <http://www.gnu.org/licenses/>. 25 */ 26 27 #include "qemu/osdep.h" 28 #include "qemu/units.h" 29 #include "qemu/error-report.h" 30 #include "qapi/error.h" 31 #include "hw/irq.h" 32 #include "hw/qdev-properties.h" 33 #include "sysemu/dma.h" 34 #include "qemu/timer.h" 35 #include "qemu/bitops.h" 36 #include "hw/sd/sdhci.h" 37 #include "migration/vmstate.h" 38 #include "sdhci-internal.h" 39 #include "qemu/log.h" 40 #include "qemu/module.h" 41 #include "trace.h" 42 #include "qom/object.h" 43 44 #define TYPE_SDHCI_BUS "sdhci-bus" 45 /* This is reusing the SDBus typedef from SD_BUS */ 46 DECLARE_INSTANCE_CHECKER(SDBus, SDHCI_BUS, 47 TYPE_SDHCI_BUS) 48 49 #define MASKED_WRITE(reg, mask, val) (reg = (reg & (mask)) | (val)) 50 51 static inline unsigned int sdhci_get_fifolen(SDHCIState *s) 52 { 53 return 1 << (9 + FIELD_EX32(s->capareg, SDHC_CAPAB, MAXBLOCKLENGTH)); 54 } 55 56 /* return true on error */ 57 static bool sdhci_check_capab_freq_range(SDHCIState *s, const char *desc, 58 uint8_t freq, Error **errp) 59 { 60 if (s->sd_spec_version >= 3) { 61 return false; 62 } 63 switch (freq) { 64 case 0: 65 case 10 ... 63: 66 break; 67 default: 68 error_setg(errp, "SD %s clock frequency can have value" 69 "in range 0-63 only", desc); 70 return true; 71 } 72 return false; 73 } 74 75 static void sdhci_check_capareg(SDHCIState *s, Error **errp) 76 { 77 uint64_t msk = s->capareg; 78 uint32_t val; 79 bool y; 80 81 switch (s->sd_spec_version) { 82 case 4: 83 val = FIELD_EX64(s->capareg, SDHC_CAPAB, BUS64BIT_V4); 84 trace_sdhci_capareg("64-bit system bus (v4)", val); 85 msk = FIELD_DP64(msk, SDHC_CAPAB, BUS64BIT_V4, 0); 86 87 val = FIELD_EX64(s->capareg, SDHC_CAPAB, UHS_II); 88 trace_sdhci_capareg("UHS-II", val); 89 msk = FIELD_DP64(msk, SDHC_CAPAB, UHS_II, 0); 90 91 val = FIELD_EX64(s->capareg, SDHC_CAPAB, ADMA3); 92 trace_sdhci_capareg("ADMA3", val); 93 msk = FIELD_DP64(msk, SDHC_CAPAB, ADMA3, 0); 94 95 /* fallthrough */ 96 case 3: 97 val = FIELD_EX64(s->capareg, SDHC_CAPAB, ASYNC_INT); 98 trace_sdhci_capareg("async interrupt", val); 99 msk = FIELD_DP64(msk, SDHC_CAPAB, ASYNC_INT, 0); 100 101 val = FIELD_EX64(s->capareg, SDHC_CAPAB, SLOT_TYPE); 102 if (val) { 103 error_setg(errp, "slot-type not supported"); 104 return; 105 } 106 trace_sdhci_capareg("slot type", val); 107 msk = FIELD_DP64(msk, SDHC_CAPAB, SLOT_TYPE, 0); 108 109 if (val != 2) { 110 val = FIELD_EX64(s->capareg, SDHC_CAPAB, EMBEDDED_8BIT); 111 trace_sdhci_capareg("8-bit bus", val); 112 } 113 msk = FIELD_DP64(msk, SDHC_CAPAB, EMBEDDED_8BIT, 0); 114 115 val = FIELD_EX64(s->capareg, SDHC_CAPAB, BUS_SPEED); 116 trace_sdhci_capareg("bus speed mask", val); 117 msk = FIELD_DP64(msk, SDHC_CAPAB, BUS_SPEED, 0); 118 119 val = FIELD_EX64(s->capareg, SDHC_CAPAB, DRIVER_STRENGTH); 120 trace_sdhci_capareg("driver strength mask", val); 121 msk = FIELD_DP64(msk, SDHC_CAPAB, DRIVER_STRENGTH, 0); 122 123 val = FIELD_EX64(s->capareg, SDHC_CAPAB, TIMER_RETUNING); 124 trace_sdhci_capareg("timer re-tuning", val); 125 msk = FIELD_DP64(msk, SDHC_CAPAB, TIMER_RETUNING, 0); 126 127 val = FIELD_EX64(s->capareg, SDHC_CAPAB, SDR50_TUNING); 128 trace_sdhci_capareg("use SDR50 tuning", val); 129 msk = FIELD_DP64(msk, SDHC_CAPAB, SDR50_TUNING, 0); 130 131 val = FIELD_EX64(s->capareg, SDHC_CAPAB, RETUNING_MODE); 132 trace_sdhci_capareg("re-tuning mode", val); 133 msk = FIELD_DP64(msk, SDHC_CAPAB, RETUNING_MODE, 0); 134 135 val = FIELD_EX64(s->capareg, SDHC_CAPAB, CLOCK_MULT); 136 trace_sdhci_capareg("clock multiplier", val); 137 msk = FIELD_DP64(msk, SDHC_CAPAB, CLOCK_MULT, 0); 138 139 /* fallthrough */ 140 case 2: /* default version */ 141 val = FIELD_EX64(s->capareg, SDHC_CAPAB, ADMA2); 142 trace_sdhci_capareg("ADMA2", val); 143 msk = FIELD_DP64(msk, SDHC_CAPAB, ADMA2, 0); 144 145 val = FIELD_EX64(s->capareg, SDHC_CAPAB, ADMA1); 146 trace_sdhci_capareg("ADMA1", val); 147 msk = FIELD_DP64(msk, SDHC_CAPAB, ADMA1, 0); 148 149 val = FIELD_EX64(s->capareg, SDHC_CAPAB, BUS64BIT); 150 trace_sdhci_capareg("64-bit system bus (v3)", val); 151 msk = FIELD_DP64(msk, SDHC_CAPAB, BUS64BIT, 0); 152 153 /* fallthrough */ 154 case 1: 155 y = FIELD_EX64(s->capareg, SDHC_CAPAB, TOUNIT); 156 msk = FIELD_DP64(msk, SDHC_CAPAB, TOUNIT, 0); 157 158 val = FIELD_EX64(s->capareg, SDHC_CAPAB, TOCLKFREQ); 159 trace_sdhci_capareg(y ? "timeout (MHz)" : "Timeout (KHz)", val); 160 if (sdhci_check_capab_freq_range(s, "timeout", val, errp)) { 161 return; 162 } 163 msk = FIELD_DP64(msk, SDHC_CAPAB, TOCLKFREQ, 0); 164 165 val = FIELD_EX64(s->capareg, SDHC_CAPAB, BASECLKFREQ); 166 trace_sdhci_capareg(y ? "base (MHz)" : "Base (KHz)", val); 167 if (sdhci_check_capab_freq_range(s, "base", val, errp)) { 168 return; 169 } 170 msk = FIELD_DP64(msk, SDHC_CAPAB, BASECLKFREQ, 0); 171 172 val = FIELD_EX64(s->capareg, SDHC_CAPAB, MAXBLOCKLENGTH); 173 if (val >= 3) { 174 error_setg(errp, "block size can be 512, 1024 or 2048 only"); 175 return; 176 } 177 trace_sdhci_capareg("max block length", sdhci_get_fifolen(s)); 178 msk = FIELD_DP64(msk, SDHC_CAPAB, MAXBLOCKLENGTH, 0); 179 180 val = FIELD_EX64(s->capareg, SDHC_CAPAB, HIGHSPEED); 181 trace_sdhci_capareg("high speed", val); 182 msk = FIELD_DP64(msk, SDHC_CAPAB, HIGHSPEED, 0); 183 184 val = FIELD_EX64(s->capareg, SDHC_CAPAB, SDMA); 185 trace_sdhci_capareg("SDMA", val); 186 msk = FIELD_DP64(msk, SDHC_CAPAB, SDMA, 0); 187 188 val = FIELD_EX64(s->capareg, SDHC_CAPAB, SUSPRESUME); 189 trace_sdhci_capareg("suspend/resume", val); 190 msk = FIELD_DP64(msk, SDHC_CAPAB, SUSPRESUME, 0); 191 192 val = FIELD_EX64(s->capareg, SDHC_CAPAB, V33); 193 trace_sdhci_capareg("3.3v", val); 194 msk = FIELD_DP64(msk, SDHC_CAPAB, V33, 0); 195 196 val = FIELD_EX64(s->capareg, SDHC_CAPAB, V30); 197 trace_sdhci_capareg("3.0v", val); 198 msk = FIELD_DP64(msk, SDHC_CAPAB, V30, 0); 199 200 val = FIELD_EX64(s->capareg, SDHC_CAPAB, V18); 201 trace_sdhci_capareg("1.8v", val); 202 msk = FIELD_DP64(msk, SDHC_CAPAB, V18, 0); 203 break; 204 205 default: 206 error_setg(errp, "Unsupported spec version: %u", s->sd_spec_version); 207 } 208 if (msk) { 209 qemu_log_mask(LOG_UNIMP, 210 "SDHCI: unknown CAPAB mask: 0x%016" PRIx64 "\n", msk); 211 } 212 } 213 214 static uint8_t sdhci_slotint(SDHCIState *s) 215 { 216 return (s->norintsts & s->norintsigen) || (s->errintsts & s->errintsigen) || 217 ((s->norintsts & SDHC_NIS_INSERT) && (s->wakcon & SDHC_WKUP_ON_INS)) || 218 ((s->norintsts & SDHC_NIS_REMOVE) && (s->wakcon & SDHC_WKUP_ON_RMV)); 219 } 220 221 static inline void sdhci_update_irq(SDHCIState *s) 222 { 223 qemu_set_irq(s->irq, sdhci_slotint(s)); 224 } 225 226 static void sdhci_raise_insertion_irq(void *opaque) 227 { 228 SDHCIState *s = (SDHCIState *)opaque; 229 230 if (s->norintsts & SDHC_NIS_REMOVE) { 231 timer_mod(s->insert_timer, 232 qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + SDHC_INSERTION_DELAY); 233 } else { 234 s->prnsts = 0x1ff0000; 235 if (s->norintstsen & SDHC_NISEN_INSERT) { 236 s->norintsts |= SDHC_NIS_INSERT; 237 } 238 sdhci_update_irq(s); 239 } 240 } 241 242 static void sdhci_set_inserted(DeviceState *dev, bool level) 243 { 244 SDHCIState *s = (SDHCIState *)dev; 245 246 trace_sdhci_set_inserted(level ? "insert" : "eject"); 247 if ((s->norintsts & SDHC_NIS_REMOVE) && level) { 248 /* Give target some time to notice card ejection */ 249 timer_mod(s->insert_timer, 250 qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + SDHC_INSERTION_DELAY); 251 } else { 252 if (level) { 253 s->prnsts = 0x1ff0000; 254 if (s->norintstsen & SDHC_NISEN_INSERT) { 255 s->norintsts |= SDHC_NIS_INSERT; 256 } 257 } else { 258 s->prnsts = 0x1fa0000; 259 s->pwrcon &= ~SDHC_POWER_ON; 260 s->clkcon &= ~SDHC_CLOCK_SDCLK_EN; 261 if (s->norintstsen & SDHC_NISEN_REMOVE) { 262 s->norintsts |= SDHC_NIS_REMOVE; 263 } 264 } 265 sdhci_update_irq(s); 266 } 267 } 268 269 static void sdhci_set_readonly(DeviceState *dev, bool level) 270 { 271 SDHCIState *s = (SDHCIState *)dev; 272 273 if (level) { 274 s->prnsts &= ~SDHC_WRITE_PROTECT; 275 } else { 276 /* Write enabled */ 277 s->prnsts |= SDHC_WRITE_PROTECT; 278 } 279 } 280 281 static void sdhci_reset(SDHCIState *s) 282 { 283 DeviceState *dev = DEVICE(s); 284 285 timer_del(s->insert_timer); 286 timer_del(s->transfer_timer); 287 288 /* Set all registers to 0. Capabilities/Version registers are not cleared 289 * and assumed to always preserve their value, given to them during 290 * initialization */ 291 memset(&s->sdmasysad, 0, (uintptr_t)&s->capareg - (uintptr_t)&s->sdmasysad); 292 293 /* Reset other state based on current card insertion/readonly status */ 294 sdhci_set_inserted(dev, sdbus_get_inserted(&s->sdbus)); 295 sdhci_set_readonly(dev, sdbus_get_readonly(&s->sdbus)); 296 297 s->data_count = 0; 298 s->stopped_state = sdhc_not_stopped; 299 s->pending_insert_state = false; 300 } 301 302 static void sdhci_poweron_reset(DeviceState *dev) 303 { 304 /* QOM (ie power-on) reset. This is identical to reset 305 * commanded via device register apart from handling of the 306 * 'pending insert on powerup' quirk. 307 */ 308 SDHCIState *s = (SDHCIState *)dev; 309 310 sdhci_reset(s); 311 312 if (s->pending_insert_quirk) { 313 s->pending_insert_state = true; 314 } 315 } 316 317 static void sdhci_data_transfer(void *opaque); 318 319 static void sdhci_send_command(SDHCIState *s) 320 { 321 SDRequest request; 322 uint8_t response[16]; 323 int rlen; 324 325 s->errintsts = 0; 326 s->acmd12errsts = 0; 327 request.cmd = s->cmdreg >> 8; 328 request.arg = s->argument; 329 330 trace_sdhci_send_command(request.cmd, request.arg); 331 rlen = sdbus_do_command(&s->sdbus, &request, response); 332 333 if (s->cmdreg & SDHC_CMD_RESPONSE) { 334 if (rlen == 4) { 335 s->rspreg[0] = ldl_be_p(response); 336 s->rspreg[1] = s->rspreg[2] = s->rspreg[3] = 0; 337 trace_sdhci_response4(s->rspreg[0]); 338 } else if (rlen == 16) { 339 s->rspreg[0] = ldl_be_p(&response[11]); 340 s->rspreg[1] = ldl_be_p(&response[7]); 341 s->rspreg[2] = ldl_be_p(&response[3]); 342 s->rspreg[3] = (response[0] << 16) | (response[1] << 8) | 343 response[2]; 344 trace_sdhci_response16(s->rspreg[3], s->rspreg[2], 345 s->rspreg[1], s->rspreg[0]); 346 } else { 347 trace_sdhci_error("timeout waiting for command response"); 348 if (s->errintstsen & SDHC_EISEN_CMDTIMEOUT) { 349 s->errintsts |= SDHC_EIS_CMDTIMEOUT; 350 s->norintsts |= SDHC_NIS_ERR; 351 } 352 } 353 354 if (!(s->quirks & SDHCI_QUIRK_NO_BUSY_IRQ) && 355 (s->norintstsen & SDHC_NISEN_TRSCMP) && 356 (s->cmdreg & SDHC_CMD_RESPONSE) == SDHC_CMD_RSP_WITH_BUSY) { 357 s->norintsts |= SDHC_NIS_TRSCMP; 358 } 359 } 360 361 if (s->norintstsen & SDHC_NISEN_CMDCMP) { 362 s->norintsts |= SDHC_NIS_CMDCMP; 363 } 364 365 sdhci_update_irq(s); 366 367 if (s->blksize && (s->cmdreg & SDHC_CMD_DATA_PRESENT)) { 368 s->data_count = 0; 369 sdhci_data_transfer(s); 370 } 371 } 372 373 static void sdhci_end_transfer(SDHCIState *s) 374 { 375 /* Automatically send CMD12 to stop transfer if AutoCMD12 enabled */ 376 if ((s->trnmod & SDHC_TRNS_ACMD12) != 0) { 377 SDRequest request; 378 uint8_t response[16]; 379 380 request.cmd = 0x0C; 381 request.arg = 0; 382 trace_sdhci_end_transfer(request.cmd, request.arg); 383 sdbus_do_command(&s->sdbus, &request, response); 384 /* Auto CMD12 response goes to the upper Response register */ 385 s->rspreg[3] = ldl_be_p(response); 386 } 387 388 s->prnsts &= ~(SDHC_DOING_READ | SDHC_DOING_WRITE | 389 SDHC_DAT_LINE_ACTIVE | SDHC_DATA_INHIBIT | 390 SDHC_SPACE_AVAILABLE | SDHC_DATA_AVAILABLE); 391 392 if (s->norintstsen & SDHC_NISEN_TRSCMP) { 393 s->norintsts |= SDHC_NIS_TRSCMP; 394 } 395 396 sdhci_update_irq(s); 397 } 398 399 /* 400 * Programmed i/o data transfer 401 */ 402 #define BLOCK_SIZE_MASK (4 * KiB - 1) 403 404 /* Fill host controller's read buffer with BLKSIZE bytes of data from card */ 405 static void sdhci_read_block_from_card(SDHCIState *s) 406 { 407 const uint16_t blk_size = s->blksize & BLOCK_SIZE_MASK; 408 409 if ((s->trnmod & SDHC_TRNS_MULTI) && 410 (s->trnmod & SDHC_TRNS_BLK_CNT_EN) && (s->blkcnt == 0)) { 411 return; 412 } 413 414 if (!FIELD_EX32(s->hostctl2, SDHC_HOSTCTL2, EXECUTE_TUNING)) { 415 /* Device is not in tuning */ 416 sdbus_read_data(&s->sdbus, s->fifo_buffer, blk_size); 417 } 418 419 if (FIELD_EX32(s->hostctl2, SDHC_HOSTCTL2, EXECUTE_TUNING)) { 420 /* Device is in tuning */ 421 s->hostctl2 &= ~R_SDHC_HOSTCTL2_EXECUTE_TUNING_MASK; 422 s->hostctl2 |= R_SDHC_HOSTCTL2_SAMPLING_CLKSEL_MASK; 423 s->prnsts &= ~(SDHC_DAT_LINE_ACTIVE | SDHC_DOING_READ | 424 SDHC_DATA_INHIBIT); 425 goto read_done; 426 } 427 428 /* New data now available for READ through Buffer Port Register */ 429 s->prnsts |= SDHC_DATA_AVAILABLE; 430 if (s->norintstsen & SDHC_NISEN_RBUFRDY) { 431 s->norintsts |= SDHC_NIS_RBUFRDY; 432 } 433 434 /* Clear DAT line active status if that was the last block */ 435 if ((s->trnmod & SDHC_TRNS_MULTI) == 0 || 436 ((s->trnmod & SDHC_TRNS_MULTI) && s->blkcnt == 1)) { 437 s->prnsts &= ~SDHC_DAT_LINE_ACTIVE; 438 } 439 440 /* If stop at block gap request was set and it's not the last block of 441 * data - generate Block Event interrupt */ 442 if (s->stopped_state == sdhc_gap_read && (s->trnmod & SDHC_TRNS_MULTI) && 443 s->blkcnt != 1) { 444 s->prnsts &= ~SDHC_DAT_LINE_ACTIVE; 445 if (s->norintstsen & SDHC_EISEN_BLKGAP) { 446 s->norintsts |= SDHC_EIS_BLKGAP; 447 } 448 } 449 450 read_done: 451 sdhci_update_irq(s); 452 } 453 454 /* Read @size byte of data from host controller @s BUFFER DATA PORT register */ 455 static uint32_t sdhci_read_dataport(SDHCIState *s, unsigned size) 456 { 457 uint32_t value = 0; 458 int i; 459 460 /* first check that a valid data exists in host controller input buffer */ 461 if ((s->prnsts & SDHC_DATA_AVAILABLE) == 0) { 462 trace_sdhci_error("read from empty buffer"); 463 return 0; 464 } 465 466 for (i = 0; i < size; i++) { 467 value |= s->fifo_buffer[s->data_count] << i * 8; 468 s->data_count++; 469 /* check if we've read all valid data (blksize bytes) from buffer */ 470 if ((s->data_count) >= (s->blksize & BLOCK_SIZE_MASK)) { 471 trace_sdhci_read_dataport(s->data_count); 472 s->prnsts &= ~SDHC_DATA_AVAILABLE; /* no more data in a buffer */ 473 s->data_count = 0; /* next buff read must start at position [0] */ 474 475 if (s->trnmod & SDHC_TRNS_BLK_CNT_EN) { 476 s->blkcnt--; 477 } 478 479 /* if that was the last block of data */ 480 if ((s->trnmod & SDHC_TRNS_MULTI) == 0 || 481 ((s->trnmod & SDHC_TRNS_BLK_CNT_EN) && (s->blkcnt == 0)) || 482 /* stop at gap request */ 483 (s->stopped_state == sdhc_gap_read && 484 !(s->prnsts & SDHC_DAT_LINE_ACTIVE))) { 485 sdhci_end_transfer(s); 486 } else { /* if there are more data, read next block from card */ 487 sdhci_read_block_from_card(s); 488 } 489 break; 490 } 491 } 492 493 return value; 494 } 495 496 /* Write data from host controller FIFO to card */ 497 static void sdhci_write_block_to_card(SDHCIState *s) 498 { 499 if (s->prnsts & SDHC_SPACE_AVAILABLE) { 500 if (s->norintstsen & SDHC_NISEN_WBUFRDY) { 501 s->norintsts |= SDHC_NIS_WBUFRDY; 502 } 503 sdhci_update_irq(s); 504 return; 505 } 506 507 if (s->trnmod & SDHC_TRNS_BLK_CNT_EN) { 508 if (s->blkcnt == 0) { 509 return; 510 } else { 511 s->blkcnt--; 512 } 513 } 514 515 sdbus_write_data(&s->sdbus, s->fifo_buffer, s->blksize & BLOCK_SIZE_MASK); 516 517 /* Next data can be written through BUFFER DATORT register */ 518 s->prnsts |= SDHC_SPACE_AVAILABLE; 519 520 /* Finish transfer if that was the last block of data */ 521 if ((s->trnmod & SDHC_TRNS_MULTI) == 0 || 522 ((s->trnmod & SDHC_TRNS_MULTI) && 523 (s->trnmod & SDHC_TRNS_BLK_CNT_EN) && (s->blkcnt == 0))) { 524 sdhci_end_transfer(s); 525 } else if (s->norintstsen & SDHC_NISEN_WBUFRDY) { 526 s->norintsts |= SDHC_NIS_WBUFRDY; 527 } 528 529 /* Generate Block Gap Event if requested and if not the last block */ 530 if (s->stopped_state == sdhc_gap_write && (s->trnmod & SDHC_TRNS_MULTI) && 531 s->blkcnt > 0) { 532 s->prnsts &= ~SDHC_DOING_WRITE; 533 if (s->norintstsen & SDHC_EISEN_BLKGAP) { 534 s->norintsts |= SDHC_EIS_BLKGAP; 535 } 536 sdhci_end_transfer(s); 537 } 538 539 sdhci_update_irq(s); 540 } 541 542 /* Write @size bytes of @value data to host controller @s Buffer Data Port 543 * register */ 544 static void sdhci_write_dataport(SDHCIState *s, uint32_t value, unsigned size) 545 { 546 unsigned i; 547 548 /* Check that there is free space left in a buffer */ 549 if (!(s->prnsts & SDHC_SPACE_AVAILABLE)) { 550 trace_sdhci_error("Can't write to data buffer: buffer full"); 551 return; 552 } 553 554 for (i = 0; i < size; i++) { 555 s->fifo_buffer[s->data_count] = value & 0xFF; 556 s->data_count++; 557 value >>= 8; 558 if (s->data_count >= (s->blksize & BLOCK_SIZE_MASK)) { 559 trace_sdhci_write_dataport(s->data_count); 560 s->data_count = 0; 561 s->prnsts &= ~SDHC_SPACE_AVAILABLE; 562 if (s->prnsts & SDHC_DOING_WRITE) { 563 sdhci_write_block_to_card(s); 564 } 565 } 566 } 567 } 568 569 /* 570 * Single DMA data transfer 571 */ 572 573 /* Multi block SDMA transfer */ 574 static void sdhci_sdma_transfer_multi_blocks(SDHCIState *s) 575 { 576 bool page_aligned = false; 577 unsigned int begin; 578 const uint16_t block_size = s->blksize & BLOCK_SIZE_MASK; 579 uint32_t boundary_chk = 1 << (((s->blksize & ~BLOCK_SIZE_MASK) >> 12) + 12); 580 uint32_t boundary_count = boundary_chk - (s->sdmasysad % boundary_chk); 581 582 if (!(s->trnmod & SDHC_TRNS_BLK_CNT_EN) || !s->blkcnt) { 583 qemu_log_mask(LOG_UNIMP, "infinite transfer is not supported\n"); 584 return; 585 } 586 587 /* XXX: Some sd/mmc drivers (for example, u-boot-slp) do not account for 588 * possible stop at page boundary if initial address is not page aligned, 589 * allow them to work properly */ 590 if ((s->sdmasysad % boundary_chk) == 0) { 591 page_aligned = true; 592 } 593 594 if (s->trnmod & SDHC_TRNS_READ) { 595 s->prnsts |= SDHC_DOING_READ | SDHC_DATA_INHIBIT | 596 SDHC_DAT_LINE_ACTIVE; 597 while (s->blkcnt) { 598 if (s->data_count == 0) { 599 sdbus_read_data(&s->sdbus, s->fifo_buffer, block_size); 600 } 601 begin = s->data_count; 602 if (((boundary_count + begin) < block_size) && page_aligned) { 603 s->data_count = boundary_count + begin; 604 boundary_count = 0; 605 } else { 606 s->data_count = block_size; 607 boundary_count -= block_size - begin; 608 if (s->trnmod & SDHC_TRNS_BLK_CNT_EN) { 609 s->blkcnt--; 610 } 611 } 612 dma_memory_write(s->dma_as, s->sdmasysad, 613 &s->fifo_buffer[begin], s->data_count - begin); 614 s->sdmasysad += s->data_count - begin; 615 if (s->data_count == block_size) { 616 s->data_count = 0; 617 } 618 if (page_aligned && boundary_count == 0) { 619 break; 620 } 621 } 622 } else { 623 s->prnsts |= SDHC_DOING_WRITE | SDHC_DATA_INHIBIT | 624 SDHC_DAT_LINE_ACTIVE; 625 while (s->blkcnt) { 626 begin = s->data_count; 627 if (((boundary_count + begin) < block_size) && page_aligned) { 628 s->data_count = boundary_count + begin; 629 boundary_count = 0; 630 } else { 631 s->data_count = block_size; 632 boundary_count -= block_size - begin; 633 } 634 dma_memory_read(s->dma_as, s->sdmasysad, 635 &s->fifo_buffer[begin], s->data_count - begin); 636 s->sdmasysad += s->data_count - begin; 637 if (s->data_count == block_size) { 638 sdbus_write_data(&s->sdbus, s->fifo_buffer, block_size); 639 s->data_count = 0; 640 if (s->trnmod & SDHC_TRNS_BLK_CNT_EN) { 641 s->blkcnt--; 642 } 643 } 644 if (page_aligned && boundary_count == 0) { 645 break; 646 } 647 } 648 } 649 650 if (s->blkcnt == 0) { 651 sdhci_end_transfer(s); 652 } else { 653 if (s->norintstsen & SDHC_NISEN_DMA) { 654 s->norintsts |= SDHC_NIS_DMA; 655 } 656 sdhci_update_irq(s); 657 } 658 } 659 660 /* single block SDMA transfer */ 661 static void sdhci_sdma_transfer_single_block(SDHCIState *s) 662 { 663 uint32_t datacnt = s->blksize & BLOCK_SIZE_MASK; 664 665 if (s->trnmod & SDHC_TRNS_READ) { 666 sdbus_read_data(&s->sdbus, s->fifo_buffer, datacnt); 667 dma_memory_write(s->dma_as, s->sdmasysad, s->fifo_buffer, datacnt); 668 } else { 669 dma_memory_read(s->dma_as, s->sdmasysad, s->fifo_buffer, datacnt); 670 sdbus_write_data(&s->sdbus, s->fifo_buffer, datacnt); 671 } 672 s->blkcnt--; 673 674 sdhci_end_transfer(s); 675 } 676 677 typedef struct ADMADescr { 678 hwaddr addr; 679 uint16_t length; 680 uint8_t attr; 681 uint8_t incr; 682 } ADMADescr; 683 684 static void get_adma_description(SDHCIState *s, ADMADescr *dscr) 685 { 686 uint32_t adma1 = 0; 687 uint64_t adma2 = 0; 688 hwaddr entry_addr = (hwaddr)s->admasysaddr; 689 switch (SDHC_DMA_TYPE(s->hostctl1)) { 690 case SDHC_CTRL_ADMA2_32: 691 dma_memory_read(s->dma_as, entry_addr, &adma2, sizeof(adma2)); 692 adma2 = le64_to_cpu(adma2); 693 /* The spec does not specify endianness of descriptor table. 694 * We currently assume that it is LE. 695 */ 696 dscr->addr = (hwaddr)extract64(adma2, 32, 32) & ~0x3ull; 697 dscr->length = (uint16_t)extract64(adma2, 16, 16); 698 dscr->attr = (uint8_t)extract64(adma2, 0, 7); 699 dscr->incr = 8; 700 break; 701 case SDHC_CTRL_ADMA1_32: 702 dma_memory_read(s->dma_as, entry_addr, &adma1, sizeof(adma1)); 703 adma1 = le32_to_cpu(adma1); 704 dscr->addr = (hwaddr)(adma1 & 0xFFFFF000); 705 dscr->attr = (uint8_t)extract32(adma1, 0, 7); 706 dscr->incr = 4; 707 if ((dscr->attr & SDHC_ADMA_ATTR_ACT_MASK) == SDHC_ADMA_ATTR_SET_LEN) { 708 dscr->length = (uint16_t)extract32(adma1, 12, 16); 709 } else { 710 dscr->length = 4 * KiB; 711 } 712 break; 713 case SDHC_CTRL_ADMA2_64: 714 dma_memory_read(s->dma_as, entry_addr, &dscr->attr, 1); 715 dma_memory_read(s->dma_as, entry_addr + 2, &dscr->length, 2); 716 dscr->length = le16_to_cpu(dscr->length); 717 dma_memory_read(s->dma_as, entry_addr + 4, &dscr->addr, 8); 718 dscr->addr = le64_to_cpu(dscr->addr); 719 dscr->attr &= (uint8_t) ~0xC0; 720 dscr->incr = 12; 721 break; 722 } 723 } 724 725 /* Advanced DMA data transfer */ 726 727 static void sdhci_do_adma(SDHCIState *s) 728 { 729 unsigned int begin, length; 730 const uint16_t block_size = s->blksize & BLOCK_SIZE_MASK; 731 ADMADescr dscr = {}; 732 int i; 733 734 for (i = 0; i < SDHC_ADMA_DESCS_PER_DELAY; ++i) { 735 s->admaerr &= ~SDHC_ADMAERR_LENGTH_MISMATCH; 736 737 get_adma_description(s, &dscr); 738 trace_sdhci_adma_loop(dscr.addr, dscr.length, dscr.attr); 739 740 if ((dscr.attr & SDHC_ADMA_ATTR_VALID) == 0) { 741 /* Indicate that error occurred in ST_FDS state */ 742 s->admaerr &= ~SDHC_ADMAERR_STATE_MASK; 743 s->admaerr |= SDHC_ADMAERR_STATE_ST_FDS; 744 745 /* Generate ADMA error interrupt */ 746 if (s->errintstsen & SDHC_EISEN_ADMAERR) { 747 s->errintsts |= SDHC_EIS_ADMAERR; 748 s->norintsts |= SDHC_NIS_ERR; 749 } 750 751 sdhci_update_irq(s); 752 return; 753 } 754 755 length = dscr.length ? dscr.length : 64 * KiB; 756 757 switch (dscr.attr & SDHC_ADMA_ATTR_ACT_MASK) { 758 case SDHC_ADMA_ATTR_ACT_TRAN: /* data transfer */ 759 760 if (s->trnmod & SDHC_TRNS_READ) { 761 while (length) { 762 if (s->data_count == 0) { 763 sdbus_read_data(&s->sdbus, s->fifo_buffer, block_size); 764 } 765 begin = s->data_count; 766 if ((length + begin) < block_size) { 767 s->data_count = length + begin; 768 length = 0; 769 } else { 770 s->data_count = block_size; 771 length -= block_size - begin; 772 } 773 dma_memory_write(s->dma_as, dscr.addr, 774 &s->fifo_buffer[begin], 775 s->data_count - begin); 776 dscr.addr += s->data_count - begin; 777 if (s->data_count == block_size) { 778 s->data_count = 0; 779 if (s->trnmod & SDHC_TRNS_BLK_CNT_EN) { 780 s->blkcnt--; 781 if (s->blkcnt == 0) { 782 break; 783 } 784 } 785 } 786 } 787 } else { 788 while (length) { 789 begin = s->data_count; 790 if ((length + begin) < block_size) { 791 s->data_count = length + begin; 792 length = 0; 793 } else { 794 s->data_count = block_size; 795 length -= block_size - begin; 796 } 797 dma_memory_read(s->dma_as, dscr.addr, 798 &s->fifo_buffer[begin], 799 s->data_count - begin); 800 dscr.addr += s->data_count - begin; 801 if (s->data_count == block_size) { 802 sdbus_write_data(&s->sdbus, s->fifo_buffer, block_size); 803 s->data_count = 0; 804 if (s->trnmod & SDHC_TRNS_BLK_CNT_EN) { 805 s->blkcnt--; 806 if (s->blkcnt == 0) { 807 break; 808 } 809 } 810 } 811 } 812 } 813 s->admasysaddr += dscr.incr; 814 break; 815 case SDHC_ADMA_ATTR_ACT_LINK: /* link to next descriptor table */ 816 s->admasysaddr = dscr.addr; 817 trace_sdhci_adma("link", s->admasysaddr); 818 break; 819 default: 820 s->admasysaddr += dscr.incr; 821 break; 822 } 823 824 if (dscr.attr & SDHC_ADMA_ATTR_INT) { 825 trace_sdhci_adma("interrupt", s->admasysaddr); 826 if (s->norintstsen & SDHC_NISEN_DMA) { 827 s->norintsts |= SDHC_NIS_DMA; 828 } 829 830 sdhci_update_irq(s); 831 } 832 833 /* ADMA transfer terminates if blkcnt == 0 or by END attribute */ 834 if (((s->trnmod & SDHC_TRNS_BLK_CNT_EN) && 835 (s->blkcnt == 0)) || (dscr.attr & SDHC_ADMA_ATTR_END)) { 836 trace_sdhci_adma_transfer_completed(); 837 if (length || ((dscr.attr & SDHC_ADMA_ATTR_END) && 838 (s->trnmod & SDHC_TRNS_BLK_CNT_EN) && 839 s->blkcnt != 0)) { 840 trace_sdhci_error("SD/MMC host ADMA length mismatch"); 841 s->admaerr |= SDHC_ADMAERR_LENGTH_MISMATCH | 842 SDHC_ADMAERR_STATE_ST_TFR; 843 if (s->errintstsen & SDHC_EISEN_ADMAERR) { 844 trace_sdhci_error("Set ADMA error flag"); 845 s->errintsts |= SDHC_EIS_ADMAERR; 846 s->norintsts |= SDHC_NIS_ERR; 847 } 848 849 sdhci_update_irq(s); 850 } 851 sdhci_end_transfer(s); 852 return; 853 } 854 855 } 856 857 /* we have unfinished business - reschedule to continue ADMA */ 858 timer_mod(s->transfer_timer, 859 qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + SDHC_TRANSFER_DELAY); 860 } 861 862 /* Perform data transfer according to controller configuration */ 863 864 static void sdhci_data_transfer(void *opaque) 865 { 866 SDHCIState *s = (SDHCIState *)opaque; 867 868 if (s->trnmod & SDHC_TRNS_DMA) { 869 switch (SDHC_DMA_TYPE(s->hostctl1)) { 870 case SDHC_CTRL_SDMA: 871 if ((s->blkcnt == 1) || !(s->trnmod & SDHC_TRNS_MULTI)) { 872 sdhci_sdma_transfer_single_block(s); 873 } else { 874 sdhci_sdma_transfer_multi_blocks(s); 875 } 876 877 break; 878 case SDHC_CTRL_ADMA1_32: 879 if (!(s->capareg & R_SDHC_CAPAB_ADMA1_MASK)) { 880 trace_sdhci_error("ADMA1 not supported"); 881 break; 882 } 883 884 sdhci_do_adma(s); 885 break; 886 case SDHC_CTRL_ADMA2_32: 887 if (!(s->capareg & R_SDHC_CAPAB_ADMA2_MASK)) { 888 trace_sdhci_error("ADMA2 not supported"); 889 break; 890 } 891 892 sdhci_do_adma(s); 893 break; 894 case SDHC_CTRL_ADMA2_64: 895 if (!(s->capareg & R_SDHC_CAPAB_ADMA2_MASK) || 896 !(s->capareg & R_SDHC_CAPAB_BUS64BIT_MASK)) { 897 trace_sdhci_error("64 bit ADMA not supported"); 898 break; 899 } 900 901 sdhci_do_adma(s); 902 break; 903 default: 904 trace_sdhci_error("Unsupported DMA type"); 905 break; 906 } 907 } else { 908 if ((s->trnmod & SDHC_TRNS_READ) && sdbus_data_ready(&s->sdbus)) { 909 s->prnsts |= SDHC_DOING_READ | SDHC_DATA_INHIBIT | 910 SDHC_DAT_LINE_ACTIVE; 911 sdhci_read_block_from_card(s); 912 } else { 913 s->prnsts |= SDHC_DOING_WRITE | SDHC_DAT_LINE_ACTIVE | 914 SDHC_SPACE_AVAILABLE | SDHC_DATA_INHIBIT; 915 sdhci_write_block_to_card(s); 916 } 917 } 918 } 919 920 static bool sdhci_can_issue_command(SDHCIState *s) 921 { 922 if (!SDHC_CLOCK_IS_ON(s->clkcon) || 923 (((s->prnsts & SDHC_DATA_INHIBIT) || s->stopped_state) && 924 ((s->cmdreg & SDHC_CMD_DATA_PRESENT) || 925 ((s->cmdreg & SDHC_CMD_RESPONSE) == SDHC_CMD_RSP_WITH_BUSY && 926 !(SDHC_COMMAND_TYPE(s->cmdreg) == SDHC_CMD_ABORT))))) { 927 return false; 928 } 929 930 return true; 931 } 932 933 /* The Buffer Data Port register must be accessed in sequential and 934 * continuous manner */ 935 static inline bool 936 sdhci_buff_access_is_sequential(SDHCIState *s, unsigned byte_num) 937 { 938 if ((s->data_count & 0x3) != byte_num) { 939 trace_sdhci_error("Non-sequential access to Buffer Data Port register" 940 "is prohibited\n"); 941 return false; 942 } 943 return true; 944 } 945 946 static uint64_t sdhci_read(void *opaque, hwaddr offset, unsigned size) 947 { 948 SDHCIState *s = (SDHCIState *)opaque; 949 uint32_t ret = 0; 950 951 switch (offset & ~0x3) { 952 case SDHC_SYSAD: 953 ret = s->sdmasysad; 954 break; 955 case SDHC_BLKSIZE: 956 ret = s->blksize | (s->blkcnt << 16); 957 break; 958 case SDHC_ARGUMENT: 959 ret = s->argument; 960 break; 961 case SDHC_TRNMOD: 962 ret = s->trnmod | (s->cmdreg << 16); 963 break; 964 case SDHC_RSPREG0 ... SDHC_RSPREG3: 965 ret = s->rspreg[((offset & ~0x3) - SDHC_RSPREG0) >> 2]; 966 break; 967 case SDHC_BDATA: 968 if (sdhci_buff_access_is_sequential(s, offset - SDHC_BDATA)) { 969 ret = sdhci_read_dataport(s, size); 970 trace_sdhci_access("rd", size << 3, offset, "->", ret, ret); 971 return ret; 972 } 973 break; 974 case SDHC_PRNSTS: 975 ret = s->prnsts; 976 ret = FIELD_DP32(ret, SDHC_PRNSTS, DAT_LVL, 977 sdbus_get_dat_lines(&s->sdbus)); 978 ret = FIELD_DP32(ret, SDHC_PRNSTS, CMD_LVL, 979 sdbus_get_cmd_line(&s->sdbus)); 980 break; 981 case SDHC_HOSTCTL: 982 ret = s->hostctl1 | (s->pwrcon << 8) | (s->blkgap << 16) | 983 (s->wakcon << 24); 984 break; 985 case SDHC_CLKCON: 986 ret = s->clkcon | (s->timeoutcon << 16); 987 break; 988 case SDHC_NORINTSTS: 989 ret = s->norintsts | (s->errintsts << 16); 990 break; 991 case SDHC_NORINTSTSEN: 992 ret = s->norintstsen | (s->errintstsen << 16); 993 break; 994 case SDHC_NORINTSIGEN: 995 ret = s->norintsigen | (s->errintsigen << 16); 996 break; 997 case SDHC_ACMD12ERRSTS: 998 ret = s->acmd12errsts | (s->hostctl2 << 16); 999 break; 1000 case SDHC_CAPAB: 1001 ret = (uint32_t)s->capareg; 1002 break; 1003 case SDHC_CAPAB + 4: 1004 ret = (uint32_t)(s->capareg >> 32); 1005 break; 1006 case SDHC_MAXCURR: 1007 ret = (uint32_t)s->maxcurr; 1008 break; 1009 case SDHC_MAXCURR + 4: 1010 ret = (uint32_t)(s->maxcurr >> 32); 1011 break; 1012 case SDHC_ADMAERR: 1013 ret = s->admaerr; 1014 break; 1015 case SDHC_ADMASYSADDR: 1016 ret = (uint32_t)s->admasysaddr; 1017 break; 1018 case SDHC_ADMASYSADDR + 4: 1019 ret = (uint32_t)(s->admasysaddr >> 32); 1020 break; 1021 case SDHC_SLOT_INT_STATUS: 1022 ret = (s->version << 16) | sdhci_slotint(s); 1023 break; 1024 default: 1025 qemu_log_mask(LOG_UNIMP, "SDHC rd_%ub @0x%02" HWADDR_PRIx " " 1026 "not implemented\n", size, offset); 1027 break; 1028 } 1029 1030 ret >>= (offset & 0x3) * 8; 1031 ret &= (1ULL << (size * 8)) - 1; 1032 trace_sdhci_access("rd", size << 3, offset, "->", ret, ret); 1033 return ret; 1034 } 1035 1036 static inline void sdhci_blkgap_write(SDHCIState *s, uint8_t value) 1037 { 1038 if ((value & SDHC_STOP_AT_GAP_REQ) && (s->blkgap & SDHC_STOP_AT_GAP_REQ)) { 1039 return; 1040 } 1041 s->blkgap = value & SDHC_STOP_AT_GAP_REQ; 1042 1043 if ((value & SDHC_CONTINUE_REQ) && s->stopped_state && 1044 (s->blkgap & SDHC_STOP_AT_GAP_REQ) == 0) { 1045 if (s->stopped_state == sdhc_gap_read) { 1046 s->prnsts |= SDHC_DAT_LINE_ACTIVE | SDHC_DOING_READ; 1047 sdhci_read_block_from_card(s); 1048 } else { 1049 s->prnsts |= SDHC_DAT_LINE_ACTIVE | SDHC_DOING_WRITE; 1050 sdhci_write_block_to_card(s); 1051 } 1052 s->stopped_state = sdhc_not_stopped; 1053 } else if (!s->stopped_state && (value & SDHC_STOP_AT_GAP_REQ)) { 1054 if (s->prnsts & SDHC_DOING_READ) { 1055 s->stopped_state = sdhc_gap_read; 1056 } else if (s->prnsts & SDHC_DOING_WRITE) { 1057 s->stopped_state = sdhc_gap_write; 1058 } 1059 } 1060 } 1061 1062 static inline void sdhci_reset_write(SDHCIState *s, uint8_t value) 1063 { 1064 switch (value) { 1065 case SDHC_RESET_ALL: 1066 sdhci_reset(s); 1067 break; 1068 case SDHC_RESET_CMD: 1069 s->prnsts &= ~SDHC_CMD_INHIBIT; 1070 s->norintsts &= ~SDHC_NIS_CMDCMP; 1071 break; 1072 case SDHC_RESET_DATA: 1073 s->data_count = 0; 1074 s->prnsts &= ~(SDHC_SPACE_AVAILABLE | SDHC_DATA_AVAILABLE | 1075 SDHC_DOING_READ | SDHC_DOING_WRITE | 1076 SDHC_DATA_INHIBIT | SDHC_DAT_LINE_ACTIVE); 1077 s->blkgap &= ~(SDHC_STOP_AT_GAP_REQ | SDHC_CONTINUE_REQ); 1078 s->stopped_state = sdhc_not_stopped; 1079 s->norintsts &= ~(SDHC_NIS_WBUFRDY | SDHC_NIS_RBUFRDY | 1080 SDHC_NIS_DMA | SDHC_NIS_TRSCMP | SDHC_NIS_BLKGAP); 1081 break; 1082 } 1083 } 1084 1085 static void 1086 sdhci_write(void *opaque, hwaddr offset, uint64_t val, unsigned size) 1087 { 1088 SDHCIState *s = (SDHCIState *)opaque; 1089 unsigned shift = 8 * (offset & 0x3); 1090 uint32_t mask = ~(((1ULL << (size * 8)) - 1) << shift); 1091 uint32_t value = val; 1092 value <<= shift; 1093 1094 switch (offset & ~0x3) { 1095 case SDHC_SYSAD: 1096 s->sdmasysad = (s->sdmasysad & mask) | value; 1097 MASKED_WRITE(s->sdmasysad, mask, value); 1098 /* Writing to last byte of sdmasysad might trigger transfer */ 1099 if (!(mask & 0xFF000000) && TRANSFERRING_DATA(s->prnsts) && s->blkcnt && 1100 s->blksize && SDHC_DMA_TYPE(s->hostctl1) == SDHC_CTRL_SDMA) { 1101 if (s->trnmod & SDHC_TRNS_MULTI) { 1102 sdhci_sdma_transfer_multi_blocks(s); 1103 } else { 1104 sdhci_sdma_transfer_single_block(s); 1105 } 1106 } 1107 break; 1108 case SDHC_BLKSIZE: 1109 if (!TRANSFERRING_DATA(s->prnsts)) { 1110 MASKED_WRITE(s->blksize, mask, value); 1111 MASKED_WRITE(s->blkcnt, mask >> 16, value >> 16); 1112 } 1113 1114 /* Limit block size to the maximum buffer size */ 1115 if (extract32(s->blksize, 0, 12) > s->buf_maxsz) { 1116 qemu_log_mask(LOG_GUEST_ERROR, "%s: Size 0x%x is larger than " 1117 "the maximum buffer 0x%x\n", __func__, s->blksize, 1118 s->buf_maxsz); 1119 1120 s->blksize = deposit32(s->blksize, 0, 12, s->buf_maxsz); 1121 } 1122 1123 break; 1124 case SDHC_ARGUMENT: 1125 MASKED_WRITE(s->argument, mask, value); 1126 break; 1127 case SDHC_TRNMOD: 1128 /* DMA can be enabled only if it is supported as indicated by 1129 * capabilities register */ 1130 if (!(s->capareg & R_SDHC_CAPAB_SDMA_MASK)) { 1131 value &= ~SDHC_TRNS_DMA; 1132 } 1133 MASKED_WRITE(s->trnmod, mask, value & SDHC_TRNMOD_MASK); 1134 MASKED_WRITE(s->cmdreg, mask >> 16, value >> 16); 1135 1136 /* Writing to the upper byte of CMDREG triggers SD command generation */ 1137 if ((mask & 0xFF000000) || !sdhci_can_issue_command(s)) { 1138 break; 1139 } 1140 1141 sdhci_send_command(s); 1142 break; 1143 case SDHC_BDATA: 1144 if (sdhci_buff_access_is_sequential(s, offset - SDHC_BDATA)) { 1145 sdhci_write_dataport(s, value >> shift, size); 1146 } 1147 break; 1148 case SDHC_HOSTCTL: 1149 if (!(mask & 0xFF0000)) { 1150 sdhci_blkgap_write(s, value >> 16); 1151 } 1152 MASKED_WRITE(s->hostctl1, mask, value); 1153 MASKED_WRITE(s->pwrcon, mask >> 8, value >> 8); 1154 MASKED_WRITE(s->wakcon, mask >> 24, value >> 24); 1155 if (!(s->prnsts & SDHC_CARD_PRESENT) || ((s->pwrcon >> 1) & 0x7) < 5 || 1156 !(s->capareg & (1 << (31 - ((s->pwrcon >> 1) & 0x7))))) { 1157 s->pwrcon &= ~SDHC_POWER_ON; 1158 } 1159 break; 1160 case SDHC_CLKCON: 1161 if (!(mask & 0xFF000000)) { 1162 sdhci_reset_write(s, value >> 24); 1163 } 1164 MASKED_WRITE(s->clkcon, mask, value); 1165 MASKED_WRITE(s->timeoutcon, mask >> 16, value >> 16); 1166 if (s->clkcon & SDHC_CLOCK_INT_EN) { 1167 s->clkcon |= SDHC_CLOCK_INT_STABLE; 1168 } else { 1169 s->clkcon &= ~SDHC_CLOCK_INT_STABLE; 1170 } 1171 break; 1172 case SDHC_NORINTSTS: 1173 if (s->norintstsen & SDHC_NISEN_CARDINT) { 1174 value &= ~SDHC_NIS_CARDINT; 1175 } 1176 s->norintsts &= mask | ~value; 1177 s->errintsts &= (mask >> 16) | ~(value >> 16); 1178 if (s->errintsts) { 1179 s->norintsts |= SDHC_NIS_ERR; 1180 } else { 1181 s->norintsts &= ~SDHC_NIS_ERR; 1182 } 1183 sdhci_update_irq(s); 1184 break; 1185 case SDHC_NORINTSTSEN: 1186 MASKED_WRITE(s->norintstsen, mask, value); 1187 MASKED_WRITE(s->errintstsen, mask >> 16, value >> 16); 1188 s->norintsts &= s->norintstsen; 1189 s->errintsts &= s->errintstsen; 1190 if (s->errintsts) { 1191 s->norintsts |= SDHC_NIS_ERR; 1192 } else { 1193 s->norintsts &= ~SDHC_NIS_ERR; 1194 } 1195 /* Quirk for Raspberry Pi: pending card insert interrupt 1196 * appears when first enabled after power on */ 1197 if ((s->norintstsen & SDHC_NISEN_INSERT) && s->pending_insert_state) { 1198 assert(s->pending_insert_quirk); 1199 s->norintsts |= SDHC_NIS_INSERT; 1200 s->pending_insert_state = false; 1201 } 1202 sdhci_update_irq(s); 1203 break; 1204 case SDHC_NORINTSIGEN: 1205 MASKED_WRITE(s->norintsigen, mask, value); 1206 MASKED_WRITE(s->errintsigen, mask >> 16, value >> 16); 1207 sdhci_update_irq(s); 1208 break; 1209 case SDHC_ADMAERR: 1210 MASKED_WRITE(s->admaerr, mask, value); 1211 break; 1212 case SDHC_ADMASYSADDR: 1213 s->admasysaddr = (s->admasysaddr & (0xFFFFFFFF00000000ULL | 1214 (uint64_t)mask)) | (uint64_t)value; 1215 break; 1216 case SDHC_ADMASYSADDR + 4: 1217 s->admasysaddr = (s->admasysaddr & (0x00000000FFFFFFFFULL | 1218 ((uint64_t)mask << 32))) | ((uint64_t)value << 32); 1219 break; 1220 case SDHC_FEAER: 1221 s->acmd12errsts |= value; 1222 s->errintsts |= (value >> 16) & s->errintstsen; 1223 if (s->acmd12errsts) { 1224 s->errintsts |= SDHC_EIS_CMD12ERR; 1225 } 1226 if (s->errintsts) { 1227 s->norintsts |= SDHC_NIS_ERR; 1228 } 1229 sdhci_update_irq(s); 1230 break; 1231 case SDHC_ACMD12ERRSTS: 1232 MASKED_WRITE(s->acmd12errsts, mask, value & UINT16_MAX); 1233 if (s->uhs_mode >= UHS_I) { 1234 MASKED_WRITE(s->hostctl2, mask >> 16, value >> 16); 1235 1236 if (FIELD_EX32(s->hostctl2, SDHC_HOSTCTL2, V18_ENA)) { 1237 sdbus_set_voltage(&s->sdbus, SD_VOLTAGE_1_8V); 1238 } else { 1239 sdbus_set_voltage(&s->sdbus, SD_VOLTAGE_3_3V); 1240 } 1241 } 1242 break; 1243 1244 case SDHC_CAPAB: 1245 case SDHC_CAPAB + 4: 1246 case SDHC_MAXCURR: 1247 case SDHC_MAXCURR + 4: 1248 qemu_log_mask(LOG_GUEST_ERROR, "SDHC wr_%ub @0x%02" HWADDR_PRIx 1249 " <- 0x%08x read-only\n", size, offset, value >> shift); 1250 break; 1251 1252 default: 1253 qemu_log_mask(LOG_UNIMP, "SDHC wr_%ub @0x%02" HWADDR_PRIx " <- 0x%08x " 1254 "not implemented\n", size, offset, value >> shift); 1255 break; 1256 } 1257 trace_sdhci_access("wr", size << 3, offset, "<-", 1258 value >> shift, value >> shift); 1259 } 1260 1261 static const MemoryRegionOps sdhci_mmio_ops = { 1262 .read = sdhci_read, 1263 .write = sdhci_write, 1264 .valid = { 1265 .min_access_size = 1, 1266 .max_access_size = 4, 1267 .unaligned = false 1268 }, 1269 .endianness = DEVICE_LITTLE_ENDIAN, 1270 }; 1271 1272 static void sdhci_init_readonly_registers(SDHCIState *s, Error **errp) 1273 { 1274 ERRP_GUARD(); 1275 1276 switch (s->sd_spec_version) { 1277 case 2 ... 3: 1278 break; 1279 default: 1280 error_setg(errp, "Only Spec v2/v3 are supported"); 1281 return; 1282 } 1283 s->version = (SDHC_HCVER_VENDOR << 8) | (s->sd_spec_version - 1); 1284 1285 sdhci_check_capareg(s, errp); 1286 if (*errp) { 1287 return; 1288 } 1289 } 1290 1291 /* --- qdev common --- */ 1292 1293 void sdhci_initfn(SDHCIState *s) 1294 { 1295 qbus_create_inplace(&s->sdbus, sizeof(s->sdbus), 1296 TYPE_SDHCI_BUS, DEVICE(s), "sd-bus"); 1297 1298 s->insert_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, sdhci_raise_insertion_irq, s); 1299 s->transfer_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, sdhci_data_transfer, s); 1300 1301 s->io_ops = &sdhci_mmio_ops; 1302 } 1303 1304 void sdhci_uninitfn(SDHCIState *s) 1305 { 1306 timer_del(s->insert_timer); 1307 timer_free(s->insert_timer); 1308 timer_del(s->transfer_timer); 1309 timer_free(s->transfer_timer); 1310 1311 g_free(s->fifo_buffer); 1312 s->fifo_buffer = NULL; 1313 } 1314 1315 void sdhci_common_realize(SDHCIState *s, Error **errp) 1316 { 1317 ERRP_GUARD(); 1318 1319 sdhci_init_readonly_registers(s, errp); 1320 if (*errp) { 1321 return; 1322 } 1323 s->buf_maxsz = sdhci_get_fifolen(s); 1324 s->fifo_buffer = g_malloc0(s->buf_maxsz); 1325 1326 memory_region_init_io(&s->iomem, OBJECT(s), s->io_ops, s, "sdhci", 1327 SDHC_REGISTERS_MAP_SIZE); 1328 } 1329 1330 void sdhci_common_unrealize(SDHCIState *s) 1331 { 1332 /* This function is expected to be called only once for each class: 1333 * - SysBus: via DeviceClass->unrealize(), 1334 * - PCI: via PCIDeviceClass->exit(). 1335 * However to avoid double-free and/or use-after-free we still nullify 1336 * this variable (better safe than sorry!). */ 1337 g_free(s->fifo_buffer); 1338 s->fifo_buffer = NULL; 1339 } 1340 1341 static bool sdhci_pending_insert_vmstate_needed(void *opaque) 1342 { 1343 SDHCIState *s = opaque; 1344 1345 return s->pending_insert_state; 1346 } 1347 1348 static const VMStateDescription sdhci_pending_insert_vmstate = { 1349 .name = "sdhci/pending-insert", 1350 .version_id = 1, 1351 .minimum_version_id = 1, 1352 .needed = sdhci_pending_insert_vmstate_needed, 1353 .fields = (VMStateField[]) { 1354 VMSTATE_BOOL(pending_insert_state, SDHCIState), 1355 VMSTATE_END_OF_LIST() 1356 }, 1357 }; 1358 1359 const VMStateDescription sdhci_vmstate = { 1360 .name = "sdhci", 1361 .version_id = 1, 1362 .minimum_version_id = 1, 1363 .fields = (VMStateField[]) { 1364 VMSTATE_UINT32(sdmasysad, SDHCIState), 1365 VMSTATE_UINT16(blksize, SDHCIState), 1366 VMSTATE_UINT16(blkcnt, SDHCIState), 1367 VMSTATE_UINT32(argument, SDHCIState), 1368 VMSTATE_UINT16(trnmod, SDHCIState), 1369 VMSTATE_UINT16(cmdreg, SDHCIState), 1370 VMSTATE_UINT32_ARRAY(rspreg, SDHCIState, 4), 1371 VMSTATE_UINT32(prnsts, SDHCIState), 1372 VMSTATE_UINT8(hostctl1, SDHCIState), 1373 VMSTATE_UINT8(pwrcon, SDHCIState), 1374 VMSTATE_UINT8(blkgap, SDHCIState), 1375 VMSTATE_UINT8(wakcon, SDHCIState), 1376 VMSTATE_UINT16(clkcon, SDHCIState), 1377 VMSTATE_UINT8(timeoutcon, SDHCIState), 1378 VMSTATE_UINT8(admaerr, SDHCIState), 1379 VMSTATE_UINT16(norintsts, SDHCIState), 1380 VMSTATE_UINT16(errintsts, SDHCIState), 1381 VMSTATE_UINT16(norintstsen, SDHCIState), 1382 VMSTATE_UINT16(errintstsen, SDHCIState), 1383 VMSTATE_UINT16(norintsigen, SDHCIState), 1384 VMSTATE_UINT16(errintsigen, SDHCIState), 1385 VMSTATE_UINT16(acmd12errsts, SDHCIState), 1386 VMSTATE_UINT16(data_count, SDHCIState), 1387 VMSTATE_UINT64(admasysaddr, SDHCIState), 1388 VMSTATE_UINT8(stopped_state, SDHCIState), 1389 VMSTATE_VBUFFER_UINT32(fifo_buffer, SDHCIState, 1, NULL, buf_maxsz), 1390 VMSTATE_TIMER_PTR(insert_timer, SDHCIState), 1391 VMSTATE_TIMER_PTR(transfer_timer, SDHCIState), 1392 VMSTATE_END_OF_LIST() 1393 }, 1394 .subsections = (const VMStateDescription*[]) { 1395 &sdhci_pending_insert_vmstate, 1396 NULL 1397 }, 1398 }; 1399 1400 void sdhci_common_class_init(ObjectClass *klass, void *data) 1401 { 1402 DeviceClass *dc = DEVICE_CLASS(klass); 1403 1404 set_bit(DEVICE_CATEGORY_STORAGE, dc->categories); 1405 dc->vmsd = &sdhci_vmstate; 1406 dc->reset = sdhci_poweron_reset; 1407 } 1408 1409 /* --- qdev SysBus --- */ 1410 1411 static Property sdhci_sysbus_properties[] = { 1412 DEFINE_SDHCI_COMMON_PROPERTIES(SDHCIState), 1413 DEFINE_PROP_BOOL("pending-insert-quirk", SDHCIState, pending_insert_quirk, 1414 false), 1415 DEFINE_PROP_LINK("dma", SDHCIState, 1416 dma_mr, TYPE_MEMORY_REGION, MemoryRegion *), 1417 DEFINE_PROP_END_OF_LIST(), 1418 }; 1419 1420 static void sdhci_sysbus_init(Object *obj) 1421 { 1422 SDHCIState *s = SYSBUS_SDHCI(obj); 1423 1424 sdhci_initfn(s); 1425 } 1426 1427 static void sdhci_sysbus_finalize(Object *obj) 1428 { 1429 SDHCIState *s = SYSBUS_SDHCI(obj); 1430 1431 if (s->dma_mr) { 1432 object_unparent(OBJECT(s->dma_mr)); 1433 } 1434 1435 sdhci_uninitfn(s); 1436 } 1437 1438 static void sdhci_sysbus_realize(DeviceState *dev, Error **errp) 1439 { 1440 ERRP_GUARD(); 1441 SDHCIState *s = SYSBUS_SDHCI(dev); 1442 SysBusDevice *sbd = SYS_BUS_DEVICE(dev); 1443 1444 sdhci_common_realize(s, errp); 1445 if (*errp) { 1446 return; 1447 } 1448 1449 if (s->dma_mr) { 1450 s->dma_as = &s->sysbus_dma_as; 1451 address_space_init(s->dma_as, s->dma_mr, "sdhci-dma"); 1452 } else { 1453 /* use system_memory() if property "dma" not set */ 1454 s->dma_as = &address_space_memory; 1455 } 1456 1457 sysbus_init_irq(sbd, &s->irq); 1458 1459 sysbus_init_mmio(sbd, &s->iomem); 1460 } 1461 1462 static void sdhci_sysbus_unrealize(DeviceState *dev) 1463 { 1464 SDHCIState *s = SYSBUS_SDHCI(dev); 1465 1466 sdhci_common_unrealize(s); 1467 1468 if (s->dma_mr) { 1469 address_space_destroy(s->dma_as); 1470 } 1471 } 1472 1473 static void sdhci_sysbus_class_init(ObjectClass *klass, void *data) 1474 { 1475 DeviceClass *dc = DEVICE_CLASS(klass); 1476 1477 device_class_set_props(dc, sdhci_sysbus_properties); 1478 dc->realize = sdhci_sysbus_realize; 1479 dc->unrealize = sdhci_sysbus_unrealize; 1480 1481 sdhci_common_class_init(klass, data); 1482 } 1483 1484 static const TypeInfo sdhci_sysbus_info = { 1485 .name = TYPE_SYSBUS_SDHCI, 1486 .parent = TYPE_SYS_BUS_DEVICE, 1487 .instance_size = sizeof(SDHCIState), 1488 .instance_init = sdhci_sysbus_init, 1489 .instance_finalize = sdhci_sysbus_finalize, 1490 .class_init = sdhci_sysbus_class_init, 1491 }; 1492 1493 /* --- qdev bus master --- */ 1494 1495 static void sdhci_bus_class_init(ObjectClass *klass, void *data) 1496 { 1497 SDBusClass *sbc = SD_BUS_CLASS(klass); 1498 1499 sbc->set_inserted = sdhci_set_inserted; 1500 sbc->set_readonly = sdhci_set_readonly; 1501 } 1502 1503 static const TypeInfo sdhci_bus_info = { 1504 .name = TYPE_SDHCI_BUS, 1505 .parent = TYPE_SD_BUS, 1506 .instance_size = sizeof(SDBus), 1507 .class_init = sdhci_bus_class_init, 1508 }; 1509 1510 /* --- qdev i.MX eSDHC --- */ 1511 1512 static uint64_t usdhc_read(void *opaque, hwaddr offset, unsigned size) 1513 { 1514 SDHCIState *s = SYSBUS_SDHCI(opaque); 1515 uint32_t ret; 1516 uint16_t hostctl1; 1517 1518 switch (offset) { 1519 default: 1520 return sdhci_read(opaque, offset, size); 1521 1522 case SDHC_HOSTCTL: 1523 /* 1524 * For a detailed explanation on the following bit 1525 * manipulation code see comments in a similar part of 1526 * usdhc_write() 1527 */ 1528 hostctl1 = SDHC_DMA_TYPE(s->hostctl1) << (8 - 3); 1529 1530 if (s->hostctl1 & SDHC_CTRL_8BITBUS) { 1531 hostctl1 |= ESDHC_CTRL_8BITBUS; 1532 } 1533 1534 if (s->hostctl1 & SDHC_CTRL_4BITBUS) { 1535 hostctl1 |= ESDHC_CTRL_4BITBUS; 1536 } 1537 1538 ret = hostctl1; 1539 ret |= (uint32_t)s->blkgap << 16; 1540 ret |= (uint32_t)s->wakcon << 24; 1541 1542 break; 1543 1544 case SDHC_PRNSTS: 1545 /* Add SDSTB (SD Clock Stable) bit to PRNSTS */ 1546 ret = sdhci_read(opaque, offset, size) & ~ESDHC_PRNSTS_SDSTB; 1547 if (s->clkcon & SDHC_CLOCK_INT_STABLE) { 1548 ret |= ESDHC_PRNSTS_SDSTB; 1549 } 1550 break; 1551 1552 case ESDHC_VENDOR_SPEC: 1553 ret = s->vendor_spec; 1554 break; 1555 case ESDHC_DLL_CTRL: 1556 case ESDHC_TUNE_CTRL_STATUS: 1557 case ESDHC_UNDOCUMENTED_REG27: 1558 case ESDHC_TUNING_CTRL: 1559 case ESDHC_MIX_CTRL: 1560 case ESDHC_WTMK_LVL: 1561 ret = 0; 1562 break; 1563 } 1564 1565 return ret; 1566 } 1567 1568 static void 1569 usdhc_write(void *opaque, hwaddr offset, uint64_t val, unsigned size) 1570 { 1571 SDHCIState *s = SYSBUS_SDHCI(opaque); 1572 uint8_t hostctl1; 1573 uint32_t value = (uint32_t)val; 1574 1575 switch (offset) { 1576 case ESDHC_DLL_CTRL: 1577 case ESDHC_TUNE_CTRL_STATUS: 1578 case ESDHC_UNDOCUMENTED_REG27: 1579 case ESDHC_TUNING_CTRL: 1580 case ESDHC_WTMK_LVL: 1581 break; 1582 1583 case ESDHC_VENDOR_SPEC: 1584 s->vendor_spec = value; 1585 switch (s->vendor) { 1586 case SDHCI_VENDOR_IMX: 1587 if (value & ESDHC_IMX_FRC_SDCLK_ON) { 1588 s->prnsts &= ~SDHC_IMX_CLOCK_GATE_OFF; 1589 } else { 1590 s->prnsts |= SDHC_IMX_CLOCK_GATE_OFF; 1591 } 1592 break; 1593 default: 1594 break; 1595 } 1596 break; 1597 1598 case SDHC_HOSTCTL: 1599 /* 1600 * Here's What ESDHCI has at offset 0x28 (SDHC_HOSTCTL) 1601 * 1602 * 7 6 5 4 3 2 1 0 1603 * |-----------+--------+--------+-----------+----------+---------| 1604 * | Card | Card | Endian | DATA3 | Data | Led | 1605 * | Detect | Detect | Mode | as Card | Transfer | Control | 1606 * | Signal | Test | | Detection | Width | | 1607 * | Selection | Level | | Pin | | | 1608 * |-----------+--------+--------+-----------+----------+---------| 1609 * 1610 * and 0x29 1611 * 1612 * 15 10 9 8 1613 * |----------+------| 1614 * | Reserved | DMA | 1615 * | | Sel. | 1616 * | | | 1617 * |----------+------| 1618 * 1619 * and here's what SDCHI spec expects those offsets to be: 1620 * 1621 * 0x28 (Host Control Register) 1622 * 1623 * 7 6 5 4 3 2 1 0 1624 * |--------+--------+----------+------+--------+----------+---------| 1625 * | Card | Card | Extended | DMA | High | Data | LED | 1626 * | Detect | Detect | Data | Sel. | Speed | Transfer | Control | 1627 * | Signal | Test | Transfer | | Enable | Width | | 1628 * | Sel. | Level | Width | | | | | 1629 * |--------+--------+----------+------+--------+----------+---------| 1630 * 1631 * and 0x29 (Power Control Register) 1632 * 1633 * |----------------------------------| 1634 * | Power Control Register | 1635 * | | 1636 * | Description omitted, | 1637 * | since it has no analog in ESDHCI | 1638 * | | 1639 * |----------------------------------| 1640 * 1641 * Since offsets 0x2A and 0x2B should be compatible between 1642 * both IP specs we only need to reconcile least 16-bit of the 1643 * word we've been given. 1644 */ 1645 1646 /* 1647 * First, save bits 7 6 and 0 since they are identical 1648 */ 1649 hostctl1 = value & (SDHC_CTRL_LED | 1650 SDHC_CTRL_CDTEST_INS | 1651 SDHC_CTRL_CDTEST_EN); 1652 /* 1653 * Second, split "Data Transfer Width" from bits 2 and 1 in to 1654 * bits 5 and 1 1655 */ 1656 if (value & ESDHC_CTRL_8BITBUS) { 1657 hostctl1 |= SDHC_CTRL_8BITBUS; 1658 } 1659 1660 if (value & ESDHC_CTRL_4BITBUS) { 1661 hostctl1 |= ESDHC_CTRL_4BITBUS; 1662 } 1663 1664 /* 1665 * Third, move DMA select from bits 9 and 8 to bits 4 and 3 1666 */ 1667 hostctl1 |= SDHC_DMA_TYPE(value >> (8 - 3)); 1668 1669 /* 1670 * Now place the corrected value into low 16-bit of the value 1671 * we are going to give standard SDHCI write function 1672 * 1673 * NOTE: This transformation should be the inverse of what can 1674 * be found in drivers/mmc/host/sdhci-esdhc-imx.c in Linux 1675 * kernel 1676 */ 1677 value &= ~UINT16_MAX; 1678 value |= hostctl1; 1679 value |= (uint16_t)s->pwrcon << 8; 1680 1681 sdhci_write(opaque, offset, value, size); 1682 break; 1683 1684 case ESDHC_MIX_CTRL: 1685 /* 1686 * So, when SD/MMC stack in Linux tries to write to "Transfer 1687 * Mode Register", ESDHC i.MX quirk code will translate it 1688 * into a write to ESDHC_MIX_CTRL, so we do the opposite in 1689 * order to get where we started 1690 * 1691 * Note that Auto CMD23 Enable bit is located in a wrong place 1692 * on i.MX, but since it is not used by QEMU we do not care. 1693 * 1694 * We don't want to call sdhci_write(.., SDHC_TRNMOD, ...) 1695 * here becuase it will result in a call to 1696 * sdhci_send_command(s) which we don't want. 1697 * 1698 */ 1699 s->trnmod = value & UINT16_MAX; 1700 break; 1701 case SDHC_TRNMOD: 1702 /* 1703 * Similar to above, but this time a write to "Command 1704 * Register" will be translated into a 4-byte write to 1705 * "Transfer Mode register" where lower 16-bit of value would 1706 * be set to zero. So what we do is fill those bits with 1707 * cached value from s->trnmod and let the SDHCI 1708 * infrastructure handle the rest 1709 */ 1710 sdhci_write(opaque, offset, val | s->trnmod, size); 1711 break; 1712 case SDHC_BLKSIZE: 1713 /* 1714 * ESDHCI does not implement "Host SDMA Buffer Boundary", and 1715 * Linux driver will try to zero this field out which will 1716 * break the rest of SDHCI emulation. 1717 * 1718 * Linux defaults to maximum possible setting (512K boundary) 1719 * and it seems to be the only option that i.MX IP implements, 1720 * so we artificially set it to that value. 1721 */ 1722 val |= 0x7 << 12; 1723 /* FALLTHROUGH */ 1724 default: 1725 sdhci_write(opaque, offset, val, size); 1726 break; 1727 } 1728 } 1729 1730 static const MemoryRegionOps usdhc_mmio_ops = { 1731 .read = usdhc_read, 1732 .write = usdhc_write, 1733 .valid = { 1734 .min_access_size = 1, 1735 .max_access_size = 4, 1736 .unaligned = false 1737 }, 1738 .endianness = DEVICE_LITTLE_ENDIAN, 1739 }; 1740 1741 static void imx_usdhc_init(Object *obj) 1742 { 1743 SDHCIState *s = SYSBUS_SDHCI(obj); 1744 1745 s->io_ops = &usdhc_mmio_ops; 1746 s->quirks = SDHCI_QUIRK_NO_BUSY_IRQ; 1747 } 1748 1749 static const TypeInfo imx_usdhc_info = { 1750 .name = TYPE_IMX_USDHC, 1751 .parent = TYPE_SYSBUS_SDHCI, 1752 .instance_init = imx_usdhc_init, 1753 }; 1754 1755 /* --- qdev Samsung s3c --- */ 1756 1757 #define S3C_SDHCI_CONTROL2 0x80 1758 #define S3C_SDHCI_CONTROL3 0x84 1759 #define S3C_SDHCI_CONTROL4 0x8c 1760 1761 static uint64_t sdhci_s3c_read(void *opaque, hwaddr offset, unsigned size) 1762 { 1763 uint64_t ret; 1764 1765 switch (offset) { 1766 case S3C_SDHCI_CONTROL2: 1767 case S3C_SDHCI_CONTROL3: 1768 case S3C_SDHCI_CONTROL4: 1769 /* ignore */ 1770 ret = 0; 1771 break; 1772 default: 1773 ret = sdhci_read(opaque, offset, size); 1774 break; 1775 } 1776 1777 return ret; 1778 } 1779 1780 static void sdhci_s3c_write(void *opaque, hwaddr offset, uint64_t val, 1781 unsigned size) 1782 { 1783 switch (offset) { 1784 case S3C_SDHCI_CONTROL2: 1785 case S3C_SDHCI_CONTROL3: 1786 case S3C_SDHCI_CONTROL4: 1787 /* ignore */ 1788 break; 1789 default: 1790 sdhci_write(opaque, offset, val, size); 1791 break; 1792 } 1793 } 1794 1795 static const MemoryRegionOps sdhci_s3c_mmio_ops = { 1796 .read = sdhci_s3c_read, 1797 .write = sdhci_s3c_write, 1798 .valid = { 1799 .min_access_size = 1, 1800 .max_access_size = 4, 1801 .unaligned = false 1802 }, 1803 .endianness = DEVICE_LITTLE_ENDIAN, 1804 }; 1805 1806 static void sdhci_s3c_init(Object *obj) 1807 { 1808 SDHCIState *s = SYSBUS_SDHCI(obj); 1809 1810 s->io_ops = &sdhci_s3c_mmio_ops; 1811 } 1812 1813 static const TypeInfo sdhci_s3c_info = { 1814 .name = TYPE_S3C_SDHCI , 1815 .parent = TYPE_SYSBUS_SDHCI, 1816 .instance_init = sdhci_s3c_init, 1817 }; 1818 1819 static void sdhci_register_types(void) 1820 { 1821 type_register_static(&sdhci_sysbus_info); 1822 type_register_static(&sdhci_bus_info); 1823 type_register_static(&imx_usdhc_info); 1824 type_register_static(&sdhci_s3c_info); 1825 } 1826 1827 type_init(sdhci_register_types) 1828