1d7dfca08SIgor Mitsyanko /* 2d7dfca08SIgor Mitsyanko * SD Association Host Standard Specification v2.0 controller emulation 3d7dfca08SIgor Mitsyanko * 4d7dfca08SIgor Mitsyanko * Copyright (c) 2011 Samsung Electronics Co., Ltd. 5d7dfca08SIgor Mitsyanko * Mitsyanko Igor <i.mitsyanko@samsung.com> 6d7dfca08SIgor Mitsyanko * Peter A.G. Crosthwaite <peter.crosthwaite@petalogix.com> 7d7dfca08SIgor Mitsyanko * 8d7dfca08SIgor Mitsyanko * Based on MMC controller for Samsung S5PC1xx-based board emulation 9d7dfca08SIgor Mitsyanko * by Alexey Merkulov and Vladimir Monakhov. 10d7dfca08SIgor Mitsyanko * 11d7dfca08SIgor Mitsyanko * This program is free software; you can redistribute it and/or modify it 12d7dfca08SIgor Mitsyanko * under the terms of the GNU General Public License as published by the 13d7dfca08SIgor Mitsyanko * Free Software Foundation; either version 2 of the License, or (at your 14d7dfca08SIgor Mitsyanko * option) any later version. 15d7dfca08SIgor Mitsyanko * 16d7dfca08SIgor Mitsyanko * This program is distributed in the hope that it will be useful, 17d7dfca08SIgor Mitsyanko * but WITHOUT ANY WARRANTY; without even the implied warranty of 18d7dfca08SIgor Mitsyanko * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. 19d7dfca08SIgor Mitsyanko * See the GNU General Public License for more details. 20d7dfca08SIgor Mitsyanko * 21d7dfca08SIgor Mitsyanko * You should have received a copy of the GNU General Public License along 22d7dfca08SIgor Mitsyanko * with this program; if not, see <http://www.gnu.org/licenses/>. 23d7dfca08SIgor Mitsyanko */ 24d7dfca08SIgor Mitsyanko 2583c9f4caSPaolo Bonzini #include "hw/hw.h" 26fa1d36dfSMarkus Armbruster #include "sysemu/block-backend.h" 27d7dfca08SIgor Mitsyanko #include "sysemu/blockdev.h" 28d7dfca08SIgor Mitsyanko #include "sysemu/dma.h" 29d7dfca08SIgor Mitsyanko #include "qemu/timer.h" 30d7dfca08SIgor Mitsyanko #include "qemu/bitops.h" 31d7dfca08SIgor Mitsyanko 3247b43a1fSPaolo Bonzini #include "sdhci.h" 33d7dfca08SIgor Mitsyanko 34d7dfca08SIgor Mitsyanko /* host controller debug messages */ 35d7dfca08SIgor Mitsyanko #ifndef SDHC_DEBUG 36d7dfca08SIgor Mitsyanko #define SDHC_DEBUG 0 37d7dfca08SIgor Mitsyanko #endif 38d7dfca08SIgor Mitsyanko 39d7dfca08SIgor Mitsyanko #if SDHC_DEBUG == 0 40d7dfca08SIgor Mitsyanko #define DPRINT_L1(fmt, args...) do { } while (0) 41d7dfca08SIgor Mitsyanko #define DPRINT_L2(fmt, args...) do { } while (0) 42d7dfca08SIgor Mitsyanko #define ERRPRINT(fmt, args...) do { } while (0) 43d7dfca08SIgor Mitsyanko #elif SDHC_DEBUG == 1 44d7dfca08SIgor Mitsyanko #define DPRINT_L1(fmt, args...) \ 45d7dfca08SIgor Mitsyanko do {fprintf(stderr, "QEMU SDHC: "fmt, ## args); } while (0) 46d7dfca08SIgor Mitsyanko #define DPRINT_L2(fmt, args...) do { } while (0) 47d7dfca08SIgor Mitsyanko #define ERRPRINT(fmt, args...) \ 48d7dfca08SIgor Mitsyanko do {fprintf(stderr, "QEMU SDHC ERROR: "fmt, ## args); } while (0) 49d7dfca08SIgor Mitsyanko #else 50d7dfca08SIgor Mitsyanko #define DPRINT_L1(fmt, args...) \ 51d7dfca08SIgor Mitsyanko do {fprintf(stderr, "QEMU SDHC: "fmt, ## args); } while (0) 52d7dfca08SIgor Mitsyanko #define DPRINT_L2(fmt, args...) \ 53d7dfca08SIgor Mitsyanko do {fprintf(stderr, "QEMU SDHC: "fmt, ## args); } while (0) 54d7dfca08SIgor Mitsyanko #define ERRPRINT(fmt, args...) \ 55d7dfca08SIgor Mitsyanko do {fprintf(stderr, "QEMU SDHC ERROR: "fmt, ## args); } while (0) 56d7dfca08SIgor Mitsyanko #endif 57d7dfca08SIgor Mitsyanko 58d7dfca08SIgor Mitsyanko /* Default SD/MMC host controller features information, which will be 59d7dfca08SIgor Mitsyanko * presented in CAPABILITIES register of generic SD host controller at reset. 60d7dfca08SIgor Mitsyanko * If not stated otherwise: 61d7dfca08SIgor Mitsyanko * 0 - not supported, 1 - supported, other - prohibited. 62d7dfca08SIgor Mitsyanko */ 63d7dfca08SIgor Mitsyanko #define SDHC_CAPAB_64BITBUS 0ul /* 64-bit System Bus Support */ 64d7dfca08SIgor Mitsyanko #define SDHC_CAPAB_18V 1ul /* Voltage support 1.8v */ 65d7dfca08SIgor Mitsyanko #define SDHC_CAPAB_30V 0ul /* Voltage support 3.0v */ 66d7dfca08SIgor Mitsyanko #define SDHC_CAPAB_33V 1ul /* Voltage support 3.3v */ 67d7dfca08SIgor Mitsyanko #define SDHC_CAPAB_SUSPRESUME 0ul /* Suspend/resume support */ 68d7dfca08SIgor Mitsyanko #define SDHC_CAPAB_SDMA 1ul /* SDMA support */ 69d7dfca08SIgor Mitsyanko #define SDHC_CAPAB_HIGHSPEED 1ul /* High speed support */ 70d7dfca08SIgor Mitsyanko #define SDHC_CAPAB_ADMA1 1ul /* ADMA1 support */ 71d7dfca08SIgor Mitsyanko #define SDHC_CAPAB_ADMA2 1ul /* ADMA2 support */ 72d7dfca08SIgor Mitsyanko /* Maximum host controller R/W buffers size 73d7dfca08SIgor Mitsyanko * Possible values: 512, 1024, 2048 bytes */ 74d7dfca08SIgor Mitsyanko #define SDHC_CAPAB_MAXBLOCKLENGTH 512ul 75d7dfca08SIgor Mitsyanko /* Maximum clock frequency for SDclock in MHz 76d7dfca08SIgor Mitsyanko * value in range 10-63 MHz, 0 - not defined */ 77c7ff8daaSKevin O'Connor #define SDHC_CAPAB_BASECLKFREQ 52ul 78d7dfca08SIgor Mitsyanko #define SDHC_CAPAB_TOUNIT 1ul /* Timeout clock unit 0 - kHz, 1 - MHz */ 79d7dfca08SIgor Mitsyanko /* Timeout clock frequency 1-63, 0 - not defined */ 80c7ff8daaSKevin O'Connor #define SDHC_CAPAB_TOCLKFREQ 52ul 81d7dfca08SIgor Mitsyanko 82d7dfca08SIgor Mitsyanko /* Now check all parameters and calculate CAPABILITIES REGISTER value */ 83d7dfca08SIgor Mitsyanko #if SDHC_CAPAB_64BITBUS > 1 || SDHC_CAPAB_18V > 1 || SDHC_CAPAB_30V > 1 || \ 84d7dfca08SIgor Mitsyanko SDHC_CAPAB_33V > 1 || SDHC_CAPAB_SUSPRESUME > 1 || SDHC_CAPAB_SDMA > 1 || \ 85d7dfca08SIgor Mitsyanko SDHC_CAPAB_HIGHSPEED > 1 || SDHC_CAPAB_ADMA2 > 1 || SDHC_CAPAB_ADMA1 > 1 ||\ 86d7dfca08SIgor Mitsyanko SDHC_CAPAB_TOUNIT > 1 87d7dfca08SIgor Mitsyanko #error Capabilities features can have value 0 or 1 only! 88d7dfca08SIgor Mitsyanko #endif 89d7dfca08SIgor Mitsyanko 90d7dfca08SIgor Mitsyanko #if SDHC_CAPAB_MAXBLOCKLENGTH == 512 91d7dfca08SIgor Mitsyanko #define MAX_BLOCK_LENGTH 0ul 92d7dfca08SIgor Mitsyanko #elif SDHC_CAPAB_MAXBLOCKLENGTH == 1024 93d7dfca08SIgor Mitsyanko #define MAX_BLOCK_LENGTH 1ul 94d7dfca08SIgor Mitsyanko #elif SDHC_CAPAB_MAXBLOCKLENGTH == 2048 95d7dfca08SIgor Mitsyanko #define MAX_BLOCK_LENGTH 2ul 96d7dfca08SIgor Mitsyanko #else 97d7dfca08SIgor Mitsyanko #error Max host controller block size can have value 512, 1024 or 2048 only! 98d7dfca08SIgor Mitsyanko #endif 99d7dfca08SIgor Mitsyanko 100d7dfca08SIgor Mitsyanko #if (SDHC_CAPAB_BASECLKFREQ > 0 && SDHC_CAPAB_BASECLKFREQ < 10) || \ 101d7dfca08SIgor Mitsyanko SDHC_CAPAB_BASECLKFREQ > 63 102d7dfca08SIgor Mitsyanko #error SDclock frequency can have value in range 0, 10-63 only! 103d7dfca08SIgor Mitsyanko #endif 104d7dfca08SIgor Mitsyanko 105d7dfca08SIgor Mitsyanko #if SDHC_CAPAB_TOCLKFREQ > 63 106d7dfca08SIgor Mitsyanko #error Timeout clock frequency can have value in range 0-63 only! 107d7dfca08SIgor Mitsyanko #endif 108d7dfca08SIgor Mitsyanko 109d7dfca08SIgor Mitsyanko #define SDHC_CAPAB_REG_DEFAULT \ 110d7dfca08SIgor Mitsyanko ((SDHC_CAPAB_64BITBUS << 28) | (SDHC_CAPAB_18V << 26) | \ 111d7dfca08SIgor Mitsyanko (SDHC_CAPAB_30V << 25) | (SDHC_CAPAB_33V << 24) | \ 112d7dfca08SIgor Mitsyanko (SDHC_CAPAB_SUSPRESUME << 23) | (SDHC_CAPAB_SDMA << 22) | \ 113d7dfca08SIgor Mitsyanko (SDHC_CAPAB_HIGHSPEED << 21) | (SDHC_CAPAB_ADMA1 << 20) | \ 114d7dfca08SIgor Mitsyanko (SDHC_CAPAB_ADMA2 << 19) | (MAX_BLOCK_LENGTH << 16) | \ 115d7dfca08SIgor Mitsyanko (SDHC_CAPAB_BASECLKFREQ << 8) | (SDHC_CAPAB_TOUNIT << 7) | \ 116d7dfca08SIgor Mitsyanko (SDHC_CAPAB_TOCLKFREQ)) 117d7dfca08SIgor Mitsyanko 118d7dfca08SIgor Mitsyanko #define MASKED_WRITE(reg, mask, val) (reg = (reg & (mask)) | (val)) 119d7dfca08SIgor Mitsyanko 120d7dfca08SIgor Mitsyanko static uint8_t sdhci_slotint(SDHCIState *s) 121d7dfca08SIgor Mitsyanko { 122d7dfca08SIgor Mitsyanko return (s->norintsts & s->norintsigen) || (s->errintsts & s->errintsigen) || 123d7dfca08SIgor Mitsyanko ((s->norintsts & SDHC_NIS_INSERT) && (s->wakcon & SDHC_WKUP_ON_INS)) || 124d7dfca08SIgor Mitsyanko ((s->norintsts & SDHC_NIS_REMOVE) && (s->wakcon & SDHC_WKUP_ON_RMV)); 125d7dfca08SIgor Mitsyanko } 126d7dfca08SIgor Mitsyanko 127d7dfca08SIgor Mitsyanko static inline void sdhci_update_irq(SDHCIState *s) 128d7dfca08SIgor Mitsyanko { 129d7dfca08SIgor Mitsyanko qemu_set_irq(s->irq, sdhci_slotint(s)); 130d7dfca08SIgor Mitsyanko } 131d7dfca08SIgor Mitsyanko 132d7dfca08SIgor Mitsyanko static void sdhci_raise_insertion_irq(void *opaque) 133d7dfca08SIgor Mitsyanko { 134d7dfca08SIgor Mitsyanko SDHCIState *s = (SDHCIState *)opaque; 135d7dfca08SIgor Mitsyanko 136d7dfca08SIgor Mitsyanko if (s->norintsts & SDHC_NIS_REMOVE) { 137bc72ad67SAlex Bligh timer_mod(s->insert_timer, 138bc72ad67SAlex Bligh qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + SDHC_INSERTION_DELAY); 139d7dfca08SIgor Mitsyanko } else { 140d7dfca08SIgor Mitsyanko s->prnsts = 0x1ff0000; 141d7dfca08SIgor Mitsyanko if (s->norintstsen & SDHC_NISEN_INSERT) { 142d7dfca08SIgor Mitsyanko s->norintsts |= SDHC_NIS_INSERT; 143d7dfca08SIgor Mitsyanko } 144d7dfca08SIgor Mitsyanko sdhci_update_irq(s); 145d7dfca08SIgor Mitsyanko } 146d7dfca08SIgor Mitsyanko } 147d7dfca08SIgor Mitsyanko 148d7dfca08SIgor Mitsyanko static void sdhci_insert_eject_cb(void *opaque, int irq, int level) 149d7dfca08SIgor Mitsyanko { 150d7dfca08SIgor Mitsyanko SDHCIState *s = (SDHCIState *)opaque; 151d7dfca08SIgor Mitsyanko DPRINT_L1("Card state changed: %s!\n", level ? "insert" : "eject"); 152d7dfca08SIgor Mitsyanko 153d7dfca08SIgor Mitsyanko if ((s->norintsts & SDHC_NIS_REMOVE) && level) { 154d7dfca08SIgor Mitsyanko /* Give target some time to notice card ejection */ 155bc72ad67SAlex Bligh timer_mod(s->insert_timer, 156bc72ad67SAlex Bligh qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + SDHC_INSERTION_DELAY); 157d7dfca08SIgor Mitsyanko } else { 158d7dfca08SIgor Mitsyanko if (level) { 159d7dfca08SIgor Mitsyanko s->prnsts = 0x1ff0000; 160d7dfca08SIgor Mitsyanko if (s->norintstsen & SDHC_NISEN_INSERT) { 161d7dfca08SIgor Mitsyanko s->norintsts |= SDHC_NIS_INSERT; 162d7dfca08SIgor Mitsyanko } 163d7dfca08SIgor Mitsyanko } else { 164d7dfca08SIgor Mitsyanko s->prnsts = 0x1fa0000; 165d7dfca08SIgor Mitsyanko s->pwrcon &= ~SDHC_POWER_ON; 166d7dfca08SIgor Mitsyanko s->clkcon &= ~SDHC_CLOCK_SDCLK_EN; 167d7dfca08SIgor Mitsyanko if (s->norintstsen & SDHC_NISEN_REMOVE) { 168d7dfca08SIgor Mitsyanko s->norintsts |= SDHC_NIS_REMOVE; 169d7dfca08SIgor Mitsyanko } 170d7dfca08SIgor Mitsyanko } 171d7dfca08SIgor Mitsyanko sdhci_update_irq(s); 172d7dfca08SIgor Mitsyanko } 173d7dfca08SIgor Mitsyanko } 174d7dfca08SIgor Mitsyanko 175d7dfca08SIgor Mitsyanko static void sdhci_card_readonly_cb(void *opaque, int irq, int level) 176d7dfca08SIgor Mitsyanko { 177d7dfca08SIgor Mitsyanko SDHCIState *s = (SDHCIState *)opaque; 178d7dfca08SIgor Mitsyanko 179d7dfca08SIgor Mitsyanko if (level) { 180d7dfca08SIgor Mitsyanko s->prnsts &= ~SDHC_WRITE_PROTECT; 181d7dfca08SIgor Mitsyanko } else { 182d7dfca08SIgor Mitsyanko /* Write enabled */ 183d7dfca08SIgor Mitsyanko s->prnsts |= SDHC_WRITE_PROTECT; 184d7dfca08SIgor Mitsyanko } 185d7dfca08SIgor Mitsyanko } 186d7dfca08SIgor Mitsyanko 187d7dfca08SIgor Mitsyanko static void sdhci_reset(SDHCIState *s) 188d7dfca08SIgor Mitsyanko { 189bc72ad67SAlex Bligh timer_del(s->insert_timer); 190bc72ad67SAlex Bligh timer_del(s->transfer_timer); 191d7dfca08SIgor Mitsyanko /* Set all registers to 0. Capabilities registers are not cleared 192d7dfca08SIgor Mitsyanko * and assumed to always preserve their value, given to them during 193d7dfca08SIgor Mitsyanko * initialization */ 194d7dfca08SIgor Mitsyanko memset(&s->sdmasysad, 0, (uintptr_t)&s->capareg - (uintptr_t)&s->sdmasysad); 195d7dfca08SIgor Mitsyanko 196d7dfca08SIgor Mitsyanko sd_set_cb(s->card, s->ro_cb, s->eject_cb); 197d7dfca08SIgor Mitsyanko s->data_count = 0; 198d7dfca08SIgor Mitsyanko s->stopped_state = sdhc_not_stopped; 199d7dfca08SIgor Mitsyanko } 200d7dfca08SIgor Mitsyanko 201d368ba43SKevin O'Connor static void sdhci_data_transfer(void *opaque); 202d7dfca08SIgor Mitsyanko 203d7dfca08SIgor Mitsyanko static void sdhci_send_command(SDHCIState *s) 204d7dfca08SIgor Mitsyanko { 205d7dfca08SIgor Mitsyanko SDRequest request; 206d7dfca08SIgor Mitsyanko uint8_t response[16]; 207d7dfca08SIgor Mitsyanko int rlen; 208d7dfca08SIgor Mitsyanko 209d7dfca08SIgor Mitsyanko s->errintsts = 0; 210d7dfca08SIgor Mitsyanko s->acmd12errsts = 0; 211d7dfca08SIgor Mitsyanko request.cmd = s->cmdreg >> 8; 212d7dfca08SIgor Mitsyanko request.arg = s->argument; 213d7dfca08SIgor Mitsyanko DPRINT_L1("sending CMD%u ARG[0x%08x]\n", request.cmd, request.arg); 214d7dfca08SIgor Mitsyanko rlen = sd_do_command(s->card, &request, response); 215d7dfca08SIgor Mitsyanko 216d7dfca08SIgor Mitsyanko if (s->cmdreg & SDHC_CMD_RESPONSE) { 217d7dfca08SIgor Mitsyanko if (rlen == 4) { 218d7dfca08SIgor Mitsyanko s->rspreg[0] = (response[0] << 24) | (response[1] << 16) | 219d7dfca08SIgor Mitsyanko (response[2] << 8) | response[3]; 220d7dfca08SIgor Mitsyanko s->rspreg[1] = s->rspreg[2] = s->rspreg[3] = 0; 221d7dfca08SIgor Mitsyanko DPRINT_L1("Response: RSPREG[31..0]=0x%08x\n", s->rspreg[0]); 222d7dfca08SIgor Mitsyanko } else if (rlen == 16) { 223d7dfca08SIgor Mitsyanko s->rspreg[0] = (response[11] << 24) | (response[12] << 16) | 224d7dfca08SIgor Mitsyanko (response[13] << 8) | response[14]; 225d7dfca08SIgor Mitsyanko s->rspreg[1] = (response[7] << 24) | (response[8] << 16) | 226d7dfca08SIgor Mitsyanko (response[9] << 8) | response[10]; 227d7dfca08SIgor Mitsyanko s->rspreg[2] = (response[3] << 24) | (response[4] << 16) | 228d7dfca08SIgor Mitsyanko (response[5] << 8) | response[6]; 229d7dfca08SIgor Mitsyanko s->rspreg[3] = (response[0] << 16) | (response[1] << 8) | 230d7dfca08SIgor Mitsyanko response[2]; 231d7dfca08SIgor Mitsyanko DPRINT_L1("Response received:\n RSPREG[127..96]=0x%08x, RSPREG[95.." 232d7dfca08SIgor Mitsyanko "64]=0x%08x,\n RSPREG[63..32]=0x%08x, RSPREG[31..0]=0x%08x\n", 233d7dfca08SIgor Mitsyanko s->rspreg[3], s->rspreg[2], s->rspreg[1], s->rspreg[0]); 234d7dfca08SIgor Mitsyanko } else { 235d7dfca08SIgor Mitsyanko ERRPRINT("Timeout waiting for command response\n"); 236d7dfca08SIgor Mitsyanko if (s->errintstsen & SDHC_EISEN_CMDTIMEOUT) { 237d7dfca08SIgor Mitsyanko s->errintsts |= SDHC_EIS_CMDTIMEOUT; 238d7dfca08SIgor Mitsyanko s->norintsts |= SDHC_NIS_ERR; 239d7dfca08SIgor Mitsyanko } 240d7dfca08SIgor Mitsyanko } 241d7dfca08SIgor Mitsyanko 242d7dfca08SIgor Mitsyanko if ((s->norintstsen & SDHC_NISEN_TRSCMP) && 243d7dfca08SIgor Mitsyanko (s->cmdreg & SDHC_CMD_RESPONSE) == SDHC_CMD_RSP_WITH_BUSY) { 244d7dfca08SIgor Mitsyanko s->norintsts |= SDHC_NIS_TRSCMP; 245d7dfca08SIgor Mitsyanko } 246d7dfca08SIgor Mitsyanko } else if (rlen != 0 && (s->errintstsen & SDHC_EISEN_CMDIDX)) { 247d7dfca08SIgor Mitsyanko s->errintsts |= SDHC_EIS_CMDIDX; 248d7dfca08SIgor Mitsyanko s->norintsts |= SDHC_NIS_ERR; 249d7dfca08SIgor Mitsyanko } 250d7dfca08SIgor Mitsyanko 251d7dfca08SIgor Mitsyanko if (s->norintstsen & SDHC_NISEN_CMDCMP) { 252d7dfca08SIgor Mitsyanko s->norintsts |= SDHC_NIS_CMDCMP; 253d7dfca08SIgor Mitsyanko } 254d7dfca08SIgor Mitsyanko 255d7dfca08SIgor Mitsyanko sdhci_update_irq(s); 256d7dfca08SIgor Mitsyanko 257d7dfca08SIgor Mitsyanko if (s->blksize && (s->cmdreg & SDHC_CMD_DATA_PRESENT)) { 258656f416cSPeter Crosthwaite s->data_count = 0; 259d368ba43SKevin O'Connor sdhci_data_transfer(s); 260d7dfca08SIgor Mitsyanko } 261d7dfca08SIgor Mitsyanko } 262d7dfca08SIgor Mitsyanko 263d7dfca08SIgor Mitsyanko static void sdhci_end_transfer(SDHCIState *s) 264d7dfca08SIgor Mitsyanko { 265d7dfca08SIgor Mitsyanko /* Automatically send CMD12 to stop transfer if AutoCMD12 enabled */ 266d7dfca08SIgor Mitsyanko if ((s->trnmod & SDHC_TRNS_ACMD12) != 0) { 267d7dfca08SIgor Mitsyanko SDRequest request; 268d7dfca08SIgor Mitsyanko uint8_t response[16]; 269d7dfca08SIgor Mitsyanko 270d7dfca08SIgor Mitsyanko request.cmd = 0x0C; 271d7dfca08SIgor Mitsyanko request.arg = 0; 272d7dfca08SIgor Mitsyanko DPRINT_L1("Automatically issue CMD%d %08x\n", request.cmd, request.arg); 273d7dfca08SIgor Mitsyanko sd_do_command(s->card, &request, response); 274d7dfca08SIgor Mitsyanko /* Auto CMD12 response goes to the upper Response register */ 275d7dfca08SIgor Mitsyanko s->rspreg[3] = (response[0] << 24) | (response[1] << 16) | 276d7dfca08SIgor Mitsyanko (response[2] << 8) | response[3]; 277d7dfca08SIgor Mitsyanko } 278d7dfca08SIgor Mitsyanko 279d7dfca08SIgor Mitsyanko s->prnsts &= ~(SDHC_DOING_READ | SDHC_DOING_WRITE | 280d7dfca08SIgor Mitsyanko SDHC_DAT_LINE_ACTIVE | SDHC_DATA_INHIBIT | 281d7dfca08SIgor Mitsyanko SDHC_SPACE_AVAILABLE | SDHC_DATA_AVAILABLE); 282d7dfca08SIgor Mitsyanko 283d7dfca08SIgor Mitsyanko if (s->norintstsen & SDHC_NISEN_TRSCMP) { 284d7dfca08SIgor Mitsyanko s->norintsts |= SDHC_NIS_TRSCMP; 285d7dfca08SIgor Mitsyanko } 286d7dfca08SIgor Mitsyanko 287d7dfca08SIgor Mitsyanko sdhci_update_irq(s); 288d7dfca08SIgor Mitsyanko } 289d7dfca08SIgor Mitsyanko 290d7dfca08SIgor Mitsyanko /* 291d7dfca08SIgor Mitsyanko * Programmed i/o data transfer 292d7dfca08SIgor Mitsyanko */ 293d7dfca08SIgor Mitsyanko 294d7dfca08SIgor Mitsyanko /* Fill host controller's read buffer with BLKSIZE bytes of data from card */ 295d7dfca08SIgor Mitsyanko static void sdhci_read_block_from_card(SDHCIState *s) 296d7dfca08SIgor Mitsyanko { 297d7dfca08SIgor Mitsyanko int index = 0; 298d7dfca08SIgor Mitsyanko 299d7dfca08SIgor Mitsyanko if ((s->trnmod & SDHC_TRNS_MULTI) && 300d7dfca08SIgor Mitsyanko (s->trnmod & SDHC_TRNS_BLK_CNT_EN) && (s->blkcnt == 0)) { 301d7dfca08SIgor Mitsyanko return; 302d7dfca08SIgor Mitsyanko } 303d7dfca08SIgor Mitsyanko 304d7dfca08SIgor Mitsyanko for (index = 0; index < (s->blksize & 0x0fff); index++) { 305d7dfca08SIgor Mitsyanko s->fifo_buffer[index] = sd_read_data(s->card); 306d7dfca08SIgor Mitsyanko } 307d7dfca08SIgor Mitsyanko 308d7dfca08SIgor Mitsyanko /* New data now available for READ through Buffer Port Register */ 309d7dfca08SIgor Mitsyanko s->prnsts |= SDHC_DATA_AVAILABLE; 310d7dfca08SIgor Mitsyanko if (s->norintstsen & SDHC_NISEN_RBUFRDY) { 311d7dfca08SIgor Mitsyanko s->norintsts |= SDHC_NIS_RBUFRDY; 312d7dfca08SIgor Mitsyanko } 313d7dfca08SIgor Mitsyanko 314d7dfca08SIgor Mitsyanko /* Clear DAT line active status if that was the last block */ 315d7dfca08SIgor Mitsyanko if ((s->trnmod & SDHC_TRNS_MULTI) == 0 || 316d7dfca08SIgor Mitsyanko ((s->trnmod & SDHC_TRNS_MULTI) && s->blkcnt == 1)) { 317d7dfca08SIgor Mitsyanko s->prnsts &= ~SDHC_DAT_LINE_ACTIVE; 318d7dfca08SIgor Mitsyanko } 319d7dfca08SIgor Mitsyanko 320d7dfca08SIgor Mitsyanko /* If stop at block gap request was set and it's not the last block of 321d7dfca08SIgor Mitsyanko * data - generate Block Event interrupt */ 322d7dfca08SIgor Mitsyanko if (s->stopped_state == sdhc_gap_read && (s->trnmod & SDHC_TRNS_MULTI) && 323d7dfca08SIgor Mitsyanko s->blkcnt != 1) { 324d7dfca08SIgor Mitsyanko s->prnsts &= ~SDHC_DAT_LINE_ACTIVE; 325d7dfca08SIgor Mitsyanko if (s->norintstsen & SDHC_EISEN_BLKGAP) { 326d7dfca08SIgor Mitsyanko s->norintsts |= SDHC_EIS_BLKGAP; 327d7dfca08SIgor Mitsyanko } 328d7dfca08SIgor Mitsyanko } 329d7dfca08SIgor Mitsyanko 330d7dfca08SIgor Mitsyanko sdhci_update_irq(s); 331d7dfca08SIgor Mitsyanko } 332d7dfca08SIgor Mitsyanko 333d7dfca08SIgor Mitsyanko /* Read @size byte of data from host controller @s BUFFER DATA PORT register */ 334d7dfca08SIgor Mitsyanko static uint32_t sdhci_read_dataport(SDHCIState *s, unsigned size) 335d7dfca08SIgor Mitsyanko { 336d7dfca08SIgor Mitsyanko uint32_t value = 0; 337d7dfca08SIgor Mitsyanko int i; 338d7dfca08SIgor Mitsyanko 339d7dfca08SIgor Mitsyanko /* first check that a valid data exists in host controller input buffer */ 340d7dfca08SIgor Mitsyanko if ((s->prnsts & SDHC_DATA_AVAILABLE) == 0) { 341d7dfca08SIgor Mitsyanko ERRPRINT("Trying to read from empty buffer\n"); 342d7dfca08SIgor Mitsyanko return 0; 343d7dfca08SIgor Mitsyanko } 344d7dfca08SIgor Mitsyanko 345d7dfca08SIgor Mitsyanko for (i = 0; i < size; i++) { 346d7dfca08SIgor Mitsyanko value |= s->fifo_buffer[s->data_count] << i * 8; 347d7dfca08SIgor Mitsyanko s->data_count++; 348d7dfca08SIgor Mitsyanko /* check if we've read all valid data (blksize bytes) from buffer */ 349d7dfca08SIgor Mitsyanko if ((s->data_count) >= (s->blksize & 0x0fff)) { 350d7dfca08SIgor Mitsyanko DPRINT_L2("All %u bytes of data have been read from input buffer\n", 351d7dfca08SIgor Mitsyanko s->data_count); 352d7dfca08SIgor Mitsyanko s->prnsts &= ~SDHC_DATA_AVAILABLE; /* no more data in a buffer */ 353d7dfca08SIgor Mitsyanko s->data_count = 0; /* next buff read must start at position [0] */ 354d7dfca08SIgor Mitsyanko 355d7dfca08SIgor Mitsyanko if (s->trnmod & SDHC_TRNS_BLK_CNT_EN) { 356d7dfca08SIgor Mitsyanko s->blkcnt--; 357d7dfca08SIgor Mitsyanko } 358d7dfca08SIgor Mitsyanko 359d7dfca08SIgor Mitsyanko /* if that was the last block of data */ 360d7dfca08SIgor Mitsyanko if ((s->trnmod & SDHC_TRNS_MULTI) == 0 || 361d7dfca08SIgor Mitsyanko ((s->trnmod & SDHC_TRNS_BLK_CNT_EN) && (s->blkcnt == 0)) || 362d7dfca08SIgor Mitsyanko /* stop at gap request */ 363d7dfca08SIgor Mitsyanko (s->stopped_state == sdhc_gap_read && 364d7dfca08SIgor Mitsyanko !(s->prnsts & SDHC_DAT_LINE_ACTIVE))) { 365d368ba43SKevin O'Connor sdhci_end_transfer(s); 366d7dfca08SIgor Mitsyanko } else { /* if there are more data, read next block from card */ 367d368ba43SKevin O'Connor sdhci_read_block_from_card(s); 368d7dfca08SIgor Mitsyanko } 369d7dfca08SIgor Mitsyanko break; 370d7dfca08SIgor Mitsyanko } 371d7dfca08SIgor Mitsyanko } 372d7dfca08SIgor Mitsyanko 373d7dfca08SIgor Mitsyanko return value; 374d7dfca08SIgor Mitsyanko } 375d7dfca08SIgor Mitsyanko 376d7dfca08SIgor Mitsyanko /* Write data from host controller FIFO to card */ 377d7dfca08SIgor Mitsyanko static void sdhci_write_block_to_card(SDHCIState *s) 378d7dfca08SIgor Mitsyanko { 379d7dfca08SIgor Mitsyanko int index = 0; 380d7dfca08SIgor Mitsyanko 381d7dfca08SIgor Mitsyanko if (s->prnsts & SDHC_SPACE_AVAILABLE) { 382d7dfca08SIgor Mitsyanko if (s->norintstsen & SDHC_NISEN_WBUFRDY) { 383d7dfca08SIgor Mitsyanko s->norintsts |= SDHC_NIS_WBUFRDY; 384d7dfca08SIgor Mitsyanko } 385d7dfca08SIgor Mitsyanko sdhci_update_irq(s); 386d7dfca08SIgor Mitsyanko return; 387d7dfca08SIgor Mitsyanko } 388d7dfca08SIgor Mitsyanko 389d7dfca08SIgor Mitsyanko if (s->trnmod & SDHC_TRNS_BLK_CNT_EN) { 390d7dfca08SIgor Mitsyanko if (s->blkcnt == 0) { 391d7dfca08SIgor Mitsyanko return; 392d7dfca08SIgor Mitsyanko } else { 393d7dfca08SIgor Mitsyanko s->blkcnt--; 394d7dfca08SIgor Mitsyanko } 395d7dfca08SIgor Mitsyanko } 396d7dfca08SIgor Mitsyanko 397d7dfca08SIgor Mitsyanko for (index = 0; index < (s->blksize & 0x0fff); index++) { 398d7dfca08SIgor Mitsyanko sd_write_data(s->card, s->fifo_buffer[index]); 399d7dfca08SIgor Mitsyanko } 400d7dfca08SIgor Mitsyanko 401d7dfca08SIgor Mitsyanko /* Next data can be written through BUFFER DATORT register */ 402d7dfca08SIgor Mitsyanko s->prnsts |= SDHC_SPACE_AVAILABLE; 403d7dfca08SIgor Mitsyanko 404d7dfca08SIgor Mitsyanko /* Finish transfer if that was the last block of data */ 405d7dfca08SIgor Mitsyanko if ((s->trnmod & SDHC_TRNS_MULTI) == 0 || 406d7dfca08SIgor Mitsyanko ((s->trnmod & SDHC_TRNS_MULTI) && 407d7dfca08SIgor Mitsyanko (s->trnmod & SDHC_TRNS_BLK_CNT_EN) && (s->blkcnt == 0))) { 408d368ba43SKevin O'Connor sdhci_end_transfer(s); 409dcdb4cd8SPeter Crosthwaite } else if (s->norintstsen & SDHC_NISEN_WBUFRDY) { 410dcdb4cd8SPeter Crosthwaite s->norintsts |= SDHC_NIS_WBUFRDY; 411d7dfca08SIgor Mitsyanko } 412d7dfca08SIgor Mitsyanko 413d7dfca08SIgor Mitsyanko /* Generate Block Gap Event if requested and if not the last block */ 414d7dfca08SIgor Mitsyanko if (s->stopped_state == sdhc_gap_write && (s->trnmod & SDHC_TRNS_MULTI) && 415d7dfca08SIgor Mitsyanko s->blkcnt > 0) { 416d7dfca08SIgor Mitsyanko s->prnsts &= ~SDHC_DOING_WRITE; 417d7dfca08SIgor Mitsyanko if (s->norintstsen & SDHC_EISEN_BLKGAP) { 418d7dfca08SIgor Mitsyanko s->norintsts |= SDHC_EIS_BLKGAP; 419d7dfca08SIgor Mitsyanko } 420d368ba43SKevin O'Connor sdhci_end_transfer(s); 421d7dfca08SIgor Mitsyanko } 422d7dfca08SIgor Mitsyanko 423d7dfca08SIgor Mitsyanko sdhci_update_irq(s); 424d7dfca08SIgor Mitsyanko } 425d7dfca08SIgor Mitsyanko 426d7dfca08SIgor Mitsyanko /* Write @size bytes of @value data to host controller @s Buffer Data Port 427d7dfca08SIgor Mitsyanko * register */ 428d7dfca08SIgor Mitsyanko static void sdhci_write_dataport(SDHCIState *s, uint32_t value, unsigned size) 429d7dfca08SIgor Mitsyanko { 430d7dfca08SIgor Mitsyanko unsigned i; 431d7dfca08SIgor Mitsyanko 432d7dfca08SIgor Mitsyanko /* Check that there is free space left in a buffer */ 433d7dfca08SIgor Mitsyanko if (!(s->prnsts & SDHC_SPACE_AVAILABLE)) { 434d7dfca08SIgor Mitsyanko ERRPRINT("Can't write to data buffer: buffer full\n"); 435d7dfca08SIgor Mitsyanko return; 436d7dfca08SIgor Mitsyanko } 437d7dfca08SIgor Mitsyanko 438d7dfca08SIgor Mitsyanko for (i = 0; i < size; i++) { 439d7dfca08SIgor Mitsyanko s->fifo_buffer[s->data_count] = value & 0xFF; 440d7dfca08SIgor Mitsyanko s->data_count++; 441d7dfca08SIgor Mitsyanko value >>= 8; 442d7dfca08SIgor Mitsyanko if (s->data_count >= (s->blksize & 0x0fff)) { 443d7dfca08SIgor Mitsyanko DPRINT_L2("write buffer filled with %u bytes of data\n", 444d7dfca08SIgor Mitsyanko s->data_count); 445d7dfca08SIgor Mitsyanko s->data_count = 0; 446d7dfca08SIgor Mitsyanko s->prnsts &= ~SDHC_SPACE_AVAILABLE; 447d7dfca08SIgor Mitsyanko if (s->prnsts & SDHC_DOING_WRITE) { 448d368ba43SKevin O'Connor sdhci_write_block_to_card(s); 449d7dfca08SIgor Mitsyanko } 450d7dfca08SIgor Mitsyanko } 451d7dfca08SIgor Mitsyanko } 452d7dfca08SIgor Mitsyanko } 453d7dfca08SIgor Mitsyanko 454d7dfca08SIgor Mitsyanko /* 455d7dfca08SIgor Mitsyanko * Single DMA data transfer 456d7dfca08SIgor Mitsyanko */ 457d7dfca08SIgor Mitsyanko 458d7dfca08SIgor Mitsyanko /* Multi block SDMA transfer */ 459d7dfca08SIgor Mitsyanko static void sdhci_sdma_transfer_multi_blocks(SDHCIState *s) 460d7dfca08SIgor Mitsyanko { 461d7dfca08SIgor Mitsyanko bool page_aligned = false; 462d7dfca08SIgor Mitsyanko unsigned int n, begin; 463d7dfca08SIgor Mitsyanko const uint16_t block_size = s->blksize & 0x0fff; 464d7dfca08SIgor Mitsyanko uint32_t boundary_chk = 1 << (((s->blksize & 0xf000) >> 12) + 12); 465d7dfca08SIgor Mitsyanko uint32_t boundary_count = boundary_chk - (s->sdmasysad % boundary_chk); 466d7dfca08SIgor Mitsyanko 467d7dfca08SIgor Mitsyanko /* XXX: Some sd/mmc drivers (for example, u-boot-slp) do not account for 468d7dfca08SIgor Mitsyanko * possible stop at page boundary if initial address is not page aligned, 469d7dfca08SIgor Mitsyanko * allow them to work properly */ 470d7dfca08SIgor Mitsyanko if ((s->sdmasysad % boundary_chk) == 0) { 471d7dfca08SIgor Mitsyanko page_aligned = true; 472d7dfca08SIgor Mitsyanko } 473d7dfca08SIgor Mitsyanko 474d7dfca08SIgor Mitsyanko if (s->trnmod & SDHC_TRNS_READ) { 475d7dfca08SIgor Mitsyanko s->prnsts |= SDHC_DOING_READ | SDHC_DATA_INHIBIT | 476d7dfca08SIgor Mitsyanko SDHC_DAT_LINE_ACTIVE; 477d7dfca08SIgor Mitsyanko while (s->blkcnt) { 478d7dfca08SIgor Mitsyanko if (s->data_count == 0) { 479d7dfca08SIgor Mitsyanko for (n = 0; n < block_size; n++) { 480d7dfca08SIgor Mitsyanko s->fifo_buffer[n] = sd_read_data(s->card); 481d7dfca08SIgor Mitsyanko } 482d7dfca08SIgor Mitsyanko } 483d7dfca08SIgor Mitsyanko begin = s->data_count; 484d7dfca08SIgor Mitsyanko if (((boundary_count + begin) < block_size) && page_aligned) { 485d7dfca08SIgor Mitsyanko s->data_count = boundary_count + begin; 486d7dfca08SIgor Mitsyanko boundary_count = 0; 487d7dfca08SIgor Mitsyanko } else { 488d7dfca08SIgor Mitsyanko s->data_count = block_size; 489d7dfca08SIgor Mitsyanko boundary_count -= block_size - begin; 490d7dfca08SIgor Mitsyanko if (s->trnmod & SDHC_TRNS_BLK_CNT_EN) { 491d7dfca08SIgor Mitsyanko s->blkcnt--; 492d7dfca08SIgor Mitsyanko } 493d7dfca08SIgor Mitsyanko } 494df32fd1cSPaolo Bonzini dma_memory_write(&address_space_memory, s->sdmasysad, 495d7dfca08SIgor Mitsyanko &s->fifo_buffer[begin], s->data_count - begin); 496d7dfca08SIgor Mitsyanko s->sdmasysad += s->data_count - begin; 497d7dfca08SIgor Mitsyanko if (s->data_count == block_size) { 498d7dfca08SIgor Mitsyanko s->data_count = 0; 499d7dfca08SIgor Mitsyanko } 500d7dfca08SIgor Mitsyanko if (page_aligned && boundary_count == 0) { 501d7dfca08SIgor Mitsyanko break; 502d7dfca08SIgor Mitsyanko } 503d7dfca08SIgor Mitsyanko } 504d7dfca08SIgor Mitsyanko } else { 505d7dfca08SIgor Mitsyanko s->prnsts |= SDHC_DOING_WRITE | SDHC_DATA_INHIBIT | 506d7dfca08SIgor Mitsyanko SDHC_DAT_LINE_ACTIVE; 507d7dfca08SIgor Mitsyanko while (s->blkcnt) { 508d7dfca08SIgor Mitsyanko begin = s->data_count; 509d7dfca08SIgor Mitsyanko if (((boundary_count + begin) < block_size) && page_aligned) { 510d7dfca08SIgor Mitsyanko s->data_count = boundary_count + begin; 511d7dfca08SIgor Mitsyanko boundary_count = 0; 512d7dfca08SIgor Mitsyanko } else { 513d7dfca08SIgor Mitsyanko s->data_count = block_size; 514d7dfca08SIgor Mitsyanko boundary_count -= block_size - begin; 515d7dfca08SIgor Mitsyanko } 516df32fd1cSPaolo Bonzini dma_memory_read(&address_space_memory, s->sdmasysad, 517d7dfca08SIgor Mitsyanko &s->fifo_buffer[begin], s->data_count); 518d7dfca08SIgor Mitsyanko s->sdmasysad += s->data_count - begin; 519d7dfca08SIgor Mitsyanko if (s->data_count == block_size) { 520d7dfca08SIgor Mitsyanko for (n = 0; n < block_size; n++) { 521d7dfca08SIgor Mitsyanko sd_write_data(s->card, s->fifo_buffer[n]); 522d7dfca08SIgor Mitsyanko } 523d7dfca08SIgor Mitsyanko s->data_count = 0; 524d7dfca08SIgor Mitsyanko if (s->trnmod & SDHC_TRNS_BLK_CNT_EN) { 525d7dfca08SIgor Mitsyanko s->blkcnt--; 526d7dfca08SIgor Mitsyanko } 527d7dfca08SIgor Mitsyanko } 528d7dfca08SIgor Mitsyanko if (page_aligned && boundary_count == 0) { 529d7dfca08SIgor Mitsyanko break; 530d7dfca08SIgor Mitsyanko } 531d7dfca08SIgor Mitsyanko } 532d7dfca08SIgor Mitsyanko } 533d7dfca08SIgor Mitsyanko 534d7dfca08SIgor Mitsyanko if (s->blkcnt == 0) { 535d368ba43SKevin O'Connor sdhci_end_transfer(s); 536d7dfca08SIgor Mitsyanko } else { 537d7dfca08SIgor Mitsyanko if (s->norintstsen & SDHC_NISEN_DMA) { 538d7dfca08SIgor Mitsyanko s->norintsts |= SDHC_NIS_DMA; 539d7dfca08SIgor Mitsyanko } 540d7dfca08SIgor Mitsyanko sdhci_update_irq(s); 541d7dfca08SIgor Mitsyanko } 542d7dfca08SIgor Mitsyanko } 543d7dfca08SIgor Mitsyanko 544d7dfca08SIgor Mitsyanko /* single block SDMA transfer */ 545d7dfca08SIgor Mitsyanko 546d7dfca08SIgor Mitsyanko static void sdhci_sdma_transfer_single_block(SDHCIState *s) 547d7dfca08SIgor Mitsyanko { 548d7dfca08SIgor Mitsyanko int n; 549d7dfca08SIgor Mitsyanko uint32_t datacnt = s->blksize & 0x0fff; 550d7dfca08SIgor Mitsyanko 551d7dfca08SIgor Mitsyanko if (s->trnmod & SDHC_TRNS_READ) { 552d7dfca08SIgor Mitsyanko for (n = 0; n < datacnt; n++) { 553d7dfca08SIgor Mitsyanko s->fifo_buffer[n] = sd_read_data(s->card); 554d7dfca08SIgor Mitsyanko } 555df32fd1cSPaolo Bonzini dma_memory_write(&address_space_memory, s->sdmasysad, s->fifo_buffer, 556d7dfca08SIgor Mitsyanko datacnt); 557d7dfca08SIgor Mitsyanko } else { 558df32fd1cSPaolo Bonzini dma_memory_read(&address_space_memory, s->sdmasysad, s->fifo_buffer, 559d7dfca08SIgor Mitsyanko datacnt); 560d7dfca08SIgor Mitsyanko for (n = 0; n < datacnt; n++) { 561d7dfca08SIgor Mitsyanko sd_write_data(s->card, s->fifo_buffer[n]); 562d7dfca08SIgor Mitsyanko } 563d7dfca08SIgor Mitsyanko } 564d7dfca08SIgor Mitsyanko 565d7dfca08SIgor Mitsyanko if (s->trnmod & SDHC_TRNS_BLK_CNT_EN) { 566d7dfca08SIgor Mitsyanko s->blkcnt--; 567d7dfca08SIgor Mitsyanko } 568d7dfca08SIgor Mitsyanko 569d368ba43SKevin O'Connor sdhci_end_transfer(s); 570d7dfca08SIgor Mitsyanko } 571d7dfca08SIgor Mitsyanko 572d7dfca08SIgor Mitsyanko typedef struct ADMADescr { 573d7dfca08SIgor Mitsyanko hwaddr addr; 574d7dfca08SIgor Mitsyanko uint16_t length; 575d7dfca08SIgor Mitsyanko uint8_t attr; 576d7dfca08SIgor Mitsyanko uint8_t incr; 577d7dfca08SIgor Mitsyanko } ADMADescr; 578d7dfca08SIgor Mitsyanko 579d7dfca08SIgor Mitsyanko static void get_adma_description(SDHCIState *s, ADMADescr *dscr) 580d7dfca08SIgor Mitsyanko { 581d7dfca08SIgor Mitsyanko uint32_t adma1 = 0; 582d7dfca08SIgor Mitsyanko uint64_t adma2 = 0; 583d7dfca08SIgor Mitsyanko hwaddr entry_addr = (hwaddr)s->admasysaddr; 584d7dfca08SIgor Mitsyanko switch (SDHC_DMA_TYPE(s->hostctl)) { 585d7dfca08SIgor Mitsyanko case SDHC_CTRL_ADMA2_32: 586df32fd1cSPaolo Bonzini dma_memory_read(&address_space_memory, entry_addr, (uint8_t *)&adma2, 587d7dfca08SIgor Mitsyanko sizeof(adma2)); 588d7dfca08SIgor Mitsyanko adma2 = le64_to_cpu(adma2); 589d7dfca08SIgor Mitsyanko /* The spec does not specify endianness of descriptor table. 590d7dfca08SIgor Mitsyanko * We currently assume that it is LE. 591d7dfca08SIgor Mitsyanko */ 592d7dfca08SIgor Mitsyanko dscr->addr = (hwaddr)extract64(adma2, 32, 32) & ~0x3ull; 593d7dfca08SIgor Mitsyanko dscr->length = (uint16_t)extract64(adma2, 16, 16); 594d7dfca08SIgor Mitsyanko dscr->attr = (uint8_t)extract64(adma2, 0, 7); 595d7dfca08SIgor Mitsyanko dscr->incr = 8; 596d7dfca08SIgor Mitsyanko break; 597d7dfca08SIgor Mitsyanko case SDHC_CTRL_ADMA1_32: 598df32fd1cSPaolo Bonzini dma_memory_read(&address_space_memory, entry_addr, (uint8_t *)&adma1, 599d7dfca08SIgor Mitsyanko sizeof(adma1)); 600d7dfca08SIgor Mitsyanko adma1 = le32_to_cpu(adma1); 601d7dfca08SIgor Mitsyanko dscr->addr = (hwaddr)(adma1 & 0xFFFFF000); 602d7dfca08SIgor Mitsyanko dscr->attr = (uint8_t)extract32(adma1, 0, 7); 603d7dfca08SIgor Mitsyanko dscr->incr = 4; 604d7dfca08SIgor Mitsyanko if ((dscr->attr & SDHC_ADMA_ATTR_ACT_MASK) == SDHC_ADMA_ATTR_SET_LEN) { 605d7dfca08SIgor Mitsyanko dscr->length = (uint16_t)extract32(adma1, 12, 16); 606d7dfca08SIgor Mitsyanko } else { 607d7dfca08SIgor Mitsyanko dscr->length = 4096; 608d7dfca08SIgor Mitsyanko } 609d7dfca08SIgor Mitsyanko break; 610d7dfca08SIgor Mitsyanko case SDHC_CTRL_ADMA2_64: 611df32fd1cSPaolo Bonzini dma_memory_read(&address_space_memory, entry_addr, 612d7dfca08SIgor Mitsyanko (uint8_t *)(&dscr->attr), 1); 613df32fd1cSPaolo Bonzini dma_memory_read(&address_space_memory, entry_addr + 2, 614d7dfca08SIgor Mitsyanko (uint8_t *)(&dscr->length), 2); 615d7dfca08SIgor Mitsyanko dscr->length = le16_to_cpu(dscr->length); 616df32fd1cSPaolo Bonzini dma_memory_read(&address_space_memory, entry_addr + 4, 617d7dfca08SIgor Mitsyanko (uint8_t *)(&dscr->addr), 8); 618d7dfca08SIgor Mitsyanko dscr->attr = le64_to_cpu(dscr->attr); 619d7dfca08SIgor Mitsyanko dscr->attr &= 0xfffffff8; 620d7dfca08SIgor Mitsyanko dscr->incr = 12; 621d7dfca08SIgor Mitsyanko break; 622d7dfca08SIgor Mitsyanko } 623d7dfca08SIgor Mitsyanko } 624d7dfca08SIgor Mitsyanko 625d7dfca08SIgor Mitsyanko /* Advanced DMA data transfer */ 626d7dfca08SIgor Mitsyanko 627d7dfca08SIgor Mitsyanko static void sdhci_do_adma(SDHCIState *s) 628d7dfca08SIgor Mitsyanko { 629d7dfca08SIgor Mitsyanko unsigned int n, begin, length; 630d7dfca08SIgor Mitsyanko const uint16_t block_size = s->blksize & 0x0fff; 631d7dfca08SIgor Mitsyanko ADMADescr dscr; 632d7dfca08SIgor Mitsyanko int i; 633d7dfca08SIgor Mitsyanko 634d7dfca08SIgor Mitsyanko for (i = 0; i < SDHC_ADMA_DESCS_PER_DELAY; ++i) { 635d7dfca08SIgor Mitsyanko s->admaerr &= ~SDHC_ADMAERR_LENGTH_MISMATCH; 636d7dfca08SIgor Mitsyanko 637d7dfca08SIgor Mitsyanko get_adma_description(s, &dscr); 638d7dfca08SIgor Mitsyanko DPRINT_L2("ADMA loop: addr=" TARGET_FMT_plx ", len=%d, attr=%x\n", 639d7dfca08SIgor Mitsyanko dscr.addr, dscr.length, dscr.attr); 640d7dfca08SIgor Mitsyanko 641d7dfca08SIgor Mitsyanko if ((dscr.attr & SDHC_ADMA_ATTR_VALID) == 0) { 642d7dfca08SIgor Mitsyanko /* Indicate that error occurred in ST_FDS state */ 643d7dfca08SIgor Mitsyanko s->admaerr &= ~SDHC_ADMAERR_STATE_MASK; 644d7dfca08SIgor Mitsyanko s->admaerr |= SDHC_ADMAERR_STATE_ST_FDS; 645d7dfca08SIgor Mitsyanko 646d7dfca08SIgor Mitsyanko /* Generate ADMA error interrupt */ 647d7dfca08SIgor Mitsyanko if (s->errintstsen & SDHC_EISEN_ADMAERR) { 648d7dfca08SIgor Mitsyanko s->errintsts |= SDHC_EIS_ADMAERR; 649d7dfca08SIgor Mitsyanko s->norintsts |= SDHC_NIS_ERR; 650d7dfca08SIgor Mitsyanko } 651d7dfca08SIgor Mitsyanko 652d7dfca08SIgor Mitsyanko sdhci_update_irq(s); 653d7dfca08SIgor Mitsyanko return; 654d7dfca08SIgor Mitsyanko } 655d7dfca08SIgor Mitsyanko 656d7dfca08SIgor Mitsyanko length = dscr.length ? dscr.length : 65536; 657d7dfca08SIgor Mitsyanko 658d7dfca08SIgor Mitsyanko switch (dscr.attr & SDHC_ADMA_ATTR_ACT_MASK) { 659d7dfca08SIgor Mitsyanko case SDHC_ADMA_ATTR_ACT_TRAN: /* data transfer */ 660d7dfca08SIgor Mitsyanko 661d7dfca08SIgor Mitsyanko if (s->trnmod & SDHC_TRNS_READ) { 662d7dfca08SIgor Mitsyanko while (length) { 663d7dfca08SIgor Mitsyanko if (s->data_count == 0) { 664d7dfca08SIgor Mitsyanko for (n = 0; n < block_size; n++) { 665d7dfca08SIgor Mitsyanko s->fifo_buffer[n] = sd_read_data(s->card); 666d7dfca08SIgor Mitsyanko } 667d7dfca08SIgor Mitsyanko } 668d7dfca08SIgor Mitsyanko begin = s->data_count; 669d7dfca08SIgor Mitsyanko if ((length + begin) < block_size) { 670d7dfca08SIgor Mitsyanko s->data_count = length + begin; 671d7dfca08SIgor Mitsyanko length = 0; 672d7dfca08SIgor Mitsyanko } else { 673d7dfca08SIgor Mitsyanko s->data_count = block_size; 674d7dfca08SIgor Mitsyanko length -= block_size - begin; 675d7dfca08SIgor Mitsyanko } 676df32fd1cSPaolo Bonzini dma_memory_write(&address_space_memory, dscr.addr, 677d7dfca08SIgor Mitsyanko &s->fifo_buffer[begin], 678d7dfca08SIgor Mitsyanko s->data_count - begin); 679d7dfca08SIgor Mitsyanko dscr.addr += s->data_count - begin; 680d7dfca08SIgor Mitsyanko if (s->data_count == block_size) { 681d7dfca08SIgor Mitsyanko s->data_count = 0; 682d7dfca08SIgor Mitsyanko if (s->trnmod & SDHC_TRNS_BLK_CNT_EN) { 683d7dfca08SIgor Mitsyanko s->blkcnt--; 684d7dfca08SIgor Mitsyanko if (s->blkcnt == 0) { 685d7dfca08SIgor Mitsyanko break; 686d7dfca08SIgor Mitsyanko } 687d7dfca08SIgor Mitsyanko } 688d7dfca08SIgor Mitsyanko } 689d7dfca08SIgor Mitsyanko } 690d7dfca08SIgor Mitsyanko } else { 691d7dfca08SIgor Mitsyanko while (length) { 692d7dfca08SIgor Mitsyanko begin = s->data_count; 693d7dfca08SIgor Mitsyanko if ((length + begin) < block_size) { 694d7dfca08SIgor Mitsyanko s->data_count = length + begin; 695d7dfca08SIgor Mitsyanko length = 0; 696d7dfca08SIgor Mitsyanko } else { 697d7dfca08SIgor Mitsyanko s->data_count = block_size; 698d7dfca08SIgor Mitsyanko length -= block_size - begin; 699d7dfca08SIgor Mitsyanko } 700df32fd1cSPaolo Bonzini dma_memory_read(&address_space_memory, dscr.addr, 7019db11cefSPeter Crosthwaite &s->fifo_buffer[begin], 7029db11cefSPeter Crosthwaite s->data_count - begin); 703d7dfca08SIgor Mitsyanko dscr.addr += s->data_count - begin; 704d7dfca08SIgor Mitsyanko if (s->data_count == block_size) { 705d7dfca08SIgor Mitsyanko for (n = 0; n < block_size; n++) { 706d7dfca08SIgor Mitsyanko sd_write_data(s->card, s->fifo_buffer[n]); 707d7dfca08SIgor Mitsyanko } 708d7dfca08SIgor Mitsyanko s->data_count = 0; 709d7dfca08SIgor Mitsyanko if (s->trnmod & SDHC_TRNS_BLK_CNT_EN) { 710d7dfca08SIgor Mitsyanko s->blkcnt--; 711d7dfca08SIgor Mitsyanko if (s->blkcnt == 0) { 712d7dfca08SIgor Mitsyanko break; 713d7dfca08SIgor Mitsyanko } 714d7dfca08SIgor Mitsyanko } 715d7dfca08SIgor Mitsyanko } 716d7dfca08SIgor Mitsyanko } 717d7dfca08SIgor Mitsyanko } 718d7dfca08SIgor Mitsyanko s->admasysaddr += dscr.incr; 719d7dfca08SIgor Mitsyanko break; 720d7dfca08SIgor Mitsyanko case SDHC_ADMA_ATTR_ACT_LINK: /* link to next descriptor table */ 721d7dfca08SIgor Mitsyanko s->admasysaddr = dscr.addr; 722d7dfca08SIgor Mitsyanko DPRINT_L1("ADMA link: admasysaddr=0x%lx\n", s->admasysaddr); 723d7dfca08SIgor Mitsyanko break; 724d7dfca08SIgor Mitsyanko default: 725d7dfca08SIgor Mitsyanko s->admasysaddr += dscr.incr; 726d7dfca08SIgor Mitsyanko break; 727d7dfca08SIgor Mitsyanko } 728d7dfca08SIgor Mitsyanko 7291d32c26fSPeter Crosthwaite if (dscr.attr & SDHC_ADMA_ATTR_INT) { 7301d32c26fSPeter Crosthwaite DPRINT_L1("ADMA interrupt: admasysaddr=0x%lx\n", s->admasysaddr); 7311d32c26fSPeter Crosthwaite if (s->norintstsen & SDHC_NISEN_DMA) { 7321d32c26fSPeter Crosthwaite s->norintsts |= SDHC_NIS_DMA; 7331d32c26fSPeter Crosthwaite } 7341d32c26fSPeter Crosthwaite 7351d32c26fSPeter Crosthwaite sdhci_update_irq(s); 7361d32c26fSPeter Crosthwaite } 7371d32c26fSPeter Crosthwaite 738d7dfca08SIgor Mitsyanko /* ADMA transfer terminates if blkcnt == 0 or by END attribute */ 739d7dfca08SIgor Mitsyanko if (((s->trnmod & SDHC_TRNS_BLK_CNT_EN) && 740d7dfca08SIgor Mitsyanko (s->blkcnt == 0)) || (dscr.attr & SDHC_ADMA_ATTR_END)) { 741d7dfca08SIgor Mitsyanko DPRINT_L2("ADMA transfer completed\n"); 742d7dfca08SIgor Mitsyanko if (length || ((dscr.attr & SDHC_ADMA_ATTR_END) && 743d7dfca08SIgor Mitsyanko (s->trnmod & SDHC_TRNS_BLK_CNT_EN) && 744d7dfca08SIgor Mitsyanko s->blkcnt != 0)) { 745d7dfca08SIgor Mitsyanko ERRPRINT("SD/MMC host ADMA length mismatch\n"); 746d7dfca08SIgor Mitsyanko s->admaerr |= SDHC_ADMAERR_LENGTH_MISMATCH | 747d7dfca08SIgor Mitsyanko SDHC_ADMAERR_STATE_ST_TFR; 748d7dfca08SIgor Mitsyanko if (s->errintstsen & SDHC_EISEN_ADMAERR) { 749d7dfca08SIgor Mitsyanko ERRPRINT("Set ADMA error flag\n"); 750d7dfca08SIgor Mitsyanko s->errintsts |= SDHC_EIS_ADMAERR; 751d7dfca08SIgor Mitsyanko s->norintsts |= SDHC_NIS_ERR; 752d7dfca08SIgor Mitsyanko } 753d7dfca08SIgor Mitsyanko 754d7dfca08SIgor Mitsyanko sdhci_update_irq(s); 755d7dfca08SIgor Mitsyanko } 756d368ba43SKevin O'Connor sdhci_end_transfer(s); 757d7dfca08SIgor Mitsyanko return; 758d7dfca08SIgor Mitsyanko } 759d7dfca08SIgor Mitsyanko 760d7dfca08SIgor Mitsyanko } 761d7dfca08SIgor Mitsyanko 762085d8134SPeter Maydell /* we have unfinished business - reschedule to continue ADMA */ 763bc72ad67SAlex Bligh timer_mod(s->transfer_timer, 764bc72ad67SAlex Bligh qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + SDHC_TRANSFER_DELAY); 765d7dfca08SIgor Mitsyanko } 766d7dfca08SIgor Mitsyanko 767d7dfca08SIgor Mitsyanko /* Perform data transfer according to controller configuration */ 768d7dfca08SIgor Mitsyanko 769d368ba43SKevin O'Connor static void sdhci_data_transfer(void *opaque) 770d7dfca08SIgor Mitsyanko { 771d368ba43SKevin O'Connor SDHCIState *s = (SDHCIState *)opaque; 772d7dfca08SIgor Mitsyanko 773d7dfca08SIgor Mitsyanko if (s->trnmod & SDHC_TRNS_DMA) { 774d7dfca08SIgor Mitsyanko switch (SDHC_DMA_TYPE(s->hostctl)) { 775d7dfca08SIgor Mitsyanko case SDHC_CTRL_SDMA: 776d7dfca08SIgor Mitsyanko if ((s->trnmod & SDHC_TRNS_MULTI) && 777d7dfca08SIgor Mitsyanko (!(s->trnmod & SDHC_TRNS_BLK_CNT_EN) || s->blkcnt == 0)) { 778d7dfca08SIgor Mitsyanko break; 779d7dfca08SIgor Mitsyanko } 780d7dfca08SIgor Mitsyanko 781d7dfca08SIgor Mitsyanko if ((s->blkcnt == 1) || !(s->trnmod & SDHC_TRNS_MULTI)) { 782d368ba43SKevin O'Connor sdhci_sdma_transfer_single_block(s); 783d7dfca08SIgor Mitsyanko } else { 784d368ba43SKevin O'Connor sdhci_sdma_transfer_multi_blocks(s); 785d7dfca08SIgor Mitsyanko } 786d7dfca08SIgor Mitsyanko 787d7dfca08SIgor Mitsyanko break; 788d7dfca08SIgor Mitsyanko case SDHC_CTRL_ADMA1_32: 789d7dfca08SIgor Mitsyanko if (!(s->capareg & SDHC_CAN_DO_ADMA1)) { 790d7dfca08SIgor Mitsyanko ERRPRINT("ADMA1 not supported\n"); 791d7dfca08SIgor Mitsyanko break; 792d7dfca08SIgor Mitsyanko } 793d7dfca08SIgor Mitsyanko 794d368ba43SKevin O'Connor sdhci_do_adma(s); 795d7dfca08SIgor Mitsyanko break; 796d7dfca08SIgor Mitsyanko case SDHC_CTRL_ADMA2_32: 797d7dfca08SIgor Mitsyanko if (!(s->capareg & SDHC_CAN_DO_ADMA2)) { 798d7dfca08SIgor Mitsyanko ERRPRINT("ADMA2 not supported\n"); 799d7dfca08SIgor Mitsyanko break; 800d7dfca08SIgor Mitsyanko } 801d7dfca08SIgor Mitsyanko 802d368ba43SKevin O'Connor sdhci_do_adma(s); 803d7dfca08SIgor Mitsyanko break; 804d7dfca08SIgor Mitsyanko case SDHC_CTRL_ADMA2_64: 805d7dfca08SIgor Mitsyanko if (!(s->capareg & SDHC_CAN_DO_ADMA2) || 806d7dfca08SIgor Mitsyanko !(s->capareg & SDHC_64_BIT_BUS_SUPPORT)) { 807d7dfca08SIgor Mitsyanko ERRPRINT("64 bit ADMA not supported\n"); 808d7dfca08SIgor Mitsyanko break; 809d7dfca08SIgor Mitsyanko } 810d7dfca08SIgor Mitsyanko 811d368ba43SKevin O'Connor sdhci_do_adma(s); 812d7dfca08SIgor Mitsyanko break; 813d7dfca08SIgor Mitsyanko default: 814d7dfca08SIgor Mitsyanko ERRPRINT("Unsupported DMA type\n"); 815d7dfca08SIgor Mitsyanko break; 816d7dfca08SIgor Mitsyanko } 817d7dfca08SIgor Mitsyanko } else { 818d7dfca08SIgor Mitsyanko if ((s->trnmod & SDHC_TRNS_READ) && sd_data_ready(s->card)) { 819d7dfca08SIgor Mitsyanko s->prnsts |= SDHC_DOING_READ | SDHC_DATA_INHIBIT | 820d7dfca08SIgor Mitsyanko SDHC_DAT_LINE_ACTIVE; 821d368ba43SKevin O'Connor sdhci_read_block_from_card(s); 822d7dfca08SIgor Mitsyanko } else { 823d7dfca08SIgor Mitsyanko s->prnsts |= SDHC_DOING_WRITE | SDHC_DAT_LINE_ACTIVE | 824d7dfca08SIgor Mitsyanko SDHC_SPACE_AVAILABLE | SDHC_DATA_INHIBIT; 825d368ba43SKevin O'Connor sdhci_write_block_to_card(s); 826d7dfca08SIgor Mitsyanko } 827d7dfca08SIgor Mitsyanko } 828d7dfca08SIgor Mitsyanko } 829d7dfca08SIgor Mitsyanko 830d7dfca08SIgor Mitsyanko static bool sdhci_can_issue_command(SDHCIState *s) 831d7dfca08SIgor Mitsyanko { 832d7dfca08SIgor Mitsyanko if (!SDHC_CLOCK_IS_ON(s->clkcon) || !(s->pwrcon & SDHC_POWER_ON) || 833d7dfca08SIgor Mitsyanko (((s->prnsts & SDHC_DATA_INHIBIT) || s->stopped_state) && 834d7dfca08SIgor Mitsyanko ((s->cmdreg & SDHC_CMD_DATA_PRESENT) || 835d7dfca08SIgor Mitsyanko ((s->cmdreg & SDHC_CMD_RESPONSE) == SDHC_CMD_RSP_WITH_BUSY && 836d7dfca08SIgor Mitsyanko !(SDHC_COMMAND_TYPE(s->cmdreg) == SDHC_CMD_ABORT))))) { 837d7dfca08SIgor Mitsyanko return false; 838d7dfca08SIgor Mitsyanko } 839d7dfca08SIgor Mitsyanko 840d7dfca08SIgor Mitsyanko return true; 841d7dfca08SIgor Mitsyanko } 842d7dfca08SIgor Mitsyanko 843d7dfca08SIgor Mitsyanko /* The Buffer Data Port register must be accessed in sequential and 844d7dfca08SIgor Mitsyanko * continuous manner */ 845d7dfca08SIgor Mitsyanko static inline bool 846d7dfca08SIgor Mitsyanko sdhci_buff_access_is_sequential(SDHCIState *s, unsigned byte_num) 847d7dfca08SIgor Mitsyanko { 848d7dfca08SIgor Mitsyanko if ((s->data_count & 0x3) != byte_num) { 849d7dfca08SIgor Mitsyanko ERRPRINT("Non-sequential access to Buffer Data Port register" 850d7dfca08SIgor Mitsyanko "is prohibited\n"); 851d7dfca08SIgor Mitsyanko return false; 852d7dfca08SIgor Mitsyanko } 853d7dfca08SIgor Mitsyanko return true; 854d7dfca08SIgor Mitsyanko } 855d7dfca08SIgor Mitsyanko 856d368ba43SKevin O'Connor static uint64_t sdhci_read(void *opaque, hwaddr offset, unsigned size) 857d7dfca08SIgor Mitsyanko { 858d368ba43SKevin O'Connor SDHCIState *s = (SDHCIState *)opaque; 859d7dfca08SIgor Mitsyanko uint32_t ret = 0; 860d7dfca08SIgor Mitsyanko 861d7dfca08SIgor Mitsyanko switch (offset & ~0x3) { 862d7dfca08SIgor Mitsyanko case SDHC_SYSAD: 863d7dfca08SIgor Mitsyanko ret = s->sdmasysad; 864d7dfca08SIgor Mitsyanko break; 865d7dfca08SIgor Mitsyanko case SDHC_BLKSIZE: 866d7dfca08SIgor Mitsyanko ret = s->blksize | (s->blkcnt << 16); 867d7dfca08SIgor Mitsyanko break; 868d7dfca08SIgor Mitsyanko case SDHC_ARGUMENT: 869d7dfca08SIgor Mitsyanko ret = s->argument; 870d7dfca08SIgor Mitsyanko break; 871d7dfca08SIgor Mitsyanko case SDHC_TRNMOD: 872d7dfca08SIgor Mitsyanko ret = s->trnmod | (s->cmdreg << 16); 873d7dfca08SIgor Mitsyanko break; 874d7dfca08SIgor Mitsyanko case SDHC_RSPREG0 ... SDHC_RSPREG3: 875d7dfca08SIgor Mitsyanko ret = s->rspreg[((offset & ~0x3) - SDHC_RSPREG0) >> 2]; 876d7dfca08SIgor Mitsyanko break; 877d7dfca08SIgor Mitsyanko case SDHC_BDATA: 878d7dfca08SIgor Mitsyanko if (sdhci_buff_access_is_sequential(s, offset - SDHC_BDATA)) { 879d368ba43SKevin O'Connor ret = sdhci_read_dataport(s, size); 880d368ba43SKevin O'Connor DPRINT_L2("read %ub: addr[0x%04x] -> %u(0x%x)\n", size, (int)offset, 881677ff2aeSPeter Crosthwaite ret, ret); 882d7dfca08SIgor Mitsyanko return ret; 883d7dfca08SIgor Mitsyanko } 884d7dfca08SIgor Mitsyanko break; 885d7dfca08SIgor Mitsyanko case SDHC_PRNSTS: 886d7dfca08SIgor Mitsyanko ret = s->prnsts; 887d7dfca08SIgor Mitsyanko break; 888d7dfca08SIgor Mitsyanko case SDHC_HOSTCTL: 889d7dfca08SIgor Mitsyanko ret = s->hostctl | (s->pwrcon << 8) | (s->blkgap << 16) | 890d7dfca08SIgor Mitsyanko (s->wakcon << 24); 891d7dfca08SIgor Mitsyanko break; 892d7dfca08SIgor Mitsyanko case SDHC_CLKCON: 893d7dfca08SIgor Mitsyanko ret = s->clkcon | (s->timeoutcon << 16); 894d7dfca08SIgor Mitsyanko break; 895d7dfca08SIgor Mitsyanko case SDHC_NORINTSTS: 896d7dfca08SIgor Mitsyanko ret = s->norintsts | (s->errintsts << 16); 897d7dfca08SIgor Mitsyanko break; 898d7dfca08SIgor Mitsyanko case SDHC_NORINTSTSEN: 899d7dfca08SIgor Mitsyanko ret = s->norintstsen | (s->errintstsen << 16); 900d7dfca08SIgor Mitsyanko break; 901d7dfca08SIgor Mitsyanko case SDHC_NORINTSIGEN: 902d7dfca08SIgor Mitsyanko ret = s->norintsigen | (s->errintsigen << 16); 903d7dfca08SIgor Mitsyanko break; 904d7dfca08SIgor Mitsyanko case SDHC_ACMD12ERRSTS: 905d7dfca08SIgor Mitsyanko ret = s->acmd12errsts; 906d7dfca08SIgor Mitsyanko break; 907d7dfca08SIgor Mitsyanko case SDHC_CAPAREG: 908d7dfca08SIgor Mitsyanko ret = s->capareg; 909d7dfca08SIgor Mitsyanko break; 910d7dfca08SIgor Mitsyanko case SDHC_MAXCURR: 911d7dfca08SIgor Mitsyanko ret = s->maxcurr; 912d7dfca08SIgor Mitsyanko break; 913d7dfca08SIgor Mitsyanko case SDHC_ADMAERR: 914d7dfca08SIgor Mitsyanko ret = s->admaerr; 915d7dfca08SIgor Mitsyanko break; 916d7dfca08SIgor Mitsyanko case SDHC_ADMASYSADDR: 917d7dfca08SIgor Mitsyanko ret = (uint32_t)s->admasysaddr; 918d7dfca08SIgor Mitsyanko break; 919d7dfca08SIgor Mitsyanko case SDHC_ADMASYSADDR + 4: 920d7dfca08SIgor Mitsyanko ret = (uint32_t)(s->admasysaddr >> 32); 921d7dfca08SIgor Mitsyanko break; 922d7dfca08SIgor Mitsyanko case SDHC_SLOT_INT_STATUS: 923d7dfca08SIgor Mitsyanko ret = (SD_HOST_SPECv2_VERS << 16) | sdhci_slotint(s); 924d7dfca08SIgor Mitsyanko break; 925d7dfca08SIgor Mitsyanko default: 926d368ba43SKevin O'Connor ERRPRINT("bad %ub read: addr[0x%04x]\n", size, (int)offset); 927d7dfca08SIgor Mitsyanko break; 928d7dfca08SIgor Mitsyanko } 929d7dfca08SIgor Mitsyanko 930d7dfca08SIgor Mitsyanko ret >>= (offset & 0x3) * 8; 931d7dfca08SIgor Mitsyanko ret &= (1ULL << (size * 8)) - 1; 932d368ba43SKevin O'Connor DPRINT_L2("read %ub: addr[0x%04x] -> %u(0x%x)\n", size, (int)offset, ret, ret); 933d7dfca08SIgor Mitsyanko return ret; 934d7dfca08SIgor Mitsyanko } 935d7dfca08SIgor Mitsyanko 936d7dfca08SIgor Mitsyanko static inline void sdhci_blkgap_write(SDHCIState *s, uint8_t value) 937d7dfca08SIgor Mitsyanko { 938d7dfca08SIgor Mitsyanko if ((value & SDHC_STOP_AT_GAP_REQ) && (s->blkgap & SDHC_STOP_AT_GAP_REQ)) { 939d7dfca08SIgor Mitsyanko return; 940d7dfca08SIgor Mitsyanko } 941d7dfca08SIgor Mitsyanko s->blkgap = value & SDHC_STOP_AT_GAP_REQ; 942d7dfca08SIgor Mitsyanko 943d7dfca08SIgor Mitsyanko if ((value & SDHC_CONTINUE_REQ) && s->stopped_state && 944d7dfca08SIgor Mitsyanko (s->blkgap & SDHC_STOP_AT_GAP_REQ) == 0) { 945d7dfca08SIgor Mitsyanko if (s->stopped_state == sdhc_gap_read) { 946d7dfca08SIgor Mitsyanko s->prnsts |= SDHC_DAT_LINE_ACTIVE | SDHC_DOING_READ; 947d368ba43SKevin O'Connor sdhci_read_block_from_card(s); 948d7dfca08SIgor Mitsyanko } else { 949d7dfca08SIgor Mitsyanko s->prnsts |= SDHC_DAT_LINE_ACTIVE | SDHC_DOING_WRITE; 950d368ba43SKevin O'Connor sdhci_write_block_to_card(s); 951d7dfca08SIgor Mitsyanko } 952d7dfca08SIgor Mitsyanko s->stopped_state = sdhc_not_stopped; 953d7dfca08SIgor Mitsyanko } else if (!s->stopped_state && (value & SDHC_STOP_AT_GAP_REQ)) { 954d7dfca08SIgor Mitsyanko if (s->prnsts & SDHC_DOING_READ) { 955d7dfca08SIgor Mitsyanko s->stopped_state = sdhc_gap_read; 956d7dfca08SIgor Mitsyanko } else if (s->prnsts & SDHC_DOING_WRITE) { 957d7dfca08SIgor Mitsyanko s->stopped_state = sdhc_gap_write; 958d7dfca08SIgor Mitsyanko } 959d7dfca08SIgor Mitsyanko } 960d7dfca08SIgor Mitsyanko } 961d7dfca08SIgor Mitsyanko 962d7dfca08SIgor Mitsyanko static inline void sdhci_reset_write(SDHCIState *s, uint8_t value) 963d7dfca08SIgor Mitsyanko { 964d7dfca08SIgor Mitsyanko switch (value) { 965d7dfca08SIgor Mitsyanko case SDHC_RESET_ALL: 966d368ba43SKevin O'Connor sdhci_reset(s); 967d7dfca08SIgor Mitsyanko break; 968d7dfca08SIgor Mitsyanko case SDHC_RESET_CMD: 969d7dfca08SIgor Mitsyanko s->prnsts &= ~SDHC_CMD_INHIBIT; 970d7dfca08SIgor Mitsyanko s->norintsts &= ~SDHC_NIS_CMDCMP; 971d7dfca08SIgor Mitsyanko break; 972d7dfca08SIgor Mitsyanko case SDHC_RESET_DATA: 973d7dfca08SIgor Mitsyanko s->data_count = 0; 974d7dfca08SIgor Mitsyanko s->prnsts &= ~(SDHC_SPACE_AVAILABLE | SDHC_DATA_AVAILABLE | 975d7dfca08SIgor Mitsyanko SDHC_DOING_READ | SDHC_DOING_WRITE | 976d7dfca08SIgor Mitsyanko SDHC_DATA_INHIBIT | SDHC_DAT_LINE_ACTIVE); 977d7dfca08SIgor Mitsyanko s->blkgap &= ~(SDHC_STOP_AT_GAP_REQ | SDHC_CONTINUE_REQ); 978d7dfca08SIgor Mitsyanko s->stopped_state = sdhc_not_stopped; 979d7dfca08SIgor Mitsyanko s->norintsts &= ~(SDHC_NIS_WBUFRDY | SDHC_NIS_RBUFRDY | 980d7dfca08SIgor Mitsyanko SDHC_NIS_DMA | SDHC_NIS_TRSCMP | SDHC_NIS_BLKGAP); 981d7dfca08SIgor Mitsyanko break; 982d7dfca08SIgor Mitsyanko } 983d7dfca08SIgor Mitsyanko } 984d7dfca08SIgor Mitsyanko 985d7dfca08SIgor Mitsyanko static void 986d368ba43SKevin O'Connor sdhci_write(void *opaque, hwaddr offset, uint64_t val, unsigned size) 987d7dfca08SIgor Mitsyanko { 988d368ba43SKevin O'Connor SDHCIState *s = (SDHCIState *)opaque; 989d7dfca08SIgor Mitsyanko unsigned shift = 8 * (offset & 0x3); 990d7dfca08SIgor Mitsyanko uint32_t mask = ~(((1ULL << (size * 8)) - 1) << shift); 991d368ba43SKevin O'Connor uint32_t value = val; 992d7dfca08SIgor Mitsyanko value <<= shift; 993d7dfca08SIgor Mitsyanko 994d7dfca08SIgor Mitsyanko switch (offset & ~0x3) { 995d7dfca08SIgor Mitsyanko case SDHC_SYSAD: 996d7dfca08SIgor Mitsyanko s->sdmasysad = (s->sdmasysad & mask) | value; 997d7dfca08SIgor Mitsyanko MASKED_WRITE(s->sdmasysad, mask, value); 998d7dfca08SIgor Mitsyanko /* Writing to last byte of sdmasysad might trigger transfer */ 999d7dfca08SIgor Mitsyanko if (!(mask & 0xFF000000) && TRANSFERRING_DATA(s->prnsts) && s->blkcnt && 1000d7dfca08SIgor Mitsyanko s->blksize && SDHC_DMA_TYPE(s->hostctl) == SDHC_CTRL_SDMA) { 1001d368ba43SKevin O'Connor sdhci_sdma_transfer_multi_blocks(s); 1002d7dfca08SIgor Mitsyanko } 1003d7dfca08SIgor Mitsyanko break; 1004d7dfca08SIgor Mitsyanko case SDHC_BLKSIZE: 1005d7dfca08SIgor Mitsyanko if (!TRANSFERRING_DATA(s->prnsts)) { 1006d7dfca08SIgor Mitsyanko MASKED_WRITE(s->blksize, mask, value); 1007d7dfca08SIgor Mitsyanko MASKED_WRITE(s->blkcnt, mask >> 16, value >> 16); 1008d7dfca08SIgor Mitsyanko } 1009d7dfca08SIgor Mitsyanko break; 1010d7dfca08SIgor Mitsyanko case SDHC_ARGUMENT: 1011d7dfca08SIgor Mitsyanko MASKED_WRITE(s->argument, mask, value); 1012d7dfca08SIgor Mitsyanko break; 1013d7dfca08SIgor Mitsyanko case SDHC_TRNMOD: 1014d7dfca08SIgor Mitsyanko /* DMA can be enabled only if it is supported as indicated by 1015d7dfca08SIgor Mitsyanko * capabilities register */ 1016d7dfca08SIgor Mitsyanko if (!(s->capareg & SDHC_CAN_DO_DMA)) { 1017d7dfca08SIgor Mitsyanko value &= ~SDHC_TRNS_DMA; 1018d7dfca08SIgor Mitsyanko } 1019d7dfca08SIgor Mitsyanko MASKED_WRITE(s->trnmod, mask, value); 1020d7dfca08SIgor Mitsyanko MASKED_WRITE(s->cmdreg, mask >> 16, value >> 16); 1021d7dfca08SIgor Mitsyanko 1022d7dfca08SIgor Mitsyanko /* Writing to the upper byte of CMDREG triggers SD command generation */ 1023d368ba43SKevin O'Connor if ((mask & 0xFF000000) || !sdhci_can_issue_command(s)) { 1024d7dfca08SIgor Mitsyanko break; 1025d7dfca08SIgor Mitsyanko } 1026d7dfca08SIgor Mitsyanko 1027d368ba43SKevin O'Connor sdhci_send_command(s); 1028d7dfca08SIgor Mitsyanko break; 1029d7dfca08SIgor Mitsyanko case SDHC_BDATA: 1030d7dfca08SIgor Mitsyanko if (sdhci_buff_access_is_sequential(s, offset - SDHC_BDATA)) { 1031d368ba43SKevin O'Connor sdhci_write_dataport(s, value >> shift, size); 1032d7dfca08SIgor Mitsyanko } 1033d7dfca08SIgor Mitsyanko break; 1034d7dfca08SIgor Mitsyanko case SDHC_HOSTCTL: 1035d7dfca08SIgor Mitsyanko if (!(mask & 0xFF0000)) { 1036d7dfca08SIgor Mitsyanko sdhci_blkgap_write(s, value >> 16); 1037d7dfca08SIgor Mitsyanko } 1038d7dfca08SIgor Mitsyanko MASKED_WRITE(s->hostctl, mask, value); 1039d7dfca08SIgor Mitsyanko MASKED_WRITE(s->pwrcon, mask >> 8, value >> 8); 1040d7dfca08SIgor Mitsyanko MASKED_WRITE(s->wakcon, mask >> 24, value >> 24); 1041d7dfca08SIgor Mitsyanko if (!(s->prnsts & SDHC_CARD_PRESENT) || ((s->pwrcon >> 1) & 0x7) < 5 || 1042d7dfca08SIgor Mitsyanko !(s->capareg & (1 << (31 - ((s->pwrcon >> 1) & 0x7))))) { 1043d7dfca08SIgor Mitsyanko s->pwrcon &= ~SDHC_POWER_ON; 1044d7dfca08SIgor Mitsyanko } 1045d7dfca08SIgor Mitsyanko break; 1046d7dfca08SIgor Mitsyanko case SDHC_CLKCON: 1047d7dfca08SIgor Mitsyanko if (!(mask & 0xFF000000)) { 1048d7dfca08SIgor Mitsyanko sdhci_reset_write(s, value >> 24); 1049d7dfca08SIgor Mitsyanko } 1050d7dfca08SIgor Mitsyanko MASKED_WRITE(s->clkcon, mask, value); 1051d7dfca08SIgor Mitsyanko MASKED_WRITE(s->timeoutcon, mask >> 16, value >> 16); 1052d7dfca08SIgor Mitsyanko if (s->clkcon & SDHC_CLOCK_INT_EN) { 1053d7dfca08SIgor Mitsyanko s->clkcon |= SDHC_CLOCK_INT_STABLE; 1054d7dfca08SIgor Mitsyanko } else { 1055d7dfca08SIgor Mitsyanko s->clkcon &= ~SDHC_CLOCK_INT_STABLE; 1056d7dfca08SIgor Mitsyanko } 1057d7dfca08SIgor Mitsyanko break; 1058d7dfca08SIgor Mitsyanko case SDHC_NORINTSTS: 1059d7dfca08SIgor Mitsyanko if (s->norintstsen & SDHC_NISEN_CARDINT) { 1060d7dfca08SIgor Mitsyanko value &= ~SDHC_NIS_CARDINT; 1061d7dfca08SIgor Mitsyanko } 1062d7dfca08SIgor Mitsyanko s->norintsts &= mask | ~value; 1063d7dfca08SIgor Mitsyanko s->errintsts &= (mask >> 16) | ~(value >> 16); 1064d7dfca08SIgor Mitsyanko if (s->errintsts) { 1065d7dfca08SIgor Mitsyanko s->norintsts |= SDHC_NIS_ERR; 1066d7dfca08SIgor Mitsyanko } else { 1067d7dfca08SIgor Mitsyanko s->norintsts &= ~SDHC_NIS_ERR; 1068d7dfca08SIgor Mitsyanko } 1069d7dfca08SIgor Mitsyanko sdhci_update_irq(s); 1070d7dfca08SIgor Mitsyanko break; 1071d7dfca08SIgor Mitsyanko case SDHC_NORINTSTSEN: 1072d7dfca08SIgor Mitsyanko MASKED_WRITE(s->norintstsen, mask, value); 1073d7dfca08SIgor Mitsyanko MASKED_WRITE(s->errintstsen, mask >> 16, value >> 16); 1074d7dfca08SIgor Mitsyanko s->norintsts &= s->norintstsen; 1075d7dfca08SIgor Mitsyanko s->errintsts &= s->errintstsen; 1076d7dfca08SIgor Mitsyanko if (s->errintsts) { 1077d7dfca08SIgor Mitsyanko s->norintsts |= SDHC_NIS_ERR; 1078d7dfca08SIgor Mitsyanko } else { 1079d7dfca08SIgor Mitsyanko s->norintsts &= ~SDHC_NIS_ERR; 1080d7dfca08SIgor Mitsyanko } 1081d7dfca08SIgor Mitsyanko sdhci_update_irq(s); 1082d7dfca08SIgor Mitsyanko break; 1083d7dfca08SIgor Mitsyanko case SDHC_NORINTSIGEN: 1084d7dfca08SIgor Mitsyanko MASKED_WRITE(s->norintsigen, mask, value); 1085d7dfca08SIgor Mitsyanko MASKED_WRITE(s->errintsigen, mask >> 16, value >> 16); 1086d7dfca08SIgor Mitsyanko sdhci_update_irq(s); 1087d7dfca08SIgor Mitsyanko break; 1088d7dfca08SIgor Mitsyanko case SDHC_ADMAERR: 1089d7dfca08SIgor Mitsyanko MASKED_WRITE(s->admaerr, mask, value); 1090d7dfca08SIgor Mitsyanko break; 1091d7dfca08SIgor Mitsyanko case SDHC_ADMASYSADDR: 1092d7dfca08SIgor Mitsyanko s->admasysaddr = (s->admasysaddr & (0xFFFFFFFF00000000ULL | 1093d7dfca08SIgor Mitsyanko (uint64_t)mask)) | (uint64_t)value; 1094d7dfca08SIgor Mitsyanko break; 1095d7dfca08SIgor Mitsyanko case SDHC_ADMASYSADDR + 4: 1096d7dfca08SIgor Mitsyanko s->admasysaddr = (s->admasysaddr & (0x00000000FFFFFFFFULL | 1097d7dfca08SIgor Mitsyanko ((uint64_t)mask << 32))) | ((uint64_t)value << 32); 1098d7dfca08SIgor Mitsyanko break; 1099d7dfca08SIgor Mitsyanko case SDHC_FEAER: 1100d7dfca08SIgor Mitsyanko s->acmd12errsts |= value; 1101d7dfca08SIgor Mitsyanko s->errintsts |= (value >> 16) & s->errintstsen; 1102d7dfca08SIgor Mitsyanko if (s->acmd12errsts) { 1103d7dfca08SIgor Mitsyanko s->errintsts |= SDHC_EIS_CMD12ERR; 1104d7dfca08SIgor Mitsyanko } 1105d7dfca08SIgor Mitsyanko if (s->errintsts) { 1106d7dfca08SIgor Mitsyanko s->norintsts |= SDHC_NIS_ERR; 1107d7dfca08SIgor Mitsyanko } 1108d7dfca08SIgor Mitsyanko sdhci_update_irq(s); 1109d7dfca08SIgor Mitsyanko break; 1110d7dfca08SIgor Mitsyanko default: 1111d7dfca08SIgor Mitsyanko ERRPRINT("bad %ub write offset: addr[0x%04x] <- %u(0x%x)\n", 1112d368ba43SKevin O'Connor size, (int)offset, value >> shift, value >> shift); 1113d7dfca08SIgor Mitsyanko break; 1114d7dfca08SIgor Mitsyanko } 1115d7dfca08SIgor Mitsyanko DPRINT_L2("write %ub: addr[0x%04x] <- %u(0x%x)\n", 1116d368ba43SKevin O'Connor size, (int)offset, value >> shift, value >> shift); 1117d7dfca08SIgor Mitsyanko } 1118d7dfca08SIgor Mitsyanko 1119d7dfca08SIgor Mitsyanko static const MemoryRegionOps sdhci_mmio_ops = { 1120d368ba43SKevin O'Connor .read = sdhci_read, 1121d368ba43SKevin O'Connor .write = sdhci_write, 1122d7dfca08SIgor Mitsyanko .valid = { 1123d7dfca08SIgor Mitsyanko .min_access_size = 1, 1124d7dfca08SIgor Mitsyanko .max_access_size = 4, 1125d7dfca08SIgor Mitsyanko .unaligned = false 1126d7dfca08SIgor Mitsyanko }, 1127d7dfca08SIgor Mitsyanko .endianness = DEVICE_LITTLE_ENDIAN, 1128d7dfca08SIgor Mitsyanko }; 1129d7dfca08SIgor Mitsyanko 1130d7dfca08SIgor Mitsyanko static inline unsigned int sdhci_get_fifolen(SDHCIState *s) 1131d7dfca08SIgor Mitsyanko { 1132d7dfca08SIgor Mitsyanko switch (SDHC_CAPAB_BLOCKSIZE(s->capareg)) { 1133d7dfca08SIgor Mitsyanko case 0: 1134d7dfca08SIgor Mitsyanko return 512; 1135d7dfca08SIgor Mitsyanko case 1: 1136d7dfca08SIgor Mitsyanko return 1024; 1137d7dfca08SIgor Mitsyanko case 2: 1138d7dfca08SIgor Mitsyanko return 2048; 1139d7dfca08SIgor Mitsyanko default: 1140d7dfca08SIgor Mitsyanko hw_error("SDHC: unsupported value for maximum block size\n"); 1141d7dfca08SIgor Mitsyanko return 0; 1142d7dfca08SIgor Mitsyanko } 1143d7dfca08SIgor Mitsyanko } 1144d7dfca08SIgor Mitsyanko 1145*7302dcd6SKevin O'Connor static void sdhci_initfn(SDHCIState *s) 1146d7dfca08SIgor Mitsyanko { 1147d7dfca08SIgor Mitsyanko DriveInfo *di; 1148d7dfca08SIgor Mitsyanko 1149d7dfca08SIgor Mitsyanko di = drive_get_next(IF_SD); 11504be74634SMarkus Armbruster s->card = sd_init(di ? blk_by_legacy_dinfo(di) : NULL, false); 11514f8a066bSKevin Wolf if (s->card == NULL) { 11524f8a066bSKevin Wolf exit(1); 11534f8a066bSKevin Wolf } 1154f3c7d038SAndreas Färber s->eject_cb = qemu_allocate_irq(sdhci_insert_eject_cb, s, 0); 1155f3c7d038SAndreas Färber s->ro_cb = qemu_allocate_irq(sdhci_card_readonly_cb, s, 0); 1156d7dfca08SIgor Mitsyanko sd_set_cb(s->card, s->ro_cb, s->eject_cb); 1157d7dfca08SIgor Mitsyanko 1158bc72ad67SAlex Bligh s->insert_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, sdhci_raise_insertion_irq, s); 1159d368ba43SKevin O'Connor s->transfer_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, sdhci_data_transfer, s); 1160d7dfca08SIgor Mitsyanko } 1161d7dfca08SIgor Mitsyanko 1162*7302dcd6SKevin O'Connor static void sdhci_uninitfn(SDHCIState *s) 1163d7dfca08SIgor Mitsyanko { 1164bc72ad67SAlex Bligh timer_del(s->insert_timer); 1165bc72ad67SAlex Bligh timer_free(s->insert_timer); 1166bc72ad67SAlex Bligh timer_del(s->transfer_timer); 1167bc72ad67SAlex Bligh timer_free(s->transfer_timer); 1168127a4e1aSAndreas Färber qemu_free_irq(s->eject_cb); 1169127a4e1aSAndreas Färber qemu_free_irq(s->ro_cb); 1170d7dfca08SIgor Mitsyanko 1171d7dfca08SIgor Mitsyanko if (s->fifo_buffer) { 1172d7dfca08SIgor Mitsyanko g_free(s->fifo_buffer); 1173d7dfca08SIgor Mitsyanko s->fifo_buffer = NULL; 1174d7dfca08SIgor Mitsyanko } 1175d7dfca08SIgor Mitsyanko } 1176d7dfca08SIgor Mitsyanko 1177d7dfca08SIgor Mitsyanko const VMStateDescription sdhci_vmstate = { 1178d7dfca08SIgor Mitsyanko .name = "sdhci", 1179d7dfca08SIgor Mitsyanko .version_id = 1, 1180d7dfca08SIgor Mitsyanko .minimum_version_id = 1, 1181d7dfca08SIgor Mitsyanko .fields = (VMStateField[]) { 1182d7dfca08SIgor Mitsyanko VMSTATE_UINT32(sdmasysad, SDHCIState), 1183d7dfca08SIgor Mitsyanko VMSTATE_UINT16(blksize, SDHCIState), 1184d7dfca08SIgor Mitsyanko VMSTATE_UINT16(blkcnt, SDHCIState), 1185d7dfca08SIgor Mitsyanko VMSTATE_UINT32(argument, SDHCIState), 1186d7dfca08SIgor Mitsyanko VMSTATE_UINT16(trnmod, SDHCIState), 1187d7dfca08SIgor Mitsyanko VMSTATE_UINT16(cmdreg, SDHCIState), 1188d7dfca08SIgor Mitsyanko VMSTATE_UINT32_ARRAY(rspreg, SDHCIState, 4), 1189d7dfca08SIgor Mitsyanko VMSTATE_UINT32(prnsts, SDHCIState), 1190d7dfca08SIgor Mitsyanko VMSTATE_UINT8(hostctl, SDHCIState), 1191d7dfca08SIgor Mitsyanko VMSTATE_UINT8(pwrcon, SDHCIState), 1192d7dfca08SIgor Mitsyanko VMSTATE_UINT8(blkgap, SDHCIState), 1193d7dfca08SIgor Mitsyanko VMSTATE_UINT8(wakcon, SDHCIState), 1194d7dfca08SIgor Mitsyanko VMSTATE_UINT16(clkcon, SDHCIState), 1195d7dfca08SIgor Mitsyanko VMSTATE_UINT8(timeoutcon, SDHCIState), 1196d7dfca08SIgor Mitsyanko VMSTATE_UINT8(admaerr, SDHCIState), 1197d7dfca08SIgor Mitsyanko VMSTATE_UINT16(norintsts, SDHCIState), 1198d7dfca08SIgor Mitsyanko VMSTATE_UINT16(errintsts, SDHCIState), 1199d7dfca08SIgor Mitsyanko VMSTATE_UINT16(norintstsen, SDHCIState), 1200d7dfca08SIgor Mitsyanko VMSTATE_UINT16(errintstsen, SDHCIState), 1201d7dfca08SIgor Mitsyanko VMSTATE_UINT16(norintsigen, SDHCIState), 1202d7dfca08SIgor Mitsyanko VMSTATE_UINT16(errintsigen, SDHCIState), 1203d7dfca08SIgor Mitsyanko VMSTATE_UINT16(acmd12errsts, SDHCIState), 1204d7dfca08SIgor Mitsyanko VMSTATE_UINT16(data_count, SDHCIState), 1205d7dfca08SIgor Mitsyanko VMSTATE_UINT64(admasysaddr, SDHCIState), 1206d7dfca08SIgor Mitsyanko VMSTATE_UINT8(stopped_state, SDHCIState), 1207d7dfca08SIgor Mitsyanko VMSTATE_VBUFFER_UINT32(fifo_buffer, SDHCIState, 1, NULL, 0, buf_maxsz), 1208d7dfca08SIgor Mitsyanko VMSTATE_TIMER(insert_timer, SDHCIState), 1209d7dfca08SIgor Mitsyanko VMSTATE_TIMER(transfer_timer, SDHCIState), 1210d7dfca08SIgor Mitsyanko VMSTATE_END_OF_LIST() 1211d7dfca08SIgor Mitsyanko } 1212d7dfca08SIgor Mitsyanko }; 1213d7dfca08SIgor Mitsyanko 1214d7dfca08SIgor Mitsyanko /* Capabilities registers provide information on supported features of this 1215d7dfca08SIgor Mitsyanko * specific host controller implementation */ 1216d7dfca08SIgor Mitsyanko static Property sdhci_properties[] = { 1217c7bcc85dSPaolo Bonzini DEFINE_PROP_UINT32("capareg", SDHCIState, capareg, 1218d7dfca08SIgor Mitsyanko SDHC_CAPAB_REG_DEFAULT), 1219c7bcc85dSPaolo Bonzini DEFINE_PROP_UINT32("maxcurr", SDHCIState, maxcurr, 0), 1220d7dfca08SIgor Mitsyanko DEFINE_PROP_END_OF_LIST(), 1221d7dfca08SIgor Mitsyanko }; 1222d7dfca08SIgor Mitsyanko 1223*7302dcd6SKevin O'Connor static void sdhci_sysbus_init(Object *obj) 1224d7dfca08SIgor Mitsyanko { 1225*7302dcd6SKevin O'Connor SDHCIState *s = SYSBUS_SDHCI(obj); 1226*7302dcd6SKevin O'Connor sdhci_initfn(s); 1227*7302dcd6SKevin O'Connor } 1228*7302dcd6SKevin O'Connor 1229*7302dcd6SKevin O'Connor static void sdhci_sysbus_finalize(Object *obj) 1230*7302dcd6SKevin O'Connor { 1231*7302dcd6SKevin O'Connor SDHCIState *s = SYSBUS_SDHCI(obj); 1232*7302dcd6SKevin O'Connor sdhci_uninitfn(s); 1233*7302dcd6SKevin O'Connor } 1234*7302dcd6SKevin O'Connor 1235*7302dcd6SKevin O'Connor static void sdhci_sysbus_realize(DeviceState *dev, Error ** errp) 1236*7302dcd6SKevin O'Connor { 1237*7302dcd6SKevin O'Connor SDHCIState *s = SYSBUS_SDHCI(dev); 1238d7dfca08SIgor Mitsyanko SysBusDevice *sbd = SYS_BUS_DEVICE(dev); 1239d7dfca08SIgor Mitsyanko 1240d7dfca08SIgor Mitsyanko s->buf_maxsz = sdhci_get_fifolen(s); 1241d7dfca08SIgor Mitsyanko s->fifo_buffer = g_malloc0(s->buf_maxsz); 1242d7dfca08SIgor Mitsyanko sysbus_init_irq(sbd, &s->irq); 124329776739SPaolo Bonzini memory_region_init_io(&s->iomem, OBJECT(s), &sdhci_mmio_ops, s, "sdhci", 1244d7dfca08SIgor Mitsyanko SDHC_REGISTERS_MAP_SIZE); 1245d7dfca08SIgor Mitsyanko sysbus_init_mmio(sbd, &s->iomem); 1246d7dfca08SIgor Mitsyanko } 1247d7dfca08SIgor Mitsyanko 1248*7302dcd6SKevin O'Connor static void sdhci_sysbus_class_init(ObjectClass *klass, void *data) 1249d7dfca08SIgor Mitsyanko { 1250d7dfca08SIgor Mitsyanko DeviceClass *dc = DEVICE_CLASS(klass); 1251d7dfca08SIgor Mitsyanko 1252d7dfca08SIgor Mitsyanko dc->vmsd = &sdhci_vmstate; 1253d7dfca08SIgor Mitsyanko dc->props = sdhci_properties; 1254*7302dcd6SKevin O'Connor dc->realize = sdhci_sysbus_realize; 1255d7dfca08SIgor Mitsyanko } 1256d7dfca08SIgor Mitsyanko 1257*7302dcd6SKevin O'Connor static const TypeInfo sdhci_sysbus_info = { 1258*7302dcd6SKevin O'Connor .name = TYPE_SYSBUS_SDHCI, 1259d7dfca08SIgor Mitsyanko .parent = TYPE_SYS_BUS_DEVICE, 1260d7dfca08SIgor Mitsyanko .instance_size = sizeof(SDHCIState), 1261*7302dcd6SKevin O'Connor .instance_init = sdhci_sysbus_init, 1262*7302dcd6SKevin O'Connor .instance_finalize = sdhci_sysbus_finalize, 1263*7302dcd6SKevin O'Connor .class_init = sdhci_sysbus_class_init, 1264d7dfca08SIgor Mitsyanko }; 1265d7dfca08SIgor Mitsyanko 1266d7dfca08SIgor Mitsyanko static void sdhci_register_types(void) 1267d7dfca08SIgor Mitsyanko { 1268*7302dcd6SKevin O'Connor type_register_static(&sdhci_sysbus_info); 1269d7dfca08SIgor Mitsyanko } 1270d7dfca08SIgor Mitsyanko 1271d7dfca08SIgor Mitsyanko type_init(sdhci_register_types) 1272