1 /* 2 * OMAP on-chip MMC/SD host emulation. 3 * 4 * Datasheet: TI Multimedia Card (MMC/SD/SDIO) Interface (SPRU765A) 5 * 6 * Copyright (C) 2006-2007 Andrzej Zaborowski <balrog@zabor.org> 7 * 8 * This program is free software; you can redistribute it and/or 9 * modify it under the terms of the GNU General Public License as 10 * published by the Free Software Foundation; either version 2 or 11 * (at your option) version 3 of the License. 12 * 13 * This program is distributed in the hope that it will be useful, 14 * but WITHOUT ANY WARRANTY; without even the implied warranty of 15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16 * GNU General Public License for more details. 17 * 18 * You should have received a copy of the GNU General Public License along 19 * with this program; if not, see <http://www.gnu.org/licenses/>. 20 */ 21 22 #include "qemu/osdep.h" 23 #include "qemu/log.h" 24 #include "qapi/error.h" 25 #include "hw/irq.h" 26 #include "hw/sysbus.h" 27 #include "hw/arm/omap.h" 28 #include "hw/sd/sd.h" 29 30 typedef struct OMAPMMCState { 31 SysBusDevice parent_obj; 32 33 SDBus sdbus; 34 35 qemu_irq irq; 36 qemu_irq dma_tx_gpio; 37 qemu_irq dma_rx_gpio; 38 MemoryRegion iomem; 39 omap_clk clk; 40 uint16_t last_cmd; 41 uint16_t sdio; 42 uint16_t rsp[8]; 43 uint32_t arg; 44 int lines; 45 int dw; 46 int mode; 47 int enable; 48 int be; 49 int rev; 50 uint16_t status; 51 uint16_t mask; 52 uint8_t cto; 53 uint16_t dto; 54 int clkdiv; 55 uint16_t fifo[32]; 56 int fifo_start; 57 int fifo_len; 58 uint16_t blen; 59 uint16_t blen_counter; 60 uint16_t nblk; 61 uint16_t nblk_counter; 62 int tx_dma; 63 int rx_dma; 64 int af_level; 65 int ae_level; 66 67 int ddir; 68 int transfer; 69 70 int cdet_wakeup; 71 int cdet_enable; 72 qemu_irq cdet; 73 } OMAPMMCState; 74 75 static void omap_mmc_interrupts_update(OMAPMMCState *s) 76 { 77 qemu_set_irq(s->irq, !!(s->status & s->mask)); 78 } 79 80 static void omap_mmc_fifolevel_update(OMAPMMCState *host) 81 { 82 if (!host->transfer && !host->fifo_len) { 83 host->status &= 0xf3ff; 84 return; 85 } 86 87 if (host->fifo_len > host->af_level && host->ddir) { 88 if (host->rx_dma) { 89 host->status &= 0xfbff; 90 qemu_irq_raise(host->dma_rx_gpio); 91 } else 92 host->status |= 0x0400; 93 } else { 94 host->status &= 0xfbff; 95 qemu_irq_lower(host->dma_rx_gpio); 96 } 97 98 if (host->fifo_len < host->ae_level && !host->ddir) { 99 if (host->tx_dma) { 100 host->status &= 0xf7ff; 101 qemu_irq_raise(host->dma_tx_gpio); 102 } else 103 host->status |= 0x0800; 104 } else { 105 qemu_irq_lower(host->dma_tx_gpio); 106 host->status &= 0xf7ff; 107 } 108 } 109 110 /* These must match the encoding of the MMC_CMD Response field */ 111 typedef enum { 112 sd_nore = 0, /* no response */ 113 sd_r1, /* normal response command */ 114 sd_r2, /* CID, CSD registers */ 115 sd_r3, /* OCR register */ 116 sd_r6 = 6, /* Published RCA response */ 117 sd_r1b = -1, 118 } sd_rsp_type_t; 119 120 /* These must match the encoding of the MMC_CMD Type field */ 121 typedef enum { 122 SD_TYPE_BC = 0, /* broadcast -- no response */ 123 SD_TYPE_BCR = 1, /* broadcast with response */ 124 SD_TYPE_AC = 2, /* addressed -- no data transfer */ 125 SD_TYPE_ADTC = 3, /* addressed with data transfer */ 126 } MMCCmdType; 127 128 static void omap_mmc_command(OMAPMMCState *host, int cmd, int dir, 129 MMCCmdType type, int busy, 130 sd_rsp_type_t resptype, int init) 131 { 132 uint32_t rspstatus, mask; 133 int rsplen, timeout; 134 SDRequest request; 135 uint8_t response[16]; 136 137 if (init && cmd == 0) { 138 host->status |= 0x0001; 139 return; 140 } 141 142 if (resptype == sd_r1 && busy) 143 resptype = sd_r1b; 144 145 if (type == SD_TYPE_ADTC) { 146 host->fifo_start = 0; 147 host->fifo_len = 0; 148 host->transfer = 1; 149 host->ddir = dir; 150 } else 151 host->transfer = 0; 152 timeout = 0; 153 mask = 0; 154 rspstatus = 0; 155 156 request.cmd = cmd; 157 request.arg = host->arg; 158 request.crc = 0; /* FIXME */ 159 160 rsplen = sdbus_do_command(&host->sdbus, &request, response); 161 162 /* TODO: validate CRCs */ 163 switch (resptype) { 164 case sd_nore: 165 rsplen = 0; 166 break; 167 168 case sd_r1: 169 case sd_r1b: 170 if (rsplen < 4) { 171 timeout = 1; 172 break; 173 } 174 rsplen = 4; 175 176 mask = OUT_OF_RANGE | ADDRESS_ERROR | BLOCK_LEN_ERROR | 177 ERASE_SEQ_ERROR | ERASE_PARAM | WP_VIOLATION | 178 LOCK_UNLOCK_FAILED | COM_CRC_ERROR | ILLEGAL_COMMAND | 179 CARD_ECC_FAILED | CC_ERROR | SD_ERROR | 180 CID_CSD_OVERWRITE; 181 if (host->sdio & (1 << 13)) 182 mask |= AKE_SEQ_ERROR; 183 rspstatus = ldl_be_p(response); 184 break; 185 186 case sd_r2: 187 if (rsplen < 16) { 188 timeout = 1; 189 break; 190 } 191 rsplen = 16; 192 break; 193 194 case sd_r3: 195 if (rsplen < 4) { 196 timeout = 1; 197 break; 198 } 199 rsplen = 4; 200 201 rspstatus = ldl_be_p(response); 202 if (rspstatus & 0x80000000) 203 host->status &= 0xe000; 204 else 205 host->status |= 0x1000; 206 break; 207 208 case sd_r6: 209 if (rsplen < 4) { 210 timeout = 1; 211 break; 212 } 213 rsplen = 4; 214 215 mask = 0xe000 | AKE_SEQ_ERROR; 216 rspstatus = (response[2] << 8) | (response[3] << 0); 217 } 218 219 if (rspstatus & mask) 220 host->status |= 0x4000; 221 else 222 host->status &= 0xb000; 223 224 if (rsplen) 225 for (rsplen = 0; rsplen < 8; rsplen ++) 226 host->rsp[~rsplen & 7] = response[(rsplen << 1) | 1] | 227 (response[(rsplen << 1) | 0] << 8); 228 229 if (timeout) 230 host->status |= 0x0080; 231 else if (cmd == 12) 232 host->status |= 0x0005; /* Makes it more real */ 233 else 234 host->status |= 0x0001; 235 } 236 237 static void omap_mmc_transfer(OMAPMMCState *host) 238 { 239 uint8_t value; 240 241 if (!host->transfer) 242 return; 243 244 while (1) { 245 if (host->ddir) { 246 if (host->fifo_len > host->af_level) 247 break; 248 249 value = sdbus_read_byte(&host->sdbus); 250 host->fifo[(host->fifo_start + host->fifo_len) & 31] = value; 251 if (-- host->blen_counter) { 252 value = sdbus_read_byte(&host->sdbus); 253 host->fifo[(host->fifo_start + host->fifo_len) & 31] |= 254 value << 8; 255 host->blen_counter --; 256 } 257 258 host->fifo_len ++; 259 } else { 260 if (!host->fifo_len) 261 break; 262 263 value = host->fifo[host->fifo_start] & 0xff; 264 sdbus_write_byte(&host->sdbus, value); 265 if (-- host->blen_counter) { 266 value = host->fifo[host->fifo_start] >> 8; 267 sdbus_write_byte(&host->sdbus, value); 268 host->blen_counter --; 269 } 270 271 host->fifo_start ++; 272 host->fifo_len --; 273 host->fifo_start &= 31; 274 } 275 276 if (host->blen_counter == 0) { 277 host->nblk_counter --; 278 host->blen_counter = host->blen; 279 280 if (host->nblk_counter == 0) { 281 host->nblk_counter = host->nblk; 282 host->transfer = 0; 283 host->status |= 0x0008; 284 break; 285 } 286 } 287 } 288 } 289 290 static void omap_mmc_update(void *opaque) 291 { 292 OMAPMMCState *s = opaque; 293 omap_mmc_transfer(s); 294 omap_mmc_fifolevel_update(s); 295 omap_mmc_interrupts_update(s); 296 } 297 298 static void omap_mmc_pseudo_reset(OMAPMMCState *host) 299 { 300 host->status = 0; 301 host->fifo_len = 0; 302 } 303 304 static void omap_mmc_reset(OMAPMMCState *host) 305 { 306 host->last_cmd = 0; 307 memset(host->rsp, 0, sizeof(host->rsp)); 308 host->arg = 0; 309 host->dw = 0; 310 host->mode = 0; 311 host->enable = 0; 312 host->mask = 0; 313 host->cto = 0; 314 host->dto = 0; 315 host->blen = 0; 316 host->blen_counter = 0; 317 host->nblk = 0; 318 host->nblk_counter = 0; 319 host->tx_dma = 0; 320 host->rx_dma = 0; 321 host->ae_level = 0x00; 322 host->af_level = 0x1f; 323 host->transfer = 0; 324 host->cdet_wakeup = 0; 325 host->cdet_enable = 0; 326 host->clkdiv = 0; 327 328 omap_mmc_pseudo_reset(host); 329 } 330 331 static uint64_t omap_mmc_read(void *opaque, hwaddr offset, unsigned size) 332 { 333 uint16_t i; 334 OMAPMMCState *s = opaque; 335 336 if (size != 2) { 337 return omap_badwidth_read16(opaque, offset); 338 } 339 340 switch (offset) { 341 case 0x00: /* MMC_CMD */ 342 return s->last_cmd; 343 344 case 0x04: /* MMC_ARGL */ 345 return s->arg & 0x0000ffff; 346 347 case 0x08: /* MMC_ARGH */ 348 return s->arg >> 16; 349 350 case 0x0c: /* MMC_CON */ 351 return (s->dw << 15) | (s->mode << 12) | (s->enable << 11) | 352 (s->be << 10) | s->clkdiv; 353 354 case 0x10: /* MMC_STAT */ 355 return s->status; 356 357 case 0x14: /* MMC_IE */ 358 return s->mask; 359 360 case 0x18: /* MMC_CTO */ 361 return s->cto; 362 363 case 0x1c: /* MMC_DTO */ 364 return s->dto; 365 366 case 0x20: /* MMC_DATA */ 367 /* TODO: support 8-bit access */ 368 i = s->fifo[s->fifo_start]; 369 if (s->fifo_len == 0) { 370 printf("MMC: FIFO underrun\n"); 371 return i; 372 } 373 s->fifo_start ++; 374 s->fifo_len --; 375 s->fifo_start &= 31; 376 omap_mmc_transfer(s); 377 omap_mmc_fifolevel_update(s); 378 omap_mmc_interrupts_update(s); 379 return i; 380 381 case 0x24: /* MMC_BLEN */ 382 return s->blen_counter; 383 384 case 0x28: /* MMC_NBLK */ 385 return s->nblk_counter; 386 387 case 0x2c: /* MMC_BUF */ 388 return (s->rx_dma << 15) | (s->af_level << 8) | 389 (s->tx_dma << 7) | s->ae_level; 390 391 case 0x30: /* MMC_SPI */ 392 return 0x0000; 393 case 0x34: /* MMC_SDIO */ 394 return (s->cdet_wakeup << 2) | (s->cdet_enable) | s->sdio; 395 case 0x38: /* MMC_SYST */ 396 return 0x0000; 397 398 case 0x3c: /* MMC_REV */ 399 return s->rev; 400 401 case 0x40: /* MMC_RSP0 */ 402 case 0x44: /* MMC_RSP1 */ 403 case 0x48: /* MMC_RSP2 */ 404 case 0x4c: /* MMC_RSP3 */ 405 case 0x50: /* MMC_RSP4 */ 406 case 0x54: /* MMC_RSP5 */ 407 case 0x58: /* MMC_RSP6 */ 408 case 0x5c: /* MMC_RSP7 */ 409 return s->rsp[(offset - 0x40) >> 2]; 410 411 /* OMAP2-specific */ 412 case 0x60: /* MMC_IOSR */ 413 case 0x64: /* MMC_SYSC */ 414 return 0; 415 case 0x68: /* MMC_SYSS */ 416 return 1; /* RSTD */ 417 } 418 419 OMAP_BAD_REG(offset); 420 return 0; 421 } 422 423 static void omap_mmc_write(void *opaque, hwaddr offset, 424 uint64_t value, unsigned size) 425 { 426 int i; 427 OMAPMMCState *s = opaque; 428 429 if (size != 2) { 430 omap_badwidth_write16(opaque, offset, value); 431 return; 432 } 433 434 switch (offset) { 435 case 0x00: /* MMC_CMD */ 436 if (!s->enable) 437 break; 438 439 s->last_cmd = value; 440 for (i = 0; i < 8; i ++) 441 s->rsp[i] = 0x0000; 442 omap_mmc_command(s, value & 63, (value >> 15) & 1, 443 (MMCCmdType)((value >> 12) & 3), 444 (value >> 11) & 1, 445 (sd_rsp_type_t) ((value >> 8) & 7), 446 (value >> 7) & 1); 447 omap_mmc_update(s); 448 break; 449 450 case 0x04: /* MMC_ARGL */ 451 s->arg &= 0xffff0000; 452 s->arg |= 0x0000ffff & value; 453 break; 454 455 case 0x08: /* MMC_ARGH */ 456 s->arg &= 0x0000ffff; 457 s->arg |= value << 16; 458 break; 459 460 case 0x0c: /* MMC_CON */ 461 s->dw = (value >> 15) & 1; 462 s->mode = (value >> 12) & 3; 463 s->enable = (value >> 11) & 1; 464 s->be = (value >> 10) & 1; 465 s->clkdiv = (value >> 0) & (s->rev >= 2 ? 0x3ff : 0xff); 466 if (s->mode != 0) { 467 qemu_log_mask(LOG_UNIMP, 468 "omap_mmc_wr: mode #%i unimplemented\n", s->mode); 469 } 470 if (s->be != 0) { 471 qemu_log_mask(LOG_UNIMP, 472 "omap_mmc_wr: Big Endian not implemented\n"); 473 } 474 if (s->dw != 0 && s->lines < 4) 475 printf("4-bit SD bus enabled\n"); 476 if (!s->enable) 477 omap_mmc_pseudo_reset(s); 478 break; 479 480 case 0x10: /* MMC_STAT */ 481 s->status &= ~value; 482 omap_mmc_interrupts_update(s); 483 break; 484 485 case 0x14: /* MMC_IE */ 486 s->mask = value & 0x7fff; 487 omap_mmc_interrupts_update(s); 488 break; 489 490 case 0x18: /* MMC_CTO */ 491 s->cto = value & 0xff; 492 if (s->cto > 0xfd && s->rev <= 1) 493 printf("MMC: CTO of 0xff and 0xfe cannot be used!\n"); 494 break; 495 496 case 0x1c: /* MMC_DTO */ 497 s->dto = value & 0xffff; 498 break; 499 500 case 0x20: /* MMC_DATA */ 501 /* TODO: support 8-bit access */ 502 if (s->fifo_len == 32) 503 break; 504 s->fifo[(s->fifo_start + s->fifo_len) & 31] = value; 505 s->fifo_len ++; 506 omap_mmc_transfer(s); 507 omap_mmc_fifolevel_update(s); 508 omap_mmc_interrupts_update(s); 509 break; 510 511 case 0x24: /* MMC_BLEN */ 512 s->blen = (value & 0x07ff) + 1; 513 s->blen_counter = s->blen; 514 break; 515 516 case 0x28: /* MMC_NBLK */ 517 s->nblk = (value & 0x07ff) + 1; 518 s->nblk_counter = s->nblk; 519 s->blen_counter = s->blen; 520 break; 521 522 case 0x2c: /* MMC_BUF */ 523 s->rx_dma = (value >> 15) & 1; 524 s->af_level = (value >> 8) & 0x1f; 525 s->tx_dma = (value >> 7) & 1; 526 s->ae_level = value & 0x1f; 527 528 if (s->rx_dma) 529 s->status &= 0xfbff; 530 if (s->tx_dma) 531 s->status &= 0xf7ff; 532 omap_mmc_fifolevel_update(s); 533 omap_mmc_interrupts_update(s); 534 break; 535 536 /* SPI, SDIO and TEST modes unimplemented */ 537 case 0x30: /* MMC_SPI (OMAP1 only) */ 538 break; 539 case 0x34: /* MMC_SDIO */ 540 s->sdio = value & (s->rev >= 2 ? 0xfbf3 : 0x2020); 541 s->cdet_wakeup = (value >> 9) & 1; 542 s->cdet_enable = (value >> 2) & 1; 543 break; 544 case 0x38: /* MMC_SYST */ 545 break; 546 547 case 0x3c: /* MMC_REV */ 548 case 0x40: /* MMC_RSP0 */ 549 case 0x44: /* MMC_RSP1 */ 550 case 0x48: /* MMC_RSP2 */ 551 case 0x4c: /* MMC_RSP3 */ 552 case 0x50: /* MMC_RSP4 */ 553 case 0x54: /* MMC_RSP5 */ 554 case 0x58: /* MMC_RSP6 */ 555 case 0x5c: /* MMC_RSP7 */ 556 OMAP_RO_REG(offset); 557 break; 558 559 /* OMAP2-specific */ 560 case 0x60: /* MMC_IOSR */ 561 if (value & 0xf) 562 printf("MMC: SDIO bits used!\n"); 563 break; 564 case 0x64: /* MMC_SYSC */ 565 if (value & (1 << 2)) /* SRTS */ 566 omap_mmc_reset(s); 567 break; 568 case 0x68: /* MMC_SYSS */ 569 OMAP_RO_REG(offset); 570 break; 571 572 default: 573 OMAP_BAD_REG(offset); 574 } 575 } 576 577 static const MemoryRegionOps omap_mmc_ops = { 578 .read = omap_mmc_read, 579 .write = omap_mmc_write, 580 .endianness = DEVICE_NATIVE_ENDIAN, 581 }; 582 583 void omap_mmc_set_clk(DeviceState *dev, omap_clk clk) 584 { 585 OMAPMMCState *s = OMAP_MMC(dev); 586 587 s->clk = clk; 588 } 589 590 static void omap_mmc_reset_hold(Object *obj, ResetType type) 591 { 592 OMAPMMCState *s = OMAP_MMC(obj); 593 594 omap_mmc_reset(s); 595 } 596 597 static void omap_mmc_initfn(Object *obj) 598 { 599 OMAPMMCState *s = OMAP_MMC(obj); 600 601 /* In theory these could be settable per-board */ 602 s->lines = 1; 603 s->rev = 1; 604 605 memory_region_init_io(&s->iomem, obj, &omap_mmc_ops, s, "omap.mmc", 0x800); 606 sysbus_init_mmio(SYS_BUS_DEVICE(s), &s->iomem); 607 608 sysbus_init_irq(SYS_BUS_DEVICE(obj), &s->irq); 609 qdev_init_gpio_out_named(DEVICE(obj), &s->dma_tx_gpio, "dma-tx", 1); 610 qdev_init_gpio_out_named(DEVICE(obj), &s->dma_rx_gpio, "dma-rx", 1); 611 612 qbus_init(&s->sdbus, sizeof(s->sdbus), TYPE_SD_BUS, DEVICE(obj), "sd-bus"); 613 } 614 615 static void omap_mmc_class_init(ObjectClass *oc, const void *data) 616 { 617 ResettableClass *rc = RESETTABLE_CLASS(oc); 618 619 rc->phases.hold = omap_mmc_reset_hold; 620 } 621 622 static const TypeInfo omap_mmc_info = { 623 .name = TYPE_OMAP_MMC, 624 .parent = TYPE_SYS_BUS_DEVICE, 625 .instance_size = sizeof(OMAPMMCState), 626 .instance_init = omap_mmc_initfn, 627 .class_init = omap_mmc_class_init, 628 }; 629 630 static void omap_mmc_register_types(void) 631 { 632 type_register_static(&omap_mmc_info); 633 } 634 635 type_init(omap_mmc_register_types) 636