1 /* 2 * OMAP on-chip MMC/SD host emulation. 3 * 4 * Datasheet: TI Multimedia Card (MMC/SD/SDIO) Interface (SPRU765A) 5 * 6 * Copyright (C) 2006-2007 Andrzej Zaborowski <balrog@zabor.org> 7 * 8 * This program is free software; you can redistribute it and/or 9 * modify it under the terms of the GNU General Public License as 10 * published by the Free Software Foundation; either version 2 or 11 * (at your option) version 3 of the License. 12 * 13 * This program is distributed in the hope that it will be useful, 14 * but WITHOUT ANY WARRANTY; without even the implied warranty of 15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16 * GNU General Public License for more details. 17 * 18 * You should have received a copy of the GNU General Public License along 19 * with this program; if not, see <http://www.gnu.org/licenses/>. 20 */ 21 22 #include "qemu/osdep.h" 23 #include "qemu/log.h" 24 #include "qapi/error.h" 25 #include "hw/irq.h" 26 #include "hw/sysbus.h" 27 #include "hw/arm/omap.h" 28 #include "hw/sd/sd.h" 29 30 typedef struct OMAPMMCState { 31 SysBusDevice parent_obj; 32 33 SDBus sdbus; 34 35 qemu_irq irq; 36 qemu_irq dma_tx_gpio; 37 qemu_irq dma_rx_gpio; 38 qemu_irq coverswitch; 39 MemoryRegion iomem; 40 omap_clk clk; 41 uint16_t last_cmd; 42 uint16_t sdio; 43 uint16_t rsp[8]; 44 uint32_t arg; 45 int lines; 46 int dw; 47 int mode; 48 int enable; 49 int be; 50 int rev; 51 uint16_t status; 52 uint16_t mask; 53 uint8_t cto; 54 uint16_t dto; 55 int clkdiv; 56 uint16_t fifo[32]; 57 int fifo_start; 58 int fifo_len; 59 uint16_t blen; 60 uint16_t blen_counter; 61 uint16_t nblk; 62 uint16_t nblk_counter; 63 int tx_dma; 64 int rx_dma; 65 int af_level; 66 int ae_level; 67 68 int ddir; 69 int transfer; 70 71 int cdet_wakeup; 72 int cdet_enable; 73 int cdet_state; 74 qemu_irq cdet; 75 } OMAPMMCState; 76 77 static void omap_mmc_interrupts_update(OMAPMMCState *s) 78 { 79 qemu_set_irq(s->irq, !!(s->status & s->mask)); 80 } 81 82 static void omap_mmc_fifolevel_update(OMAPMMCState *host) 83 { 84 if (!host->transfer && !host->fifo_len) { 85 host->status &= 0xf3ff; 86 return; 87 } 88 89 if (host->fifo_len > host->af_level && host->ddir) { 90 if (host->rx_dma) { 91 host->status &= 0xfbff; 92 qemu_irq_raise(host->dma_rx_gpio); 93 } else 94 host->status |= 0x0400; 95 } else { 96 host->status &= 0xfbff; 97 qemu_irq_lower(host->dma_rx_gpio); 98 } 99 100 if (host->fifo_len < host->ae_level && !host->ddir) { 101 if (host->tx_dma) { 102 host->status &= 0xf7ff; 103 qemu_irq_raise(host->dma_tx_gpio); 104 } else 105 host->status |= 0x0800; 106 } else { 107 qemu_irq_lower(host->dma_tx_gpio); 108 host->status &= 0xf7ff; 109 } 110 } 111 112 /* These must match the encoding of the MMC_CMD Response field */ 113 typedef enum { 114 sd_nore = 0, /* no response */ 115 sd_r1, /* normal response command */ 116 sd_r2, /* CID, CSD registers */ 117 sd_r3, /* OCR register */ 118 sd_r6 = 6, /* Published RCA response */ 119 sd_r1b = -1, 120 } sd_rsp_type_t; 121 122 /* These must match the encoding of the MMC_CMD Type field */ 123 typedef enum { 124 SD_TYPE_BC = 0, /* broadcast -- no response */ 125 SD_TYPE_BCR = 1, /* broadcast with response */ 126 SD_TYPE_AC = 2, /* addressed -- no data transfer */ 127 SD_TYPE_ADTC = 3, /* addressed with data transfer */ 128 } MMCCmdType; 129 130 static void omap_mmc_command(OMAPMMCState *host, int cmd, int dir, 131 MMCCmdType type, int busy, 132 sd_rsp_type_t resptype, int init) 133 { 134 uint32_t rspstatus, mask; 135 int rsplen, timeout; 136 SDRequest request; 137 uint8_t response[16]; 138 139 if (init && cmd == 0) { 140 host->status |= 0x0001; 141 return; 142 } 143 144 if (resptype == sd_r1 && busy) 145 resptype = sd_r1b; 146 147 if (type == SD_TYPE_ADTC) { 148 host->fifo_start = 0; 149 host->fifo_len = 0; 150 host->transfer = 1; 151 host->ddir = dir; 152 } else 153 host->transfer = 0; 154 timeout = 0; 155 mask = 0; 156 rspstatus = 0; 157 158 request.cmd = cmd; 159 request.arg = host->arg; 160 request.crc = 0; /* FIXME */ 161 162 rsplen = sdbus_do_command(&host->sdbus, &request, response); 163 164 /* TODO: validate CRCs */ 165 switch (resptype) { 166 case sd_nore: 167 rsplen = 0; 168 break; 169 170 case sd_r1: 171 case sd_r1b: 172 if (rsplen < 4) { 173 timeout = 1; 174 break; 175 } 176 rsplen = 4; 177 178 mask = OUT_OF_RANGE | ADDRESS_ERROR | BLOCK_LEN_ERROR | 179 ERASE_SEQ_ERROR | ERASE_PARAM | WP_VIOLATION | 180 LOCK_UNLOCK_FAILED | COM_CRC_ERROR | ILLEGAL_COMMAND | 181 CARD_ECC_FAILED | CC_ERROR | SD_ERROR | 182 CID_CSD_OVERWRITE; 183 if (host->sdio & (1 << 13)) 184 mask |= AKE_SEQ_ERROR; 185 rspstatus = ldl_be_p(response); 186 break; 187 188 case sd_r2: 189 if (rsplen < 16) { 190 timeout = 1; 191 break; 192 } 193 rsplen = 16; 194 break; 195 196 case sd_r3: 197 if (rsplen < 4) { 198 timeout = 1; 199 break; 200 } 201 rsplen = 4; 202 203 rspstatus = ldl_be_p(response); 204 if (rspstatus & 0x80000000) 205 host->status &= 0xe000; 206 else 207 host->status |= 0x1000; 208 break; 209 210 case sd_r6: 211 if (rsplen < 4) { 212 timeout = 1; 213 break; 214 } 215 rsplen = 4; 216 217 mask = 0xe000 | AKE_SEQ_ERROR; 218 rspstatus = (response[2] << 8) | (response[3] << 0); 219 } 220 221 if (rspstatus & mask) 222 host->status |= 0x4000; 223 else 224 host->status &= 0xb000; 225 226 if (rsplen) 227 for (rsplen = 0; rsplen < 8; rsplen ++) 228 host->rsp[~rsplen & 7] = response[(rsplen << 1) | 1] | 229 (response[(rsplen << 1) | 0] << 8); 230 231 if (timeout) 232 host->status |= 0x0080; 233 else if (cmd == 12) 234 host->status |= 0x0005; /* Makes it more real */ 235 else 236 host->status |= 0x0001; 237 } 238 239 static void omap_mmc_transfer(OMAPMMCState *host) 240 { 241 uint8_t value; 242 243 if (!host->transfer) 244 return; 245 246 while (1) { 247 if (host->ddir) { 248 if (host->fifo_len > host->af_level) 249 break; 250 251 value = sdbus_read_byte(&host->sdbus); 252 host->fifo[(host->fifo_start + host->fifo_len) & 31] = value; 253 if (-- host->blen_counter) { 254 value = sdbus_read_byte(&host->sdbus); 255 host->fifo[(host->fifo_start + host->fifo_len) & 31] |= 256 value << 8; 257 host->blen_counter --; 258 } 259 260 host->fifo_len ++; 261 } else { 262 if (!host->fifo_len) 263 break; 264 265 value = host->fifo[host->fifo_start] & 0xff; 266 sdbus_write_byte(&host->sdbus, value); 267 if (-- host->blen_counter) { 268 value = host->fifo[host->fifo_start] >> 8; 269 sdbus_write_byte(&host->sdbus, value); 270 host->blen_counter --; 271 } 272 273 host->fifo_start ++; 274 host->fifo_len --; 275 host->fifo_start &= 31; 276 } 277 278 if (host->blen_counter == 0) { 279 host->nblk_counter --; 280 host->blen_counter = host->blen; 281 282 if (host->nblk_counter == 0) { 283 host->nblk_counter = host->nblk; 284 host->transfer = 0; 285 host->status |= 0x0008; 286 break; 287 } 288 } 289 } 290 } 291 292 static void omap_mmc_update(void *opaque) 293 { 294 OMAPMMCState *s = opaque; 295 omap_mmc_transfer(s); 296 omap_mmc_fifolevel_update(s); 297 omap_mmc_interrupts_update(s); 298 } 299 300 static void omap_mmc_pseudo_reset(OMAPMMCState *host) 301 { 302 host->status = 0; 303 host->fifo_len = 0; 304 } 305 306 static void omap_mmc_reset(OMAPMMCState *host) 307 { 308 host->last_cmd = 0; 309 memset(host->rsp, 0, sizeof(host->rsp)); 310 host->arg = 0; 311 host->dw = 0; 312 host->mode = 0; 313 host->enable = 0; 314 host->mask = 0; 315 host->cto = 0; 316 host->dto = 0; 317 host->blen = 0; 318 host->blen_counter = 0; 319 host->nblk = 0; 320 host->nblk_counter = 0; 321 host->tx_dma = 0; 322 host->rx_dma = 0; 323 host->ae_level = 0x00; 324 host->af_level = 0x1f; 325 host->transfer = 0; 326 host->cdet_wakeup = 0; 327 host->cdet_enable = 0; 328 qemu_set_irq(host->coverswitch, host->cdet_state); 329 host->clkdiv = 0; 330 331 omap_mmc_pseudo_reset(host); 332 } 333 334 static uint64_t omap_mmc_read(void *opaque, hwaddr offset, unsigned size) 335 { 336 uint16_t i; 337 OMAPMMCState *s = opaque; 338 339 if (size != 2) { 340 return omap_badwidth_read16(opaque, offset); 341 } 342 343 switch (offset) { 344 case 0x00: /* MMC_CMD */ 345 return s->last_cmd; 346 347 case 0x04: /* MMC_ARGL */ 348 return s->arg & 0x0000ffff; 349 350 case 0x08: /* MMC_ARGH */ 351 return s->arg >> 16; 352 353 case 0x0c: /* MMC_CON */ 354 return (s->dw << 15) | (s->mode << 12) | (s->enable << 11) | 355 (s->be << 10) | s->clkdiv; 356 357 case 0x10: /* MMC_STAT */ 358 return s->status; 359 360 case 0x14: /* MMC_IE */ 361 return s->mask; 362 363 case 0x18: /* MMC_CTO */ 364 return s->cto; 365 366 case 0x1c: /* MMC_DTO */ 367 return s->dto; 368 369 case 0x20: /* MMC_DATA */ 370 /* TODO: support 8-bit access */ 371 i = s->fifo[s->fifo_start]; 372 if (s->fifo_len == 0) { 373 printf("MMC: FIFO underrun\n"); 374 return i; 375 } 376 s->fifo_start ++; 377 s->fifo_len --; 378 s->fifo_start &= 31; 379 omap_mmc_transfer(s); 380 omap_mmc_fifolevel_update(s); 381 omap_mmc_interrupts_update(s); 382 return i; 383 384 case 0x24: /* MMC_BLEN */ 385 return s->blen_counter; 386 387 case 0x28: /* MMC_NBLK */ 388 return s->nblk_counter; 389 390 case 0x2c: /* MMC_BUF */ 391 return (s->rx_dma << 15) | (s->af_level << 8) | 392 (s->tx_dma << 7) | s->ae_level; 393 394 case 0x30: /* MMC_SPI */ 395 return 0x0000; 396 case 0x34: /* MMC_SDIO */ 397 return (s->cdet_wakeup << 2) | (s->cdet_enable) | s->sdio; 398 case 0x38: /* MMC_SYST */ 399 return 0x0000; 400 401 case 0x3c: /* MMC_REV */ 402 return s->rev; 403 404 case 0x40: /* MMC_RSP0 */ 405 case 0x44: /* MMC_RSP1 */ 406 case 0x48: /* MMC_RSP2 */ 407 case 0x4c: /* MMC_RSP3 */ 408 case 0x50: /* MMC_RSP4 */ 409 case 0x54: /* MMC_RSP5 */ 410 case 0x58: /* MMC_RSP6 */ 411 case 0x5c: /* MMC_RSP7 */ 412 return s->rsp[(offset - 0x40) >> 2]; 413 414 /* OMAP2-specific */ 415 case 0x60: /* MMC_IOSR */ 416 case 0x64: /* MMC_SYSC */ 417 return 0; 418 case 0x68: /* MMC_SYSS */ 419 return 1; /* RSTD */ 420 } 421 422 OMAP_BAD_REG(offset); 423 return 0; 424 } 425 426 static void omap_mmc_write(void *opaque, hwaddr offset, 427 uint64_t value, unsigned size) 428 { 429 int i; 430 OMAPMMCState *s = opaque; 431 432 if (size != 2) { 433 omap_badwidth_write16(opaque, offset, value); 434 return; 435 } 436 437 switch (offset) { 438 case 0x00: /* MMC_CMD */ 439 if (!s->enable) 440 break; 441 442 s->last_cmd = value; 443 for (i = 0; i < 8; i ++) 444 s->rsp[i] = 0x0000; 445 omap_mmc_command(s, value & 63, (value >> 15) & 1, 446 (MMCCmdType)((value >> 12) & 3), 447 (value >> 11) & 1, 448 (sd_rsp_type_t) ((value >> 8) & 7), 449 (value >> 7) & 1); 450 omap_mmc_update(s); 451 break; 452 453 case 0x04: /* MMC_ARGL */ 454 s->arg &= 0xffff0000; 455 s->arg |= 0x0000ffff & value; 456 break; 457 458 case 0x08: /* MMC_ARGH */ 459 s->arg &= 0x0000ffff; 460 s->arg |= value << 16; 461 break; 462 463 case 0x0c: /* MMC_CON */ 464 s->dw = (value >> 15) & 1; 465 s->mode = (value >> 12) & 3; 466 s->enable = (value >> 11) & 1; 467 s->be = (value >> 10) & 1; 468 s->clkdiv = (value >> 0) & (s->rev >= 2 ? 0x3ff : 0xff); 469 if (s->mode != 0) { 470 qemu_log_mask(LOG_UNIMP, 471 "omap_mmc_wr: mode #%i unimplemented\n", s->mode); 472 } 473 if (s->be != 0) { 474 qemu_log_mask(LOG_UNIMP, 475 "omap_mmc_wr: Big Endian not implemented\n"); 476 } 477 if (s->dw != 0 && s->lines < 4) 478 printf("4-bit SD bus enabled\n"); 479 if (!s->enable) 480 omap_mmc_pseudo_reset(s); 481 break; 482 483 case 0x10: /* MMC_STAT */ 484 s->status &= ~value; 485 omap_mmc_interrupts_update(s); 486 break; 487 488 case 0x14: /* MMC_IE */ 489 s->mask = value & 0x7fff; 490 omap_mmc_interrupts_update(s); 491 break; 492 493 case 0x18: /* MMC_CTO */ 494 s->cto = value & 0xff; 495 if (s->cto > 0xfd && s->rev <= 1) 496 printf("MMC: CTO of 0xff and 0xfe cannot be used!\n"); 497 break; 498 499 case 0x1c: /* MMC_DTO */ 500 s->dto = value & 0xffff; 501 break; 502 503 case 0x20: /* MMC_DATA */ 504 /* TODO: support 8-bit access */ 505 if (s->fifo_len == 32) 506 break; 507 s->fifo[(s->fifo_start + s->fifo_len) & 31] = value; 508 s->fifo_len ++; 509 omap_mmc_transfer(s); 510 omap_mmc_fifolevel_update(s); 511 omap_mmc_interrupts_update(s); 512 break; 513 514 case 0x24: /* MMC_BLEN */ 515 s->blen = (value & 0x07ff) + 1; 516 s->blen_counter = s->blen; 517 break; 518 519 case 0x28: /* MMC_NBLK */ 520 s->nblk = (value & 0x07ff) + 1; 521 s->nblk_counter = s->nblk; 522 s->blen_counter = s->blen; 523 break; 524 525 case 0x2c: /* MMC_BUF */ 526 s->rx_dma = (value >> 15) & 1; 527 s->af_level = (value >> 8) & 0x1f; 528 s->tx_dma = (value >> 7) & 1; 529 s->ae_level = value & 0x1f; 530 531 if (s->rx_dma) 532 s->status &= 0xfbff; 533 if (s->tx_dma) 534 s->status &= 0xf7ff; 535 omap_mmc_fifolevel_update(s); 536 omap_mmc_interrupts_update(s); 537 break; 538 539 /* SPI, SDIO and TEST modes unimplemented */ 540 case 0x30: /* MMC_SPI (OMAP1 only) */ 541 break; 542 case 0x34: /* MMC_SDIO */ 543 s->sdio = value & (s->rev >= 2 ? 0xfbf3 : 0x2020); 544 s->cdet_wakeup = (value >> 9) & 1; 545 s->cdet_enable = (value >> 2) & 1; 546 break; 547 case 0x38: /* MMC_SYST */ 548 break; 549 550 case 0x3c: /* MMC_REV */ 551 case 0x40: /* MMC_RSP0 */ 552 case 0x44: /* MMC_RSP1 */ 553 case 0x48: /* MMC_RSP2 */ 554 case 0x4c: /* MMC_RSP3 */ 555 case 0x50: /* MMC_RSP4 */ 556 case 0x54: /* MMC_RSP5 */ 557 case 0x58: /* MMC_RSP6 */ 558 case 0x5c: /* MMC_RSP7 */ 559 OMAP_RO_REG(offset); 560 break; 561 562 /* OMAP2-specific */ 563 case 0x60: /* MMC_IOSR */ 564 if (value & 0xf) 565 printf("MMC: SDIO bits used!\n"); 566 break; 567 case 0x64: /* MMC_SYSC */ 568 if (value & (1 << 2)) /* SRTS */ 569 omap_mmc_reset(s); 570 break; 571 case 0x68: /* MMC_SYSS */ 572 OMAP_RO_REG(offset); 573 break; 574 575 default: 576 OMAP_BAD_REG(offset); 577 } 578 } 579 580 static const MemoryRegionOps omap_mmc_ops = { 581 .read = omap_mmc_read, 582 .write = omap_mmc_write, 583 .endianness = DEVICE_NATIVE_ENDIAN, 584 }; 585 586 void omap_mmc_set_clk(DeviceState *dev, omap_clk clk) 587 { 588 OMAPMMCState *s = OMAP_MMC(dev); 589 590 s->clk = clk; 591 } 592 593 DeviceState *omap_mmc_init(hwaddr base, 594 MemoryRegion *sysmem, 595 qemu_irq irq, qemu_irq dma[], omap_clk clk) 596 { 597 DeviceState *dev; 598 OMAPMMCState *s; 599 600 dev = qdev_new(TYPE_OMAP_MMC); 601 s = OMAP_MMC(dev); 602 sysbus_realize_and_unref(SYS_BUS_DEVICE(s), &error_fatal); 603 604 omap_mmc_set_clk(dev, clk); 605 606 memory_region_add_subregion(sysmem, base, 607 sysbus_mmio_get_region(SYS_BUS_DEVICE(s), 0)); 608 qdev_connect_gpio_out_named(dev, "dma-tx", 0, dma[0]); 609 qdev_connect_gpio_out_named(dev, "dma-rx", 0, dma[1]); 610 sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, irq); 611 612 return dev; 613 } 614 615 static void omap_mmc_reset_hold(Object *obj, ResetType type) 616 { 617 OMAPMMCState *s = OMAP_MMC(obj); 618 619 omap_mmc_reset(s); 620 } 621 622 static void omap_mmc_initfn(Object *obj) 623 { 624 OMAPMMCState *s = OMAP_MMC(obj); 625 626 /* In theory these could be settable per-board */ 627 s->lines = 1; 628 s->rev = 1; 629 630 memory_region_init_io(&s->iomem, obj, &omap_mmc_ops, s, "omap.mmc", 0x800); 631 sysbus_init_mmio(SYS_BUS_DEVICE(s), &s->iomem); 632 633 sysbus_init_irq(SYS_BUS_DEVICE(obj), &s->irq); 634 qdev_init_gpio_out_named(DEVICE(obj), &s->dma_tx_gpio, "dma-tx", 1); 635 qdev_init_gpio_out_named(DEVICE(obj), &s->dma_rx_gpio, "dma-rx", 1); 636 637 qbus_init(&s->sdbus, sizeof(s->sdbus), TYPE_SD_BUS, DEVICE(obj), "sd-bus"); 638 } 639 640 static void omap_mmc_class_init(ObjectClass *oc, void *data) 641 { 642 ResettableClass *rc = RESETTABLE_CLASS(oc); 643 644 rc->phases.hold = omap_mmc_reset_hold; 645 } 646 647 static const TypeInfo omap_mmc_info = { 648 .name = TYPE_OMAP_MMC, 649 .parent = TYPE_SYS_BUS_DEVICE, 650 .instance_size = sizeof(OMAPMMCState), 651 .instance_init = omap_mmc_initfn, 652 .class_init = omap_mmc_class_init, 653 }; 654 655 static void omap_mmc_register_types(void) 656 { 657 type_register_static(&omap_mmc_info); 658 } 659 660 type_init(omap_mmc_register_types) 661