1 /* 2 * Cadence SDHCI emulation 3 * 4 * Copyright (c) 2020 Wind River Systems, Inc. 5 * 6 * Author: 7 * Bin Meng <bin.meng@windriver.com> 8 * 9 * This program is free software; you can redistribute it and/or 10 * modify it under the terms of the GNU General Public License as 11 * published by the Free Software Foundation; either version 2 or 12 * (at your option) version 3 of the License. 13 * 14 * This program is distributed in the hope that it will be useful, 15 * but WITHOUT ANY WARRANTY; without even the implied warranty of 16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 17 * GNU General Public License for more details. 18 * 19 * You should have received a copy of the GNU General Public License along 20 * with this program; if not, see <http://www.gnu.org/licenses/>. 21 */ 22 23 #include "qemu/osdep.h" 24 #include "qemu/bitops.h" 25 #include "qemu/error-report.h" 26 #include "qemu/log.h" 27 #include "qapi/error.h" 28 #include "migration/vmstate.h" 29 #include "hw/sd/cadence_sdhci.h" 30 #include "sdhci-internal.h" 31 32 /* HRS - Host Register Set (specific to Cadence) */ 33 34 #define CADENCE_SDHCI_HRS00 0x00 /* general information */ 35 #define CADENCE_SDHCI_HRS00_SWR BIT(0) 36 #define CADENCE_SDHCI_HRS00_POR_VAL 0x00010000 37 38 #define CADENCE_SDHCI_HRS04 0x10 /* PHY access port */ 39 #define CADENCE_SDHCI_HRS04_WR BIT(24) 40 #define CADENCE_SDHCI_HRS04_RD BIT(25) 41 #define CADENCE_SDHCI_HRS04_ACK BIT(26) 42 43 #define CADENCE_SDHCI_HRS06 0x18 /* eMMC control */ 44 #define CADENCE_SDHCI_HRS06_TUNE_UP BIT(15) 45 46 /* SRS - Slot Register Set (SDHCI-compatible) */ 47 48 #define CADENCE_SDHCI_SRS_BASE 0x200 49 50 #define TO_REG(addr) ((addr) / sizeof(uint32_t)) 51 52 static void cadence_sdhci_instance_init(Object *obj) 53 { 54 CadenceSDHCIState *s = CADENCE_SDHCI(obj); 55 56 object_initialize_child(OBJECT(s), "generic-sdhci", 57 &s->sdhci, TYPE_SYSBUS_SDHCI); 58 } 59 60 static void cadence_sdhci_reset(DeviceState *dev) 61 { 62 CadenceSDHCIState *s = CADENCE_SDHCI(dev); 63 64 memset(s->regs, 0, CADENCE_SDHCI_REG_SIZE); 65 s->regs[TO_REG(CADENCE_SDHCI_HRS00)] = CADENCE_SDHCI_HRS00_POR_VAL; 66 67 device_cold_reset(DEVICE(&s->sdhci)); 68 } 69 70 static uint64_t cadence_sdhci_read(void *opaque, hwaddr addr, unsigned int size) 71 { 72 CadenceSDHCIState *s = opaque; 73 uint32_t val; 74 75 val = s->regs[TO_REG(addr)]; 76 77 return (uint64_t)val; 78 } 79 80 static void cadence_sdhci_write(void *opaque, hwaddr addr, uint64_t val, 81 unsigned int size) 82 { 83 CadenceSDHCIState *s = opaque; 84 uint32_t val32 = (uint32_t)val; 85 86 switch (addr) { 87 case CADENCE_SDHCI_HRS00: 88 /* 89 * The only writable bit is SWR (software reset) and it automatically 90 * clears to zero, so essentially this register remains unchanged. 91 */ 92 if (val32 & CADENCE_SDHCI_HRS00_SWR) { 93 cadence_sdhci_reset(DEVICE(s)); 94 } 95 96 break; 97 case CADENCE_SDHCI_HRS04: 98 /* 99 * Only emulate the ACK bit behavior when read or write transaction 100 * are requested. 101 */ 102 if (val32 & (CADENCE_SDHCI_HRS04_WR | CADENCE_SDHCI_HRS04_RD)) { 103 val32 |= CADENCE_SDHCI_HRS04_ACK; 104 } else { 105 val32 &= ~CADENCE_SDHCI_HRS04_ACK; 106 } 107 108 s->regs[TO_REG(addr)] = val32; 109 break; 110 case CADENCE_SDHCI_HRS06: 111 if (val32 & CADENCE_SDHCI_HRS06_TUNE_UP) { 112 val32 &= ~CADENCE_SDHCI_HRS06_TUNE_UP; 113 } 114 115 s->regs[TO_REG(addr)] = val32; 116 break; 117 default: 118 s->regs[TO_REG(addr)] = val32; 119 break; 120 } 121 } 122 123 static const MemoryRegionOps cadence_sdhci_ops = { 124 .read = cadence_sdhci_read, 125 .write = cadence_sdhci_write, 126 .endianness = DEVICE_NATIVE_ENDIAN, 127 .impl = { 128 .min_access_size = 4, 129 .max_access_size = 4, 130 }, 131 .valid = { 132 .min_access_size = 4, 133 .max_access_size = 4, 134 } 135 }; 136 137 static void cadence_sdhci_realize(DeviceState *dev, Error **errp) 138 { 139 CadenceSDHCIState *s = CADENCE_SDHCI(dev); 140 SysBusDevice *sbd = SYS_BUS_DEVICE(dev); 141 SysBusDevice *sbd_sdhci = SYS_BUS_DEVICE(&s->sdhci); 142 143 memory_region_init(&s->container, OBJECT(s), 144 "cadence.sdhci-container", 0x1000); 145 sysbus_init_mmio(sbd, &s->container); 146 147 memory_region_init_io(&s->iomem, OBJECT(s), &cadence_sdhci_ops, 148 s, TYPE_CADENCE_SDHCI, CADENCE_SDHCI_REG_SIZE); 149 memory_region_add_subregion(&s->container, 0, &s->iomem); 150 151 sysbus_realize(sbd_sdhci, errp); 152 memory_region_add_subregion(&s->container, CADENCE_SDHCI_SRS_BASE, 153 sysbus_mmio_get_region(sbd_sdhci, 0)); 154 155 /* propagate irq and "sd-bus" from generic-sdhci */ 156 sysbus_pass_irq(sbd, sbd_sdhci); 157 s->bus = qdev_get_child_bus(DEVICE(sbd_sdhci), "sd-bus"); 158 } 159 160 static const VMStateDescription vmstate_cadence_sdhci = { 161 .name = TYPE_CADENCE_SDHCI, 162 .version_id = 1, 163 .fields = (VMStateField[]) { 164 VMSTATE_UINT32_ARRAY(regs, CadenceSDHCIState, CADENCE_SDHCI_NUM_REGS), 165 VMSTATE_END_OF_LIST(), 166 }, 167 }; 168 169 static void cadence_sdhci_class_init(ObjectClass *classp, void *data) 170 { 171 DeviceClass *dc = DEVICE_CLASS(classp); 172 173 dc->desc = "Cadence SD/SDIO/eMMC Host Controller (SD4HC)"; 174 dc->realize = cadence_sdhci_realize; 175 dc->reset = cadence_sdhci_reset; 176 dc->vmsd = &vmstate_cadence_sdhci; 177 } 178 179 static TypeInfo cadence_sdhci_info = { 180 .name = TYPE_CADENCE_SDHCI, 181 .parent = TYPE_SYS_BUS_DEVICE, 182 .instance_size = sizeof(CadenceSDHCIState), 183 .instance_init = cadence_sdhci_instance_init, 184 .class_init = cadence_sdhci_class_init, 185 }; 186 187 static void cadence_sdhci_register_types(void) 188 { 189 type_register_static(&cadence_sdhci_info); 190 } 191 192 type_init(cadence_sdhci_register_types) 193