1 /* 2 * QEMU VMWARE PVSCSI paravirtual SCSI bus 3 * 4 * Copyright (c) 2012 Ravello Systems LTD (http://ravellosystems.com) 5 * 6 * Developed by Daynix Computing LTD (http://www.daynix.com) 7 * 8 * Based on implementation by Paolo Bonzini 9 * http://lists.gnu.org/archive/html/qemu-devel/2011-08/msg00729.html 10 * 11 * Authors: 12 * Paolo Bonzini <pbonzini@redhat.com> 13 * Dmitry Fleytman <dmitry@daynix.com> 14 * Yan Vugenfirer <yan@daynix.com> 15 * 16 * This work is licensed under the terms of the GNU GPL, version 2. 17 * See the COPYING file in the top-level directory. 18 * 19 * NOTE about MSI-X: 20 * MSI-X support has been removed for the moment because it leads Windows OS 21 * to crash on startup. The crash happens because Windows driver requires 22 * MSI-X shared memory to be part of the same BAR used for rings state 23 * registers, etc. This is not supported by QEMU infrastructure so separate 24 * BAR created from MSI-X purposes. Windows driver fails to deal with 2 BARs. 25 * 26 */ 27 28 #include "qemu/osdep.h" 29 #include "qapi/error.h" 30 #include "qemu/main-loop.h" 31 #include "qemu/module.h" 32 #include "hw/scsi/scsi.h" 33 #include "migration/vmstate.h" 34 #include "scsi/constants.h" 35 #include "hw/pci/msi.h" 36 #include "hw/qdev-properties.h" 37 #include "vmw_pvscsi.h" 38 #include "trace.h" 39 #include "qom/object.h" 40 41 42 #define PVSCSI_USE_64BIT (true) 43 #define PVSCSI_PER_VECTOR_MASK (false) 44 45 #define PVSCSI_MAX_DEVS (64) 46 #define PVSCSI_MSIX_NUM_VECTORS (1) 47 48 #define PVSCSI_MAX_SG_ELEM 2048 49 50 #define PVSCSI_MAX_CMD_DATA_WORDS \ 51 (sizeof(PVSCSICmdDescSetupRings)/sizeof(uint32_t)) 52 53 #define RS_GET_FIELD(m, field) \ 54 (ldl_le_pci_dma(&container_of(m, PVSCSIState, rings)->parent_obj, \ 55 (m)->rs_pa + offsetof(struct PVSCSIRingsState, field))) 56 #define RS_SET_FIELD(m, field, val) \ 57 (stl_le_pci_dma(&container_of(m, PVSCSIState, rings)->parent_obj, \ 58 (m)->rs_pa + offsetof(struct PVSCSIRingsState, field), val, \ 59 MEMTXATTRS_UNSPECIFIED)) 60 61 struct PVSCSIClass { 62 PCIDeviceClass parent_class; 63 DeviceRealize parent_dc_realize; 64 }; 65 66 #define TYPE_PVSCSI "pvscsi" 67 OBJECT_DECLARE_TYPE(PVSCSIState, PVSCSIClass, PVSCSI) 68 69 70 /* Compatibility flags for migration */ 71 #define PVSCSI_COMPAT_OLD_PCI_CONFIGURATION_BIT 0 72 #define PVSCSI_COMPAT_OLD_PCI_CONFIGURATION \ 73 (1 << PVSCSI_COMPAT_OLD_PCI_CONFIGURATION_BIT) 74 #define PVSCSI_COMPAT_DISABLE_PCIE_BIT 1 75 #define PVSCSI_COMPAT_DISABLE_PCIE \ 76 (1 << PVSCSI_COMPAT_DISABLE_PCIE_BIT) 77 78 #define PVSCSI_USE_OLD_PCI_CONFIGURATION(s) \ 79 ((s)->compat_flags & PVSCSI_COMPAT_OLD_PCI_CONFIGURATION) 80 #define PVSCSI_MSI_OFFSET(s) \ 81 (PVSCSI_USE_OLD_PCI_CONFIGURATION(s) ? 0x50 : 0x7c) 82 #define PVSCSI_EXP_EP_OFFSET (0x40) 83 84 typedef struct PVSCSIRingInfo { 85 uint64_t rs_pa; 86 uint32_t txr_len_mask; 87 uint32_t rxr_len_mask; 88 uint32_t msg_len_mask; 89 uint64_t req_ring_pages_pa[PVSCSI_SETUP_RINGS_MAX_NUM_PAGES]; 90 uint64_t cmp_ring_pages_pa[PVSCSI_SETUP_RINGS_MAX_NUM_PAGES]; 91 uint64_t msg_ring_pages_pa[PVSCSI_SETUP_MSG_RING_MAX_NUM_PAGES]; 92 uint64_t consumed_ptr; 93 uint64_t filled_cmp_ptr; 94 uint64_t filled_msg_ptr; 95 } PVSCSIRingInfo; 96 97 typedef struct PVSCSISGState { 98 hwaddr elemAddr; 99 hwaddr dataAddr; 100 uint32_t resid; 101 } PVSCSISGState; 102 103 typedef QTAILQ_HEAD(, PVSCSIRequest) PVSCSIRequestList; 104 105 struct PVSCSIState { 106 PCIDevice parent_obj; 107 MemoryRegion io_space; 108 SCSIBus bus; 109 QEMUBH *completion_worker; 110 PVSCSIRequestList pending_queue; 111 PVSCSIRequestList completion_queue; 112 113 uint64_t reg_interrupt_status; /* Interrupt status register value */ 114 uint64_t reg_interrupt_enabled; /* Interrupt mask register value */ 115 uint64_t reg_command_status; /* Command status register value */ 116 117 /* Command data adoption mechanism */ 118 uint64_t curr_cmd; /* Last command arrived */ 119 uint32_t curr_cmd_data_cntr; /* Amount of data for last command */ 120 121 /* Collector for current command data */ 122 uint32_t curr_cmd_data[PVSCSI_MAX_CMD_DATA_WORDS]; 123 124 uint8_t rings_info_valid; /* Whether data rings initialized */ 125 uint8_t msg_ring_info_valid; /* Whether message ring initialized */ 126 uint8_t use_msg; /* Whether to use message ring */ 127 128 uint8_t msi_used; /* For migration compatibility */ 129 PVSCSIRingInfo rings; /* Data transfer rings manager */ 130 uint32_t resetting; /* Reset in progress */ 131 132 uint32_t compat_flags; 133 }; 134 135 typedef struct PVSCSIRequest { 136 SCSIRequest *sreq; 137 PVSCSIState *dev; 138 uint8_t sense_key; 139 uint8_t completed; 140 int lun; 141 QEMUSGList sgl; 142 PVSCSISGState sg; 143 struct PVSCSIRingReqDesc req; 144 struct PVSCSIRingCmpDesc cmp; 145 QTAILQ_ENTRY(PVSCSIRequest) next; 146 } PVSCSIRequest; 147 148 /* Integer binary logarithm */ 149 static int 150 pvscsi_log2(uint32_t input) 151 { 152 int log = 0; 153 assert(input > 0); 154 while (input >> ++log) { 155 } 156 return log; 157 } 158 159 static void 160 pvscsi_ring_init_data(PVSCSIRingInfo *m, PVSCSICmdDescSetupRings *ri) 161 { 162 int i; 163 uint32_t txr_len_log2, rxr_len_log2; 164 uint32_t req_ring_size, cmp_ring_size; 165 m->rs_pa = ri->ringsStatePPN << VMW_PAGE_SHIFT; 166 167 req_ring_size = ri->reqRingNumPages * PVSCSI_MAX_NUM_REQ_ENTRIES_PER_PAGE; 168 cmp_ring_size = ri->cmpRingNumPages * PVSCSI_MAX_NUM_CMP_ENTRIES_PER_PAGE; 169 txr_len_log2 = pvscsi_log2(req_ring_size - 1); 170 rxr_len_log2 = pvscsi_log2(cmp_ring_size - 1); 171 172 m->txr_len_mask = MASK(txr_len_log2); 173 m->rxr_len_mask = MASK(rxr_len_log2); 174 175 m->consumed_ptr = 0; 176 m->filled_cmp_ptr = 0; 177 178 for (i = 0; i < ri->reqRingNumPages; i++) { 179 m->req_ring_pages_pa[i] = ri->reqRingPPNs[i] << VMW_PAGE_SHIFT; 180 } 181 182 for (i = 0; i < ri->cmpRingNumPages; i++) { 183 m->cmp_ring_pages_pa[i] = ri->cmpRingPPNs[i] << VMW_PAGE_SHIFT; 184 } 185 186 RS_SET_FIELD(m, reqProdIdx, 0); 187 RS_SET_FIELD(m, reqConsIdx, 0); 188 RS_SET_FIELD(m, reqNumEntriesLog2, txr_len_log2); 189 190 RS_SET_FIELD(m, cmpProdIdx, 0); 191 RS_SET_FIELD(m, cmpConsIdx, 0); 192 RS_SET_FIELD(m, cmpNumEntriesLog2, rxr_len_log2); 193 194 trace_pvscsi_ring_init_data(txr_len_log2, rxr_len_log2); 195 196 /* Flush ring state page changes */ 197 smp_wmb(); 198 } 199 200 static int 201 pvscsi_ring_init_msg(PVSCSIRingInfo *m, PVSCSICmdDescSetupMsgRing *ri) 202 { 203 int i; 204 uint32_t len_log2; 205 uint32_t ring_size; 206 207 if (!ri->numPages || ri->numPages > PVSCSI_SETUP_MSG_RING_MAX_NUM_PAGES) { 208 return -1; 209 } 210 ring_size = ri->numPages * PVSCSI_MAX_NUM_MSG_ENTRIES_PER_PAGE; 211 len_log2 = pvscsi_log2(ring_size - 1); 212 213 m->msg_len_mask = MASK(len_log2); 214 215 m->filled_msg_ptr = 0; 216 217 for (i = 0; i < ri->numPages; i++) { 218 m->msg_ring_pages_pa[i] = ri->ringPPNs[i] << VMW_PAGE_SHIFT; 219 } 220 221 RS_SET_FIELD(m, msgProdIdx, 0); 222 RS_SET_FIELD(m, msgConsIdx, 0); 223 RS_SET_FIELD(m, msgNumEntriesLog2, len_log2); 224 225 trace_pvscsi_ring_init_msg(len_log2); 226 227 /* Flush ring state page changes */ 228 smp_wmb(); 229 230 return 0; 231 } 232 233 static void 234 pvscsi_ring_cleanup(PVSCSIRingInfo *mgr) 235 { 236 mgr->rs_pa = 0; 237 mgr->txr_len_mask = 0; 238 mgr->rxr_len_mask = 0; 239 mgr->msg_len_mask = 0; 240 mgr->consumed_ptr = 0; 241 mgr->filled_cmp_ptr = 0; 242 mgr->filled_msg_ptr = 0; 243 memset(mgr->req_ring_pages_pa, 0, sizeof(mgr->req_ring_pages_pa)); 244 memset(mgr->cmp_ring_pages_pa, 0, sizeof(mgr->cmp_ring_pages_pa)); 245 memset(mgr->msg_ring_pages_pa, 0, sizeof(mgr->msg_ring_pages_pa)); 246 } 247 248 static hwaddr 249 pvscsi_ring_pop_req_descr(PVSCSIRingInfo *mgr) 250 { 251 uint32_t ready_ptr = RS_GET_FIELD(mgr, reqProdIdx); 252 uint32_t ring_size = PVSCSI_MAX_NUM_PAGES_REQ_RING 253 * PVSCSI_MAX_NUM_REQ_ENTRIES_PER_PAGE; 254 255 if (ready_ptr != mgr->consumed_ptr 256 && ready_ptr - mgr->consumed_ptr < ring_size) { 257 uint32_t next_ready_ptr = 258 mgr->consumed_ptr++ & mgr->txr_len_mask; 259 uint32_t next_ready_page = 260 next_ready_ptr / PVSCSI_MAX_NUM_REQ_ENTRIES_PER_PAGE; 261 uint32_t inpage_idx = 262 next_ready_ptr % PVSCSI_MAX_NUM_REQ_ENTRIES_PER_PAGE; 263 264 return mgr->req_ring_pages_pa[next_ready_page] + 265 inpage_idx * sizeof(PVSCSIRingReqDesc); 266 } else { 267 return 0; 268 } 269 } 270 271 static void 272 pvscsi_ring_flush_req(PVSCSIRingInfo *mgr) 273 { 274 RS_SET_FIELD(mgr, reqConsIdx, mgr->consumed_ptr); 275 } 276 277 static hwaddr 278 pvscsi_ring_pop_cmp_descr(PVSCSIRingInfo *mgr) 279 { 280 /* 281 * According to Linux driver code it explicitly verifies that number 282 * of requests being processed by device is less then the size of 283 * completion queue, so device may omit completion queue overflow 284 * conditions check. We assume that this is true for other (Windows) 285 * drivers as well. 286 */ 287 288 uint32_t free_cmp_ptr = 289 mgr->filled_cmp_ptr++ & mgr->rxr_len_mask; 290 uint32_t free_cmp_page = 291 free_cmp_ptr / PVSCSI_MAX_NUM_CMP_ENTRIES_PER_PAGE; 292 uint32_t inpage_idx = 293 free_cmp_ptr % PVSCSI_MAX_NUM_CMP_ENTRIES_PER_PAGE; 294 return mgr->cmp_ring_pages_pa[free_cmp_page] + 295 inpage_idx * sizeof(PVSCSIRingCmpDesc); 296 } 297 298 static hwaddr 299 pvscsi_ring_pop_msg_descr(PVSCSIRingInfo *mgr) 300 { 301 uint32_t free_msg_ptr = 302 mgr->filled_msg_ptr++ & mgr->msg_len_mask; 303 uint32_t free_msg_page = 304 free_msg_ptr / PVSCSI_MAX_NUM_MSG_ENTRIES_PER_PAGE; 305 uint32_t inpage_idx = 306 free_msg_ptr % PVSCSI_MAX_NUM_MSG_ENTRIES_PER_PAGE; 307 return mgr->msg_ring_pages_pa[free_msg_page] + 308 inpage_idx * sizeof(PVSCSIRingMsgDesc); 309 } 310 311 static void 312 pvscsi_ring_flush_cmp(PVSCSIRingInfo *mgr) 313 { 314 /* Flush descriptor changes */ 315 smp_wmb(); 316 317 trace_pvscsi_ring_flush_cmp(mgr->filled_cmp_ptr); 318 319 RS_SET_FIELD(mgr, cmpProdIdx, mgr->filled_cmp_ptr); 320 } 321 322 static bool 323 pvscsi_ring_msg_has_room(PVSCSIRingInfo *mgr) 324 { 325 uint32_t prodIdx = RS_GET_FIELD(mgr, msgProdIdx); 326 uint32_t consIdx = RS_GET_FIELD(mgr, msgConsIdx); 327 328 return (prodIdx - consIdx) < (mgr->msg_len_mask + 1); 329 } 330 331 static void 332 pvscsi_ring_flush_msg(PVSCSIRingInfo *mgr) 333 { 334 /* Flush descriptor changes */ 335 smp_wmb(); 336 337 trace_pvscsi_ring_flush_msg(mgr->filled_msg_ptr); 338 339 RS_SET_FIELD(mgr, msgProdIdx, mgr->filled_msg_ptr); 340 } 341 342 static void 343 pvscsi_reset_state(PVSCSIState *s) 344 { 345 s->curr_cmd = PVSCSI_CMD_FIRST; 346 s->curr_cmd_data_cntr = 0; 347 s->reg_command_status = PVSCSI_COMMAND_PROCESSING_SUCCEEDED; 348 s->reg_interrupt_status = 0; 349 pvscsi_ring_cleanup(&s->rings); 350 s->rings_info_valid = FALSE; 351 s->msg_ring_info_valid = FALSE; 352 QTAILQ_INIT(&s->pending_queue); 353 QTAILQ_INIT(&s->completion_queue); 354 } 355 356 static void 357 pvscsi_update_irq_status(PVSCSIState *s) 358 { 359 PCIDevice *d = PCI_DEVICE(s); 360 bool should_raise = s->reg_interrupt_enabled & s->reg_interrupt_status; 361 362 trace_pvscsi_update_irq_level(should_raise, s->reg_interrupt_enabled, 363 s->reg_interrupt_status); 364 365 if (msi_enabled(d)) { 366 if (should_raise) { 367 trace_pvscsi_update_irq_msi(); 368 msi_notify(d, PVSCSI_VECTOR_COMPLETION); 369 } 370 return; 371 } 372 373 pci_set_irq(d, !!should_raise); 374 } 375 376 static void 377 pvscsi_raise_completion_interrupt(PVSCSIState *s) 378 { 379 s->reg_interrupt_status |= PVSCSI_INTR_CMPL_0; 380 381 /* Memory barrier to flush interrupt status register changes*/ 382 smp_wmb(); 383 384 pvscsi_update_irq_status(s); 385 } 386 387 static void 388 pvscsi_raise_message_interrupt(PVSCSIState *s) 389 { 390 s->reg_interrupt_status |= PVSCSI_INTR_MSG_0; 391 392 /* Memory barrier to flush interrupt status register changes*/ 393 smp_wmb(); 394 395 pvscsi_update_irq_status(s); 396 } 397 398 static void 399 pvscsi_cmp_ring_put(PVSCSIState *s, struct PVSCSIRingCmpDesc *cmp_desc) 400 { 401 hwaddr cmp_descr_pa; 402 403 cmp_descr_pa = pvscsi_ring_pop_cmp_descr(&s->rings); 404 trace_pvscsi_cmp_ring_put(cmp_descr_pa); 405 cpu_physical_memory_write(cmp_descr_pa, cmp_desc, sizeof(*cmp_desc)); 406 } 407 408 static void 409 pvscsi_msg_ring_put(PVSCSIState *s, struct PVSCSIRingMsgDesc *msg_desc) 410 { 411 hwaddr msg_descr_pa; 412 413 msg_descr_pa = pvscsi_ring_pop_msg_descr(&s->rings); 414 trace_pvscsi_msg_ring_put(msg_descr_pa); 415 cpu_physical_memory_write(msg_descr_pa, msg_desc, sizeof(*msg_desc)); 416 } 417 418 static void 419 pvscsi_process_completion_queue(void *opaque) 420 { 421 PVSCSIState *s = opaque; 422 PVSCSIRequest *pvscsi_req; 423 bool has_completed = false; 424 425 while (!QTAILQ_EMPTY(&s->completion_queue)) { 426 pvscsi_req = QTAILQ_FIRST(&s->completion_queue); 427 QTAILQ_REMOVE(&s->completion_queue, pvscsi_req, next); 428 pvscsi_cmp_ring_put(s, &pvscsi_req->cmp); 429 g_free(pvscsi_req); 430 has_completed = true; 431 } 432 433 if (has_completed) { 434 pvscsi_ring_flush_cmp(&s->rings); 435 pvscsi_raise_completion_interrupt(s); 436 } 437 } 438 439 static void 440 pvscsi_reset_adapter(PVSCSIState *s) 441 { 442 s->resetting++; 443 qbus_reset_all(BUS(&s->bus)); 444 s->resetting--; 445 pvscsi_process_completion_queue(s); 446 assert(QTAILQ_EMPTY(&s->pending_queue)); 447 pvscsi_reset_state(s); 448 } 449 450 static void 451 pvscsi_schedule_completion_processing(PVSCSIState *s) 452 { 453 /* Try putting more complete requests on the ring. */ 454 if (!QTAILQ_EMPTY(&s->completion_queue)) { 455 qemu_bh_schedule(s->completion_worker); 456 } 457 } 458 459 static void 460 pvscsi_complete_request(PVSCSIState *s, PVSCSIRequest *r) 461 { 462 assert(!r->completed); 463 464 trace_pvscsi_complete_request(r->cmp.context, r->cmp.dataLen, 465 r->sense_key); 466 if (r->sreq != NULL) { 467 scsi_req_unref(r->sreq); 468 r->sreq = NULL; 469 } 470 r->completed = 1; 471 QTAILQ_REMOVE(&s->pending_queue, r, next); 472 QTAILQ_INSERT_TAIL(&s->completion_queue, r, next); 473 pvscsi_schedule_completion_processing(s); 474 } 475 476 static QEMUSGList *pvscsi_get_sg_list(SCSIRequest *r) 477 { 478 PVSCSIRequest *req = r->hba_private; 479 480 trace_pvscsi_get_sg_list(req->sgl.nsg, req->sgl.size); 481 482 return &req->sgl; 483 } 484 485 static void 486 pvscsi_get_next_sg_elem(PVSCSISGState *sg) 487 { 488 struct PVSCSISGElement elem; 489 490 cpu_physical_memory_read(sg->elemAddr, &elem, sizeof(elem)); 491 if ((elem.flags & ~PVSCSI_KNOWN_FLAGS) != 0) { 492 /* 493 * There is PVSCSI_SGE_FLAG_CHAIN_ELEMENT flag described in 494 * header file but its value is unknown. This flag requires 495 * additional processing, so we put warning here to catch it 496 * some day and make proper implementation 497 */ 498 trace_pvscsi_get_next_sg_elem(elem.flags); 499 } 500 501 sg->elemAddr += sizeof(elem); 502 sg->dataAddr = elem.addr; 503 sg->resid = elem.length; 504 } 505 506 static void 507 pvscsi_write_sense(PVSCSIRequest *r, uint8_t *sense, int len) 508 { 509 r->cmp.senseLen = MIN(r->req.senseLen, len); 510 r->sense_key = sense[(sense[0] & 2) ? 1 : 2]; 511 cpu_physical_memory_write(r->req.senseAddr, sense, r->cmp.senseLen); 512 } 513 514 static void 515 pvscsi_command_failed(SCSIRequest *req) 516 { 517 PVSCSIRequest *pvscsi_req = req->hba_private; 518 PVSCSIState *s; 519 520 if (!pvscsi_req) { 521 trace_pvscsi_command_complete_not_found(req->tag); 522 return; 523 } 524 s = pvscsi_req->dev; 525 526 switch (req->host_status) { 527 case SCSI_HOST_NO_LUN: 528 pvscsi_req->cmp.hostStatus = BTSTAT_LUNMISMATCH; 529 break; 530 case SCSI_HOST_BUSY: 531 pvscsi_req->cmp.hostStatus = BTSTAT_ABORTQUEUE; 532 break; 533 case SCSI_HOST_TIME_OUT: 534 case SCSI_HOST_ABORTED: 535 pvscsi_req->cmp.hostStatus = BTSTAT_SENTRST; 536 break; 537 case SCSI_HOST_BAD_RESPONSE: 538 pvscsi_req->cmp.hostStatus = BTSTAT_SELTIMEO; 539 break; 540 case SCSI_HOST_RESET: 541 pvscsi_req->cmp.hostStatus = BTSTAT_BUSRESET; 542 break; 543 default: 544 pvscsi_req->cmp.hostStatus = BTSTAT_HASOFTWARE; 545 break; 546 } 547 pvscsi_req->cmp.scsiStatus = GOOD; 548 qemu_sglist_destroy(&pvscsi_req->sgl); 549 pvscsi_complete_request(s, pvscsi_req); 550 } 551 552 static void 553 pvscsi_command_complete(SCSIRequest *req, size_t resid) 554 { 555 PVSCSIRequest *pvscsi_req = req->hba_private; 556 PVSCSIState *s; 557 558 if (!pvscsi_req) { 559 trace_pvscsi_command_complete_not_found(req->tag); 560 return; 561 } 562 s = pvscsi_req->dev; 563 564 if (resid) { 565 /* Short transfer. */ 566 trace_pvscsi_command_complete_data_run(); 567 pvscsi_req->cmp.hostStatus = BTSTAT_DATARUN; 568 } 569 570 pvscsi_req->cmp.scsiStatus = req->status; 571 if (pvscsi_req->cmp.scsiStatus == CHECK_CONDITION) { 572 uint8_t sense[SCSI_SENSE_BUF_SIZE]; 573 int sense_len = 574 scsi_req_get_sense(pvscsi_req->sreq, sense, sizeof(sense)); 575 576 trace_pvscsi_command_complete_sense_len(sense_len); 577 pvscsi_write_sense(pvscsi_req, sense, sense_len); 578 } 579 qemu_sglist_destroy(&pvscsi_req->sgl); 580 pvscsi_complete_request(s, pvscsi_req); 581 } 582 583 static void 584 pvscsi_send_msg(PVSCSIState *s, SCSIDevice *dev, uint32_t msg_type) 585 { 586 if (s->msg_ring_info_valid && pvscsi_ring_msg_has_room(&s->rings)) { 587 PVSCSIMsgDescDevStatusChanged msg = {0}; 588 589 msg.type = msg_type; 590 msg.bus = dev->channel; 591 msg.target = dev->id; 592 msg.lun[1] = dev->lun; 593 594 pvscsi_msg_ring_put(s, (PVSCSIRingMsgDesc *)&msg); 595 pvscsi_ring_flush_msg(&s->rings); 596 pvscsi_raise_message_interrupt(s); 597 } 598 } 599 600 static void 601 pvscsi_hotplug(HotplugHandler *hotplug_dev, DeviceState *dev, Error **errp) 602 { 603 PVSCSIState *s = PVSCSI(hotplug_dev); 604 605 pvscsi_send_msg(s, SCSI_DEVICE(dev), PVSCSI_MSG_DEV_ADDED); 606 } 607 608 static void 609 pvscsi_hot_unplug(HotplugHandler *hotplug_dev, DeviceState *dev, Error **errp) 610 { 611 PVSCSIState *s = PVSCSI(hotplug_dev); 612 613 pvscsi_send_msg(s, SCSI_DEVICE(dev), PVSCSI_MSG_DEV_REMOVED); 614 qdev_simple_device_unplug_cb(hotplug_dev, dev, errp); 615 } 616 617 static void 618 pvscsi_request_cancelled(SCSIRequest *req) 619 { 620 PVSCSIRequest *pvscsi_req = req->hba_private; 621 PVSCSIState *s = pvscsi_req->dev; 622 623 if (pvscsi_req->completed) { 624 return; 625 } 626 627 if (pvscsi_req->dev->resetting) { 628 pvscsi_req->cmp.hostStatus = BTSTAT_BUSRESET; 629 } else { 630 pvscsi_req->cmp.hostStatus = BTSTAT_ABORTQUEUE; 631 } 632 633 pvscsi_complete_request(s, pvscsi_req); 634 } 635 636 static SCSIDevice* 637 pvscsi_device_find(PVSCSIState *s, int channel, int target, 638 uint8_t *requested_lun, uint8_t *target_lun) 639 { 640 if (requested_lun[0] || requested_lun[2] || requested_lun[3] || 641 requested_lun[4] || requested_lun[5] || requested_lun[6] || 642 requested_lun[7] || (target > PVSCSI_MAX_DEVS)) { 643 return NULL; 644 } else { 645 *target_lun = requested_lun[1]; 646 return scsi_device_find(&s->bus, channel, target, *target_lun); 647 } 648 } 649 650 static PVSCSIRequest * 651 pvscsi_queue_pending_descriptor(PVSCSIState *s, SCSIDevice **d, 652 struct PVSCSIRingReqDesc *descr) 653 { 654 PVSCSIRequest *pvscsi_req; 655 uint8_t lun; 656 657 pvscsi_req = g_malloc0(sizeof(*pvscsi_req)); 658 pvscsi_req->dev = s; 659 pvscsi_req->req = *descr; 660 pvscsi_req->cmp.context = pvscsi_req->req.context; 661 QTAILQ_INSERT_TAIL(&s->pending_queue, pvscsi_req, next); 662 663 *d = pvscsi_device_find(s, descr->bus, descr->target, descr->lun, &lun); 664 if (*d) { 665 pvscsi_req->lun = lun; 666 } 667 668 return pvscsi_req; 669 } 670 671 static void 672 pvscsi_convert_sglist(PVSCSIRequest *r) 673 { 674 uint32_t chunk_size, elmcnt = 0; 675 uint64_t data_length = r->req.dataLen; 676 PVSCSISGState sg = r->sg; 677 while (data_length && elmcnt < PVSCSI_MAX_SG_ELEM) { 678 while (!sg.resid && elmcnt++ < PVSCSI_MAX_SG_ELEM) { 679 pvscsi_get_next_sg_elem(&sg); 680 trace_pvscsi_convert_sglist(r->req.context, r->sg.dataAddr, 681 r->sg.resid); 682 } 683 chunk_size = MIN(data_length, sg.resid); 684 if (chunk_size) { 685 qemu_sglist_add(&r->sgl, sg.dataAddr, chunk_size); 686 } 687 688 sg.dataAddr += chunk_size; 689 data_length -= chunk_size; 690 sg.resid -= chunk_size; 691 } 692 } 693 694 static void 695 pvscsi_build_sglist(PVSCSIState *s, PVSCSIRequest *r) 696 { 697 PCIDevice *d = PCI_DEVICE(s); 698 699 pci_dma_sglist_init(&r->sgl, d, 1); 700 if (r->req.flags & PVSCSI_FLAG_CMD_WITH_SG_LIST) { 701 pvscsi_convert_sglist(r); 702 } else { 703 qemu_sglist_add(&r->sgl, r->req.dataAddr, r->req.dataLen); 704 } 705 } 706 707 static void 708 pvscsi_process_request_descriptor(PVSCSIState *s, 709 struct PVSCSIRingReqDesc *descr) 710 { 711 SCSIDevice *d; 712 PVSCSIRequest *r = pvscsi_queue_pending_descriptor(s, &d, descr); 713 int64_t n; 714 715 trace_pvscsi_process_req_descr(descr->cdb[0], descr->context); 716 717 if (!d) { 718 r->cmp.hostStatus = BTSTAT_SELTIMEO; 719 trace_pvscsi_process_req_descr_unknown_device(); 720 pvscsi_complete_request(s, r); 721 return; 722 } 723 724 if (descr->flags & PVSCSI_FLAG_CMD_WITH_SG_LIST) { 725 r->sg.elemAddr = descr->dataAddr; 726 } 727 728 r->sreq = scsi_req_new(d, descr->context, r->lun, descr->cdb, r); 729 if (r->sreq->cmd.mode == SCSI_XFER_FROM_DEV && 730 (descr->flags & PVSCSI_FLAG_CMD_DIR_TODEVICE)) { 731 r->cmp.hostStatus = BTSTAT_BADMSG; 732 trace_pvscsi_process_req_descr_invalid_dir(); 733 scsi_req_cancel(r->sreq); 734 return; 735 } 736 if (r->sreq->cmd.mode == SCSI_XFER_TO_DEV && 737 (descr->flags & PVSCSI_FLAG_CMD_DIR_TOHOST)) { 738 r->cmp.hostStatus = BTSTAT_BADMSG; 739 trace_pvscsi_process_req_descr_invalid_dir(); 740 scsi_req_cancel(r->sreq); 741 return; 742 } 743 744 pvscsi_build_sglist(s, r); 745 n = scsi_req_enqueue(r->sreq); 746 747 if (n) { 748 scsi_req_continue(r->sreq); 749 } 750 } 751 752 static void 753 pvscsi_process_io(PVSCSIState *s) 754 { 755 PVSCSIRingReqDesc descr; 756 hwaddr next_descr_pa; 757 758 if (!s->rings_info_valid) { 759 return; 760 } 761 762 while ((next_descr_pa = pvscsi_ring_pop_req_descr(&s->rings)) != 0) { 763 764 /* Only read after production index verification */ 765 smp_rmb(); 766 767 trace_pvscsi_process_io(next_descr_pa); 768 cpu_physical_memory_read(next_descr_pa, &descr, sizeof(descr)); 769 pvscsi_process_request_descriptor(s, &descr); 770 } 771 772 pvscsi_ring_flush_req(&s->rings); 773 } 774 775 static void 776 pvscsi_dbg_dump_tx_rings_config(PVSCSICmdDescSetupRings *rc) 777 { 778 int i; 779 trace_pvscsi_tx_rings_ppn("Rings State", rc->ringsStatePPN); 780 781 trace_pvscsi_tx_rings_num_pages("Request Ring", rc->reqRingNumPages); 782 for (i = 0; i < rc->reqRingNumPages; i++) { 783 trace_pvscsi_tx_rings_ppn("Request Ring", rc->reqRingPPNs[i]); 784 } 785 786 trace_pvscsi_tx_rings_num_pages("Confirm Ring", rc->cmpRingNumPages); 787 for (i = 0; i < rc->cmpRingNumPages; i++) { 788 trace_pvscsi_tx_rings_ppn("Confirm Ring", rc->cmpRingPPNs[i]); 789 } 790 } 791 792 static uint64_t 793 pvscsi_on_cmd_config(PVSCSIState *s) 794 { 795 trace_pvscsi_on_cmd_noimpl("PVSCSI_CMD_CONFIG"); 796 return PVSCSI_COMMAND_PROCESSING_FAILED; 797 } 798 799 static uint64_t 800 pvscsi_on_cmd_unplug(PVSCSIState *s) 801 { 802 trace_pvscsi_on_cmd_noimpl("PVSCSI_CMD_DEVICE_UNPLUG"); 803 return PVSCSI_COMMAND_PROCESSING_FAILED; 804 } 805 806 static uint64_t 807 pvscsi_on_issue_scsi(PVSCSIState *s) 808 { 809 trace_pvscsi_on_cmd_noimpl("PVSCSI_CMD_ISSUE_SCSI"); 810 return PVSCSI_COMMAND_PROCESSING_FAILED; 811 } 812 813 static uint64_t 814 pvscsi_on_cmd_setup_rings(PVSCSIState *s) 815 { 816 PVSCSICmdDescSetupRings *rc = 817 (PVSCSICmdDescSetupRings *) s->curr_cmd_data; 818 819 trace_pvscsi_on_cmd_arrived("PVSCSI_CMD_SETUP_RINGS"); 820 821 if (!rc->reqRingNumPages 822 || rc->reqRingNumPages > PVSCSI_SETUP_RINGS_MAX_NUM_PAGES 823 || !rc->cmpRingNumPages 824 || rc->cmpRingNumPages > PVSCSI_SETUP_RINGS_MAX_NUM_PAGES) { 825 return PVSCSI_COMMAND_PROCESSING_FAILED; 826 } 827 828 pvscsi_dbg_dump_tx_rings_config(rc); 829 pvscsi_ring_init_data(&s->rings, rc); 830 831 s->rings_info_valid = TRUE; 832 return PVSCSI_COMMAND_PROCESSING_SUCCEEDED; 833 } 834 835 static uint64_t 836 pvscsi_on_cmd_abort(PVSCSIState *s) 837 { 838 PVSCSICmdDescAbortCmd *cmd = (PVSCSICmdDescAbortCmd *) s->curr_cmd_data; 839 PVSCSIRequest *r, *next; 840 841 trace_pvscsi_on_cmd_abort(cmd->context, cmd->target); 842 843 QTAILQ_FOREACH_SAFE(r, &s->pending_queue, next, next) { 844 if (r->req.context == cmd->context) { 845 break; 846 } 847 } 848 if (r) { 849 assert(!r->completed); 850 r->cmp.hostStatus = BTSTAT_ABORTQUEUE; 851 scsi_req_cancel(r->sreq); 852 } 853 854 return PVSCSI_COMMAND_PROCESSING_SUCCEEDED; 855 } 856 857 static uint64_t 858 pvscsi_on_cmd_unknown(PVSCSIState *s) 859 { 860 trace_pvscsi_on_cmd_unknown_data(s->curr_cmd_data[0]); 861 return PVSCSI_COMMAND_PROCESSING_FAILED; 862 } 863 864 static uint64_t 865 pvscsi_on_cmd_reset_device(PVSCSIState *s) 866 { 867 uint8_t target_lun = 0; 868 struct PVSCSICmdDescResetDevice *cmd = 869 (struct PVSCSICmdDescResetDevice *) s->curr_cmd_data; 870 SCSIDevice *sdev; 871 872 sdev = pvscsi_device_find(s, 0, cmd->target, cmd->lun, &target_lun); 873 874 trace_pvscsi_on_cmd_reset_dev(cmd->target, (int) target_lun, sdev); 875 876 if (sdev != NULL) { 877 s->resetting++; 878 device_legacy_reset(&sdev->qdev); 879 s->resetting--; 880 return PVSCSI_COMMAND_PROCESSING_SUCCEEDED; 881 } 882 883 return PVSCSI_COMMAND_PROCESSING_FAILED; 884 } 885 886 static uint64_t 887 pvscsi_on_cmd_reset_bus(PVSCSIState *s) 888 { 889 trace_pvscsi_on_cmd_arrived("PVSCSI_CMD_RESET_BUS"); 890 891 s->resetting++; 892 qbus_reset_all(BUS(&s->bus)); 893 s->resetting--; 894 return PVSCSI_COMMAND_PROCESSING_SUCCEEDED; 895 } 896 897 static uint64_t 898 pvscsi_on_cmd_setup_msg_ring(PVSCSIState *s) 899 { 900 PVSCSICmdDescSetupMsgRing *rc = 901 (PVSCSICmdDescSetupMsgRing *) s->curr_cmd_data; 902 903 trace_pvscsi_on_cmd_arrived("PVSCSI_CMD_SETUP_MSG_RING"); 904 905 if (!s->use_msg) { 906 return PVSCSI_COMMAND_PROCESSING_FAILED; 907 } 908 909 if (s->rings_info_valid) { 910 if (pvscsi_ring_init_msg(&s->rings, rc) < 0) { 911 return PVSCSI_COMMAND_PROCESSING_FAILED; 912 } 913 s->msg_ring_info_valid = TRUE; 914 } 915 return sizeof(PVSCSICmdDescSetupMsgRing) / sizeof(uint32_t); 916 } 917 918 static uint64_t 919 pvscsi_on_cmd_adapter_reset(PVSCSIState *s) 920 { 921 trace_pvscsi_on_cmd_arrived("PVSCSI_CMD_ADAPTER_RESET"); 922 923 pvscsi_reset_adapter(s); 924 return PVSCSI_COMMAND_PROCESSING_SUCCEEDED; 925 } 926 927 static const struct { 928 int data_size; 929 uint64_t (*handler_fn)(PVSCSIState *s); 930 } pvscsi_commands[] = { 931 [PVSCSI_CMD_FIRST] = { 932 .data_size = 0, 933 .handler_fn = pvscsi_on_cmd_unknown, 934 }, 935 936 /* Not implemented, data size defined based on what arrives on windows */ 937 [PVSCSI_CMD_CONFIG] = { 938 .data_size = 6 * sizeof(uint32_t), 939 .handler_fn = pvscsi_on_cmd_config, 940 }, 941 942 /* Command not implemented, data size is unknown */ 943 [PVSCSI_CMD_ISSUE_SCSI] = { 944 .data_size = 0, 945 .handler_fn = pvscsi_on_issue_scsi, 946 }, 947 948 /* Command not implemented, data size is unknown */ 949 [PVSCSI_CMD_DEVICE_UNPLUG] = { 950 .data_size = 0, 951 .handler_fn = pvscsi_on_cmd_unplug, 952 }, 953 954 [PVSCSI_CMD_SETUP_RINGS] = { 955 .data_size = sizeof(PVSCSICmdDescSetupRings), 956 .handler_fn = pvscsi_on_cmd_setup_rings, 957 }, 958 959 [PVSCSI_CMD_RESET_DEVICE] = { 960 .data_size = sizeof(struct PVSCSICmdDescResetDevice), 961 .handler_fn = pvscsi_on_cmd_reset_device, 962 }, 963 964 [PVSCSI_CMD_RESET_BUS] = { 965 .data_size = 0, 966 .handler_fn = pvscsi_on_cmd_reset_bus, 967 }, 968 969 [PVSCSI_CMD_SETUP_MSG_RING] = { 970 .data_size = sizeof(PVSCSICmdDescSetupMsgRing), 971 .handler_fn = pvscsi_on_cmd_setup_msg_ring, 972 }, 973 974 [PVSCSI_CMD_ADAPTER_RESET] = { 975 .data_size = 0, 976 .handler_fn = pvscsi_on_cmd_adapter_reset, 977 }, 978 979 [PVSCSI_CMD_ABORT_CMD] = { 980 .data_size = sizeof(struct PVSCSICmdDescAbortCmd), 981 .handler_fn = pvscsi_on_cmd_abort, 982 }, 983 }; 984 985 static void 986 pvscsi_do_command_processing(PVSCSIState *s) 987 { 988 size_t bytes_arrived = s->curr_cmd_data_cntr * sizeof(uint32_t); 989 990 assert(s->curr_cmd < PVSCSI_CMD_LAST); 991 if (bytes_arrived >= pvscsi_commands[s->curr_cmd].data_size) { 992 s->reg_command_status = pvscsi_commands[s->curr_cmd].handler_fn(s); 993 s->curr_cmd = PVSCSI_CMD_FIRST; 994 s->curr_cmd_data_cntr = 0; 995 } 996 } 997 998 static void 999 pvscsi_on_command_data(PVSCSIState *s, uint32_t value) 1000 { 1001 size_t bytes_arrived = s->curr_cmd_data_cntr * sizeof(uint32_t); 1002 1003 assert(bytes_arrived < sizeof(s->curr_cmd_data)); 1004 s->curr_cmd_data[s->curr_cmd_data_cntr++] = value; 1005 1006 pvscsi_do_command_processing(s); 1007 } 1008 1009 static void 1010 pvscsi_on_command(PVSCSIState *s, uint64_t cmd_id) 1011 { 1012 if ((cmd_id > PVSCSI_CMD_FIRST) && (cmd_id < PVSCSI_CMD_LAST)) { 1013 s->curr_cmd = cmd_id; 1014 } else { 1015 s->curr_cmd = PVSCSI_CMD_FIRST; 1016 trace_pvscsi_on_cmd_unknown(cmd_id); 1017 } 1018 1019 s->curr_cmd_data_cntr = 0; 1020 s->reg_command_status = PVSCSI_COMMAND_NOT_ENOUGH_DATA; 1021 1022 pvscsi_do_command_processing(s); 1023 } 1024 1025 static void 1026 pvscsi_io_write(void *opaque, hwaddr addr, 1027 uint64_t val, unsigned size) 1028 { 1029 PVSCSIState *s = opaque; 1030 1031 switch (addr) { 1032 case PVSCSI_REG_OFFSET_COMMAND: 1033 pvscsi_on_command(s, val); 1034 break; 1035 1036 case PVSCSI_REG_OFFSET_COMMAND_DATA: 1037 pvscsi_on_command_data(s, (uint32_t) val); 1038 break; 1039 1040 case PVSCSI_REG_OFFSET_INTR_STATUS: 1041 trace_pvscsi_io_write("PVSCSI_REG_OFFSET_INTR_STATUS", val); 1042 s->reg_interrupt_status &= ~val; 1043 pvscsi_update_irq_status(s); 1044 pvscsi_schedule_completion_processing(s); 1045 break; 1046 1047 case PVSCSI_REG_OFFSET_INTR_MASK: 1048 trace_pvscsi_io_write("PVSCSI_REG_OFFSET_INTR_MASK", val); 1049 s->reg_interrupt_enabled = val; 1050 pvscsi_update_irq_status(s); 1051 break; 1052 1053 case PVSCSI_REG_OFFSET_KICK_NON_RW_IO: 1054 trace_pvscsi_io_write("PVSCSI_REG_OFFSET_KICK_NON_RW_IO", val); 1055 pvscsi_process_io(s); 1056 break; 1057 1058 case PVSCSI_REG_OFFSET_KICK_RW_IO: 1059 trace_pvscsi_io_write("PVSCSI_REG_OFFSET_KICK_RW_IO", val); 1060 pvscsi_process_io(s); 1061 break; 1062 1063 case PVSCSI_REG_OFFSET_DEBUG: 1064 trace_pvscsi_io_write("PVSCSI_REG_OFFSET_DEBUG", val); 1065 break; 1066 1067 default: 1068 trace_pvscsi_io_write_unknown(addr, size, val); 1069 break; 1070 } 1071 1072 } 1073 1074 static uint64_t 1075 pvscsi_io_read(void *opaque, hwaddr addr, unsigned size) 1076 { 1077 PVSCSIState *s = opaque; 1078 1079 switch (addr) { 1080 case PVSCSI_REG_OFFSET_INTR_STATUS: 1081 trace_pvscsi_io_read("PVSCSI_REG_OFFSET_INTR_STATUS", 1082 s->reg_interrupt_status); 1083 return s->reg_interrupt_status; 1084 1085 case PVSCSI_REG_OFFSET_INTR_MASK: 1086 trace_pvscsi_io_read("PVSCSI_REG_OFFSET_INTR_MASK", 1087 s->reg_interrupt_status); 1088 return s->reg_interrupt_enabled; 1089 1090 case PVSCSI_REG_OFFSET_COMMAND_STATUS: 1091 trace_pvscsi_io_read("PVSCSI_REG_OFFSET_COMMAND_STATUS", 1092 s->reg_interrupt_status); 1093 return s->reg_command_status; 1094 1095 default: 1096 trace_pvscsi_io_read_unknown(addr, size); 1097 return 0; 1098 } 1099 } 1100 1101 1102 static void 1103 pvscsi_init_msi(PVSCSIState *s) 1104 { 1105 int res; 1106 PCIDevice *d = PCI_DEVICE(s); 1107 1108 res = msi_init(d, PVSCSI_MSI_OFFSET(s), PVSCSI_MSIX_NUM_VECTORS, 1109 PVSCSI_USE_64BIT, PVSCSI_PER_VECTOR_MASK, NULL); 1110 if (res < 0) { 1111 trace_pvscsi_init_msi_fail(res); 1112 s->msi_used = false; 1113 } else { 1114 s->msi_used = true; 1115 } 1116 } 1117 1118 static void 1119 pvscsi_cleanup_msi(PVSCSIState *s) 1120 { 1121 PCIDevice *d = PCI_DEVICE(s); 1122 1123 msi_uninit(d); 1124 } 1125 1126 static const MemoryRegionOps pvscsi_ops = { 1127 .read = pvscsi_io_read, 1128 .write = pvscsi_io_write, 1129 .endianness = DEVICE_LITTLE_ENDIAN, 1130 .impl = { 1131 .min_access_size = 4, 1132 .max_access_size = 4, 1133 }, 1134 }; 1135 1136 static const struct SCSIBusInfo pvscsi_scsi_info = { 1137 .tcq = true, 1138 .max_target = PVSCSI_MAX_DEVS, 1139 .max_channel = 0, 1140 .max_lun = 0, 1141 1142 .get_sg_list = pvscsi_get_sg_list, 1143 .complete = pvscsi_command_complete, 1144 .cancel = pvscsi_request_cancelled, 1145 .fail = pvscsi_command_failed, 1146 }; 1147 1148 static void 1149 pvscsi_realizefn(PCIDevice *pci_dev, Error **errp) 1150 { 1151 PVSCSIState *s = PVSCSI(pci_dev); 1152 1153 trace_pvscsi_state("init"); 1154 1155 /* PCI subsystem ID, subsystem vendor ID, revision */ 1156 if (PVSCSI_USE_OLD_PCI_CONFIGURATION(s)) { 1157 pci_set_word(pci_dev->config + PCI_SUBSYSTEM_ID, 0x1000); 1158 } else { 1159 pci_set_word(pci_dev->config + PCI_SUBSYSTEM_VENDOR_ID, 1160 PCI_VENDOR_ID_VMWARE); 1161 pci_set_word(pci_dev->config + PCI_SUBSYSTEM_ID, 1162 PCI_DEVICE_ID_VMWARE_PVSCSI); 1163 pci_config_set_revision(pci_dev->config, 0x2); 1164 } 1165 1166 /* PCI latency timer = 255 */ 1167 pci_dev->config[PCI_LATENCY_TIMER] = 0xff; 1168 1169 /* Interrupt pin A */ 1170 pci_config_set_interrupt_pin(pci_dev->config, 1); 1171 1172 memory_region_init_io(&s->io_space, OBJECT(s), &pvscsi_ops, s, 1173 "pvscsi-io", PVSCSI_MEM_SPACE_SIZE); 1174 pci_register_bar(pci_dev, 0, PCI_BASE_ADDRESS_SPACE_MEMORY, &s->io_space); 1175 1176 pvscsi_init_msi(s); 1177 1178 if (pci_is_express(pci_dev) && pci_bus_is_express(pci_get_bus(pci_dev))) { 1179 pcie_endpoint_cap_init(pci_dev, PVSCSI_EXP_EP_OFFSET); 1180 } 1181 1182 s->completion_worker = qemu_bh_new(pvscsi_process_completion_queue, s); 1183 1184 scsi_bus_init(&s->bus, sizeof(s->bus), DEVICE(pci_dev), &pvscsi_scsi_info); 1185 /* override default SCSI bus hotplug-handler, with pvscsi's one */ 1186 qbus_set_hotplug_handler(BUS(&s->bus), OBJECT(s)); 1187 pvscsi_reset_state(s); 1188 } 1189 1190 static void 1191 pvscsi_uninit(PCIDevice *pci_dev) 1192 { 1193 PVSCSIState *s = PVSCSI(pci_dev); 1194 1195 trace_pvscsi_state("uninit"); 1196 qemu_bh_delete(s->completion_worker); 1197 1198 pvscsi_cleanup_msi(s); 1199 } 1200 1201 static void 1202 pvscsi_reset(DeviceState *dev) 1203 { 1204 PCIDevice *d = PCI_DEVICE(dev); 1205 PVSCSIState *s = PVSCSI(d); 1206 1207 trace_pvscsi_state("reset"); 1208 pvscsi_reset_adapter(s); 1209 } 1210 1211 static int 1212 pvscsi_pre_save(void *opaque) 1213 { 1214 PVSCSIState *s = (PVSCSIState *) opaque; 1215 1216 trace_pvscsi_state("presave"); 1217 1218 assert(QTAILQ_EMPTY(&s->pending_queue)); 1219 assert(QTAILQ_EMPTY(&s->completion_queue)); 1220 1221 return 0; 1222 } 1223 1224 static int 1225 pvscsi_post_load(void *opaque, int version_id) 1226 { 1227 trace_pvscsi_state("postload"); 1228 return 0; 1229 } 1230 1231 static bool pvscsi_vmstate_need_pcie_device(void *opaque) 1232 { 1233 PVSCSIState *s = PVSCSI(opaque); 1234 1235 return !(s->compat_flags & PVSCSI_COMPAT_DISABLE_PCIE); 1236 } 1237 1238 static bool pvscsi_vmstate_test_pci_device(void *opaque, int version_id) 1239 { 1240 return !pvscsi_vmstate_need_pcie_device(opaque); 1241 } 1242 1243 static const VMStateDescription vmstate_pvscsi_pcie_device = { 1244 .name = "pvscsi/pcie", 1245 .needed = pvscsi_vmstate_need_pcie_device, 1246 .fields = (VMStateField[]) { 1247 VMSTATE_PCI_DEVICE(parent_obj, PVSCSIState), 1248 VMSTATE_END_OF_LIST() 1249 } 1250 }; 1251 1252 static const VMStateDescription vmstate_pvscsi = { 1253 .name = "pvscsi", 1254 .version_id = 0, 1255 .minimum_version_id = 0, 1256 .pre_save = pvscsi_pre_save, 1257 .post_load = pvscsi_post_load, 1258 .fields = (VMStateField[]) { 1259 VMSTATE_STRUCT_TEST(parent_obj, PVSCSIState, 1260 pvscsi_vmstate_test_pci_device, 0, 1261 vmstate_pci_device, PCIDevice), 1262 VMSTATE_UINT8(msi_used, PVSCSIState), 1263 VMSTATE_UINT32(resetting, PVSCSIState), 1264 VMSTATE_UINT64(reg_interrupt_status, PVSCSIState), 1265 VMSTATE_UINT64(reg_interrupt_enabled, PVSCSIState), 1266 VMSTATE_UINT64(reg_command_status, PVSCSIState), 1267 VMSTATE_UINT64(curr_cmd, PVSCSIState), 1268 VMSTATE_UINT32(curr_cmd_data_cntr, PVSCSIState), 1269 VMSTATE_UINT32_ARRAY(curr_cmd_data, PVSCSIState, 1270 ARRAY_SIZE(((PVSCSIState *)NULL)->curr_cmd_data)), 1271 VMSTATE_UINT8(rings_info_valid, PVSCSIState), 1272 VMSTATE_UINT8(msg_ring_info_valid, PVSCSIState), 1273 VMSTATE_UINT8(use_msg, PVSCSIState), 1274 1275 VMSTATE_UINT64(rings.rs_pa, PVSCSIState), 1276 VMSTATE_UINT32(rings.txr_len_mask, PVSCSIState), 1277 VMSTATE_UINT32(rings.rxr_len_mask, PVSCSIState), 1278 VMSTATE_UINT64_ARRAY(rings.req_ring_pages_pa, PVSCSIState, 1279 PVSCSI_SETUP_RINGS_MAX_NUM_PAGES), 1280 VMSTATE_UINT64_ARRAY(rings.cmp_ring_pages_pa, PVSCSIState, 1281 PVSCSI_SETUP_RINGS_MAX_NUM_PAGES), 1282 VMSTATE_UINT64(rings.consumed_ptr, PVSCSIState), 1283 VMSTATE_UINT64(rings.filled_cmp_ptr, PVSCSIState), 1284 1285 VMSTATE_END_OF_LIST() 1286 }, 1287 .subsections = (const VMStateDescription*[]) { 1288 &vmstate_pvscsi_pcie_device, 1289 NULL 1290 } 1291 }; 1292 1293 static Property pvscsi_properties[] = { 1294 DEFINE_PROP_UINT8("use_msg", PVSCSIState, use_msg, 1), 1295 DEFINE_PROP_BIT("x-old-pci-configuration", PVSCSIState, compat_flags, 1296 PVSCSI_COMPAT_OLD_PCI_CONFIGURATION_BIT, false), 1297 DEFINE_PROP_BIT("x-disable-pcie", PVSCSIState, compat_flags, 1298 PVSCSI_COMPAT_DISABLE_PCIE_BIT, false), 1299 DEFINE_PROP_END_OF_LIST(), 1300 }; 1301 1302 static void pvscsi_realize(DeviceState *qdev, Error **errp) 1303 { 1304 PVSCSIClass *pvs_c = PVSCSI_GET_CLASS(qdev); 1305 PCIDevice *pci_dev = PCI_DEVICE(qdev); 1306 PVSCSIState *s = PVSCSI(qdev); 1307 1308 if (!(s->compat_flags & PVSCSI_COMPAT_DISABLE_PCIE)) { 1309 pci_dev->cap_present |= QEMU_PCI_CAP_EXPRESS; 1310 } 1311 1312 pvs_c->parent_dc_realize(qdev, errp); 1313 } 1314 1315 static void pvscsi_class_init(ObjectClass *klass, void *data) 1316 { 1317 DeviceClass *dc = DEVICE_CLASS(klass); 1318 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); 1319 PVSCSIClass *pvs_k = PVSCSI_CLASS(klass); 1320 HotplugHandlerClass *hc = HOTPLUG_HANDLER_CLASS(klass); 1321 1322 k->realize = pvscsi_realizefn; 1323 k->exit = pvscsi_uninit; 1324 k->vendor_id = PCI_VENDOR_ID_VMWARE; 1325 k->device_id = PCI_DEVICE_ID_VMWARE_PVSCSI; 1326 k->class_id = PCI_CLASS_STORAGE_SCSI; 1327 k->subsystem_id = 0x1000; 1328 device_class_set_parent_realize(dc, pvscsi_realize, 1329 &pvs_k->parent_dc_realize); 1330 dc->reset = pvscsi_reset; 1331 dc->vmsd = &vmstate_pvscsi; 1332 device_class_set_props(dc, pvscsi_properties); 1333 set_bit(DEVICE_CATEGORY_STORAGE, dc->categories); 1334 hc->unplug = pvscsi_hot_unplug; 1335 hc->plug = pvscsi_hotplug; 1336 } 1337 1338 static const TypeInfo pvscsi_info = { 1339 .name = TYPE_PVSCSI, 1340 .parent = TYPE_PCI_DEVICE, 1341 .class_size = sizeof(PVSCSIClass), 1342 .instance_size = sizeof(PVSCSIState), 1343 .class_init = pvscsi_class_init, 1344 .interfaces = (InterfaceInfo[]) { 1345 { TYPE_HOTPLUG_HANDLER }, 1346 { INTERFACE_PCIE_DEVICE }, 1347 { INTERFACE_CONVENTIONAL_PCI_DEVICE }, 1348 { } 1349 } 1350 }; 1351 1352 static void 1353 pvscsi_register_types(void) 1354 { 1355 type_register_static(&pvscsi_info); 1356 } 1357 1358 type_init(pvscsi_register_types); 1359