1 /* 2 * QEMU VMWARE PVSCSI paravirtual SCSI bus 3 * 4 * Copyright (c) 2012 Ravello Systems LTD (http://ravellosystems.com) 5 * 6 * Developed by Daynix Computing LTD (http://www.daynix.com) 7 * 8 * Based on implementation by Paolo Bonzini 9 * http://lists.gnu.org/archive/html/qemu-devel/2011-08/msg00729.html 10 * 11 * Authors: 12 * Paolo Bonzini <pbonzini@redhat.com> 13 * Dmitry Fleytman <dmitry@daynix.com> 14 * Yan Vugenfirer <yan@daynix.com> 15 * 16 * This work is licensed under the terms of the GNU GPL, version 2. 17 * See the COPYING file in the top-level directory. 18 * 19 * NOTE about MSI-X: 20 * MSI-X support has been removed for the moment because it leads Windows OS 21 * to crash on startup. The crash happens because Windows driver requires 22 * MSI-X shared memory to be part of the same BAR used for rings state 23 * registers, etc. This is not supported by QEMU infrastructure so separate 24 * BAR created from MSI-X purposes. Windows driver fails to deal with 2 BARs. 25 * 26 */ 27 28 #include "qemu/osdep.h" 29 #include "qapi/error.h" 30 #include "qemu/main-loop.h" 31 #include "qemu/module.h" 32 #include "hw/scsi/scsi.h" 33 #include "migration/vmstate.h" 34 #include "scsi/constants.h" 35 #include "hw/pci/msi.h" 36 #include "hw/qdev-properties.h" 37 #include "vmw_pvscsi.h" 38 #include "trace.h" 39 #include "qom/object.h" 40 41 42 #define PVSCSI_USE_64BIT (true) 43 #define PVSCSI_PER_VECTOR_MASK (false) 44 45 #define PVSCSI_MAX_DEVS (64) 46 #define PVSCSI_MSIX_NUM_VECTORS (1) 47 48 #define PVSCSI_MAX_SG_ELEM 2048 49 50 #define PVSCSI_MAX_CMD_DATA_WORDS \ 51 (sizeof(PVSCSICmdDescSetupRings)/sizeof(uint32_t)) 52 53 #define RS_GET_FIELD(m, field) \ 54 (ldl_le_pci_dma(&container_of(m, PVSCSIState, rings)->parent_obj, \ 55 (m)->rs_pa + offsetof(struct PVSCSIRingsState, field), \ 56 MEMTXATTRS_UNSPECIFIED)) 57 #define RS_SET_FIELD(m, field, val) \ 58 (stl_le_pci_dma(&container_of(m, PVSCSIState, rings)->parent_obj, \ 59 (m)->rs_pa + offsetof(struct PVSCSIRingsState, field), val, \ 60 MEMTXATTRS_UNSPECIFIED)) 61 62 struct PVSCSIClass { 63 PCIDeviceClass parent_class; 64 DeviceRealize parent_dc_realize; 65 }; 66 67 #define TYPE_PVSCSI "pvscsi" 68 OBJECT_DECLARE_TYPE(PVSCSIState, PVSCSIClass, PVSCSI) 69 70 71 /* Compatibility flags for migration */ 72 #define PVSCSI_COMPAT_OLD_PCI_CONFIGURATION_BIT 0 73 #define PVSCSI_COMPAT_OLD_PCI_CONFIGURATION \ 74 (1 << PVSCSI_COMPAT_OLD_PCI_CONFIGURATION_BIT) 75 #define PVSCSI_COMPAT_DISABLE_PCIE_BIT 1 76 #define PVSCSI_COMPAT_DISABLE_PCIE \ 77 (1 << PVSCSI_COMPAT_DISABLE_PCIE_BIT) 78 79 #define PVSCSI_USE_OLD_PCI_CONFIGURATION(s) \ 80 ((s)->compat_flags & PVSCSI_COMPAT_OLD_PCI_CONFIGURATION) 81 #define PVSCSI_MSI_OFFSET(s) \ 82 (PVSCSI_USE_OLD_PCI_CONFIGURATION(s) ? 0x50 : 0x7c) 83 #define PVSCSI_EXP_EP_OFFSET (0x40) 84 85 typedef struct PVSCSIRingInfo { 86 uint64_t rs_pa; 87 uint32_t txr_len_mask; 88 uint32_t rxr_len_mask; 89 uint32_t msg_len_mask; 90 uint64_t req_ring_pages_pa[PVSCSI_SETUP_RINGS_MAX_NUM_PAGES]; 91 uint64_t cmp_ring_pages_pa[PVSCSI_SETUP_RINGS_MAX_NUM_PAGES]; 92 uint64_t msg_ring_pages_pa[PVSCSI_SETUP_MSG_RING_MAX_NUM_PAGES]; 93 uint64_t consumed_ptr; 94 uint64_t filled_cmp_ptr; 95 uint64_t filled_msg_ptr; 96 } PVSCSIRingInfo; 97 98 typedef struct PVSCSISGState { 99 hwaddr elemAddr; 100 hwaddr dataAddr; 101 uint32_t resid; 102 } PVSCSISGState; 103 104 typedef QTAILQ_HEAD(, PVSCSIRequest) PVSCSIRequestList; 105 106 struct PVSCSIState { 107 PCIDevice parent_obj; 108 MemoryRegion io_space; 109 SCSIBus bus; 110 QEMUBH *completion_worker; 111 PVSCSIRequestList pending_queue; 112 PVSCSIRequestList completion_queue; 113 114 uint64_t reg_interrupt_status; /* Interrupt status register value */ 115 uint64_t reg_interrupt_enabled; /* Interrupt mask register value */ 116 uint64_t reg_command_status; /* Command status register value */ 117 118 /* Command data adoption mechanism */ 119 uint64_t curr_cmd; /* Last command arrived */ 120 uint32_t curr_cmd_data_cntr; /* Amount of data for last command */ 121 122 /* Collector for current command data */ 123 uint32_t curr_cmd_data[PVSCSI_MAX_CMD_DATA_WORDS]; 124 125 uint8_t rings_info_valid; /* Whether data rings initialized */ 126 uint8_t msg_ring_info_valid; /* Whether message ring initialized */ 127 uint8_t use_msg; /* Whether to use message ring */ 128 129 uint8_t msi_used; /* For migration compatibility */ 130 PVSCSIRingInfo rings; /* Data transfer rings manager */ 131 uint32_t resetting; /* Reset in progress */ 132 133 uint32_t compat_flags; 134 }; 135 136 typedef struct PVSCSIRequest { 137 SCSIRequest *sreq; 138 PVSCSIState *dev; 139 uint8_t sense_key; 140 uint8_t completed; 141 int lun; 142 QEMUSGList sgl; 143 PVSCSISGState sg; 144 struct PVSCSIRingReqDesc req; 145 struct PVSCSIRingCmpDesc cmp; 146 QTAILQ_ENTRY(PVSCSIRequest) next; 147 } PVSCSIRequest; 148 149 /* Integer binary logarithm */ 150 static int 151 pvscsi_log2(uint32_t input) 152 { 153 int log = 0; 154 assert(input > 0); 155 while (input >> ++log) { 156 } 157 return log; 158 } 159 160 static void 161 pvscsi_ring_init_data(PVSCSIRingInfo *m, PVSCSICmdDescSetupRings *ri) 162 { 163 int i; 164 uint32_t txr_len_log2, rxr_len_log2; 165 uint32_t req_ring_size, cmp_ring_size; 166 m->rs_pa = ri->ringsStatePPN << VMW_PAGE_SHIFT; 167 168 req_ring_size = ri->reqRingNumPages * PVSCSI_MAX_NUM_REQ_ENTRIES_PER_PAGE; 169 cmp_ring_size = ri->cmpRingNumPages * PVSCSI_MAX_NUM_CMP_ENTRIES_PER_PAGE; 170 txr_len_log2 = pvscsi_log2(req_ring_size - 1); 171 rxr_len_log2 = pvscsi_log2(cmp_ring_size - 1); 172 173 m->txr_len_mask = MASK(txr_len_log2); 174 m->rxr_len_mask = MASK(rxr_len_log2); 175 176 m->consumed_ptr = 0; 177 m->filled_cmp_ptr = 0; 178 179 for (i = 0; i < ri->reqRingNumPages; i++) { 180 m->req_ring_pages_pa[i] = ri->reqRingPPNs[i] << VMW_PAGE_SHIFT; 181 } 182 183 for (i = 0; i < ri->cmpRingNumPages; i++) { 184 m->cmp_ring_pages_pa[i] = ri->cmpRingPPNs[i] << VMW_PAGE_SHIFT; 185 } 186 187 RS_SET_FIELD(m, reqProdIdx, 0); 188 RS_SET_FIELD(m, reqConsIdx, 0); 189 RS_SET_FIELD(m, reqNumEntriesLog2, txr_len_log2); 190 191 RS_SET_FIELD(m, cmpProdIdx, 0); 192 RS_SET_FIELD(m, cmpConsIdx, 0); 193 RS_SET_FIELD(m, cmpNumEntriesLog2, rxr_len_log2); 194 195 trace_pvscsi_ring_init_data(txr_len_log2, rxr_len_log2); 196 197 /* Flush ring state page changes */ 198 smp_wmb(); 199 } 200 201 static int 202 pvscsi_ring_init_msg(PVSCSIRingInfo *m, PVSCSICmdDescSetupMsgRing *ri) 203 { 204 int i; 205 uint32_t len_log2; 206 uint32_t ring_size; 207 208 if (!ri->numPages || ri->numPages > PVSCSI_SETUP_MSG_RING_MAX_NUM_PAGES) { 209 return -1; 210 } 211 ring_size = ri->numPages * PVSCSI_MAX_NUM_MSG_ENTRIES_PER_PAGE; 212 len_log2 = pvscsi_log2(ring_size - 1); 213 214 m->msg_len_mask = MASK(len_log2); 215 216 m->filled_msg_ptr = 0; 217 218 for (i = 0; i < ri->numPages; i++) { 219 m->msg_ring_pages_pa[i] = ri->ringPPNs[i] << VMW_PAGE_SHIFT; 220 } 221 222 RS_SET_FIELD(m, msgProdIdx, 0); 223 RS_SET_FIELD(m, msgConsIdx, 0); 224 RS_SET_FIELD(m, msgNumEntriesLog2, len_log2); 225 226 trace_pvscsi_ring_init_msg(len_log2); 227 228 /* Flush ring state page changes */ 229 smp_wmb(); 230 231 return 0; 232 } 233 234 static void 235 pvscsi_ring_cleanup(PVSCSIRingInfo *mgr) 236 { 237 mgr->rs_pa = 0; 238 mgr->txr_len_mask = 0; 239 mgr->rxr_len_mask = 0; 240 mgr->msg_len_mask = 0; 241 mgr->consumed_ptr = 0; 242 mgr->filled_cmp_ptr = 0; 243 mgr->filled_msg_ptr = 0; 244 memset(mgr->req_ring_pages_pa, 0, sizeof(mgr->req_ring_pages_pa)); 245 memset(mgr->cmp_ring_pages_pa, 0, sizeof(mgr->cmp_ring_pages_pa)); 246 memset(mgr->msg_ring_pages_pa, 0, sizeof(mgr->msg_ring_pages_pa)); 247 } 248 249 static hwaddr 250 pvscsi_ring_pop_req_descr(PVSCSIRingInfo *mgr) 251 { 252 uint32_t ready_ptr = RS_GET_FIELD(mgr, reqProdIdx); 253 uint32_t ring_size = PVSCSI_MAX_NUM_PAGES_REQ_RING 254 * PVSCSI_MAX_NUM_REQ_ENTRIES_PER_PAGE; 255 256 if (ready_ptr != mgr->consumed_ptr 257 && ready_ptr - mgr->consumed_ptr < ring_size) { 258 uint32_t next_ready_ptr = 259 mgr->consumed_ptr++ & mgr->txr_len_mask; 260 uint32_t next_ready_page = 261 next_ready_ptr / PVSCSI_MAX_NUM_REQ_ENTRIES_PER_PAGE; 262 uint32_t inpage_idx = 263 next_ready_ptr % PVSCSI_MAX_NUM_REQ_ENTRIES_PER_PAGE; 264 265 return mgr->req_ring_pages_pa[next_ready_page] + 266 inpage_idx * sizeof(PVSCSIRingReqDesc); 267 } else { 268 return 0; 269 } 270 } 271 272 static void 273 pvscsi_ring_flush_req(PVSCSIRingInfo *mgr) 274 { 275 RS_SET_FIELD(mgr, reqConsIdx, mgr->consumed_ptr); 276 } 277 278 static hwaddr 279 pvscsi_ring_pop_cmp_descr(PVSCSIRingInfo *mgr) 280 { 281 /* 282 * According to Linux driver code it explicitly verifies that number 283 * of requests being processed by device is less then the size of 284 * completion queue, so device may omit completion queue overflow 285 * conditions check. We assume that this is true for other (Windows) 286 * drivers as well. 287 */ 288 289 uint32_t free_cmp_ptr = 290 mgr->filled_cmp_ptr++ & mgr->rxr_len_mask; 291 uint32_t free_cmp_page = 292 free_cmp_ptr / PVSCSI_MAX_NUM_CMP_ENTRIES_PER_PAGE; 293 uint32_t inpage_idx = 294 free_cmp_ptr % PVSCSI_MAX_NUM_CMP_ENTRIES_PER_PAGE; 295 return mgr->cmp_ring_pages_pa[free_cmp_page] + 296 inpage_idx * sizeof(PVSCSIRingCmpDesc); 297 } 298 299 static hwaddr 300 pvscsi_ring_pop_msg_descr(PVSCSIRingInfo *mgr) 301 { 302 uint32_t free_msg_ptr = 303 mgr->filled_msg_ptr++ & mgr->msg_len_mask; 304 uint32_t free_msg_page = 305 free_msg_ptr / PVSCSI_MAX_NUM_MSG_ENTRIES_PER_PAGE; 306 uint32_t inpage_idx = 307 free_msg_ptr % PVSCSI_MAX_NUM_MSG_ENTRIES_PER_PAGE; 308 return mgr->msg_ring_pages_pa[free_msg_page] + 309 inpage_idx * sizeof(PVSCSIRingMsgDesc); 310 } 311 312 static void 313 pvscsi_ring_flush_cmp(PVSCSIRingInfo *mgr) 314 { 315 /* Flush descriptor changes */ 316 smp_wmb(); 317 318 trace_pvscsi_ring_flush_cmp(mgr->filled_cmp_ptr); 319 320 RS_SET_FIELD(mgr, cmpProdIdx, mgr->filled_cmp_ptr); 321 } 322 323 static bool 324 pvscsi_ring_msg_has_room(PVSCSIRingInfo *mgr) 325 { 326 uint32_t prodIdx = RS_GET_FIELD(mgr, msgProdIdx); 327 uint32_t consIdx = RS_GET_FIELD(mgr, msgConsIdx); 328 329 return (prodIdx - consIdx) < (mgr->msg_len_mask + 1); 330 } 331 332 static void 333 pvscsi_ring_flush_msg(PVSCSIRingInfo *mgr) 334 { 335 /* Flush descriptor changes */ 336 smp_wmb(); 337 338 trace_pvscsi_ring_flush_msg(mgr->filled_msg_ptr); 339 340 RS_SET_FIELD(mgr, msgProdIdx, mgr->filled_msg_ptr); 341 } 342 343 static void 344 pvscsi_reset_state(PVSCSIState *s) 345 { 346 s->curr_cmd = PVSCSI_CMD_FIRST; 347 s->curr_cmd_data_cntr = 0; 348 s->reg_command_status = PVSCSI_COMMAND_PROCESSING_SUCCEEDED; 349 s->reg_interrupt_status = 0; 350 pvscsi_ring_cleanup(&s->rings); 351 s->rings_info_valid = FALSE; 352 s->msg_ring_info_valid = FALSE; 353 QTAILQ_INIT(&s->pending_queue); 354 QTAILQ_INIT(&s->completion_queue); 355 } 356 357 static void 358 pvscsi_update_irq_status(PVSCSIState *s) 359 { 360 PCIDevice *d = PCI_DEVICE(s); 361 bool should_raise = s->reg_interrupt_enabled & s->reg_interrupt_status; 362 363 trace_pvscsi_update_irq_level(should_raise, s->reg_interrupt_enabled, 364 s->reg_interrupt_status); 365 366 if (msi_enabled(d)) { 367 if (should_raise) { 368 trace_pvscsi_update_irq_msi(); 369 msi_notify(d, PVSCSI_VECTOR_COMPLETION); 370 } 371 return; 372 } 373 374 pci_set_irq(d, !!should_raise); 375 } 376 377 static void 378 pvscsi_raise_completion_interrupt(PVSCSIState *s) 379 { 380 s->reg_interrupt_status |= PVSCSI_INTR_CMPL_0; 381 382 /* Memory barrier to flush interrupt status register changes*/ 383 smp_wmb(); 384 385 pvscsi_update_irq_status(s); 386 } 387 388 static void 389 pvscsi_raise_message_interrupt(PVSCSIState *s) 390 { 391 s->reg_interrupt_status |= PVSCSI_INTR_MSG_0; 392 393 /* Memory barrier to flush interrupt status register changes*/ 394 smp_wmb(); 395 396 pvscsi_update_irq_status(s); 397 } 398 399 static void 400 pvscsi_cmp_ring_put(PVSCSIState *s, struct PVSCSIRingCmpDesc *cmp_desc) 401 { 402 hwaddr cmp_descr_pa; 403 404 cmp_descr_pa = pvscsi_ring_pop_cmp_descr(&s->rings); 405 trace_pvscsi_cmp_ring_put(cmp_descr_pa); 406 cpu_physical_memory_write(cmp_descr_pa, cmp_desc, sizeof(*cmp_desc)); 407 } 408 409 static void 410 pvscsi_msg_ring_put(PVSCSIState *s, struct PVSCSIRingMsgDesc *msg_desc) 411 { 412 hwaddr msg_descr_pa; 413 414 msg_descr_pa = pvscsi_ring_pop_msg_descr(&s->rings); 415 trace_pvscsi_msg_ring_put(msg_descr_pa); 416 cpu_physical_memory_write(msg_descr_pa, msg_desc, sizeof(*msg_desc)); 417 } 418 419 static void 420 pvscsi_process_completion_queue(void *opaque) 421 { 422 PVSCSIState *s = opaque; 423 PVSCSIRequest *pvscsi_req; 424 bool has_completed = false; 425 426 while (!QTAILQ_EMPTY(&s->completion_queue)) { 427 pvscsi_req = QTAILQ_FIRST(&s->completion_queue); 428 QTAILQ_REMOVE(&s->completion_queue, pvscsi_req, next); 429 pvscsi_cmp_ring_put(s, &pvscsi_req->cmp); 430 g_free(pvscsi_req); 431 has_completed = true; 432 } 433 434 if (has_completed) { 435 pvscsi_ring_flush_cmp(&s->rings); 436 pvscsi_raise_completion_interrupt(s); 437 } 438 } 439 440 static void 441 pvscsi_reset_adapter(PVSCSIState *s) 442 { 443 s->resetting++; 444 qbus_reset_all(BUS(&s->bus)); 445 s->resetting--; 446 pvscsi_process_completion_queue(s); 447 assert(QTAILQ_EMPTY(&s->pending_queue)); 448 pvscsi_reset_state(s); 449 } 450 451 static void 452 pvscsi_schedule_completion_processing(PVSCSIState *s) 453 { 454 /* Try putting more complete requests on the ring. */ 455 if (!QTAILQ_EMPTY(&s->completion_queue)) { 456 qemu_bh_schedule(s->completion_worker); 457 } 458 } 459 460 static void 461 pvscsi_complete_request(PVSCSIState *s, PVSCSIRequest *r) 462 { 463 assert(!r->completed); 464 465 trace_pvscsi_complete_request(r->cmp.context, r->cmp.dataLen, 466 r->sense_key); 467 if (r->sreq != NULL) { 468 scsi_req_unref(r->sreq); 469 r->sreq = NULL; 470 } 471 r->completed = 1; 472 QTAILQ_REMOVE(&s->pending_queue, r, next); 473 QTAILQ_INSERT_TAIL(&s->completion_queue, r, next); 474 pvscsi_schedule_completion_processing(s); 475 } 476 477 static QEMUSGList *pvscsi_get_sg_list(SCSIRequest *r) 478 { 479 PVSCSIRequest *req = r->hba_private; 480 481 trace_pvscsi_get_sg_list(req->sgl.nsg, req->sgl.size); 482 483 return &req->sgl; 484 } 485 486 static void 487 pvscsi_get_next_sg_elem(PVSCSISGState *sg) 488 { 489 struct PVSCSISGElement elem; 490 491 cpu_physical_memory_read(sg->elemAddr, &elem, sizeof(elem)); 492 if ((elem.flags & ~PVSCSI_KNOWN_FLAGS) != 0) { 493 /* 494 * There is PVSCSI_SGE_FLAG_CHAIN_ELEMENT flag described in 495 * header file but its value is unknown. This flag requires 496 * additional processing, so we put warning here to catch it 497 * some day and make proper implementation 498 */ 499 trace_pvscsi_get_next_sg_elem(elem.flags); 500 } 501 502 sg->elemAddr += sizeof(elem); 503 sg->dataAddr = elem.addr; 504 sg->resid = elem.length; 505 } 506 507 static void 508 pvscsi_write_sense(PVSCSIRequest *r, uint8_t *sense, int len) 509 { 510 r->cmp.senseLen = MIN(r->req.senseLen, len); 511 r->sense_key = sense[(sense[0] & 2) ? 1 : 2]; 512 cpu_physical_memory_write(r->req.senseAddr, sense, r->cmp.senseLen); 513 } 514 515 static void 516 pvscsi_command_failed(SCSIRequest *req) 517 { 518 PVSCSIRequest *pvscsi_req = req->hba_private; 519 PVSCSIState *s; 520 521 if (!pvscsi_req) { 522 trace_pvscsi_command_complete_not_found(req->tag); 523 return; 524 } 525 s = pvscsi_req->dev; 526 527 switch (req->host_status) { 528 case SCSI_HOST_NO_LUN: 529 pvscsi_req->cmp.hostStatus = BTSTAT_LUNMISMATCH; 530 break; 531 case SCSI_HOST_BUSY: 532 pvscsi_req->cmp.hostStatus = BTSTAT_ABORTQUEUE; 533 break; 534 case SCSI_HOST_TIME_OUT: 535 case SCSI_HOST_ABORTED: 536 pvscsi_req->cmp.hostStatus = BTSTAT_SENTRST; 537 break; 538 case SCSI_HOST_BAD_RESPONSE: 539 pvscsi_req->cmp.hostStatus = BTSTAT_SELTIMEO; 540 break; 541 case SCSI_HOST_RESET: 542 pvscsi_req->cmp.hostStatus = BTSTAT_BUSRESET; 543 break; 544 default: 545 pvscsi_req->cmp.hostStatus = BTSTAT_HASOFTWARE; 546 break; 547 } 548 pvscsi_req->cmp.scsiStatus = GOOD; 549 qemu_sglist_destroy(&pvscsi_req->sgl); 550 pvscsi_complete_request(s, pvscsi_req); 551 } 552 553 static void 554 pvscsi_command_complete(SCSIRequest *req, size_t resid) 555 { 556 PVSCSIRequest *pvscsi_req = req->hba_private; 557 PVSCSIState *s; 558 559 if (!pvscsi_req) { 560 trace_pvscsi_command_complete_not_found(req->tag); 561 return; 562 } 563 s = pvscsi_req->dev; 564 565 if (resid) { 566 /* Short transfer. */ 567 trace_pvscsi_command_complete_data_run(); 568 pvscsi_req->cmp.hostStatus = BTSTAT_DATARUN; 569 } 570 571 pvscsi_req->cmp.scsiStatus = req->status; 572 if (pvscsi_req->cmp.scsiStatus == CHECK_CONDITION) { 573 uint8_t sense[SCSI_SENSE_BUF_SIZE]; 574 int sense_len = 575 scsi_req_get_sense(pvscsi_req->sreq, sense, sizeof(sense)); 576 577 trace_pvscsi_command_complete_sense_len(sense_len); 578 pvscsi_write_sense(pvscsi_req, sense, sense_len); 579 } 580 qemu_sglist_destroy(&pvscsi_req->sgl); 581 pvscsi_complete_request(s, pvscsi_req); 582 } 583 584 static void 585 pvscsi_send_msg(PVSCSIState *s, SCSIDevice *dev, uint32_t msg_type) 586 { 587 if (s->msg_ring_info_valid && pvscsi_ring_msg_has_room(&s->rings)) { 588 PVSCSIMsgDescDevStatusChanged msg = {0}; 589 590 msg.type = msg_type; 591 msg.bus = dev->channel; 592 msg.target = dev->id; 593 msg.lun[1] = dev->lun; 594 595 pvscsi_msg_ring_put(s, (PVSCSIRingMsgDesc *)&msg); 596 pvscsi_ring_flush_msg(&s->rings); 597 pvscsi_raise_message_interrupt(s); 598 } 599 } 600 601 static void 602 pvscsi_hotplug(HotplugHandler *hotplug_dev, DeviceState *dev, Error **errp) 603 { 604 PVSCSIState *s = PVSCSI(hotplug_dev); 605 606 pvscsi_send_msg(s, SCSI_DEVICE(dev), PVSCSI_MSG_DEV_ADDED); 607 } 608 609 static void 610 pvscsi_hot_unplug(HotplugHandler *hotplug_dev, DeviceState *dev, Error **errp) 611 { 612 PVSCSIState *s = PVSCSI(hotplug_dev); 613 614 pvscsi_send_msg(s, SCSI_DEVICE(dev), PVSCSI_MSG_DEV_REMOVED); 615 qdev_simple_device_unplug_cb(hotplug_dev, dev, errp); 616 } 617 618 static void 619 pvscsi_request_cancelled(SCSIRequest *req) 620 { 621 PVSCSIRequest *pvscsi_req = req->hba_private; 622 PVSCSIState *s = pvscsi_req->dev; 623 624 if (pvscsi_req->completed) { 625 return; 626 } 627 628 if (pvscsi_req->dev->resetting) { 629 pvscsi_req->cmp.hostStatus = BTSTAT_BUSRESET; 630 } else { 631 pvscsi_req->cmp.hostStatus = BTSTAT_ABORTQUEUE; 632 } 633 634 pvscsi_complete_request(s, pvscsi_req); 635 } 636 637 static SCSIDevice* 638 pvscsi_device_find(PVSCSIState *s, int channel, int target, 639 uint8_t *requested_lun, uint8_t *target_lun) 640 { 641 if (requested_lun[0] || requested_lun[2] || requested_lun[3] || 642 requested_lun[4] || requested_lun[5] || requested_lun[6] || 643 requested_lun[7] || (target > PVSCSI_MAX_DEVS)) { 644 return NULL; 645 } else { 646 *target_lun = requested_lun[1]; 647 return scsi_device_find(&s->bus, channel, target, *target_lun); 648 } 649 } 650 651 static PVSCSIRequest * 652 pvscsi_queue_pending_descriptor(PVSCSIState *s, SCSIDevice **d, 653 struct PVSCSIRingReqDesc *descr) 654 { 655 PVSCSIRequest *pvscsi_req; 656 uint8_t lun; 657 658 pvscsi_req = g_malloc0(sizeof(*pvscsi_req)); 659 pvscsi_req->dev = s; 660 pvscsi_req->req = *descr; 661 pvscsi_req->cmp.context = pvscsi_req->req.context; 662 QTAILQ_INSERT_TAIL(&s->pending_queue, pvscsi_req, next); 663 664 *d = pvscsi_device_find(s, descr->bus, descr->target, descr->lun, &lun); 665 if (*d) { 666 pvscsi_req->lun = lun; 667 } 668 669 return pvscsi_req; 670 } 671 672 static void 673 pvscsi_convert_sglist(PVSCSIRequest *r) 674 { 675 uint32_t chunk_size, elmcnt = 0; 676 uint64_t data_length = r->req.dataLen; 677 PVSCSISGState sg = r->sg; 678 while (data_length && elmcnt < PVSCSI_MAX_SG_ELEM) { 679 while (!sg.resid && elmcnt++ < PVSCSI_MAX_SG_ELEM) { 680 pvscsi_get_next_sg_elem(&sg); 681 trace_pvscsi_convert_sglist(r->req.context, r->sg.dataAddr, 682 r->sg.resid); 683 } 684 chunk_size = MIN(data_length, sg.resid); 685 if (chunk_size) { 686 qemu_sglist_add(&r->sgl, sg.dataAddr, chunk_size); 687 } 688 689 sg.dataAddr += chunk_size; 690 data_length -= chunk_size; 691 sg.resid -= chunk_size; 692 } 693 } 694 695 static void 696 pvscsi_build_sglist(PVSCSIState *s, PVSCSIRequest *r) 697 { 698 PCIDevice *d = PCI_DEVICE(s); 699 700 pci_dma_sglist_init(&r->sgl, d, 1); 701 if (r->req.flags & PVSCSI_FLAG_CMD_WITH_SG_LIST) { 702 pvscsi_convert_sglist(r); 703 } else { 704 qemu_sglist_add(&r->sgl, r->req.dataAddr, r->req.dataLen); 705 } 706 } 707 708 static void 709 pvscsi_process_request_descriptor(PVSCSIState *s, 710 struct PVSCSIRingReqDesc *descr) 711 { 712 SCSIDevice *d; 713 PVSCSIRequest *r = pvscsi_queue_pending_descriptor(s, &d, descr); 714 int64_t n; 715 716 trace_pvscsi_process_req_descr(descr->cdb[0], descr->context); 717 718 if (!d) { 719 r->cmp.hostStatus = BTSTAT_SELTIMEO; 720 trace_pvscsi_process_req_descr_unknown_device(); 721 pvscsi_complete_request(s, r); 722 return; 723 } 724 725 if (descr->flags & PVSCSI_FLAG_CMD_WITH_SG_LIST) { 726 r->sg.elemAddr = descr->dataAddr; 727 } 728 729 r->sreq = scsi_req_new(d, descr->context, r->lun, descr->cdb, r); 730 if (r->sreq->cmd.mode == SCSI_XFER_FROM_DEV && 731 (descr->flags & PVSCSI_FLAG_CMD_DIR_TODEVICE)) { 732 r->cmp.hostStatus = BTSTAT_BADMSG; 733 trace_pvscsi_process_req_descr_invalid_dir(); 734 scsi_req_cancel(r->sreq); 735 return; 736 } 737 if (r->sreq->cmd.mode == SCSI_XFER_TO_DEV && 738 (descr->flags & PVSCSI_FLAG_CMD_DIR_TOHOST)) { 739 r->cmp.hostStatus = BTSTAT_BADMSG; 740 trace_pvscsi_process_req_descr_invalid_dir(); 741 scsi_req_cancel(r->sreq); 742 return; 743 } 744 745 pvscsi_build_sglist(s, r); 746 n = scsi_req_enqueue(r->sreq); 747 748 if (n) { 749 scsi_req_continue(r->sreq); 750 } 751 } 752 753 static void 754 pvscsi_process_io(PVSCSIState *s) 755 { 756 PVSCSIRingReqDesc descr; 757 hwaddr next_descr_pa; 758 759 if (!s->rings_info_valid) { 760 return; 761 } 762 763 while ((next_descr_pa = pvscsi_ring_pop_req_descr(&s->rings)) != 0) { 764 765 /* Only read after production index verification */ 766 smp_rmb(); 767 768 trace_pvscsi_process_io(next_descr_pa); 769 cpu_physical_memory_read(next_descr_pa, &descr, sizeof(descr)); 770 pvscsi_process_request_descriptor(s, &descr); 771 } 772 773 pvscsi_ring_flush_req(&s->rings); 774 } 775 776 static void 777 pvscsi_dbg_dump_tx_rings_config(PVSCSICmdDescSetupRings *rc) 778 { 779 int i; 780 trace_pvscsi_tx_rings_ppn("Rings State", rc->ringsStatePPN); 781 782 trace_pvscsi_tx_rings_num_pages("Request Ring", rc->reqRingNumPages); 783 for (i = 0; i < rc->reqRingNumPages; i++) { 784 trace_pvscsi_tx_rings_ppn("Request Ring", rc->reqRingPPNs[i]); 785 } 786 787 trace_pvscsi_tx_rings_num_pages("Confirm Ring", rc->cmpRingNumPages); 788 for (i = 0; i < rc->cmpRingNumPages; i++) { 789 trace_pvscsi_tx_rings_ppn("Confirm Ring", rc->cmpRingPPNs[i]); 790 } 791 } 792 793 static uint64_t 794 pvscsi_on_cmd_config(PVSCSIState *s) 795 { 796 trace_pvscsi_on_cmd_noimpl("PVSCSI_CMD_CONFIG"); 797 return PVSCSI_COMMAND_PROCESSING_FAILED; 798 } 799 800 static uint64_t 801 pvscsi_on_cmd_unplug(PVSCSIState *s) 802 { 803 trace_pvscsi_on_cmd_noimpl("PVSCSI_CMD_DEVICE_UNPLUG"); 804 return PVSCSI_COMMAND_PROCESSING_FAILED; 805 } 806 807 static uint64_t 808 pvscsi_on_issue_scsi(PVSCSIState *s) 809 { 810 trace_pvscsi_on_cmd_noimpl("PVSCSI_CMD_ISSUE_SCSI"); 811 return PVSCSI_COMMAND_PROCESSING_FAILED; 812 } 813 814 static uint64_t 815 pvscsi_on_cmd_setup_rings(PVSCSIState *s) 816 { 817 PVSCSICmdDescSetupRings *rc = 818 (PVSCSICmdDescSetupRings *) s->curr_cmd_data; 819 820 trace_pvscsi_on_cmd_arrived("PVSCSI_CMD_SETUP_RINGS"); 821 822 if (!rc->reqRingNumPages 823 || rc->reqRingNumPages > PVSCSI_SETUP_RINGS_MAX_NUM_PAGES 824 || !rc->cmpRingNumPages 825 || rc->cmpRingNumPages > PVSCSI_SETUP_RINGS_MAX_NUM_PAGES) { 826 return PVSCSI_COMMAND_PROCESSING_FAILED; 827 } 828 829 pvscsi_dbg_dump_tx_rings_config(rc); 830 pvscsi_ring_init_data(&s->rings, rc); 831 832 s->rings_info_valid = TRUE; 833 return PVSCSI_COMMAND_PROCESSING_SUCCEEDED; 834 } 835 836 static uint64_t 837 pvscsi_on_cmd_abort(PVSCSIState *s) 838 { 839 PVSCSICmdDescAbortCmd *cmd = (PVSCSICmdDescAbortCmd *) s->curr_cmd_data; 840 PVSCSIRequest *r, *next; 841 842 trace_pvscsi_on_cmd_abort(cmd->context, cmd->target); 843 844 QTAILQ_FOREACH_SAFE(r, &s->pending_queue, next, next) { 845 if (r->req.context == cmd->context) { 846 break; 847 } 848 } 849 if (r) { 850 assert(!r->completed); 851 r->cmp.hostStatus = BTSTAT_ABORTQUEUE; 852 scsi_req_cancel(r->sreq); 853 } 854 855 return PVSCSI_COMMAND_PROCESSING_SUCCEEDED; 856 } 857 858 static uint64_t 859 pvscsi_on_cmd_unknown(PVSCSIState *s) 860 { 861 trace_pvscsi_on_cmd_unknown_data(s->curr_cmd_data[0]); 862 return PVSCSI_COMMAND_PROCESSING_FAILED; 863 } 864 865 static uint64_t 866 pvscsi_on_cmd_reset_device(PVSCSIState *s) 867 { 868 uint8_t target_lun = 0; 869 struct PVSCSICmdDescResetDevice *cmd = 870 (struct PVSCSICmdDescResetDevice *) s->curr_cmd_data; 871 SCSIDevice *sdev; 872 873 sdev = pvscsi_device_find(s, 0, cmd->target, cmd->lun, &target_lun); 874 875 trace_pvscsi_on_cmd_reset_dev(cmd->target, (int) target_lun, sdev); 876 877 if (sdev != NULL) { 878 s->resetting++; 879 device_legacy_reset(&sdev->qdev); 880 s->resetting--; 881 return PVSCSI_COMMAND_PROCESSING_SUCCEEDED; 882 } 883 884 return PVSCSI_COMMAND_PROCESSING_FAILED; 885 } 886 887 static uint64_t 888 pvscsi_on_cmd_reset_bus(PVSCSIState *s) 889 { 890 trace_pvscsi_on_cmd_arrived("PVSCSI_CMD_RESET_BUS"); 891 892 s->resetting++; 893 qbus_reset_all(BUS(&s->bus)); 894 s->resetting--; 895 return PVSCSI_COMMAND_PROCESSING_SUCCEEDED; 896 } 897 898 static uint64_t 899 pvscsi_on_cmd_setup_msg_ring(PVSCSIState *s) 900 { 901 PVSCSICmdDescSetupMsgRing *rc = 902 (PVSCSICmdDescSetupMsgRing *) s->curr_cmd_data; 903 904 trace_pvscsi_on_cmd_arrived("PVSCSI_CMD_SETUP_MSG_RING"); 905 906 if (!s->use_msg) { 907 return PVSCSI_COMMAND_PROCESSING_FAILED; 908 } 909 910 if (s->rings_info_valid) { 911 if (pvscsi_ring_init_msg(&s->rings, rc) < 0) { 912 return PVSCSI_COMMAND_PROCESSING_FAILED; 913 } 914 s->msg_ring_info_valid = TRUE; 915 } 916 return sizeof(PVSCSICmdDescSetupMsgRing) / sizeof(uint32_t); 917 } 918 919 static uint64_t 920 pvscsi_on_cmd_adapter_reset(PVSCSIState *s) 921 { 922 trace_pvscsi_on_cmd_arrived("PVSCSI_CMD_ADAPTER_RESET"); 923 924 pvscsi_reset_adapter(s); 925 return PVSCSI_COMMAND_PROCESSING_SUCCEEDED; 926 } 927 928 static const struct { 929 int data_size; 930 uint64_t (*handler_fn)(PVSCSIState *s); 931 } pvscsi_commands[] = { 932 [PVSCSI_CMD_FIRST] = { 933 .data_size = 0, 934 .handler_fn = pvscsi_on_cmd_unknown, 935 }, 936 937 /* Not implemented, data size defined based on what arrives on windows */ 938 [PVSCSI_CMD_CONFIG] = { 939 .data_size = 6 * sizeof(uint32_t), 940 .handler_fn = pvscsi_on_cmd_config, 941 }, 942 943 /* Command not implemented, data size is unknown */ 944 [PVSCSI_CMD_ISSUE_SCSI] = { 945 .data_size = 0, 946 .handler_fn = pvscsi_on_issue_scsi, 947 }, 948 949 /* Command not implemented, data size is unknown */ 950 [PVSCSI_CMD_DEVICE_UNPLUG] = { 951 .data_size = 0, 952 .handler_fn = pvscsi_on_cmd_unplug, 953 }, 954 955 [PVSCSI_CMD_SETUP_RINGS] = { 956 .data_size = sizeof(PVSCSICmdDescSetupRings), 957 .handler_fn = pvscsi_on_cmd_setup_rings, 958 }, 959 960 [PVSCSI_CMD_RESET_DEVICE] = { 961 .data_size = sizeof(struct PVSCSICmdDescResetDevice), 962 .handler_fn = pvscsi_on_cmd_reset_device, 963 }, 964 965 [PVSCSI_CMD_RESET_BUS] = { 966 .data_size = 0, 967 .handler_fn = pvscsi_on_cmd_reset_bus, 968 }, 969 970 [PVSCSI_CMD_SETUP_MSG_RING] = { 971 .data_size = sizeof(PVSCSICmdDescSetupMsgRing), 972 .handler_fn = pvscsi_on_cmd_setup_msg_ring, 973 }, 974 975 [PVSCSI_CMD_ADAPTER_RESET] = { 976 .data_size = 0, 977 .handler_fn = pvscsi_on_cmd_adapter_reset, 978 }, 979 980 [PVSCSI_CMD_ABORT_CMD] = { 981 .data_size = sizeof(struct PVSCSICmdDescAbortCmd), 982 .handler_fn = pvscsi_on_cmd_abort, 983 }, 984 }; 985 986 static void 987 pvscsi_do_command_processing(PVSCSIState *s) 988 { 989 size_t bytes_arrived = s->curr_cmd_data_cntr * sizeof(uint32_t); 990 991 assert(s->curr_cmd < PVSCSI_CMD_LAST); 992 if (bytes_arrived >= pvscsi_commands[s->curr_cmd].data_size) { 993 s->reg_command_status = pvscsi_commands[s->curr_cmd].handler_fn(s); 994 s->curr_cmd = PVSCSI_CMD_FIRST; 995 s->curr_cmd_data_cntr = 0; 996 } 997 } 998 999 static void 1000 pvscsi_on_command_data(PVSCSIState *s, uint32_t value) 1001 { 1002 size_t bytes_arrived = s->curr_cmd_data_cntr * sizeof(uint32_t); 1003 1004 assert(bytes_arrived < sizeof(s->curr_cmd_data)); 1005 s->curr_cmd_data[s->curr_cmd_data_cntr++] = value; 1006 1007 pvscsi_do_command_processing(s); 1008 } 1009 1010 static void 1011 pvscsi_on_command(PVSCSIState *s, uint64_t cmd_id) 1012 { 1013 if ((cmd_id > PVSCSI_CMD_FIRST) && (cmd_id < PVSCSI_CMD_LAST)) { 1014 s->curr_cmd = cmd_id; 1015 } else { 1016 s->curr_cmd = PVSCSI_CMD_FIRST; 1017 trace_pvscsi_on_cmd_unknown(cmd_id); 1018 } 1019 1020 s->curr_cmd_data_cntr = 0; 1021 s->reg_command_status = PVSCSI_COMMAND_NOT_ENOUGH_DATA; 1022 1023 pvscsi_do_command_processing(s); 1024 } 1025 1026 static void 1027 pvscsi_io_write(void *opaque, hwaddr addr, 1028 uint64_t val, unsigned size) 1029 { 1030 PVSCSIState *s = opaque; 1031 1032 switch (addr) { 1033 case PVSCSI_REG_OFFSET_COMMAND: 1034 pvscsi_on_command(s, val); 1035 break; 1036 1037 case PVSCSI_REG_OFFSET_COMMAND_DATA: 1038 pvscsi_on_command_data(s, (uint32_t) val); 1039 break; 1040 1041 case PVSCSI_REG_OFFSET_INTR_STATUS: 1042 trace_pvscsi_io_write("PVSCSI_REG_OFFSET_INTR_STATUS", val); 1043 s->reg_interrupt_status &= ~val; 1044 pvscsi_update_irq_status(s); 1045 pvscsi_schedule_completion_processing(s); 1046 break; 1047 1048 case PVSCSI_REG_OFFSET_INTR_MASK: 1049 trace_pvscsi_io_write("PVSCSI_REG_OFFSET_INTR_MASK", val); 1050 s->reg_interrupt_enabled = val; 1051 pvscsi_update_irq_status(s); 1052 break; 1053 1054 case PVSCSI_REG_OFFSET_KICK_NON_RW_IO: 1055 trace_pvscsi_io_write("PVSCSI_REG_OFFSET_KICK_NON_RW_IO", val); 1056 pvscsi_process_io(s); 1057 break; 1058 1059 case PVSCSI_REG_OFFSET_KICK_RW_IO: 1060 trace_pvscsi_io_write("PVSCSI_REG_OFFSET_KICK_RW_IO", val); 1061 pvscsi_process_io(s); 1062 break; 1063 1064 case PVSCSI_REG_OFFSET_DEBUG: 1065 trace_pvscsi_io_write("PVSCSI_REG_OFFSET_DEBUG", val); 1066 break; 1067 1068 default: 1069 trace_pvscsi_io_write_unknown(addr, size, val); 1070 break; 1071 } 1072 1073 } 1074 1075 static uint64_t 1076 pvscsi_io_read(void *opaque, hwaddr addr, unsigned size) 1077 { 1078 PVSCSIState *s = opaque; 1079 1080 switch (addr) { 1081 case PVSCSI_REG_OFFSET_INTR_STATUS: 1082 trace_pvscsi_io_read("PVSCSI_REG_OFFSET_INTR_STATUS", 1083 s->reg_interrupt_status); 1084 return s->reg_interrupt_status; 1085 1086 case PVSCSI_REG_OFFSET_INTR_MASK: 1087 trace_pvscsi_io_read("PVSCSI_REG_OFFSET_INTR_MASK", 1088 s->reg_interrupt_status); 1089 return s->reg_interrupt_enabled; 1090 1091 case PVSCSI_REG_OFFSET_COMMAND_STATUS: 1092 trace_pvscsi_io_read("PVSCSI_REG_OFFSET_COMMAND_STATUS", 1093 s->reg_interrupt_status); 1094 return s->reg_command_status; 1095 1096 default: 1097 trace_pvscsi_io_read_unknown(addr, size); 1098 return 0; 1099 } 1100 } 1101 1102 1103 static void 1104 pvscsi_init_msi(PVSCSIState *s) 1105 { 1106 int res; 1107 PCIDevice *d = PCI_DEVICE(s); 1108 1109 res = msi_init(d, PVSCSI_MSI_OFFSET(s), PVSCSI_MSIX_NUM_VECTORS, 1110 PVSCSI_USE_64BIT, PVSCSI_PER_VECTOR_MASK, NULL); 1111 if (res < 0) { 1112 trace_pvscsi_init_msi_fail(res); 1113 s->msi_used = false; 1114 } else { 1115 s->msi_used = true; 1116 } 1117 } 1118 1119 static void 1120 pvscsi_cleanup_msi(PVSCSIState *s) 1121 { 1122 PCIDevice *d = PCI_DEVICE(s); 1123 1124 msi_uninit(d); 1125 } 1126 1127 static const MemoryRegionOps pvscsi_ops = { 1128 .read = pvscsi_io_read, 1129 .write = pvscsi_io_write, 1130 .endianness = DEVICE_LITTLE_ENDIAN, 1131 .impl = { 1132 .min_access_size = 4, 1133 .max_access_size = 4, 1134 }, 1135 }; 1136 1137 static const struct SCSIBusInfo pvscsi_scsi_info = { 1138 .tcq = true, 1139 .max_target = PVSCSI_MAX_DEVS, 1140 .max_channel = 0, 1141 .max_lun = 0, 1142 1143 .get_sg_list = pvscsi_get_sg_list, 1144 .complete = pvscsi_command_complete, 1145 .cancel = pvscsi_request_cancelled, 1146 .fail = pvscsi_command_failed, 1147 }; 1148 1149 static void 1150 pvscsi_realizefn(PCIDevice *pci_dev, Error **errp) 1151 { 1152 PVSCSIState *s = PVSCSI(pci_dev); 1153 1154 trace_pvscsi_state("init"); 1155 1156 /* PCI subsystem ID, subsystem vendor ID, revision */ 1157 if (PVSCSI_USE_OLD_PCI_CONFIGURATION(s)) { 1158 pci_set_word(pci_dev->config + PCI_SUBSYSTEM_ID, 0x1000); 1159 } else { 1160 pci_set_word(pci_dev->config + PCI_SUBSYSTEM_VENDOR_ID, 1161 PCI_VENDOR_ID_VMWARE); 1162 pci_set_word(pci_dev->config + PCI_SUBSYSTEM_ID, 1163 PCI_DEVICE_ID_VMWARE_PVSCSI); 1164 pci_config_set_revision(pci_dev->config, 0x2); 1165 } 1166 1167 /* PCI latency timer = 255 */ 1168 pci_dev->config[PCI_LATENCY_TIMER] = 0xff; 1169 1170 /* Interrupt pin A */ 1171 pci_config_set_interrupt_pin(pci_dev->config, 1); 1172 1173 memory_region_init_io(&s->io_space, OBJECT(s), &pvscsi_ops, s, 1174 "pvscsi-io", PVSCSI_MEM_SPACE_SIZE); 1175 pci_register_bar(pci_dev, 0, PCI_BASE_ADDRESS_SPACE_MEMORY, &s->io_space); 1176 1177 pvscsi_init_msi(s); 1178 1179 if (pci_is_express(pci_dev) && pci_bus_is_express(pci_get_bus(pci_dev))) { 1180 pcie_endpoint_cap_init(pci_dev, PVSCSI_EXP_EP_OFFSET); 1181 } 1182 1183 s->completion_worker = qemu_bh_new(pvscsi_process_completion_queue, s); 1184 1185 scsi_bus_init(&s->bus, sizeof(s->bus), DEVICE(pci_dev), &pvscsi_scsi_info); 1186 /* override default SCSI bus hotplug-handler, with pvscsi's one */ 1187 qbus_set_hotplug_handler(BUS(&s->bus), OBJECT(s)); 1188 pvscsi_reset_state(s); 1189 } 1190 1191 static void 1192 pvscsi_uninit(PCIDevice *pci_dev) 1193 { 1194 PVSCSIState *s = PVSCSI(pci_dev); 1195 1196 trace_pvscsi_state("uninit"); 1197 qemu_bh_delete(s->completion_worker); 1198 1199 pvscsi_cleanup_msi(s); 1200 } 1201 1202 static void 1203 pvscsi_reset(DeviceState *dev) 1204 { 1205 PCIDevice *d = PCI_DEVICE(dev); 1206 PVSCSIState *s = PVSCSI(d); 1207 1208 trace_pvscsi_state("reset"); 1209 pvscsi_reset_adapter(s); 1210 } 1211 1212 static int 1213 pvscsi_pre_save(void *opaque) 1214 { 1215 PVSCSIState *s = (PVSCSIState *) opaque; 1216 1217 trace_pvscsi_state("presave"); 1218 1219 assert(QTAILQ_EMPTY(&s->pending_queue)); 1220 assert(QTAILQ_EMPTY(&s->completion_queue)); 1221 1222 return 0; 1223 } 1224 1225 static int 1226 pvscsi_post_load(void *opaque, int version_id) 1227 { 1228 trace_pvscsi_state("postload"); 1229 return 0; 1230 } 1231 1232 static bool pvscsi_vmstate_need_pcie_device(void *opaque) 1233 { 1234 PVSCSIState *s = PVSCSI(opaque); 1235 1236 return !(s->compat_flags & PVSCSI_COMPAT_DISABLE_PCIE); 1237 } 1238 1239 static bool pvscsi_vmstate_test_pci_device(void *opaque, int version_id) 1240 { 1241 return !pvscsi_vmstate_need_pcie_device(opaque); 1242 } 1243 1244 static const VMStateDescription vmstate_pvscsi_pcie_device = { 1245 .name = "pvscsi/pcie", 1246 .needed = pvscsi_vmstate_need_pcie_device, 1247 .fields = (VMStateField[]) { 1248 VMSTATE_PCI_DEVICE(parent_obj, PVSCSIState), 1249 VMSTATE_END_OF_LIST() 1250 } 1251 }; 1252 1253 static const VMStateDescription vmstate_pvscsi = { 1254 .name = "pvscsi", 1255 .version_id = 0, 1256 .minimum_version_id = 0, 1257 .pre_save = pvscsi_pre_save, 1258 .post_load = pvscsi_post_load, 1259 .fields = (VMStateField[]) { 1260 VMSTATE_STRUCT_TEST(parent_obj, PVSCSIState, 1261 pvscsi_vmstate_test_pci_device, 0, 1262 vmstate_pci_device, PCIDevice), 1263 VMSTATE_UINT8(msi_used, PVSCSIState), 1264 VMSTATE_UINT32(resetting, PVSCSIState), 1265 VMSTATE_UINT64(reg_interrupt_status, PVSCSIState), 1266 VMSTATE_UINT64(reg_interrupt_enabled, PVSCSIState), 1267 VMSTATE_UINT64(reg_command_status, PVSCSIState), 1268 VMSTATE_UINT64(curr_cmd, PVSCSIState), 1269 VMSTATE_UINT32(curr_cmd_data_cntr, PVSCSIState), 1270 VMSTATE_UINT32_ARRAY(curr_cmd_data, PVSCSIState, 1271 ARRAY_SIZE(((PVSCSIState *)NULL)->curr_cmd_data)), 1272 VMSTATE_UINT8(rings_info_valid, PVSCSIState), 1273 VMSTATE_UINT8(msg_ring_info_valid, PVSCSIState), 1274 VMSTATE_UINT8(use_msg, PVSCSIState), 1275 1276 VMSTATE_UINT64(rings.rs_pa, PVSCSIState), 1277 VMSTATE_UINT32(rings.txr_len_mask, PVSCSIState), 1278 VMSTATE_UINT32(rings.rxr_len_mask, PVSCSIState), 1279 VMSTATE_UINT64_ARRAY(rings.req_ring_pages_pa, PVSCSIState, 1280 PVSCSI_SETUP_RINGS_MAX_NUM_PAGES), 1281 VMSTATE_UINT64_ARRAY(rings.cmp_ring_pages_pa, PVSCSIState, 1282 PVSCSI_SETUP_RINGS_MAX_NUM_PAGES), 1283 VMSTATE_UINT64(rings.consumed_ptr, PVSCSIState), 1284 VMSTATE_UINT64(rings.filled_cmp_ptr, PVSCSIState), 1285 1286 VMSTATE_END_OF_LIST() 1287 }, 1288 .subsections = (const VMStateDescription*[]) { 1289 &vmstate_pvscsi_pcie_device, 1290 NULL 1291 } 1292 }; 1293 1294 static Property pvscsi_properties[] = { 1295 DEFINE_PROP_UINT8("use_msg", PVSCSIState, use_msg, 1), 1296 DEFINE_PROP_BIT("x-old-pci-configuration", PVSCSIState, compat_flags, 1297 PVSCSI_COMPAT_OLD_PCI_CONFIGURATION_BIT, false), 1298 DEFINE_PROP_BIT("x-disable-pcie", PVSCSIState, compat_flags, 1299 PVSCSI_COMPAT_DISABLE_PCIE_BIT, false), 1300 DEFINE_PROP_END_OF_LIST(), 1301 }; 1302 1303 static void pvscsi_realize(DeviceState *qdev, Error **errp) 1304 { 1305 PVSCSIClass *pvs_c = PVSCSI_GET_CLASS(qdev); 1306 PCIDevice *pci_dev = PCI_DEVICE(qdev); 1307 PVSCSIState *s = PVSCSI(qdev); 1308 1309 if (!(s->compat_flags & PVSCSI_COMPAT_DISABLE_PCIE)) { 1310 pci_dev->cap_present |= QEMU_PCI_CAP_EXPRESS; 1311 } 1312 1313 pvs_c->parent_dc_realize(qdev, errp); 1314 } 1315 1316 static void pvscsi_class_init(ObjectClass *klass, void *data) 1317 { 1318 DeviceClass *dc = DEVICE_CLASS(klass); 1319 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); 1320 PVSCSIClass *pvs_k = PVSCSI_CLASS(klass); 1321 HotplugHandlerClass *hc = HOTPLUG_HANDLER_CLASS(klass); 1322 1323 k->realize = pvscsi_realizefn; 1324 k->exit = pvscsi_uninit; 1325 k->vendor_id = PCI_VENDOR_ID_VMWARE; 1326 k->device_id = PCI_DEVICE_ID_VMWARE_PVSCSI; 1327 k->class_id = PCI_CLASS_STORAGE_SCSI; 1328 k->subsystem_id = 0x1000; 1329 device_class_set_parent_realize(dc, pvscsi_realize, 1330 &pvs_k->parent_dc_realize); 1331 dc->reset = pvscsi_reset; 1332 dc->vmsd = &vmstate_pvscsi; 1333 device_class_set_props(dc, pvscsi_properties); 1334 set_bit(DEVICE_CATEGORY_STORAGE, dc->categories); 1335 hc->unplug = pvscsi_hot_unplug; 1336 hc->plug = pvscsi_hotplug; 1337 } 1338 1339 static const TypeInfo pvscsi_info = { 1340 .name = TYPE_PVSCSI, 1341 .parent = TYPE_PCI_DEVICE, 1342 .class_size = sizeof(PVSCSIClass), 1343 .instance_size = sizeof(PVSCSIState), 1344 .class_init = pvscsi_class_init, 1345 .interfaces = (InterfaceInfo[]) { 1346 { TYPE_HOTPLUG_HANDLER }, 1347 { INTERFACE_PCIE_DEVICE }, 1348 { INTERFACE_CONVENTIONAL_PCI_DEVICE }, 1349 { } 1350 } 1351 }; 1352 1353 static void 1354 pvscsi_register_types(void) 1355 { 1356 type_register_static(&pvscsi_info); 1357 } 1358 1359 type_init(pvscsi_register_types); 1360