1*e351b826SPaolo Bonzini #ifndef MPTSAS_H 2*e351b826SPaolo Bonzini #define MPTSAS_H 3*e351b826SPaolo Bonzini 4*e351b826SPaolo Bonzini #include "mpi.h" 5*e351b826SPaolo Bonzini 6*e351b826SPaolo Bonzini #define MPTSAS_NUM_PORTS 8 7*e351b826SPaolo Bonzini #define MPTSAS_MAX_FRAMES 2048 /* Firmware limit at 65535 */ 8*e351b826SPaolo Bonzini 9*e351b826SPaolo Bonzini #define MPTSAS_REQUEST_QUEUE_DEPTH 128 10*e351b826SPaolo Bonzini #define MPTSAS_REPLY_QUEUE_DEPTH 128 11*e351b826SPaolo Bonzini 12*e351b826SPaolo Bonzini #define MPTSAS_MAXIMUM_CHAIN_DEPTH 0x22 13*e351b826SPaolo Bonzini 14*e351b826SPaolo Bonzini typedef struct MPTSASState MPTSASState; 15*e351b826SPaolo Bonzini typedef struct MPTSASRequest MPTSASRequest; 16*e351b826SPaolo Bonzini 17*e351b826SPaolo Bonzini enum { 18*e351b826SPaolo Bonzini DOORBELL_NONE, 19*e351b826SPaolo Bonzini DOORBELL_WRITE, 20*e351b826SPaolo Bonzini DOORBELL_READ 21*e351b826SPaolo Bonzini }; 22*e351b826SPaolo Bonzini 23*e351b826SPaolo Bonzini struct MPTSASState { 24*e351b826SPaolo Bonzini PCIDevice dev; 25*e351b826SPaolo Bonzini MemoryRegion mmio_io; 26*e351b826SPaolo Bonzini MemoryRegion port_io; 27*e351b826SPaolo Bonzini MemoryRegion diag_io; 28*e351b826SPaolo Bonzini QEMUBH *request_bh; 29*e351b826SPaolo Bonzini 30*e351b826SPaolo Bonzini uint32_t msi_available; 31*e351b826SPaolo Bonzini uint64_t sas_addr; 32*e351b826SPaolo Bonzini 33*e351b826SPaolo Bonzini bool msi_in_use; 34*e351b826SPaolo Bonzini 35*e351b826SPaolo Bonzini /* Doorbell register */ 36*e351b826SPaolo Bonzini uint32_t state; 37*e351b826SPaolo Bonzini uint8_t who_init; 38*e351b826SPaolo Bonzini uint8_t doorbell_state; 39*e351b826SPaolo Bonzini 40*e351b826SPaolo Bonzini /* Buffer for requests that are sent through the doorbell register. */ 41*e351b826SPaolo Bonzini uint32_t doorbell_msg[256]; 42*e351b826SPaolo Bonzini int doorbell_idx; 43*e351b826SPaolo Bonzini int doorbell_cnt; 44*e351b826SPaolo Bonzini 45*e351b826SPaolo Bonzini uint16_t doorbell_reply[256]; 46*e351b826SPaolo Bonzini int doorbell_reply_idx; 47*e351b826SPaolo Bonzini int doorbell_reply_size; 48*e351b826SPaolo Bonzini 49*e351b826SPaolo Bonzini /* Other registers */ 50*e351b826SPaolo Bonzini uint8_t diagnostic_idx; 51*e351b826SPaolo Bonzini uint32_t diagnostic; 52*e351b826SPaolo Bonzini uint32_t intr_mask; 53*e351b826SPaolo Bonzini uint32_t intr_status; 54*e351b826SPaolo Bonzini 55*e351b826SPaolo Bonzini /* Request queues */ 56*e351b826SPaolo Bonzini uint32_t request_post[MPTSAS_REQUEST_QUEUE_DEPTH + 1]; 57*e351b826SPaolo Bonzini uint16_t request_post_head; 58*e351b826SPaolo Bonzini uint16_t request_post_tail; 59*e351b826SPaolo Bonzini 60*e351b826SPaolo Bonzini uint32_t reply_post[MPTSAS_REPLY_QUEUE_DEPTH + 1]; 61*e351b826SPaolo Bonzini uint16_t reply_post_head; 62*e351b826SPaolo Bonzini uint16_t reply_post_tail; 63*e351b826SPaolo Bonzini 64*e351b826SPaolo Bonzini uint32_t reply_free[MPTSAS_REPLY_QUEUE_DEPTH + 1]; 65*e351b826SPaolo Bonzini uint16_t reply_free_head; 66*e351b826SPaolo Bonzini uint16_t reply_free_tail; 67*e351b826SPaolo Bonzini 68*e351b826SPaolo Bonzini /* IOC Facts */ 69*e351b826SPaolo Bonzini hwaddr host_mfa_high_addr; 70*e351b826SPaolo Bonzini hwaddr sense_buffer_high_addr; 71*e351b826SPaolo Bonzini uint16_t max_devices; 72*e351b826SPaolo Bonzini uint16_t max_buses; 73*e351b826SPaolo Bonzini uint16_t reply_frame_size; 74*e351b826SPaolo Bonzini 75*e351b826SPaolo Bonzini SCSIBus bus; 76*e351b826SPaolo Bonzini QTAILQ_HEAD(, MPTSASRequest) pending; 77*e351b826SPaolo Bonzini }; 78*e351b826SPaolo Bonzini 79*e351b826SPaolo Bonzini void mptsas_fix_scsi_io_endianness(MPIMsgSCSIIORequest *req); 80*e351b826SPaolo Bonzini void mptsas_fix_scsi_io_reply_endianness(MPIMsgSCSIIOReply *reply); 81*e351b826SPaolo Bonzini void mptsas_fix_scsi_task_mgmt_endianness(MPIMsgSCSITaskMgmt *req); 82*e351b826SPaolo Bonzini void mptsas_fix_scsi_task_mgmt_reply_endianness(MPIMsgSCSITaskMgmtReply *reply); 83*e351b826SPaolo Bonzini void mptsas_fix_ioc_init_endianness(MPIMsgIOCInit *req); 84*e351b826SPaolo Bonzini void mptsas_fix_ioc_init_reply_endianness(MPIMsgIOCInitReply *reply); 85*e351b826SPaolo Bonzini void mptsas_fix_ioc_facts_endianness(MPIMsgIOCFacts *req); 86*e351b826SPaolo Bonzini void mptsas_fix_ioc_facts_reply_endianness(MPIMsgIOCFactsReply *reply); 87*e351b826SPaolo Bonzini void mptsas_fix_config_endianness(MPIMsgConfig *req); 88*e351b826SPaolo Bonzini void mptsas_fix_config_reply_endianness(MPIMsgConfigReply *reply); 89*e351b826SPaolo Bonzini void mptsas_fix_port_facts_endianness(MPIMsgPortFacts *req); 90*e351b826SPaolo Bonzini void mptsas_fix_port_facts_reply_endianness(MPIMsgPortFactsReply *reply); 91*e351b826SPaolo Bonzini void mptsas_fix_port_enable_endianness(MPIMsgPortEnable *req); 92*e351b826SPaolo Bonzini void mptsas_fix_port_enable_reply_endianness(MPIMsgPortEnableReply *reply); 93*e351b826SPaolo Bonzini void mptsas_fix_event_notification_endianness(MPIMsgEventNotify *req); 94*e351b826SPaolo Bonzini void mptsas_fix_event_notification_reply_endianness(MPIMsgEventNotifyReply *reply); 95*e351b826SPaolo Bonzini 96*e351b826SPaolo Bonzini void mptsas_reply(MPTSASState *s, MPIDefaultReply *reply); 97*e351b826SPaolo Bonzini 98*e351b826SPaolo Bonzini void mptsas_process_config(MPTSASState *s, MPIMsgConfig *req); 99*e351b826SPaolo Bonzini 100*e351b826SPaolo Bonzini #endif /* MPTSAS_H */ 101