1e351b826SPaolo Bonzini #ifndef MPTSAS_H 2e351b826SPaolo Bonzini #define MPTSAS_H 3e351b826SPaolo Bonzini 4e351b826SPaolo Bonzini #include "mpi.h" 5e351b826SPaolo Bonzini 6e351b826SPaolo Bonzini #define MPTSAS_NUM_PORTS 8 7e351b826SPaolo Bonzini #define MPTSAS_MAX_FRAMES 2048 /* Firmware limit at 65535 */ 8e351b826SPaolo Bonzini 9e351b826SPaolo Bonzini #define MPTSAS_REQUEST_QUEUE_DEPTH 128 10e351b826SPaolo Bonzini #define MPTSAS_REPLY_QUEUE_DEPTH 128 11e351b826SPaolo Bonzini 12e351b826SPaolo Bonzini #define MPTSAS_MAXIMUM_CHAIN_DEPTH 0x22 13e351b826SPaolo Bonzini 14e351b826SPaolo Bonzini typedef struct MPTSASState MPTSASState; 15e351b826SPaolo Bonzini typedef struct MPTSASRequest MPTSASRequest; 16e351b826SPaolo Bonzini 17e351b826SPaolo Bonzini enum { 18e351b826SPaolo Bonzini DOORBELL_NONE, 19e351b826SPaolo Bonzini DOORBELL_WRITE, 20e351b826SPaolo Bonzini DOORBELL_READ 21e351b826SPaolo Bonzini }; 22e351b826SPaolo Bonzini 23e351b826SPaolo Bonzini struct MPTSASState { 24e351b826SPaolo Bonzini PCIDevice dev; 25e351b826SPaolo Bonzini MemoryRegion mmio_io; 26e351b826SPaolo Bonzini MemoryRegion port_io; 27e351b826SPaolo Bonzini MemoryRegion diag_io; 28e351b826SPaolo Bonzini QEMUBH *request_bh; 29e351b826SPaolo Bonzini 30*444dd1afSCao jin /* properties */ 31*444dd1afSCao jin OnOffAuto msi; 32e351b826SPaolo Bonzini uint64_t sas_addr; 33e351b826SPaolo Bonzini 34e351b826SPaolo Bonzini bool msi_in_use; 35e351b826SPaolo Bonzini 36e351b826SPaolo Bonzini /* Doorbell register */ 37e351b826SPaolo Bonzini uint32_t state; 38e351b826SPaolo Bonzini uint8_t who_init; 39e351b826SPaolo Bonzini uint8_t doorbell_state; 40e351b826SPaolo Bonzini 41e351b826SPaolo Bonzini /* Buffer for requests that are sent through the doorbell register. */ 42e351b826SPaolo Bonzini uint32_t doorbell_msg[256]; 43e351b826SPaolo Bonzini int doorbell_idx; 44e351b826SPaolo Bonzini int doorbell_cnt; 45e351b826SPaolo Bonzini 46e351b826SPaolo Bonzini uint16_t doorbell_reply[256]; 47e351b826SPaolo Bonzini int doorbell_reply_idx; 48e351b826SPaolo Bonzini int doorbell_reply_size; 49e351b826SPaolo Bonzini 50e351b826SPaolo Bonzini /* Other registers */ 51e351b826SPaolo Bonzini uint8_t diagnostic_idx; 52e351b826SPaolo Bonzini uint32_t diagnostic; 53e351b826SPaolo Bonzini uint32_t intr_mask; 54e351b826SPaolo Bonzini uint32_t intr_status; 55e351b826SPaolo Bonzini 56e351b826SPaolo Bonzini /* Request queues */ 57e351b826SPaolo Bonzini uint32_t request_post[MPTSAS_REQUEST_QUEUE_DEPTH + 1]; 58e351b826SPaolo Bonzini uint16_t request_post_head; 59e351b826SPaolo Bonzini uint16_t request_post_tail; 60e351b826SPaolo Bonzini 61e351b826SPaolo Bonzini uint32_t reply_post[MPTSAS_REPLY_QUEUE_DEPTH + 1]; 62e351b826SPaolo Bonzini uint16_t reply_post_head; 63e351b826SPaolo Bonzini uint16_t reply_post_tail; 64e351b826SPaolo Bonzini 65e351b826SPaolo Bonzini uint32_t reply_free[MPTSAS_REPLY_QUEUE_DEPTH + 1]; 66e351b826SPaolo Bonzini uint16_t reply_free_head; 67e351b826SPaolo Bonzini uint16_t reply_free_tail; 68e351b826SPaolo Bonzini 69e351b826SPaolo Bonzini /* IOC Facts */ 70e351b826SPaolo Bonzini hwaddr host_mfa_high_addr; 71e351b826SPaolo Bonzini hwaddr sense_buffer_high_addr; 72e351b826SPaolo Bonzini uint16_t max_devices; 73e351b826SPaolo Bonzini uint16_t max_buses; 74e351b826SPaolo Bonzini uint16_t reply_frame_size; 75e351b826SPaolo Bonzini 76e351b826SPaolo Bonzini SCSIBus bus; 77e351b826SPaolo Bonzini QTAILQ_HEAD(, MPTSASRequest) pending; 78e351b826SPaolo Bonzini }; 79e351b826SPaolo Bonzini 80e351b826SPaolo Bonzini void mptsas_fix_scsi_io_endianness(MPIMsgSCSIIORequest *req); 81e351b826SPaolo Bonzini void mptsas_fix_scsi_io_reply_endianness(MPIMsgSCSIIOReply *reply); 82e351b826SPaolo Bonzini void mptsas_fix_scsi_task_mgmt_endianness(MPIMsgSCSITaskMgmt *req); 83e351b826SPaolo Bonzini void mptsas_fix_scsi_task_mgmt_reply_endianness(MPIMsgSCSITaskMgmtReply *reply); 84e351b826SPaolo Bonzini void mptsas_fix_ioc_init_endianness(MPIMsgIOCInit *req); 85e351b826SPaolo Bonzini void mptsas_fix_ioc_init_reply_endianness(MPIMsgIOCInitReply *reply); 86e351b826SPaolo Bonzini void mptsas_fix_ioc_facts_endianness(MPIMsgIOCFacts *req); 87e351b826SPaolo Bonzini void mptsas_fix_ioc_facts_reply_endianness(MPIMsgIOCFactsReply *reply); 88e351b826SPaolo Bonzini void mptsas_fix_config_endianness(MPIMsgConfig *req); 89e351b826SPaolo Bonzini void mptsas_fix_config_reply_endianness(MPIMsgConfigReply *reply); 90e351b826SPaolo Bonzini void mptsas_fix_port_facts_endianness(MPIMsgPortFacts *req); 91e351b826SPaolo Bonzini void mptsas_fix_port_facts_reply_endianness(MPIMsgPortFactsReply *reply); 92e351b826SPaolo Bonzini void mptsas_fix_port_enable_endianness(MPIMsgPortEnable *req); 93e351b826SPaolo Bonzini void mptsas_fix_port_enable_reply_endianness(MPIMsgPortEnableReply *reply); 94e351b826SPaolo Bonzini void mptsas_fix_event_notification_endianness(MPIMsgEventNotify *req); 95e351b826SPaolo Bonzini void mptsas_fix_event_notification_reply_endianness(MPIMsgEventNotifyReply *reply); 96e351b826SPaolo Bonzini 97e351b826SPaolo Bonzini void mptsas_reply(MPTSASState *s, MPIDefaultReply *reply); 98e351b826SPaolo Bonzini 99e351b826SPaolo Bonzini void mptsas_process_config(MPTSASState *s, MPIMsgConfig *req); 100e351b826SPaolo Bonzini 101e351b826SPaolo Bonzini #endif /* MPTSAS_H */ 102