1 /* 2 * QEMU ESP/NCR53C9x emulation 3 * 4 * Copyright (c) 2005-2006 Fabrice Bellard 5 * Copyright (c) 2012 Herve Poussineau 6 * 7 * Permission is hereby granted, free of charge, to any person obtaining a copy 8 * of this software and associated documentation files (the "Software"), to deal 9 * in the Software without restriction, including without limitation the rights 10 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 11 * copies of the Software, and to permit persons to whom the Software is 12 * furnished to do so, subject to the following conditions: 13 * 14 * The above copyright notice and this permission notice shall be included in 15 * all copies or substantial portions of the Software. 16 * 17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 22 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 23 * THE SOFTWARE. 24 */ 25 26 #include "qemu/osdep.h" 27 #include "hw/sysbus.h" 28 #include "migration/vmstate.h" 29 #include "hw/irq.h" 30 #include "hw/scsi/esp.h" 31 #include "trace.h" 32 #include "qemu/log.h" 33 #include "qemu/module.h" 34 35 /* 36 * On Sparc32, this is the ESP (NCR53C90) part of chip STP2000 (Master I/O), 37 * also produced as NCR89C100. See 38 * http://www.ibiblio.org/pub/historic-linux/early-ports/Sparc/NCR/NCR89C100.txt 39 * and 40 * http://www.ibiblio.org/pub/historic-linux/early-ports/Sparc/NCR/NCR53C9X.txt 41 * 42 * On Macintosh Quadra it is a NCR53C96. 43 */ 44 45 static void esp_raise_irq(ESPState *s) 46 { 47 if (!(s->rregs[ESP_RSTAT] & STAT_INT)) { 48 s->rregs[ESP_RSTAT] |= STAT_INT; 49 qemu_irq_raise(s->irq); 50 trace_esp_raise_irq(); 51 } 52 } 53 54 static void esp_lower_irq(ESPState *s) 55 { 56 if (s->rregs[ESP_RSTAT] & STAT_INT) { 57 s->rregs[ESP_RSTAT] &= ~STAT_INT; 58 qemu_irq_lower(s->irq); 59 trace_esp_lower_irq(); 60 } 61 } 62 63 static void esp_raise_drq(ESPState *s) 64 { 65 qemu_irq_raise(s->irq_data); 66 trace_esp_raise_drq(); 67 } 68 69 static void esp_lower_drq(ESPState *s) 70 { 71 qemu_irq_lower(s->irq_data); 72 trace_esp_lower_drq(); 73 } 74 75 void esp_dma_enable(ESPState *s, int irq, int level) 76 { 77 if (level) { 78 s->dma_enabled = 1; 79 trace_esp_dma_enable(); 80 if (s->dma_cb) { 81 s->dma_cb(s); 82 s->dma_cb = NULL; 83 } 84 } else { 85 trace_esp_dma_disable(); 86 s->dma_enabled = 0; 87 } 88 } 89 90 void esp_request_cancelled(SCSIRequest *req) 91 { 92 ESPState *s = req->hba_private; 93 94 if (req == s->current_req) { 95 scsi_req_unref(s->current_req); 96 s->current_req = NULL; 97 s->current_dev = NULL; 98 } 99 } 100 101 static void esp_fifo_push(Fifo8 *fifo, uint8_t val) 102 { 103 if (fifo8_num_used(fifo) == fifo->capacity) { 104 trace_esp_error_fifo_overrun(); 105 return; 106 } 107 108 fifo8_push(fifo, val); 109 } 110 111 static uint8_t esp_fifo_pop(Fifo8 *fifo) 112 { 113 if (fifo8_is_empty(fifo)) { 114 return 0; 115 } 116 117 return fifo8_pop(fifo); 118 } 119 120 static uint32_t esp_fifo_pop_buf(Fifo8 *fifo, uint8_t *dest, int maxlen) 121 { 122 const uint8_t *buf; 123 uint32_t n; 124 125 if (maxlen == 0) { 126 return 0; 127 } 128 129 buf = fifo8_pop_buf(fifo, maxlen, &n); 130 if (dest) { 131 memcpy(dest, buf, n); 132 } 133 134 return n; 135 } 136 137 static uint32_t esp_get_tc(ESPState *s) 138 { 139 uint32_t dmalen; 140 141 dmalen = s->rregs[ESP_TCLO]; 142 dmalen |= s->rregs[ESP_TCMID] << 8; 143 dmalen |= s->rregs[ESP_TCHI] << 16; 144 145 return dmalen; 146 } 147 148 static void esp_set_tc(ESPState *s, uint32_t dmalen) 149 { 150 s->rregs[ESP_TCLO] = dmalen; 151 s->rregs[ESP_TCMID] = dmalen >> 8; 152 s->rregs[ESP_TCHI] = dmalen >> 16; 153 } 154 155 static uint32_t esp_get_stc(ESPState *s) 156 { 157 uint32_t dmalen; 158 159 dmalen = s->wregs[ESP_TCLO]; 160 dmalen |= s->wregs[ESP_TCMID] << 8; 161 dmalen |= s->wregs[ESP_TCHI] << 16; 162 163 return dmalen; 164 } 165 166 static uint8_t esp_pdma_read(ESPState *s) 167 { 168 uint8_t val; 169 170 if (s->do_cmd) { 171 val = esp_fifo_pop(&s->cmdfifo); 172 } else { 173 val = esp_fifo_pop(&s->fifo); 174 } 175 176 return val; 177 } 178 179 static void esp_pdma_write(ESPState *s, uint8_t val) 180 { 181 uint32_t dmalen = esp_get_tc(s); 182 183 if (dmalen == 0) { 184 return; 185 } 186 187 if (s->do_cmd) { 188 esp_fifo_push(&s->cmdfifo, val); 189 } else { 190 esp_fifo_push(&s->fifo, val); 191 } 192 193 dmalen--; 194 esp_set_tc(s, dmalen); 195 } 196 197 static int esp_select(ESPState *s) 198 { 199 int target; 200 201 target = s->wregs[ESP_WBUSID] & BUSID_DID; 202 203 s->ti_size = 0; 204 fifo8_reset(&s->fifo); 205 206 if (s->current_req) { 207 /* Started a new command before the old one finished. Cancel it. */ 208 scsi_req_cancel(s->current_req); 209 s->async_len = 0; 210 } 211 212 s->current_dev = scsi_device_find(&s->bus, 0, target, 0); 213 if (!s->current_dev) { 214 /* No such drive */ 215 s->rregs[ESP_RSTAT] = 0; 216 s->rregs[ESP_RINTR] |= INTR_DC; 217 s->rregs[ESP_RSEQ] = SEQ_0; 218 esp_raise_irq(s); 219 return -1; 220 } 221 222 /* 223 * Note that we deliberately don't raise the IRQ here: this will be done 224 * either in do_busid_cmd() for DATA OUT transfers or by the deferred 225 * IRQ mechanism in esp_transfer_data() for DATA IN transfers 226 */ 227 s->rregs[ESP_RINTR] |= INTR_FC; 228 s->rregs[ESP_RSEQ] = SEQ_CD; 229 return 0; 230 } 231 232 static uint32_t get_cmd(ESPState *s, uint32_t maxlen) 233 { 234 uint8_t buf[ESP_CMDFIFO_SZ]; 235 uint32_t dmalen, n; 236 int target; 237 238 target = s->wregs[ESP_WBUSID] & BUSID_DID; 239 if (s->dma) { 240 dmalen = MIN(esp_get_tc(s), maxlen); 241 if (dmalen == 0) { 242 return 0; 243 } 244 if (s->dma_memory_read) { 245 s->dma_memory_read(s->dma_opaque, buf, dmalen); 246 dmalen = MIN(fifo8_num_free(&s->cmdfifo), dmalen); 247 fifo8_push_all(&s->cmdfifo, buf, dmalen); 248 } else { 249 if (esp_select(s) < 0) { 250 fifo8_reset(&s->cmdfifo); 251 return -1; 252 } 253 esp_raise_drq(s); 254 fifo8_reset(&s->cmdfifo); 255 return 0; 256 } 257 } else { 258 dmalen = MIN(fifo8_num_used(&s->fifo), maxlen); 259 if (dmalen == 0) { 260 return 0; 261 } 262 n = esp_fifo_pop_buf(&s->fifo, buf, dmalen); 263 if (n >= 3) { 264 buf[0] = buf[2] >> 5; 265 } 266 n = MIN(fifo8_num_free(&s->cmdfifo), n); 267 fifo8_push_all(&s->cmdfifo, buf, n); 268 } 269 trace_esp_get_cmd(dmalen, target); 270 271 if (esp_select(s) < 0) { 272 fifo8_reset(&s->cmdfifo); 273 return -1; 274 } 275 return dmalen; 276 } 277 278 static void do_busid_cmd(ESPState *s, uint8_t busid) 279 { 280 uint32_t cmdlen; 281 int32_t datalen; 282 int lun; 283 SCSIDevice *current_lun; 284 uint8_t buf[ESP_CMDFIFO_SZ]; 285 286 trace_esp_do_busid_cmd(busid); 287 lun = busid & 7; 288 cmdlen = fifo8_num_used(&s->cmdfifo); 289 if (!cmdlen || !s->current_dev) { 290 return; 291 } 292 esp_fifo_pop_buf(&s->cmdfifo, buf, cmdlen); 293 294 current_lun = scsi_device_find(&s->bus, 0, s->current_dev->id, lun); 295 s->current_req = scsi_req_new(current_lun, 0, lun, buf, s); 296 datalen = scsi_req_enqueue(s->current_req); 297 s->ti_size = datalen; 298 fifo8_reset(&s->cmdfifo); 299 if (datalen != 0) { 300 s->rregs[ESP_RSTAT] = STAT_TC; 301 s->rregs[ESP_RSEQ] = SEQ_CD; 302 s->ti_cmd = 0; 303 esp_set_tc(s, 0); 304 if (datalen > 0) { 305 /* 306 * Switch to DATA IN phase but wait until initial data xfer is 307 * complete before raising the command completion interrupt 308 */ 309 s->data_in_ready = false; 310 s->rregs[ESP_RSTAT] |= STAT_DI; 311 } else { 312 s->rregs[ESP_RSTAT] |= STAT_DO; 313 s->rregs[ESP_RINTR] |= INTR_BS | INTR_FC; 314 esp_raise_irq(s); 315 esp_lower_drq(s); 316 } 317 scsi_req_continue(s->current_req); 318 return; 319 } 320 } 321 322 static void do_cmd(ESPState *s) 323 { 324 uint8_t busid = esp_fifo_pop(&s->cmdfifo); 325 int len; 326 327 s->cmdfifo_cdb_offset--; 328 329 /* Ignore extended messages for now */ 330 if (s->cmdfifo_cdb_offset) { 331 len = MIN(s->cmdfifo_cdb_offset, fifo8_num_used(&s->cmdfifo)); 332 esp_fifo_pop_buf(&s->cmdfifo, NULL, len); 333 s->cmdfifo_cdb_offset = 0; 334 } 335 336 do_busid_cmd(s, busid); 337 } 338 339 static void satn_pdma_cb(ESPState *s) 340 { 341 s->do_cmd = 0; 342 if (!fifo8_is_empty(&s->cmdfifo)) { 343 s->cmdfifo_cdb_offset = 1; 344 do_cmd(s); 345 } 346 } 347 348 static void handle_satn(ESPState *s) 349 { 350 int32_t cmdlen; 351 352 if (s->dma && !s->dma_enabled) { 353 s->dma_cb = handle_satn; 354 return; 355 } 356 s->pdma_cb = satn_pdma_cb; 357 cmdlen = get_cmd(s, ESP_CMDFIFO_SZ); 358 if (cmdlen > 0) { 359 s->cmdfifo_cdb_offset = 1; 360 do_cmd(s); 361 } else if (cmdlen == 0) { 362 s->do_cmd = 1; 363 /* Target present, but no cmd yet - switch to command phase */ 364 s->rregs[ESP_RSEQ] = SEQ_CD; 365 s->rregs[ESP_RSTAT] = STAT_CD; 366 } 367 } 368 369 static void s_without_satn_pdma_cb(ESPState *s) 370 { 371 uint32_t len; 372 373 s->do_cmd = 0; 374 len = fifo8_num_used(&s->cmdfifo); 375 if (len) { 376 s->cmdfifo_cdb_offset = 0; 377 do_busid_cmd(s, 0); 378 } 379 } 380 381 static void handle_s_without_atn(ESPState *s) 382 { 383 int32_t cmdlen; 384 385 if (s->dma && !s->dma_enabled) { 386 s->dma_cb = handle_s_without_atn; 387 return; 388 } 389 s->pdma_cb = s_without_satn_pdma_cb; 390 cmdlen = get_cmd(s, ESP_CMDFIFO_SZ); 391 if (cmdlen > 0) { 392 s->cmdfifo_cdb_offset = 0; 393 do_busid_cmd(s, 0); 394 } else if (cmdlen == 0) { 395 s->do_cmd = 1; 396 /* Target present, but no cmd yet - switch to command phase */ 397 s->rregs[ESP_RSEQ] = SEQ_CD; 398 s->rregs[ESP_RSTAT] = STAT_CD; 399 } 400 } 401 402 static void satn_stop_pdma_cb(ESPState *s) 403 { 404 s->do_cmd = 0; 405 if (!fifo8_is_empty(&s->cmdfifo)) { 406 trace_esp_handle_satn_stop(fifo8_num_used(&s->cmdfifo)); 407 s->do_cmd = 1; 408 s->cmdfifo_cdb_offset = 1; 409 s->rregs[ESP_RSTAT] = STAT_TC | STAT_CD; 410 s->rregs[ESP_RINTR] |= INTR_BS | INTR_FC; 411 s->rregs[ESP_RSEQ] = SEQ_CD; 412 esp_raise_irq(s); 413 } 414 } 415 416 static void handle_satn_stop(ESPState *s) 417 { 418 int32_t cmdlen; 419 420 if (s->dma && !s->dma_enabled) { 421 s->dma_cb = handle_satn_stop; 422 return; 423 } 424 s->pdma_cb = satn_stop_pdma_cb; 425 cmdlen = get_cmd(s, 1); 426 if (cmdlen > 0) { 427 trace_esp_handle_satn_stop(fifo8_num_used(&s->cmdfifo)); 428 s->do_cmd = 1; 429 s->cmdfifo_cdb_offset = 1; 430 s->rregs[ESP_RSTAT] = STAT_MO; 431 s->rregs[ESP_RINTR] |= INTR_BS | INTR_FC; 432 s->rregs[ESP_RSEQ] = SEQ_MO; 433 esp_raise_irq(s); 434 } else if (cmdlen == 0) { 435 s->do_cmd = 1; 436 /* Target present, switch to message out phase */ 437 s->rregs[ESP_RSEQ] = SEQ_MO; 438 s->rregs[ESP_RSTAT] = STAT_MO; 439 } 440 } 441 442 static void write_response_pdma_cb(ESPState *s) 443 { 444 s->rregs[ESP_RSTAT] = STAT_TC | STAT_ST; 445 s->rregs[ESP_RINTR] |= INTR_BS | INTR_FC; 446 s->rregs[ESP_RSEQ] = SEQ_CD; 447 esp_raise_irq(s); 448 } 449 450 static void write_response(ESPState *s) 451 { 452 uint8_t buf[2]; 453 454 trace_esp_write_response(s->status); 455 456 buf[0] = s->status; 457 buf[1] = 0; 458 459 if (s->dma) { 460 if (s->dma_memory_write) { 461 s->dma_memory_write(s->dma_opaque, buf, 2); 462 s->rregs[ESP_RSTAT] = STAT_TC | STAT_ST; 463 s->rregs[ESP_RINTR] |= INTR_BS | INTR_FC; 464 s->rregs[ESP_RSEQ] = SEQ_CD; 465 } else { 466 s->pdma_cb = write_response_pdma_cb; 467 esp_raise_drq(s); 468 return; 469 } 470 } else { 471 fifo8_reset(&s->fifo); 472 fifo8_push_all(&s->fifo, buf, 2); 473 s->rregs[ESP_RFLAGS] = 2; 474 } 475 esp_raise_irq(s); 476 } 477 478 static void esp_dma_done(ESPState *s) 479 { 480 s->rregs[ESP_RSTAT] |= STAT_TC; 481 s->rregs[ESP_RINTR] |= INTR_BS; 482 s->rregs[ESP_RSEQ] = 0; 483 s->rregs[ESP_RFLAGS] = 0; 484 esp_set_tc(s, 0); 485 esp_raise_irq(s); 486 } 487 488 static void do_dma_pdma_cb(ESPState *s) 489 { 490 int to_device = ((s->rregs[ESP_RSTAT] & 7) == STAT_DO); 491 int len; 492 uint32_t n; 493 494 if (s->do_cmd) { 495 s->ti_size = 0; 496 s->do_cmd = 0; 497 do_cmd(s); 498 esp_lower_drq(s); 499 return; 500 } 501 502 if (!s->current_req) { 503 return; 504 } 505 506 if (to_device) { 507 /* Copy FIFO data to device */ 508 len = MIN(s->async_len, ESP_FIFO_SZ); 509 len = MIN(len, fifo8_num_used(&s->fifo)); 510 n = esp_fifo_pop_buf(&s->fifo, s->async_buf, len); 511 s->async_buf += n; 512 s->async_len -= n; 513 s->ti_size += n; 514 515 if (n < len) { 516 /* Unaligned accesses can cause FIFO wraparound */ 517 len = len - n; 518 n = esp_fifo_pop_buf(&s->fifo, s->async_buf, len); 519 s->async_buf += n; 520 s->async_len -= n; 521 s->ti_size += n; 522 } 523 524 if (s->async_len == 0) { 525 scsi_req_continue(s->current_req); 526 return; 527 } 528 529 if (esp_get_tc(s) == 0) { 530 esp_lower_drq(s); 531 esp_dma_done(s); 532 } 533 534 return; 535 } else { 536 if (s->async_len == 0) { 537 /* Defer until the scsi layer has completed */ 538 scsi_req_continue(s->current_req); 539 s->data_in_ready = false; 540 return; 541 } 542 543 if (esp_get_tc(s) != 0) { 544 /* Copy device data to FIFO */ 545 len = MIN(s->async_len, esp_get_tc(s)); 546 len = MIN(len, fifo8_num_free(&s->fifo)); 547 fifo8_push_all(&s->fifo, s->async_buf, len); 548 s->async_buf += len; 549 s->async_len -= len; 550 s->ti_size -= len; 551 esp_set_tc(s, esp_get_tc(s) - len); 552 553 if (esp_get_tc(s) == 0) { 554 /* Indicate transfer to FIFO is complete */ 555 s->rregs[ESP_RSTAT] |= STAT_TC; 556 } 557 return; 558 } 559 560 /* Partially filled a scsi buffer. Complete immediately. */ 561 esp_lower_drq(s); 562 esp_dma_done(s); 563 } 564 } 565 566 static void esp_do_dma(ESPState *s) 567 { 568 uint32_t len, cmdlen; 569 int to_device = ((s->rregs[ESP_RSTAT] & 7) == STAT_DO); 570 uint8_t buf[ESP_CMDFIFO_SZ]; 571 572 len = esp_get_tc(s); 573 if (s->do_cmd) { 574 /* 575 * handle_ti_cmd() case: esp_do_dma() is called only from 576 * handle_ti_cmd() with do_cmd != NULL (see the assert()) 577 */ 578 cmdlen = fifo8_num_used(&s->cmdfifo); 579 trace_esp_do_dma(cmdlen, len); 580 if (s->dma_memory_read) { 581 s->dma_memory_read(s->dma_opaque, buf, len); 582 fifo8_push_all(&s->cmdfifo, buf, len); 583 } else { 584 s->pdma_cb = do_dma_pdma_cb; 585 esp_raise_drq(s); 586 return; 587 } 588 trace_esp_handle_ti_cmd(cmdlen); 589 s->ti_size = 0; 590 if ((s->rregs[ESP_RSTAT] & 7) == STAT_CD) { 591 /* No command received */ 592 if (s->cmdfifo_cdb_offset == fifo8_num_used(&s->cmdfifo)) { 593 return; 594 } 595 596 /* Command has been received */ 597 s->do_cmd = 0; 598 do_cmd(s); 599 } else { 600 /* 601 * Extra message out bytes received: update cmdfifo_cdb_offset 602 * and then switch to commmand phase 603 */ 604 s->cmdfifo_cdb_offset = fifo8_num_used(&s->cmdfifo); 605 s->rregs[ESP_RSTAT] = STAT_TC | STAT_CD; 606 s->rregs[ESP_RSEQ] = SEQ_CD; 607 s->rregs[ESP_RINTR] |= INTR_BS; 608 esp_raise_irq(s); 609 } 610 return; 611 } 612 if (!s->current_req) { 613 return; 614 } 615 if (s->async_len == 0) { 616 /* Defer until data is available. */ 617 return; 618 } 619 if (len > s->async_len) { 620 len = s->async_len; 621 } 622 if (to_device) { 623 if (s->dma_memory_read) { 624 s->dma_memory_read(s->dma_opaque, s->async_buf, len); 625 } else { 626 s->pdma_cb = do_dma_pdma_cb; 627 esp_raise_drq(s); 628 return; 629 } 630 } else { 631 if (s->dma_memory_write) { 632 s->dma_memory_write(s->dma_opaque, s->async_buf, len); 633 } else { 634 /* Adjust TC for any leftover data in the FIFO */ 635 if (!fifo8_is_empty(&s->fifo)) { 636 esp_set_tc(s, esp_get_tc(s) - fifo8_num_used(&s->fifo)); 637 } 638 639 /* Copy device data to FIFO */ 640 len = MIN(len, fifo8_num_free(&s->fifo)); 641 fifo8_push_all(&s->fifo, s->async_buf, len); 642 s->async_buf += len; 643 s->async_len -= len; 644 s->ti_size -= len; 645 646 /* 647 * MacOS toolbox uses a TI length of 16 bytes for all commands, so 648 * commands shorter than this must be padded accordingly 649 */ 650 if (len < esp_get_tc(s) && esp_get_tc(s) <= ESP_FIFO_SZ) { 651 while (fifo8_num_used(&s->fifo) < ESP_FIFO_SZ) { 652 esp_fifo_push(&s->fifo, 0); 653 len++; 654 } 655 } 656 657 esp_set_tc(s, esp_get_tc(s) - len); 658 s->pdma_cb = do_dma_pdma_cb; 659 esp_raise_drq(s); 660 661 /* Indicate transfer to FIFO is complete */ 662 s->rregs[ESP_RSTAT] |= STAT_TC; 663 return; 664 } 665 } 666 esp_set_tc(s, esp_get_tc(s) - len); 667 s->async_buf += len; 668 s->async_len -= len; 669 if (to_device) { 670 s->ti_size += len; 671 } else { 672 s->ti_size -= len; 673 } 674 if (s->async_len == 0) { 675 scsi_req_continue(s->current_req); 676 /* 677 * If there is still data to be read from the device then 678 * complete the DMA operation immediately. Otherwise defer 679 * until the scsi layer has completed. 680 */ 681 if (to_device || esp_get_tc(s) != 0 || s->ti_size == 0) { 682 return; 683 } 684 } 685 686 /* Partially filled a scsi buffer. Complete immediately. */ 687 esp_dma_done(s); 688 esp_lower_drq(s); 689 } 690 691 static void esp_do_nodma(ESPState *s) 692 { 693 int to_device = ((s->rregs[ESP_RSTAT] & 7) == STAT_DO); 694 uint32_t cmdlen; 695 int len; 696 697 if (s->do_cmd) { 698 cmdlen = fifo8_num_used(&s->cmdfifo); 699 trace_esp_handle_ti_cmd(cmdlen); 700 s->ti_size = 0; 701 if ((s->rregs[ESP_RSTAT] & 7) == STAT_CD) { 702 /* No command received */ 703 if (s->cmdfifo_cdb_offset == fifo8_num_used(&s->cmdfifo)) { 704 return; 705 } 706 707 /* Command has been received */ 708 s->do_cmd = 0; 709 do_cmd(s); 710 } else { 711 /* 712 * Extra message out bytes received: update cmdfifo_cdb_offset 713 * and then switch to commmand phase 714 */ 715 s->cmdfifo_cdb_offset = fifo8_num_used(&s->cmdfifo); 716 s->rregs[ESP_RSTAT] = STAT_TC | STAT_CD; 717 s->rregs[ESP_RSEQ] = SEQ_CD; 718 s->rregs[ESP_RINTR] |= INTR_BS; 719 esp_raise_irq(s); 720 } 721 return; 722 } 723 724 if (!s->current_req) { 725 return; 726 } 727 728 if (s->async_len == 0) { 729 /* Defer until data is available. */ 730 return; 731 } 732 733 if (to_device) { 734 len = MIN(fifo8_num_used(&s->fifo), ESP_FIFO_SZ); 735 esp_fifo_pop_buf(&s->fifo, s->async_buf, len); 736 s->async_buf += len; 737 s->async_len -= len; 738 s->ti_size += len; 739 } else { 740 len = MIN(s->ti_size, s->async_len); 741 len = MIN(len, fifo8_num_free(&s->fifo)); 742 fifo8_push_all(&s->fifo, s->async_buf, len); 743 s->async_buf += len; 744 s->async_len -= len; 745 s->ti_size -= len; 746 } 747 748 if (s->async_len == 0) { 749 scsi_req_continue(s->current_req); 750 751 if (to_device || s->ti_size == 0) { 752 return; 753 } 754 } 755 756 s->rregs[ESP_RINTR] |= INTR_BS; 757 esp_raise_irq(s); 758 } 759 760 void esp_command_complete(SCSIRequest *req, size_t resid) 761 { 762 ESPState *s = req->hba_private; 763 764 trace_esp_command_complete(); 765 if (s->ti_size != 0) { 766 trace_esp_command_complete_unexpected(); 767 } 768 s->ti_size = 0; 769 s->async_len = 0; 770 if (req->status) { 771 trace_esp_command_complete_fail(); 772 } 773 s->status = req->status; 774 s->rregs[ESP_RSTAT] = STAT_ST; 775 esp_dma_done(s); 776 esp_lower_drq(s); 777 if (s->current_req) { 778 scsi_req_unref(s->current_req); 779 s->current_req = NULL; 780 s->current_dev = NULL; 781 } 782 } 783 784 void esp_transfer_data(SCSIRequest *req, uint32_t len) 785 { 786 ESPState *s = req->hba_private; 787 int to_device = ((s->rregs[ESP_RSTAT] & 7) == STAT_DO); 788 uint32_t dmalen = esp_get_tc(s); 789 790 assert(!s->do_cmd); 791 trace_esp_transfer_data(dmalen, s->ti_size); 792 s->async_len = len; 793 s->async_buf = scsi_req_get_buf(req); 794 795 if (!to_device && !s->data_in_ready) { 796 /* 797 * Initial incoming data xfer is complete so raise command 798 * completion interrupt 799 */ 800 s->data_in_ready = true; 801 s->rregs[ESP_RSTAT] |= STAT_TC; 802 s->rregs[ESP_RINTR] |= INTR_BS; 803 esp_raise_irq(s); 804 805 /* 806 * If data is ready to transfer and the TI command has already 807 * been executed, start DMA immediately. Otherwise DMA will start 808 * when host sends the TI command 809 */ 810 if (s->ti_size && (s->rregs[ESP_CMD] == (CMD_TI | CMD_DMA))) { 811 esp_do_dma(s); 812 } 813 return; 814 } 815 816 if (s->ti_cmd == 0) { 817 /* 818 * Always perform the initial transfer upon reception of the next TI 819 * command to ensure the DMA/non-DMA status of the command is correct. 820 * It is not possible to use s->dma directly in the section below as 821 * some OSs send non-DMA NOP commands after a DMA transfer. Hence if the 822 * async data transfer is delayed then s->dma is set incorrectly. 823 */ 824 return; 825 } 826 827 if (s->ti_cmd & CMD_DMA) { 828 if (dmalen) { 829 esp_do_dma(s); 830 } else if (s->ti_size <= 0) { 831 /* 832 * If this was the last part of a DMA transfer then the 833 * completion interrupt is deferred to here. 834 */ 835 esp_dma_done(s); 836 esp_lower_drq(s); 837 } 838 } else { 839 esp_do_nodma(s); 840 } 841 } 842 843 static void handle_ti(ESPState *s) 844 { 845 uint32_t dmalen; 846 847 if (s->dma && !s->dma_enabled) { 848 s->dma_cb = handle_ti; 849 return; 850 } 851 852 s->ti_cmd = s->rregs[ESP_CMD]; 853 if (s->dma) { 854 dmalen = esp_get_tc(s); 855 trace_esp_handle_ti(dmalen); 856 s->rregs[ESP_RSTAT] &= ~STAT_TC; 857 esp_do_dma(s); 858 } else { 859 trace_esp_handle_ti(s->ti_size); 860 esp_do_nodma(s); 861 } 862 } 863 864 void esp_hard_reset(ESPState *s) 865 { 866 memset(s->rregs, 0, ESP_REGS); 867 memset(s->wregs, 0, ESP_REGS); 868 s->tchi_written = 0; 869 s->ti_size = 0; 870 fifo8_reset(&s->fifo); 871 fifo8_reset(&s->cmdfifo); 872 s->dma = 0; 873 s->do_cmd = 0; 874 s->dma_cb = NULL; 875 876 s->rregs[ESP_CFG1] = 7; 877 } 878 879 static void esp_soft_reset(ESPState *s) 880 { 881 qemu_irq_lower(s->irq); 882 qemu_irq_lower(s->irq_data); 883 esp_hard_reset(s); 884 } 885 886 static void parent_esp_reset(ESPState *s, int irq, int level) 887 { 888 if (level) { 889 esp_soft_reset(s); 890 } 891 } 892 893 uint64_t esp_reg_read(ESPState *s, uint32_t saddr) 894 { 895 uint32_t val; 896 897 switch (saddr) { 898 case ESP_FIFO: 899 if (s->dma_memory_read && s->dma_memory_write && 900 (s->rregs[ESP_RSTAT] & STAT_PIO_MASK) == 0) { 901 /* Data out. */ 902 qemu_log_mask(LOG_UNIMP, "esp: PIO data read not implemented\n"); 903 s->rregs[ESP_FIFO] = 0; 904 } else { 905 s->rregs[ESP_FIFO] = esp_fifo_pop(&s->fifo); 906 } 907 val = s->rregs[ESP_FIFO]; 908 break; 909 case ESP_RINTR: 910 /* 911 * Clear sequence step, interrupt register and all status bits 912 * except TC 913 */ 914 val = s->rregs[ESP_RINTR]; 915 s->rregs[ESP_RINTR] = 0; 916 s->rregs[ESP_RSTAT] &= ~STAT_TC; 917 s->rregs[ESP_RSEQ] = SEQ_0; 918 esp_lower_irq(s); 919 break; 920 case ESP_TCHI: 921 /* Return the unique id if the value has never been written */ 922 if (!s->tchi_written) { 923 val = s->chip_id; 924 } else { 925 val = s->rregs[saddr]; 926 } 927 break; 928 case ESP_RFLAGS: 929 /* Bottom 5 bits indicate number of bytes in FIFO */ 930 val = fifo8_num_used(&s->fifo); 931 break; 932 default: 933 val = s->rregs[saddr]; 934 break; 935 } 936 937 trace_esp_mem_readb(saddr, val); 938 return val; 939 } 940 941 void esp_reg_write(ESPState *s, uint32_t saddr, uint64_t val) 942 { 943 trace_esp_mem_writeb(saddr, s->wregs[saddr], val); 944 switch (saddr) { 945 case ESP_TCHI: 946 s->tchi_written = true; 947 /* fall through */ 948 case ESP_TCLO: 949 case ESP_TCMID: 950 s->rregs[ESP_RSTAT] &= ~STAT_TC; 951 break; 952 case ESP_FIFO: 953 if (s->do_cmd) { 954 esp_fifo_push(&s->cmdfifo, val); 955 } else { 956 esp_fifo_push(&s->fifo, val); 957 } 958 959 /* Non-DMA transfers raise an interrupt after every byte */ 960 if (s->rregs[ESP_CMD] == CMD_TI) { 961 s->rregs[ESP_RINTR] |= INTR_FC | INTR_BS; 962 esp_raise_irq(s); 963 } 964 break; 965 case ESP_CMD: 966 s->rregs[saddr] = val; 967 if (val & CMD_DMA) { 968 s->dma = 1; 969 /* Reload DMA counter. */ 970 if (esp_get_stc(s) == 0) { 971 esp_set_tc(s, 0x10000); 972 } else { 973 esp_set_tc(s, esp_get_stc(s)); 974 } 975 } else { 976 s->dma = 0; 977 } 978 switch (val & CMD_CMD) { 979 case CMD_NOP: 980 trace_esp_mem_writeb_cmd_nop(val); 981 break; 982 case CMD_FLUSH: 983 trace_esp_mem_writeb_cmd_flush(val); 984 fifo8_reset(&s->fifo); 985 break; 986 case CMD_RESET: 987 trace_esp_mem_writeb_cmd_reset(val); 988 esp_soft_reset(s); 989 break; 990 case CMD_BUSRESET: 991 trace_esp_mem_writeb_cmd_bus_reset(val); 992 if (!(s->wregs[ESP_CFG1] & CFG1_RESREPT)) { 993 s->rregs[ESP_RINTR] |= INTR_RST; 994 esp_raise_irq(s); 995 } 996 break; 997 case CMD_TI: 998 trace_esp_mem_writeb_cmd_ti(val); 999 handle_ti(s); 1000 break; 1001 case CMD_ICCS: 1002 trace_esp_mem_writeb_cmd_iccs(val); 1003 write_response(s); 1004 s->rregs[ESP_RINTR] |= INTR_FC; 1005 s->rregs[ESP_RSTAT] |= STAT_MI; 1006 break; 1007 case CMD_MSGACC: 1008 trace_esp_mem_writeb_cmd_msgacc(val); 1009 s->rregs[ESP_RINTR] |= INTR_DC; 1010 s->rregs[ESP_RSEQ] = 0; 1011 s->rregs[ESP_RFLAGS] = 0; 1012 esp_raise_irq(s); 1013 break; 1014 case CMD_PAD: 1015 trace_esp_mem_writeb_cmd_pad(val); 1016 s->rregs[ESP_RSTAT] = STAT_TC; 1017 s->rregs[ESP_RINTR] |= INTR_FC; 1018 s->rregs[ESP_RSEQ] = 0; 1019 break; 1020 case CMD_SATN: 1021 trace_esp_mem_writeb_cmd_satn(val); 1022 break; 1023 case CMD_RSTATN: 1024 trace_esp_mem_writeb_cmd_rstatn(val); 1025 break; 1026 case CMD_SEL: 1027 trace_esp_mem_writeb_cmd_sel(val); 1028 handle_s_without_atn(s); 1029 break; 1030 case CMD_SELATN: 1031 trace_esp_mem_writeb_cmd_selatn(val); 1032 handle_satn(s); 1033 break; 1034 case CMD_SELATNS: 1035 trace_esp_mem_writeb_cmd_selatns(val); 1036 handle_satn_stop(s); 1037 break; 1038 case CMD_ENSEL: 1039 trace_esp_mem_writeb_cmd_ensel(val); 1040 s->rregs[ESP_RINTR] = 0; 1041 break; 1042 case CMD_DISSEL: 1043 trace_esp_mem_writeb_cmd_dissel(val); 1044 s->rregs[ESP_RINTR] = 0; 1045 esp_raise_irq(s); 1046 break; 1047 default: 1048 trace_esp_error_unhandled_command(val); 1049 break; 1050 } 1051 break; 1052 case ESP_WBUSID ... ESP_WSYNO: 1053 break; 1054 case ESP_CFG1: 1055 case ESP_CFG2: case ESP_CFG3: 1056 case ESP_RES3: case ESP_RES4: 1057 s->rregs[saddr] = val; 1058 break; 1059 case ESP_WCCF ... ESP_WTEST: 1060 break; 1061 default: 1062 trace_esp_error_invalid_write(val, saddr); 1063 return; 1064 } 1065 s->wregs[saddr] = val; 1066 } 1067 1068 static bool esp_mem_accepts(void *opaque, hwaddr addr, 1069 unsigned size, bool is_write, 1070 MemTxAttrs attrs) 1071 { 1072 return (size == 1) || (is_write && size == 4); 1073 } 1074 1075 static bool esp_is_before_version_5(void *opaque, int version_id) 1076 { 1077 ESPState *s = ESP(opaque); 1078 1079 version_id = MIN(version_id, s->mig_version_id); 1080 return version_id < 5; 1081 } 1082 1083 static bool esp_is_version_5(void *opaque, int version_id) 1084 { 1085 ESPState *s = ESP(opaque); 1086 1087 version_id = MIN(version_id, s->mig_version_id); 1088 return version_id == 5; 1089 } 1090 1091 int esp_pre_save(void *opaque) 1092 { 1093 ESPState *s = ESP(object_resolve_path_component( 1094 OBJECT(opaque), "esp")); 1095 1096 s->mig_version_id = vmstate_esp.version_id; 1097 return 0; 1098 } 1099 1100 static int esp_post_load(void *opaque, int version_id) 1101 { 1102 ESPState *s = ESP(opaque); 1103 int len, i; 1104 1105 version_id = MIN(version_id, s->mig_version_id); 1106 1107 if (version_id < 5) { 1108 esp_set_tc(s, s->mig_dma_left); 1109 1110 /* Migrate ti_buf to fifo */ 1111 len = s->mig_ti_wptr - s->mig_ti_rptr; 1112 for (i = 0; i < len; i++) { 1113 fifo8_push(&s->fifo, s->mig_ti_buf[i]); 1114 } 1115 1116 /* Migrate cmdbuf to cmdfifo */ 1117 for (i = 0; i < s->mig_cmdlen; i++) { 1118 fifo8_push(&s->cmdfifo, s->mig_cmdbuf[i]); 1119 } 1120 } 1121 1122 s->mig_version_id = vmstate_esp.version_id; 1123 return 0; 1124 } 1125 1126 const VMStateDescription vmstate_esp = { 1127 .name = "esp", 1128 .version_id = 5, 1129 .minimum_version_id = 3, 1130 .post_load = esp_post_load, 1131 .fields = (VMStateField[]) { 1132 VMSTATE_BUFFER(rregs, ESPState), 1133 VMSTATE_BUFFER(wregs, ESPState), 1134 VMSTATE_INT32(ti_size, ESPState), 1135 VMSTATE_UINT32_TEST(mig_ti_rptr, ESPState, esp_is_before_version_5), 1136 VMSTATE_UINT32_TEST(mig_ti_wptr, ESPState, esp_is_before_version_5), 1137 VMSTATE_BUFFER_TEST(mig_ti_buf, ESPState, esp_is_before_version_5), 1138 VMSTATE_UINT32(status, ESPState), 1139 VMSTATE_UINT32_TEST(mig_deferred_status, ESPState, 1140 esp_is_before_version_5), 1141 VMSTATE_BOOL_TEST(mig_deferred_complete, ESPState, 1142 esp_is_before_version_5), 1143 VMSTATE_UINT32(dma, ESPState), 1144 VMSTATE_STATIC_BUFFER(mig_cmdbuf, ESPState, 0, 1145 esp_is_before_version_5, 0, 16), 1146 VMSTATE_STATIC_BUFFER(mig_cmdbuf, ESPState, 4, 1147 esp_is_before_version_5, 16, 1148 sizeof(typeof_field(ESPState, mig_cmdbuf))), 1149 VMSTATE_UINT32_TEST(mig_cmdlen, ESPState, esp_is_before_version_5), 1150 VMSTATE_UINT32(do_cmd, ESPState), 1151 VMSTATE_UINT32_TEST(mig_dma_left, ESPState, esp_is_before_version_5), 1152 VMSTATE_BOOL_TEST(data_in_ready, ESPState, esp_is_version_5), 1153 VMSTATE_UINT8_TEST(cmdfifo_cdb_offset, ESPState, esp_is_version_5), 1154 VMSTATE_FIFO8_TEST(fifo, ESPState, esp_is_version_5), 1155 VMSTATE_FIFO8_TEST(cmdfifo, ESPState, esp_is_version_5), 1156 VMSTATE_UINT8_TEST(ti_cmd, ESPState, esp_is_version_5), 1157 VMSTATE_END_OF_LIST() 1158 }, 1159 }; 1160 1161 static void sysbus_esp_mem_write(void *opaque, hwaddr addr, 1162 uint64_t val, unsigned int size) 1163 { 1164 SysBusESPState *sysbus = opaque; 1165 ESPState *s = ESP(&sysbus->esp); 1166 uint32_t saddr; 1167 1168 saddr = addr >> sysbus->it_shift; 1169 esp_reg_write(s, saddr, val); 1170 } 1171 1172 static uint64_t sysbus_esp_mem_read(void *opaque, hwaddr addr, 1173 unsigned int size) 1174 { 1175 SysBusESPState *sysbus = opaque; 1176 ESPState *s = ESP(&sysbus->esp); 1177 uint32_t saddr; 1178 1179 saddr = addr >> sysbus->it_shift; 1180 return esp_reg_read(s, saddr); 1181 } 1182 1183 static const MemoryRegionOps sysbus_esp_mem_ops = { 1184 .read = sysbus_esp_mem_read, 1185 .write = sysbus_esp_mem_write, 1186 .endianness = DEVICE_NATIVE_ENDIAN, 1187 .valid.accepts = esp_mem_accepts, 1188 }; 1189 1190 static void sysbus_esp_pdma_write(void *opaque, hwaddr addr, 1191 uint64_t val, unsigned int size) 1192 { 1193 SysBusESPState *sysbus = opaque; 1194 ESPState *s = ESP(&sysbus->esp); 1195 uint32_t dmalen; 1196 1197 trace_esp_pdma_write(size); 1198 1199 switch (size) { 1200 case 1: 1201 esp_pdma_write(s, val); 1202 break; 1203 case 2: 1204 esp_pdma_write(s, val >> 8); 1205 esp_pdma_write(s, val); 1206 break; 1207 } 1208 dmalen = esp_get_tc(s); 1209 if (dmalen == 0 || fifo8_num_free(&s->fifo) < 2) { 1210 s->pdma_cb(s); 1211 } 1212 } 1213 1214 static uint64_t sysbus_esp_pdma_read(void *opaque, hwaddr addr, 1215 unsigned int size) 1216 { 1217 SysBusESPState *sysbus = opaque; 1218 ESPState *s = ESP(&sysbus->esp); 1219 uint64_t val = 0; 1220 1221 trace_esp_pdma_read(size); 1222 1223 switch (size) { 1224 case 1: 1225 val = esp_pdma_read(s); 1226 break; 1227 case 2: 1228 val = esp_pdma_read(s); 1229 val = (val << 8) | esp_pdma_read(s); 1230 break; 1231 } 1232 if (fifo8_num_used(&s->fifo) < 2) { 1233 s->pdma_cb(s); 1234 } 1235 return val; 1236 } 1237 1238 static const MemoryRegionOps sysbus_esp_pdma_ops = { 1239 .read = sysbus_esp_pdma_read, 1240 .write = sysbus_esp_pdma_write, 1241 .endianness = DEVICE_NATIVE_ENDIAN, 1242 .valid.min_access_size = 1, 1243 .valid.max_access_size = 4, 1244 .impl.min_access_size = 1, 1245 .impl.max_access_size = 2, 1246 }; 1247 1248 static const struct SCSIBusInfo esp_scsi_info = { 1249 .tcq = false, 1250 .max_target = ESP_MAX_DEVS, 1251 .max_lun = 7, 1252 1253 .transfer_data = esp_transfer_data, 1254 .complete = esp_command_complete, 1255 .cancel = esp_request_cancelled 1256 }; 1257 1258 static void sysbus_esp_gpio_demux(void *opaque, int irq, int level) 1259 { 1260 SysBusESPState *sysbus = SYSBUS_ESP(opaque); 1261 ESPState *s = ESP(&sysbus->esp); 1262 1263 switch (irq) { 1264 case 0: 1265 parent_esp_reset(s, irq, level); 1266 break; 1267 case 1: 1268 esp_dma_enable(opaque, irq, level); 1269 break; 1270 } 1271 } 1272 1273 static void sysbus_esp_realize(DeviceState *dev, Error **errp) 1274 { 1275 SysBusDevice *sbd = SYS_BUS_DEVICE(dev); 1276 SysBusESPState *sysbus = SYSBUS_ESP(dev); 1277 ESPState *s = ESP(&sysbus->esp); 1278 1279 if (!qdev_realize(DEVICE(s), NULL, errp)) { 1280 return; 1281 } 1282 1283 sysbus_init_irq(sbd, &s->irq); 1284 sysbus_init_irq(sbd, &s->irq_data); 1285 assert(sysbus->it_shift != -1); 1286 1287 s->chip_id = TCHI_FAS100A; 1288 memory_region_init_io(&sysbus->iomem, OBJECT(sysbus), &sysbus_esp_mem_ops, 1289 sysbus, "esp-regs", ESP_REGS << sysbus->it_shift); 1290 sysbus_init_mmio(sbd, &sysbus->iomem); 1291 memory_region_init_io(&sysbus->pdma, OBJECT(sysbus), &sysbus_esp_pdma_ops, 1292 sysbus, "esp-pdma", 4); 1293 sysbus_init_mmio(sbd, &sysbus->pdma); 1294 1295 qdev_init_gpio_in(dev, sysbus_esp_gpio_demux, 2); 1296 1297 scsi_bus_new(&s->bus, sizeof(s->bus), dev, &esp_scsi_info, NULL); 1298 } 1299 1300 static void sysbus_esp_hard_reset(DeviceState *dev) 1301 { 1302 SysBusESPState *sysbus = SYSBUS_ESP(dev); 1303 ESPState *s = ESP(&sysbus->esp); 1304 1305 esp_hard_reset(s); 1306 } 1307 1308 static void sysbus_esp_init(Object *obj) 1309 { 1310 SysBusESPState *sysbus = SYSBUS_ESP(obj); 1311 1312 object_initialize_child(obj, "esp", &sysbus->esp, TYPE_ESP); 1313 } 1314 1315 static const VMStateDescription vmstate_sysbus_esp_scsi = { 1316 .name = "sysbusespscsi", 1317 .version_id = 2, 1318 .minimum_version_id = 1, 1319 .pre_save = esp_pre_save, 1320 .fields = (VMStateField[]) { 1321 VMSTATE_UINT8_V(esp.mig_version_id, SysBusESPState, 2), 1322 VMSTATE_STRUCT(esp, SysBusESPState, 0, vmstate_esp, ESPState), 1323 VMSTATE_END_OF_LIST() 1324 } 1325 }; 1326 1327 static void sysbus_esp_class_init(ObjectClass *klass, void *data) 1328 { 1329 DeviceClass *dc = DEVICE_CLASS(klass); 1330 1331 dc->realize = sysbus_esp_realize; 1332 dc->reset = sysbus_esp_hard_reset; 1333 dc->vmsd = &vmstate_sysbus_esp_scsi; 1334 set_bit(DEVICE_CATEGORY_STORAGE, dc->categories); 1335 } 1336 1337 static const TypeInfo sysbus_esp_info = { 1338 .name = TYPE_SYSBUS_ESP, 1339 .parent = TYPE_SYS_BUS_DEVICE, 1340 .instance_init = sysbus_esp_init, 1341 .instance_size = sizeof(SysBusESPState), 1342 .class_init = sysbus_esp_class_init, 1343 }; 1344 1345 static void esp_finalize(Object *obj) 1346 { 1347 ESPState *s = ESP(obj); 1348 1349 fifo8_destroy(&s->fifo); 1350 fifo8_destroy(&s->cmdfifo); 1351 } 1352 1353 static void esp_init(Object *obj) 1354 { 1355 ESPState *s = ESP(obj); 1356 1357 fifo8_create(&s->fifo, ESP_FIFO_SZ); 1358 fifo8_create(&s->cmdfifo, ESP_CMDFIFO_SZ); 1359 } 1360 1361 static void esp_class_init(ObjectClass *klass, void *data) 1362 { 1363 DeviceClass *dc = DEVICE_CLASS(klass); 1364 1365 /* internal device for sysbusesp/pciespscsi, not user-creatable */ 1366 dc->user_creatable = false; 1367 set_bit(DEVICE_CATEGORY_STORAGE, dc->categories); 1368 } 1369 1370 static const TypeInfo esp_info = { 1371 .name = TYPE_ESP, 1372 .parent = TYPE_DEVICE, 1373 .instance_init = esp_init, 1374 .instance_finalize = esp_finalize, 1375 .instance_size = sizeof(ESPState), 1376 .class_init = esp_class_init, 1377 }; 1378 1379 static void esp_register_types(void) 1380 { 1381 type_register_static(&sysbus_esp_info); 1382 type_register_static(&esp_info); 1383 } 1384 1385 type_init(esp_register_types) 1386