1 /* 2 * QEMU ESP/NCR53C9x emulation 3 * 4 * Copyright (c) 2005-2006 Fabrice Bellard 5 * Copyright (c) 2012 Herve Poussineau 6 * 7 * Permission is hereby granted, free of charge, to any person obtaining a copy 8 * of this software and associated documentation files (the "Software"), to deal 9 * in the Software without restriction, including without limitation the rights 10 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 11 * copies of the Software, and to permit persons to whom the Software is 12 * furnished to do so, subject to the following conditions: 13 * 14 * The above copyright notice and this permission notice shall be included in 15 * all copies or substantial portions of the Software. 16 * 17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 22 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 23 * THE SOFTWARE. 24 */ 25 26 #include "qemu/osdep.h" 27 #include "hw/sysbus.h" 28 #include "migration/vmstate.h" 29 #include "hw/irq.h" 30 #include "hw/scsi/esp.h" 31 #include "trace.h" 32 #include "qemu/log.h" 33 #include "qemu/module.h" 34 35 /* 36 * On Sparc32, this is the ESP (NCR53C90) part of chip STP2000 (Master I/O), 37 * also produced as NCR89C100. See 38 * http://www.ibiblio.org/pub/historic-linux/early-ports/Sparc/NCR/NCR89C100.txt 39 * and 40 * http://www.ibiblio.org/pub/historic-linux/early-ports/Sparc/NCR/NCR53C9X.txt 41 * 42 * On Macintosh Quadra it is a NCR53C96. 43 */ 44 45 static void esp_raise_irq(ESPState *s) 46 { 47 if (!(s->rregs[ESP_RSTAT] & STAT_INT)) { 48 s->rregs[ESP_RSTAT] |= STAT_INT; 49 qemu_irq_raise(s->irq); 50 trace_esp_raise_irq(); 51 } 52 } 53 54 static void esp_lower_irq(ESPState *s) 55 { 56 if (s->rregs[ESP_RSTAT] & STAT_INT) { 57 s->rregs[ESP_RSTAT] &= ~STAT_INT; 58 qemu_irq_lower(s->irq); 59 trace_esp_lower_irq(); 60 } 61 } 62 63 static void esp_raise_drq(ESPState *s) 64 { 65 qemu_irq_raise(s->irq_data); 66 trace_esp_raise_drq(); 67 } 68 69 static void esp_lower_drq(ESPState *s) 70 { 71 qemu_irq_lower(s->irq_data); 72 trace_esp_lower_drq(); 73 } 74 75 void esp_dma_enable(ESPState *s, int irq, int level) 76 { 77 if (level) { 78 s->dma_enabled = 1; 79 trace_esp_dma_enable(); 80 if (s->dma_cb) { 81 s->dma_cb(s); 82 s->dma_cb = NULL; 83 } 84 } else { 85 trace_esp_dma_disable(); 86 s->dma_enabled = 0; 87 } 88 } 89 90 void esp_request_cancelled(SCSIRequest *req) 91 { 92 ESPState *s = req->hba_private; 93 94 if (req == s->current_req) { 95 scsi_req_unref(s->current_req); 96 s->current_req = NULL; 97 s->current_dev = NULL; 98 s->async_len = 0; 99 } 100 } 101 102 static void esp_fifo_push(Fifo8 *fifo, uint8_t val) 103 { 104 if (fifo8_num_used(fifo) == fifo->capacity) { 105 trace_esp_error_fifo_overrun(); 106 return; 107 } 108 109 fifo8_push(fifo, val); 110 } 111 112 static uint8_t esp_fifo_pop(Fifo8 *fifo) 113 { 114 if (fifo8_is_empty(fifo)) { 115 return 0; 116 } 117 118 return fifo8_pop(fifo); 119 } 120 121 static uint32_t esp_fifo_pop_buf(Fifo8 *fifo, uint8_t *dest, int maxlen) 122 { 123 const uint8_t *buf; 124 uint32_t n, n2; 125 int len; 126 127 if (maxlen == 0) { 128 return 0; 129 } 130 131 len = maxlen; 132 buf = fifo8_pop_buf(fifo, len, &n); 133 if (dest) { 134 memcpy(dest, buf, n); 135 } 136 137 /* Add FIFO wraparound if needed */ 138 len -= n; 139 len = MIN(len, fifo8_num_used(fifo)); 140 if (len) { 141 buf = fifo8_pop_buf(fifo, len, &n2); 142 if (dest) { 143 memcpy(&dest[n], buf, n2); 144 } 145 n += n2; 146 } 147 148 return n; 149 } 150 151 static uint32_t esp_get_tc(ESPState *s) 152 { 153 uint32_t dmalen; 154 155 dmalen = s->rregs[ESP_TCLO]; 156 dmalen |= s->rregs[ESP_TCMID] << 8; 157 dmalen |= s->rregs[ESP_TCHI] << 16; 158 159 return dmalen; 160 } 161 162 static void esp_set_tc(ESPState *s, uint32_t dmalen) 163 { 164 uint32_t old_tc = esp_get_tc(s); 165 166 s->rregs[ESP_TCLO] = dmalen; 167 s->rregs[ESP_TCMID] = dmalen >> 8; 168 s->rregs[ESP_TCHI] = dmalen >> 16; 169 170 if (old_tc && dmalen == 0) { 171 s->rregs[ESP_RSTAT] |= STAT_TC; 172 } 173 } 174 175 static uint32_t esp_get_stc(ESPState *s) 176 { 177 uint32_t dmalen; 178 179 dmalen = s->wregs[ESP_TCLO]; 180 dmalen |= s->wregs[ESP_TCMID] << 8; 181 dmalen |= s->wregs[ESP_TCHI] << 16; 182 183 return dmalen; 184 } 185 186 static uint8_t esp_pdma_read(ESPState *s) 187 { 188 uint8_t val; 189 190 if (s->do_cmd) { 191 val = esp_fifo_pop(&s->cmdfifo); 192 } else { 193 val = esp_fifo_pop(&s->fifo); 194 } 195 196 return val; 197 } 198 199 static void esp_pdma_write(ESPState *s, uint8_t val) 200 { 201 uint32_t dmalen = esp_get_tc(s); 202 203 if (dmalen == 0) { 204 return; 205 } 206 207 if (s->do_cmd) { 208 esp_fifo_push(&s->cmdfifo, val); 209 } else { 210 esp_fifo_push(&s->fifo, val); 211 } 212 213 dmalen--; 214 esp_set_tc(s, dmalen); 215 } 216 217 static void esp_set_pdma_cb(ESPState *s, enum pdma_cb cb) 218 { 219 s->pdma_cb = cb; 220 } 221 222 static int esp_select(ESPState *s) 223 { 224 int target; 225 226 target = s->wregs[ESP_WBUSID] & BUSID_DID; 227 228 s->ti_size = 0; 229 230 if (s->current_req) { 231 /* Started a new command before the old one finished. Cancel it. */ 232 scsi_req_cancel(s->current_req); 233 } 234 235 s->current_dev = scsi_device_find(&s->bus, 0, target, 0); 236 if (!s->current_dev) { 237 /* No such drive */ 238 s->rregs[ESP_RSTAT] = 0; 239 s->rregs[ESP_RINTR] = INTR_DC; 240 s->rregs[ESP_RSEQ] = SEQ_0; 241 esp_raise_irq(s); 242 return -1; 243 } 244 245 /* 246 * Note that we deliberately don't raise the IRQ here: this will be done 247 * either in do_command_phase() for DATA OUT transfers or by the deferred 248 * IRQ mechanism in esp_transfer_data() for DATA IN transfers 249 */ 250 s->rregs[ESP_RINTR] |= INTR_FC; 251 s->rregs[ESP_RSEQ] = SEQ_CD; 252 return 0; 253 } 254 255 static uint32_t get_cmd(ESPState *s, uint32_t maxlen) 256 { 257 uint8_t buf[ESP_CMDFIFO_SZ]; 258 uint32_t dmalen, n; 259 int target; 260 261 target = s->wregs[ESP_WBUSID] & BUSID_DID; 262 if (s->dma) { 263 dmalen = MIN(esp_get_tc(s), maxlen); 264 if (dmalen == 0) { 265 return 0; 266 } 267 if (s->dma_memory_read) { 268 s->dma_memory_read(s->dma_opaque, buf, dmalen); 269 dmalen = MIN(fifo8_num_free(&s->cmdfifo), dmalen); 270 fifo8_push_all(&s->cmdfifo, buf, dmalen); 271 } else { 272 return 0; 273 } 274 } else { 275 dmalen = MIN(fifo8_num_used(&s->fifo), maxlen); 276 if (dmalen == 0) { 277 return 0; 278 } 279 n = esp_fifo_pop_buf(&s->fifo, buf, dmalen); 280 n = MIN(fifo8_num_free(&s->cmdfifo), n); 281 fifo8_push_all(&s->cmdfifo, buf, n); 282 } 283 trace_esp_get_cmd(dmalen, target); 284 285 return dmalen; 286 } 287 288 static void do_command_phase(ESPState *s) 289 { 290 uint32_t cmdlen; 291 int32_t datalen; 292 SCSIDevice *current_lun; 293 uint8_t buf[ESP_CMDFIFO_SZ]; 294 295 trace_esp_do_command_phase(s->lun); 296 cmdlen = fifo8_num_used(&s->cmdfifo); 297 if (!cmdlen || !s->current_dev) { 298 return; 299 } 300 esp_fifo_pop_buf(&s->cmdfifo, buf, cmdlen); 301 302 current_lun = scsi_device_find(&s->bus, 0, s->current_dev->id, s->lun); 303 if (!current_lun) { 304 /* No such drive */ 305 s->rregs[ESP_RSTAT] = 0; 306 s->rregs[ESP_RINTR] = INTR_DC; 307 s->rregs[ESP_RSEQ] = SEQ_0; 308 esp_raise_irq(s); 309 return; 310 } 311 312 s->current_req = scsi_req_new(current_lun, 0, s->lun, buf, cmdlen, s); 313 datalen = scsi_req_enqueue(s->current_req); 314 s->ti_size = datalen; 315 fifo8_reset(&s->cmdfifo); 316 if (datalen != 0) { 317 s->rregs[ESP_RSTAT] = STAT_TC; 318 s->rregs[ESP_RSEQ] = SEQ_CD; 319 s->ti_cmd = 0; 320 esp_set_tc(s, 0); 321 if (datalen > 0) { 322 /* 323 * Switch to DATA IN phase but wait until initial data xfer is 324 * complete before raising the command completion interrupt 325 */ 326 s->data_in_ready = false; 327 s->rregs[ESP_RSTAT] |= STAT_DI; 328 } else { 329 s->rregs[ESP_RSTAT] |= STAT_DO; 330 s->rregs[ESP_RINTR] |= INTR_BS | INTR_FC; 331 esp_raise_irq(s); 332 esp_lower_drq(s); 333 } 334 scsi_req_continue(s->current_req); 335 return; 336 } 337 } 338 339 static void do_message_phase(ESPState *s) 340 { 341 if (s->cmdfifo_cdb_offset) { 342 uint8_t message = esp_fifo_pop(&s->cmdfifo); 343 344 trace_esp_do_identify(message); 345 s->lun = message & 7; 346 s->cmdfifo_cdb_offset--; 347 } 348 349 /* Ignore extended messages for now */ 350 if (s->cmdfifo_cdb_offset) { 351 int len = MIN(s->cmdfifo_cdb_offset, fifo8_num_used(&s->cmdfifo)); 352 esp_fifo_pop_buf(&s->cmdfifo, NULL, len); 353 s->cmdfifo_cdb_offset = 0; 354 } 355 } 356 357 static void do_cmd(ESPState *s) 358 { 359 do_message_phase(s); 360 assert(s->cmdfifo_cdb_offset == 0); 361 do_command_phase(s); 362 } 363 364 static void satn_pdma_cb(ESPState *s) 365 { 366 if (!esp_get_tc(s) && !fifo8_is_empty(&s->cmdfifo)) { 367 s->cmdfifo_cdb_offset = 1; 368 s->do_cmd = 0; 369 do_cmd(s); 370 } 371 } 372 373 static void handle_satn(ESPState *s) 374 { 375 int32_t cmdlen; 376 377 if (s->dma && !s->dma_enabled) { 378 s->dma_cb = handle_satn; 379 return; 380 } 381 esp_set_pdma_cb(s, SATN_PDMA_CB); 382 if (esp_select(s) < 0) { 383 return; 384 } 385 cmdlen = get_cmd(s, ESP_CMDFIFO_SZ); 386 if (cmdlen > 0) { 387 s->cmdfifo_cdb_offset = 1; 388 s->do_cmd = 0; 389 do_cmd(s); 390 } else if (cmdlen == 0) { 391 if (s->dma) { 392 esp_raise_drq(s); 393 } 394 s->do_cmd = 1; 395 /* Target present, but no cmd yet - switch to command phase */ 396 s->rregs[ESP_RSEQ] = SEQ_CD; 397 s->rregs[ESP_RSTAT] = STAT_CD; 398 } 399 } 400 401 static void s_without_satn_pdma_cb(ESPState *s) 402 { 403 if (!esp_get_tc(s) && !fifo8_is_empty(&s->cmdfifo)) { 404 s->cmdfifo_cdb_offset = 0; 405 s->do_cmd = 0; 406 do_cmd(s); 407 } 408 } 409 410 static void handle_s_without_atn(ESPState *s) 411 { 412 int32_t cmdlen; 413 414 if (s->dma && !s->dma_enabled) { 415 s->dma_cb = handle_s_without_atn; 416 return; 417 } 418 esp_set_pdma_cb(s, S_WITHOUT_SATN_PDMA_CB); 419 if (esp_select(s) < 0) { 420 return; 421 } 422 cmdlen = get_cmd(s, ESP_CMDFIFO_SZ); 423 if (cmdlen > 0) { 424 s->cmdfifo_cdb_offset = 0; 425 s->do_cmd = 0; 426 do_cmd(s); 427 } else if (cmdlen == 0) { 428 if (s->dma) { 429 esp_raise_drq(s); 430 } 431 s->do_cmd = 1; 432 /* Target present, but no cmd yet - switch to command phase */ 433 s->rregs[ESP_RSEQ] = SEQ_CD; 434 s->rregs[ESP_RSTAT] = STAT_CD; 435 } 436 } 437 438 static void satn_stop_pdma_cb(ESPState *s) 439 { 440 if (!esp_get_tc(s) && !fifo8_is_empty(&s->cmdfifo)) { 441 trace_esp_handle_satn_stop(fifo8_num_used(&s->cmdfifo)); 442 s->do_cmd = 1; 443 s->cmdfifo_cdb_offset = 1; 444 s->rregs[ESP_RSTAT] = STAT_TC | STAT_CD; 445 s->rregs[ESP_RINTR] |= INTR_BS | INTR_FC; 446 s->rregs[ESP_RSEQ] = SEQ_CD; 447 esp_raise_irq(s); 448 } 449 } 450 451 static void handle_satn_stop(ESPState *s) 452 { 453 int32_t cmdlen; 454 455 if (s->dma && !s->dma_enabled) { 456 s->dma_cb = handle_satn_stop; 457 return; 458 } 459 esp_set_pdma_cb(s, SATN_STOP_PDMA_CB); 460 if (esp_select(s) < 0) { 461 return; 462 } 463 cmdlen = get_cmd(s, 1); 464 if (cmdlen > 0) { 465 trace_esp_handle_satn_stop(fifo8_num_used(&s->cmdfifo)); 466 s->do_cmd = 1; 467 s->cmdfifo_cdb_offset = 1; 468 s->rregs[ESP_RSTAT] = STAT_MO; 469 s->rregs[ESP_RINTR] |= INTR_BS | INTR_FC; 470 s->rregs[ESP_RSEQ] = SEQ_MO; 471 esp_raise_irq(s); 472 } else if (cmdlen == 0) { 473 if (s->dma) { 474 esp_raise_drq(s); 475 } 476 s->do_cmd = 1; 477 /* Target present, switch to message out phase */ 478 s->rregs[ESP_RSEQ] = SEQ_MO; 479 s->rregs[ESP_RSTAT] = STAT_MO; 480 } 481 } 482 483 static void write_response_pdma_cb(ESPState *s) 484 { 485 s->rregs[ESP_RSTAT] = STAT_TC | STAT_ST; 486 s->rregs[ESP_RINTR] |= INTR_BS | INTR_FC; 487 s->rregs[ESP_RSEQ] = SEQ_CD; 488 esp_raise_irq(s); 489 } 490 491 static void write_response(ESPState *s) 492 { 493 uint8_t buf[2]; 494 495 trace_esp_write_response(s->status); 496 497 buf[0] = s->status; 498 buf[1] = 0; 499 500 if (s->dma) { 501 if (s->dma_memory_write) { 502 s->dma_memory_write(s->dma_opaque, buf, 2); 503 s->rregs[ESP_RSTAT] = STAT_TC | STAT_ST; 504 s->rregs[ESP_RINTR] |= INTR_BS | INTR_FC; 505 s->rregs[ESP_RSEQ] = SEQ_CD; 506 } else { 507 esp_set_pdma_cb(s, WRITE_RESPONSE_PDMA_CB); 508 esp_raise_drq(s); 509 return; 510 } 511 } else { 512 fifo8_reset(&s->fifo); 513 fifo8_push_all(&s->fifo, buf, 2); 514 s->rregs[ESP_RFLAGS] = 2; 515 } 516 esp_raise_irq(s); 517 } 518 519 static void esp_dma_done(ESPState *s) 520 { 521 s->rregs[ESP_RSTAT] |= STAT_TC; 522 s->rregs[ESP_RINTR] |= INTR_BS; 523 s->rregs[ESP_RFLAGS] = 0; 524 esp_set_tc(s, 0); 525 esp_raise_irq(s); 526 } 527 528 static void do_dma_pdma_cb(ESPState *s) 529 { 530 int to_device = ((s->rregs[ESP_RSTAT] & 7) == STAT_DO); 531 int len; 532 uint32_t n; 533 534 if (s->do_cmd) { 535 /* Ensure we have received complete command after SATN and stop */ 536 if (esp_get_tc(s) || fifo8_is_empty(&s->cmdfifo)) { 537 return; 538 } 539 540 s->ti_size = 0; 541 if ((s->rregs[ESP_RSTAT] & 7) == STAT_CD) { 542 /* No command received */ 543 if (s->cmdfifo_cdb_offset == fifo8_num_used(&s->cmdfifo)) { 544 return; 545 } 546 547 /* Command has been received */ 548 s->do_cmd = 0; 549 do_cmd(s); 550 } else { 551 /* 552 * Extra message out bytes received: update cmdfifo_cdb_offset 553 * and then switch to command phase 554 */ 555 s->cmdfifo_cdb_offset = fifo8_num_used(&s->cmdfifo); 556 s->rregs[ESP_RSTAT] = STAT_TC | STAT_CD; 557 s->rregs[ESP_RSEQ] = SEQ_CD; 558 s->rregs[ESP_RINTR] |= INTR_BS; 559 esp_raise_irq(s); 560 } 561 return; 562 } 563 564 if (!s->current_req) { 565 return; 566 } 567 568 if (to_device) { 569 /* Copy FIFO data to device */ 570 len = MIN(s->async_len, ESP_FIFO_SZ); 571 len = MIN(len, fifo8_num_used(&s->fifo)); 572 n = esp_fifo_pop_buf(&s->fifo, s->async_buf, len); 573 s->async_buf += n; 574 s->async_len -= n; 575 s->ti_size += n; 576 577 if (n < len) { 578 /* Unaligned accesses can cause FIFO wraparound */ 579 len = len - n; 580 n = esp_fifo_pop_buf(&s->fifo, s->async_buf, len); 581 s->async_buf += n; 582 s->async_len -= n; 583 s->ti_size += n; 584 } 585 586 if (s->async_len == 0) { 587 scsi_req_continue(s->current_req); 588 return; 589 } 590 591 if (esp_get_tc(s) == 0) { 592 esp_lower_drq(s); 593 esp_dma_done(s); 594 } 595 596 return; 597 } else { 598 if (s->async_len == 0) { 599 /* Defer until the scsi layer has completed */ 600 scsi_req_continue(s->current_req); 601 s->data_in_ready = false; 602 return; 603 } 604 605 if (esp_get_tc(s) == 0) { 606 esp_lower_drq(s); 607 esp_dma_done(s); 608 } 609 610 /* Copy device data to FIFO */ 611 len = MIN(s->async_len, esp_get_tc(s)); 612 len = MIN(len, fifo8_num_free(&s->fifo)); 613 fifo8_push_all(&s->fifo, s->async_buf, len); 614 s->async_buf += len; 615 s->async_len -= len; 616 s->ti_size -= len; 617 esp_set_tc(s, esp_get_tc(s) - len); 618 } 619 } 620 621 static void esp_do_dma(ESPState *s) 622 { 623 uint32_t len, cmdlen; 624 int to_device = ((s->rregs[ESP_RSTAT] & 7) == STAT_DO); 625 uint8_t buf[ESP_CMDFIFO_SZ]; 626 627 len = esp_get_tc(s); 628 if (s->do_cmd) { 629 /* 630 * handle_ti_cmd() case: esp_do_dma() is called only from 631 * handle_ti_cmd() with do_cmd != NULL (see the assert()) 632 */ 633 cmdlen = fifo8_num_used(&s->cmdfifo); 634 trace_esp_do_dma(cmdlen, len); 635 if (s->dma_memory_read) { 636 len = MIN(len, fifo8_num_free(&s->cmdfifo)); 637 s->dma_memory_read(s->dma_opaque, buf, len); 638 fifo8_push_all(&s->cmdfifo, buf, len); 639 } else { 640 esp_set_pdma_cb(s, DO_DMA_PDMA_CB); 641 esp_raise_drq(s); 642 return; 643 } 644 trace_esp_handle_ti_cmd(cmdlen); 645 s->ti_size = 0; 646 if ((s->rregs[ESP_RSTAT] & 7) == STAT_CD) { 647 /* No command received */ 648 if (s->cmdfifo_cdb_offset == fifo8_num_used(&s->cmdfifo)) { 649 return; 650 } 651 652 /* Command has been received */ 653 s->do_cmd = 0; 654 do_cmd(s); 655 } else { 656 /* 657 * Extra message out bytes received: update cmdfifo_cdb_offset 658 * and then switch to command phase 659 */ 660 s->cmdfifo_cdb_offset = fifo8_num_used(&s->cmdfifo); 661 s->rregs[ESP_RSTAT] = STAT_TC | STAT_CD; 662 s->rregs[ESP_RSEQ] = SEQ_CD; 663 s->rregs[ESP_RINTR] |= INTR_BS; 664 esp_raise_irq(s); 665 } 666 return; 667 } 668 if (!s->current_req) { 669 return; 670 } 671 if (s->async_len == 0) { 672 /* Defer until data is available. */ 673 return; 674 } 675 if (len > s->async_len) { 676 len = s->async_len; 677 } 678 if (to_device) { 679 if (s->dma_memory_read) { 680 s->dma_memory_read(s->dma_opaque, s->async_buf, len); 681 682 esp_set_tc(s, esp_get_tc(s) - len); 683 s->async_buf += len; 684 s->async_len -= len; 685 s->ti_size += len; 686 687 if (s->async_len == 0) { 688 scsi_req_continue(s->current_req); 689 /* 690 * If there is still data to be read from the device then 691 * complete the DMA operation immediately. Otherwise defer 692 * until the scsi layer has completed. 693 */ 694 return; 695 } 696 697 /* Partially filled a scsi buffer. Complete immediately. */ 698 esp_dma_done(s); 699 esp_lower_drq(s); 700 } else { 701 esp_set_pdma_cb(s, DO_DMA_PDMA_CB); 702 esp_raise_drq(s); 703 } 704 } else { 705 if (s->dma_memory_write) { 706 s->dma_memory_write(s->dma_opaque, s->async_buf, len); 707 708 esp_set_tc(s, esp_get_tc(s) - len); 709 s->async_buf += len; 710 s->async_len -= len; 711 s->ti_size -= len; 712 713 if (s->async_len == 0) { 714 scsi_req_continue(s->current_req); 715 /* 716 * If there is still data to be read from the device then 717 * complete the DMA operation immediately. Otherwise defer 718 * until the scsi layer has completed. 719 */ 720 if (esp_get_tc(s) != 0 || s->ti_size == 0) { 721 return; 722 } 723 } 724 725 /* Partially filled a scsi buffer. Complete immediately. */ 726 esp_dma_done(s); 727 esp_lower_drq(s); 728 } else { 729 /* Adjust TC for any leftover data in the FIFO */ 730 if (!fifo8_is_empty(&s->fifo)) { 731 esp_set_tc(s, esp_get_tc(s) - fifo8_num_used(&s->fifo)); 732 } 733 734 /* Copy device data to FIFO */ 735 len = MIN(len, fifo8_num_free(&s->fifo)); 736 fifo8_push_all(&s->fifo, s->async_buf, len); 737 s->async_buf += len; 738 s->async_len -= len; 739 s->ti_size -= len; 740 741 /* 742 * MacOS toolbox uses a TI length of 16 bytes for all commands, so 743 * commands shorter than this must be padded accordingly 744 */ 745 if (len < esp_get_tc(s) && esp_get_tc(s) <= ESP_FIFO_SZ) { 746 while (fifo8_num_used(&s->fifo) < ESP_FIFO_SZ) { 747 esp_fifo_push(&s->fifo, 0); 748 len++; 749 } 750 } 751 752 esp_set_tc(s, esp_get_tc(s) - len); 753 esp_set_pdma_cb(s, DO_DMA_PDMA_CB); 754 esp_raise_drq(s); 755 } 756 } 757 } 758 759 static void esp_do_nodma(ESPState *s) 760 { 761 int to_device = ((s->rregs[ESP_RSTAT] & 7) == STAT_DO); 762 uint32_t cmdlen; 763 int len; 764 765 if (s->do_cmd) { 766 cmdlen = fifo8_num_used(&s->cmdfifo); 767 trace_esp_handle_ti_cmd(cmdlen); 768 s->ti_size = 0; 769 if ((s->rregs[ESP_RSTAT] & 7) == STAT_CD) { 770 /* No command received */ 771 if (s->cmdfifo_cdb_offset == fifo8_num_used(&s->cmdfifo)) { 772 return; 773 } 774 775 /* Command has been received */ 776 s->do_cmd = 0; 777 do_cmd(s); 778 } else { 779 /* 780 * Extra message out bytes received: update cmdfifo_cdb_offset 781 * and then switch to command phase 782 */ 783 s->cmdfifo_cdb_offset = fifo8_num_used(&s->cmdfifo); 784 s->rregs[ESP_RSTAT] = STAT_TC | STAT_CD; 785 s->rregs[ESP_RSEQ] = SEQ_CD; 786 s->rregs[ESP_RINTR] |= INTR_BS; 787 esp_raise_irq(s); 788 } 789 return; 790 } 791 792 if (!s->current_req) { 793 return; 794 } 795 796 if (s->async_len == 0) { 797 /* Defer until data is available. */ 798 return; 799 } 800 801 if (to_device) { 802 len = MIN(s->async_len, ESP_FIFO_SZ); 803 len = MIN(len, fifo8_num_used(&s->fifo)); 804 esp_fifo_pop_buf(&s->fifo, s->async_buf, len); 805 s->async_buf += len; 806 s->async_len -= len; 807 s->ti_size += len; 808 } else { 809 if (fifo8_is_empty(&s->fifo)) { 810 fifo8_push(&s->fifo, s->async_buf[0]); 811 s->async_buf++; 812 s->async_len--; 813 s->ti_size--; 814 } 815 } 816 817 if (s->async_len == 0) { 818 scsi_req_continue(s->current_req); 819 return; 820 } 821 822 s->rregs[ESP_RINTR] |= INTR_BS; 823 esp_raise_irq(s); 824 } 825 826 static void esp_pdma_cb(ESPState *s) 827 { 828 switch (s->pdma_cb) { 829 case SATN_PDMA_CB: 830 satn_pdma_cb(s); 831 break; 832 case S_WITHOUT_SATN_PDMA_CB: 833 s_without_satn_pdma_cb(s); 834 break; 835 case SATN_STOP_PDMA_CB: 836 satn_stop_pdma_cb(s); 837 break; 838 case WRITE_RESPONSE_PDMA_CB: 839 write_response_pdma_cb(s); 840 break; 841 case DO_DMA_PDMA_CB: 842 do_dma_pdma_cb(s); 843 break; 844 default: 845 g_assert_not_reached(); 846 } 847 } 848 849 void esp_command_complete(SCSIRequest *req, size_t resid) 850 { 851 ESPState *s = req->hba_private; 852 int to_device = ((s->rregs[ESP_RSTAT] & 7) == STAT_DO); 853 854 trace_esp_command_complete(); 855 856 /* 857 * Non-DMA transfers from the target will leave the last byte in 858 * the FIFO so don't reset ti_size in this case 859 */ 860 if (s->dma || to_device) { 861 if (s->ti_size != 0) { 862 trace_esp_command_complete_unexpected(); 863 } 864 s->ti_size = 0; 865 } 866 867 s->async_len = 0; 868 if (req->status) { 869 trace_esp_command_complete_fail(); 870 } 871 s->status = req->status; 872 873 /* 874 * If the transfer is finished, switch to status phase. For non-DMA 875 * transfers from the target the last byte is still in the FIFO 876 */ 877 if (s->ti_size == 0) { 878 s->rregs[ESP_RSTAT] &= ~7; 879 s->rregs[ESP_RSTAT] |= STAT_ST; 880 esp_dma_done(s); 881 esp_lower_drq(s); 882 } 883 884 if (s->current_req) { 885 scsi_req_unref(s->current_req); 886 s->current_req = NULL; 887 s->current_dev = NULL; 888 } 889 } 890 891 void esp_transfer_data(SCSIRequest *req, uint32_t len) 892 { 893 ESPState *s = req->hba_private; 894 int to_device = ((s->rregs[ESP_RSTAT] & 7) == STAT_DO); 895 uint32_t dmalen = esp_get_tc(s); 896 897 assert(!s->do_cmd); 898 trace_esp_transfer_data(dmalen, s->ti_size); 899 s->async_len = len; 900 s->async_buf = scsi_req_get_buf(req); 901 902 if (!to_device && !s->data_in_ready) { 903 /* 904 * Initial incoming data xfer is complete so raise command 905 * completion interrupt 906 */ 907 s->data_in_ready = true; 908 s->rregs[ESP_RSTAT] |= STAT_TC; 909 s->rregs[ESP_RINTR] |= INTR_BS; 910 esp_raise_irq(s); 911 } 912 913 if (s->ti_cmd == 0) { 914 /* 915 * Always perform the initial transfer upon reception of the next TI 916 * command to ensure the DMA/non-DMA status of the command is correct. 917 * It is not possible to use s->dma directly in the section below as 918 * some OSs send non-DMA NOP commands after a DMA transfer. Hence if the 919 * async data transfer is delayed then s->dma is set incorrectly. 920 */ 921 return; 922 } 923 924 if (s->ti_cmd == (CMD_TI | CMD_DMA)) { 925 if (dmalen) { 926 esp_do_dma(s); 927 } else if (s->ti_size <= 0) { 928 /* 929 * If this was the last part of a DMA transfer then the 930 * completion interrupt is deferred to here. 931 */ 932 esp_dma_done(s); 933 esp_lower_drq(s); 934 } 935 } else if (s->ti_cmd == CMD_TI) { 936 esp_do_nodma(s); 937 } 938 } 939 940 static void handle_ti(ESPState *s) 941 { 942 uint32_t dmalen; 943 944 if (s->dma && !s->dma_enabled) { 945 s->dma_cb = handle_ti; 946 return; 947 } 948 949 s->ti_cmd = s->rregs[ESP_CMD]; 950 if (s->dma) { 951 dmalen = esp_get_tc(s); 952 trace_esp_handle_ti(dmalen); 953 s->rregs[ESP_RSTAT] &= ~STAT_TC; 954 esp_do_dma(s); 955 } else { 956 trace_esp_handle_ti(s->ti_size); 957 esp_do_nodma(s); 958 } 959 } 960 961 void esp_hard_reset(ESPState *s) 962 { 963 memset(s->rregs, 0, ESP_REGS); 964 memset(s->wregs, 0, ESP_REGS); 965 s->tchi_written = 0; 966 s->ti_size = 0; 967 s->async_len = 0; 968 fifo8_reset(&s->fifo); 969 fifo8_reset(&s->cmdfifo); 970 s->dma = 0; 971 s->do_cmd = 0; 972 s->dma_cb = NULL; 973 974 s->rregs[ESP_CFG1] = 7; 975 } 976 977 static void esp_soft_reset(ESPState *s) 978 { 979 qemu_irq_lower(s->irq); 980 qemu_irq_lower(s->irq_data); 981 esp_hard_reset(s); 982 } 983 984 static void esp_bus_reset(ESPState *s) 985 { 986 bus_cold_reset(BUS(&s->bus)); 987 } 988 989 static void parent_esp_reset(ESPState *s, int irq, int level) 990 { 991 if (level) { 992 esp_soft_reset(s); 993 } 994 } 995 996 static void esp_run_cmd(ESPState *s) 997 { 998 uint8_t cmd = s->rregs[ESP_CMD]; 999 1000 if (cmd & CMD_DMA) { 1001 s->dma = 1; 1002 /* Reload DMA counter. */ 1003 if (esp_get_stc(s) == 0) { 1004 esp_set_tc(s, 0x10000); 1005 } else { 1006 esp_set_tc(s, esp_get_stc(s)); 1007 } 1008 } else { 1009 s->dma = 0; 1010 } 1011 switch (cmd & CMD_CMD) { 1012 case CMD_NOP: 1013 trace_esp_mem_writeb_cmd_nop(cmd); 1014 break; 1015 case CMD_FLUSH: 1016 trace_esp_mem_writeb_cmd_flush(cmd); 1017 fifo8_reset(&s->fifo); 1018 break; 1019 case CMD_RESET: 1020 trace_esp_mem_writeb_cmd_reset(cmd); 1021 esp_soft_reset(s); 1022 break; 1023 case CMD_BUSRESET: 1024 trace_esp_mem_writeb_cmd_bus_reset(cmd); 1025 esp_bus_reset(s); 1026 if (!(s->wregs[ESP_CFG1] & CFG1_RESREPT)) { 1027 s->rregs[ESP_RINTR] |= INTR_RST; 1028 esp_raise_irq(s); 1029 } 1030 break; 1031 case CMD_TI: 1032 trace_esp_mem_writeb_cmd_ti(cmd); 1033 handle_ti(s); 1034 break; 1035 case CMD_ICCS: 1036 trace_esp_mem_writeb_cmd_iccs(cmd); 1037 write_response(s); 1038 s->rregs[ESP_RINTR] |= INTR_FC; 1039 s->rregs[ESP_RSTAT] |= STAT_MI; 1040 break; 1041 case CMD_MSGACC: 1042 trace_esp_mem_writeb_cmd_msgacc(cmd); 1043 s->rregs[ESP_RINTR] |= INTR_DC; 1044 s->rregs[ESP_RSEQ] = 0; 1045 s->rregs[ESP_RFLAGS] = 0; 1046 esp_raise_irq(s); 1047 break; 1048 case CMD_PAD: 1049 trace_esp_mem_writeb_cmd_pad(cmd); 1050 s->rregs[ESP_RSTAT] = STAT_TC; 1051 s->rregs[ESP_RINTR] |= INTR_FC; 1052 s->rregs[ESP_RSEQ] = 0; 1053 break; 1054 case CMD_SATN: 1055 trace_esp_mem_writeb_cmd_satn(cmd); 1056 break; 1057 case CMD_RSTATN: 1058 trace_esp_mem_writeb_cmd_rstatn(cmd); 1059 break; 1060 case CMD_SEL: 1061 trace_esp_mem_writeb_cmd_sel(cmd); 1062 handle_s_without_atn(s); 1063 break; 1064 case CMD_SELATN: 1065 trace_esp_mem_writeb_cmd_selatn(cmd); 1066 handle_satn(s); 1067 break; 1068 case CMD_SELATNS: 1069 trace_esp_mem_writeb_cmd_selatns(cmd); 1070 handle_satn_stop(s); 1071 break; 1072 case CMD_ENSEL: 1073 trace_esp_mem_writeb_cmd_ensel(cmd); 1074 s->rregs[ESP_RINTR] = 0; 1075 break; 1076 case CMD_DISSEL: 1077 trace_esp_mem_writeb_cmd_dissel(cmd); 1078 s->rregs[ESP_RINTR] = 0; 1079 esp_raise_irq(s); 1080 break; 1081 default: 1082 trace_esp_error_unhandled_command(cmd); 1083 break; 1084 } 1085 } 1086 1087 uint64_t esp_reg_read(ESPState *s, uint32_t saddr) 1088 { 1089 uint32_t val; 1090 1091 switch (saddr) { 1092 case ESP_FIFO: 1093 if (s->dma_memory_read && s->dma_memory_write && 1094 (s->rregs[ESP_RSTAT] & STAT_PIO_MASK) == 0) { 1095 /* Data out. */ 1096 qemu_log_mask(LOG_UNIMP, "esp: PIO data read not implemented\n"); 1097 s->rregs[ESP_FIFO] = 0; 1098 } else { 1099 if ((s->rregs[ESP_RSTAT] & 0x7) == STAT_DI) { 1100 if (s->ti_size) { 1101 esp_do_nodma(s); 1102 } else { 1103 /* 1104 * The last byte of a non-DMA transfer has been read out 1105 * of the FIFO so switch to status phase 1106 */ 1107 s->rregs[ESP_RSTAT] = STAT_TC | STAT_ST; 1108 } 1109 } 1110 s->rregs[ESP_FIFO] = esp_fifo_pop(&s->fifo); 1111 } 1112 val = s->rregs[ESP_FIFO]; 1113 break; 1114 case ESP_RINTR: 1115 /* 1116 * Clear sequence step, interrupt register and all status bits 1117 * except TC 1118 */ 1119 val = s->rregs[ESP_RINTR]; 1120 s->rregs[ESP_RINTR] = 0; 1121 s->rregs[ESP_RSTAT] &= ~STAT_TC; 1122 /* 1123 * According to the datasheet ESP_RSEQ should be cleared, but as the 1124 * emulation currently defers information transfers to the next TI 1125 * command leave it for now so that pedantic guests such as the old 1126 * Linux 2.6 driver see the correct flags before the next SCSI phase 1127 * transition. 1128 * 1129 * s->rregs[ESP_RSEQ] = SEQ_0; 1130 */ 1131 esp_lower_irq(s); 1132 break; 1133 case ESP_TCHI: 1134 /* Return the unique id if the value has never been written */ 1135 if (!s->tchi_written) { 1136 val = s->chip_id; 1137 } else { 1138 val = s->rregs[saddr]; 1139 } 1140 break; 1141 case ESP_RFLAGS: 1142 /* Bottom 5 bits indicate number of bytes in FIFO */ 1143 val = fifo8_num_used(&s->fifo); 1144 break; 1145 default: 1146 val = s->rregs[saddr]; 1147 break; 1148 } 1149 1150 trace_esp_mem_readb(saddr, val); 1151 return val; 1152 } 1153 1154 void esp_reg_write(ESPState *s, uint32_t saddr, uint64_t val) 1155 { 1156 trace_esp_mem_writeb(saddr, s->wregs[saddr], val); 1157 switch (saddr) { 1158 case ESP_TCHI: 1159 s->tchi_written = true; 1160 /* fall through */ 1161 case ESP_TCLO: 1162 case ESP_TCMID: 1163 s->rregs[ESP_RSTAT] &= ~STAT_TC; 1164 break; 1165 case ESP_FIFO: 1166 if (s->do_cmd) { 1167 esp_fifo_push(&s->cmdfifo, val); 1168 1169 /* 1170 * If any unexpected message out/command phase data is 1171 * transferred using non-DMA, raise the interrupt 1172 */ 1173 if (s->rregs[ESP_CMD] == CMD_TI) { 1174 s->rregs[ESP_RINTR] |= INTR_BS; 1175 esp_raise_irq(s); 1176 } 1177 } else { 1178 esp_fifo_push(&s->fifo, val); 1179 } 1180 break; 1181 case ESP_CMD: 1182 s->rregs[saddr] = val; 1183 esp_run_cmd(s); 1184 break; 1185 case ESP_WBUSID ... ESP_WSYNO: 1186 break; 1187 case ESP_CFG1: 1188 case ESP_CFG2: case ESP_CFG3: 1189 case ESP_RES3: case ESP_RES4: 1190 s->rregs[saddr] = val; 1191 break; 1192 case ESP_WCCF ... ESP_WTEST: 1193 break; 1194 default: 1195 trace_esp_error_invalid_write(val, saddr); 1196 return; 1197 } 1198 s->wregs[saddr] = val; 1199 } 1200 1201 static bool esp_mem_accepts(void *opaque, hwaddr addr, 1202 unsigned size, bool is_write, 1203 MemTxAttrs attrs) 1204 { 1205 return (size == 1) || (is_write && size == 4); 1206 } 1207 1208 static bool esp_is_before_version_5(void *opaque, int version_id) 1209 { 1210 ESPState *s = ESP(opaque); 1211 1212 version_id = MIN(version_id, s->mig_version_id); 1213 return version_id < 5; 1214 } 1215 1216 static bool esp_is_version_5(void *opaque, int version_id) 1217 { 1218 ESPState *s = ESP(opaque); 1219 1220 version_id = MIN(version_id, s->mig_version_id); 1221 return version_id >= 5; 1222 } 1223 1224 static bool esp_is_version_6(void *opaque, int version_id) 1225 { 1226 ESPState *s = ESP(opaque); 1227 1228 version_id = MIN(version_id, s->mig_version_id); 1229 return version_id >= 6; 1230 } 1231 1232 int esp_pre_save(void *opaque) 1233 { 1234 ESPState *s = ESP(object_resolve_path_component( 1235 OBJECT(opaque), "esp")); 1236 1237 s->mig_version_id = vmstate_esp.version_id; 1238 return 0; 1239 } 1240 1241 static int esp_post_load(void *opaque, int version_id) 1242 { 1243 ESPState *s = ESP(opaque); 1244 int len, i; 1245 1246 version_id = MIN(version_id, s->mig_version_id); 1247 1248 if (version_id < 5) { 1249 esp_set_tc(s, s->mig_dma_left); 1250 1251 /* Migrate ti_buf to fifo */ 1252 len = s->mig_ti_wptr - s->mig_ti_rptr; 1253 for (i = 0; i < len; i++) { 1254 fifo8_push(&s->fifo, s->mig_ti_buf[i]); 1255 } 1256 1257 /* Migrate cmdbuf to cmdfifo */ 1258 for (i = 0; i < s->mig_cmdlen; i++) { 1259 fifo8_push(&s->cmdfifo, s->mig_cmdbuf[i]); 1260 } 1261 } 1262 1263 s->mig_version_id = vmstate_esp.version_id; 1264 return 0; 1265 } 1266 1267 /* 1268 * PDMA (or pseudo-DMA) is only used on the Macintosh and requires the 1269 * guest CPU to perform the transfers between the SCSI bus and memory 1270 * itself. This is indicated by the dma_memory_read and dma_memory_write 1271 * functions being NULL (in contrast to the ESP PCI device) whilst 1272 * dma_enabled is still set. 1273 */ 1274 1275 static bool esp_pdma_needed(void *opaque) 1276 { 1277 ESPState *s = ESP(opaque); 1278 1279 return s->dma_memory_read == NULL && s->dma_memory_write == NULL && 1280 s->dma_enabled; 1281 } 1282 1283 static const VMStateDescription vmstate_esp_pdma = { 1284 .name = "esp/pdma", 1285 .version_id = 0, 1286 .minimum_version_id = 0, 1287 .needed = esp_pdma_needed, 1288 .fields = (const VMStateField[]) { 1289 VMSTATE_UINT8(pdma_cb, ESPState), 1290 VMSTATE_END_OF_LIST() 1291 } 1292 }; 1293 1294 const VMStateDescription vmstate_esp = { 1295 .name = "esp", 1296 .version_id = 6, 1297 .minimum_version_id = 3, 1298 .post_load = esp_post_load, 1299 .fields = (const VMStateField[]) { 1300 VMSTATE_BUFFER(rregs, ESPState), 1301 VMSTATE_BUFFER(wregs, ESPState), 1302 VMSTATE_INT32(ti_size, ESPState), 1303 VMSTATE_UINT32_TEST(mig_ti_rptr, ESPState, esp_is_before_version_5), 1304 VMSTATE_UINT32_TEST(mig_ti_wptr, ESPState, esp_is_before_version_5), 1305 VMSTATE_BUFFER_TEST(mig_ti_buf, ESPState, esp_is_before_version_5), 1306 VMSTATE_UINT32(status, ESPState), 1307 VMSTATE_UINT32_TEST(mig_deferred_status, ESPState, 1308 esp_is_before_version_5), 1309 VMSTATE_BOOL_TEST(mig_deferred_complete, ESPState, 1310 esp_is_before_version_5), 1311 VMSTATE_UINT32(dma, ESPState), 1312 VMSTATE_STATIC_BUFFER(mig_cmdbuf, ESPState, 0, 1313 esp_is_before_version_5, 0, 16), 1314 VMSTATE_STATIC_BUFFER(mig_cmdbuf, ESPState, 4, 1315 esp_is_before_version_5, 16, 1316 sizeof(typeof_field(ESPState, mig_cmdbuf))), 1317 VMSTATE_UINT32_TEST(mig_cmdlen, ESPState, esp_is_before_version_5), 1318 VMSTATE_UINT32(do_cmd, ESPState), 1319 VMSTATE_UINT32_TEST(mig_dma_left, ESPState, esp_is_before_version_5), 1320 VMSTATE_BOOL_TEST(data_in_ready, ESPState, esp_is_version_5), 1321 VMSTATE_UINT8_TEST(cmdfifo_cdb_offset, ESPState, esp_is_version_5), 1322 VMSTATE_FIFO8_TEST(fifo, ESPState, esp_is_version_5), 1323 VMSTATE_FIFO8_TEST(cmdfifo, ESPState, esp_is_version_5), 1324 VMSTATE_UINT8_TEST(ti_cmd, ESPState, esp_is_version_5), 1325 VMSTATE_UINT8_TEST(lun, ESPState, esp_is_version_6), 1326 VMSTATE_END_OF_LIST() 1327 }, 1328 .subsections = (const VMStateDescription * const []) { 1329 &vmstate_esp_pdma, 1330 NULL 1331 } 1332 }; 1333 1334 static void sysbus_esp_mem_write(void *opaque, hwaddr addr, 1335 uint64_t val, unsigned int size) 1336 { 1337 SysBusESPState *sysbus = opaque; 1338 ESPState *s = ESP(&sysbus->esp); 1339 uint32_t saddr; 1340 1341 saddr = addr >> sysbus->it_shift; 1342 esp_reg_write(s, saddr, val); 1343 } 1344 1345 static uint64_t sysbus_esp_mem_read(void *opaque, hwaddr addr, 1346 unsigned int size) 1347 { 1348 SysBusESPState *sysbus = opaque; 1349 ESPState *s = ESP(&sysbus->esp); 1350 uint32_t saddr; 1351 1352 saddr = addr >> sysbus->it_shift; 1353 return esp_reg_read(s, saddr); 1354 } 1355 1356 static const MemoryRegionOps sysbus_esp_mem_ops = { 1357 .read = sysbus_esp_mem_read, 1358 .write = sysbus_esp_mem_write, 1359 .endianness = DEVICE_NATIVE_ENDIAN, 1360 .valid.accepts = esp_mem_accepts, 1361 }; 1362 1363 static void sysbus_esp_pdma_write(void *opaque, hwaddr addr, 1364 uint64_t val, unsigned int size) 1365 { 1366 SysBusESPState *sysbus = opaque; 1367 ESPState *s = ESP(&sysbus->esp); 1368 1369 trace_esp_pdma_write(size); 1370 1371 switch (size) { 1372 case 1: 1373 esp_pdma_write(s, val); 1374 break; 1375 case 2: 1376 esp_pdma_write(s, val >> 8); 1377 esp_pdma_write(s, val); 1378 break; 1379 } 1380 esp_pdma_cb(s); 1381 } 1382 1383 static uint64_t sysbus_esp_pdma_read(void *opaque, hwaddr addr, 1384 unsigned int size) 1385 { 1386 SysBusESPState *sysbus = opaque; 1387 ESPState *s = ESP(&sysbus->esp); 1388 uint64_t val = 0; 1389 1390 trace_esp_pdma_read(size); 1391 1392 switch (size) { 1393 case 1: 1394 val = esp_pdma_read(s); 1395 break; 1396 case 2: 1397 val = esp_pdma_read(s); 1398 val = (val << 8) | esp_pdma_read(s); 1399 break; 1400 } 1401 if (fifo8_num_used(&s->fifo) < 2) { 1402 esp_pdma_cb(s); 1403 } 1404 return val; 1405 } 1406 1407 static void *esp_load_request(QEMUFile *f, SCSIRequest *req) 1408 { 1409 ESPState *s = container_of(req->bus, ESPState, bus); 1410 1411 scsi_req_ref(req); 1412 s->current_req = req; 1413 return s; 1414 } 1415 1416 static const MemoryRegionOps sysbus_esp_pdma_ops = { 1417 .read = sysbus_esp_pdma_read, 1418 .write = sysbus_esp_pdma_write, 1419 .endianness = DEVICE_NATIVE_ENDIAN, 1420 .valid.min_access_size = 1, 1421 .valid.max_access_size = 4, 1422 .impl.min_access_size = 1, 1423 .impl.max_access_size = 2, 1424 }; 1425 1426 static const struct SCSIBusInfo esp_scsi_info = { 1427 .tcq = false, 1428 .max_target = ESP_MAX_DEVS, 1429 .max_lun = 7, 1430 1431 .load_request = esp_load_request, 1432 .transfer_data = esp_transfer_data, 1433 .complete = esp_command_complete, 1434 .cancel = esp_request_cancelled 1435 }; 1436 1437 static void sysbus_esp_gpio_demux(void *opaque, int irq, int level) 1438 { 1439 SysBusESPState *sysbus = SYSBUS_ESP(opaque); 1440 ESPState *s = ESP(&sysbus->esp); 1441 1442 switch (irq) { 1443 case 0: 1444 parent_esp_reset(s, irq, level); 1445 break; 1446 case 1: 1447 esp_dma_enable(s, irq, level); 1448 break; 1449 } 1450 } 1451 1452 static void sysbus_esp_realize(DeviceState *dev, Error **errp) 1453 { 1454 SysBusDevice *sbd = SYS_BUS_DEVICE(dev); 1455 SysBusESPState *sysbus = SYSBUS_ESP(dev); 1456 ESPState *s = ESP(&sysbus->esp); 1457 1458 if (!qdev_realize(DEVICE(s), NULL, errp)) { 1459 return; 1460 } 1461 1462 sysbus_init_irq(sbd, &s->irq); 1463 sysbus_init_irq(sbd, &s->irq_data); 1464 assert(sysbus->it_shift != -1); 1465 1466 s->chip_id = TCHI_FAS100A; 1467 memory_region_init_io(&sysbus->iomem, OBJECT(sysbus), &sysbus_esp_mem_ops, 1468 sysbus, "esp-regs", ESP_REGS << sysbus->it_shift); 1469 sysbus_init_mmio(sbd, &sysbus->iomem); 1470 memory_region_init_io(&sysbus->pdma, OBJECT(sysbus), &sysbus_esp_pdma_ops, 1471 sysbus, "esp-pdma", 4); 1472 sysbus_init_mmio(sbd, &sysbus->pdma); 1473 1474 qdev_init_gpio_in(dev, sysbus_esp_gpio_demux, 2); 1475 1476 scsi_bus_init(&s->bus, sizeof(s->bus), dev, &esp_scsi_info); 1477 } 1478 1479 static void sysbus_esp_hard_reset(DeviceState *dev) 1480 { 1481 SysBusESPState *sysbus = SYSBUS_ESP(dev); 1482 ESPState *s = ESP(&sysbus->esp); 1483 1484 esp_hard_reset(s); 1485 } 1486 1487 static void sysbus_esp_init(Object *obj) 1488 { 1489 SysBusESPState *sysbus = SYSBUS_ESP(obj); 1490 1491 object_initialize_child(obj, "esp", &sysbus->esp, TYPE_ESP); 1492 } 1493 1494 static const VMStateDescription vmstate_sysbus_esp_scsi = { 1495 .name = "sysbusespscsi", 1496 .version_id = 2, 1497 .minimum_version_id = 1, 1498 .pre_save = esp_pre_save, 1499 .fields = (const VMStateField[]) { 1500 VMSTATE_UINT8_V(esp.mig_version_id, SysBusESPState, 2), 1501 VMSTATE_STRUCT(esp, SysBusESPState, 0, vmstate_esp, ESPState), 1502 VMSTATE_END_OF_LIST() 1503 } 1504 }; 1505 1506 static void sysbus_esp_class_init(ObjectClass *klass, void *data) 1507 { 1508 DeviceClass *dc = DEVICE_CLASS(klass); 1509 1510 dc->realize = sysbus_esp_realize; 1511 dc->reset = sysbus_esp_hard_reset; 1512 dc->vmsd = &vmstate_sysbus_esp_scsi; 1513 set_bit(DEVICE_CATEGORY_STORAGE, dc->categories); 1514 } 1515 1516 static const TypeInfo sysbus_esp_info = { 1517 .name = TYPE_SYSBUS_ESP, 1518 .parent = TYPE_SYS_BUS_DEVICE, 1519 .instance_init = sysbus_esp_init, 1520 .instance_size = sizeof(SysBusESPState), 1521 .class_init = sysbus_esp_class_init, 1522 }; 1523 1524 static void esp_finalize(Object *obj) 1525 { 1526 ESPState *s = ESP(obj); 1527 1528 fifo8_destroy(&s->fifo); 1529 fifo8_destroy(&s->cmdfifo); 1530 } 1531 1532 static void esp_init(Object *obj) 1533 { 1534 ESPState *s = ESP(obj); 1535 1536 fifo8_create(&s->fifo, ESP_FIFO_SZ); 1537 fifo8_create(&s->cmdfifo, ESP_CMDFIFO_SZ); 1538 } 1539 1540 static void esp_class_init(ObjectClass *klass, void *data) 1541 { 1542 DeviceClass *dc = DEVICE_CLASS(klass); 1543 1544 /* internal device for sysbusesp/pciespscsi, not user-creatable */ 1545 dc->user_creatable = false; 1546 set_bit(DEVICE_CATEGORY_STORAGE, dc->categories); 1547 } 1548 1549 static const TypeInfo esp_info = { 1550 .name = TYPE_ESP, 1551 .parent = TYPE_DEVICE, 1552 .instance_init = esp_init, 1553 .instance_finalize = esp_finalize, 1554 .instance_size = sizeof(ESPState), 1555 .class_init = esp_class_init, 1556 }; 1557 1558 static void esp_register_types(void) 1559 { 1560 type_register_static(&sysbus_esp_info); 1561 type_register_static(&esp_info); 1562 } 1563 1564 type_init(esp_register_types) 1565