1 /* 2 * QEMU ESP/NCR53C9x emulation 3 * 4 * Copyright (c) 2005-2006 Fabrice Bellard 5 * Copyright (c) 2012 Herve Poussineau 6 * 7 * Permission is hereby granted, free of charge, to any person obtaining a copy 8 * of this software and associated documentation files (the "Software"), to deal 9 * in the Software without restriction, including without limitation the rights 10 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 11 * copies of the Software, and to permit persons to whom the Software is 12 * furnished to do so, subject to the following conditions: 13 * 14 * The above copyright notice and this permission notice shall be included in 15 * all copies or substantial portions of the Software. 16 * 17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 22 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 23 * THE SOFTWARE. 24 */ 25 26 #include "qemu/osdep.h" 27 #include "hw/sysbus.h" 28 #include "migration/vmstate.h" 29 #include "hw/irq.h" 30 #include "hw/scsi/esp.h" 31 #include "trace.h" 32 #include "qemu/log.h" 33 #include "qemu/module.h" 34 35 /* 36 * On Sparc32, this is the ESP (NCR53C90) part of chip STP2000 (Master I/O), 37 * also produced as NCR89C100. See 38 * http://www.ibiblio.org/pub/historic-linux/early-ports/Sparc/NCR/NCR89C100.txt 39 * and 40 * http://www.ibiblio.org/pub/historic-linux/early-ports/Sparc/NCR/NCR53C9X.txt 41 * 42 * On Macintosh Quadra it is a NCR53C96. 43 */ 44 45 static void esp_raise_irq(ESPState *s) 46 { 47 if (!(s->rregs[ESP_RSTAT] & STAT_INT)) { 48 s->rregs[ESP_RSTAT] |= STAT_INT; 49 qemu_irq_raise(s->irq); 50 trace_esp_raise_irq(); 51 } 52 } 53 54 static void esp_lower_irq(ESPState *s) 55 { 56 if (s->rregs[ESP_RSTAT] & STAT_INT) { 57 s->rregs[ESP_RSTAT] &= ~STAT_INT; 58 qemu_irq_lower(s->irq); 59 trace_esp_lower_irq(); 60 } 61 } 62 63 static void esp_raise_drq(ESPState *s) 64 { 65 qemu_irq_raise(s->irq_data); 66 trace_esp_raise_drq(); 67 } 68 69 static void esp_lower_drq(ESPState *s) 70 { 71 qemu_irq_lower(s->irq_data); 72 trace_esp_lower_drq(); 73 } 74 75 void esp_dma_enable(ESPState *s, int irq, int level) 76 { 77 if (level) { 78 s->dma_enabled = 1; 79 trace_esp_dma_enable(); 80 if (s->dma_cb) { 81 s->dma_cb(s); 82 s->dma_cb = NULL; 83 } 84 } else { 85 trace_esp_dma_disable(); 86 s->dma_enabled = 0; 87 } 88 } 89 90 void esp_request_cancelled(SCSIRequest *req) 91 { 92 ESPState *s = req->hba_private; 93 94 if (req == s->current_req) { 95 scsi_req_unref(s->current_req); 96 s->current_req = NULL; 97 s->current_dev = NULL; 98 s->async_len = 0; 99 } 100 } 101 102 static void esp_fifo_push(Fifo8 *fifo, uint8_t val) 103 { 104 if (fifo8_num_used(fifo) == fifo->capacity) { 105 trace_esp_error_fifo_overrun(); 106 return; 107 } 108 109 fifo8_push(fifo, val); 110 } 111 112 static uint8_t esp_fifo_pop(Fifo8 *fifo) 113 { 114 if (fifo8_is_empty(fifo)) { 115 return 0; 116 } 117 118 return fifo8_pop(fifo); 119 } 120 121 static uint32_t esp_fifo_pop_buf(Fifo8 *fifo, uint8_t *dest, int maxlen) 122 { 123 const uint8_t *buf; 124 uint32_t n, n2; 125 int len; 126 127 if (maxlen == 0) { 128 return 0; 129 } 130 131 len = maxlen; 132 buf = fifo8_pop_buf(fifo, len, &n); 133 if (dest) { 134 memcpy(dest, buf, n); 135 } 136 137 /* Add FIFO wraparound if needed */ 138 len -= n; 139 len = MIN(len, fifo8_num_used(fifo)); 140 if (len) { 141 buf = fifo8_pop_buf(fifo, len, &n2); 142 if (dest) { 143 memcpy(&dest[n], buf, n2); 144 } 145 n += n2; 146 } 147 148 return n; 149 } 150 151 static uint32_t esp_get_tc(ESPState *s) 152 { 153 uint32_t dmalen; 154 155 dmalen = s->rregs[ESP_TCLO]; 156 dmalen |= s->rregs[ESP_TCMID] << 8; 157 dmalen |= s->rregs[ESP_TCHI] << 16; 158 159 return dmalen; 160 } 161 162 static void esp_set_tc(ESPState *s, uint32_t dmalen) 163 { 164 uint32_t old_tc = esp_get_tc(s); 165 166 s->rregs[ESP_TCLO] = dmalen; 167 s->rregs[ESP_TCMID] = dmalen >> 8; 168 s->rregs[ESP_TCHI] = dmalen >> 16; 169 170 if (old_tc && dmalen == 0) { 171 s->rregs[ESP_RSTAT] |= STAT_TC; 172 } 173 } 174 175 static uint32_t esp_get_stc(ESPState *s) 176 { 177 uint32_t dmalen; 178 179 dmalen = s->wregs[ESP_TCLO]; 180 dmalen |= s->wregs[ESP_TCMID] << 8; 181 dmalen |= s->wregs[ESP_TCHI] << 16; 182 183 return dmalen; 184 } 185 186 static const char *esp_phase_names[8] = { 187 "DATA OUT", "DATA IN", "COMMAND", "STATUS", 188 "(reserved)", "(reserved)", "MESSAGE OUT", "MESSAGE IN" 189 }; 190 191 static void esp_set_phase(ESPState *s, uint8_t phase) 192 { 193 s->rregs[ESP_RSTAT] &= ~7; 194 s->rregs[ESP_RSTAT] |= phase; 195 196 trace_esp_set_phase(esp_phase_names[phase]); 197 } 198 199 static uint8_t esp_pdma_read(ESPState *s) 200 { 201 uint8_t val; 202 203 val = esp_fifo_pop(&s->fifo); 204 return val; 205 } 206 207 static void esp_pdma_write(ESPState *s, uint8_t val) 208 { 209 uint32_t dmalen = esp_get_tc(s); 210 211 if (dmalen == 0) { 212 return; 213 } 214 215 esp_fifo_push(&s->fifo, val); 216 217 dmalen--; 218 esp_set_tc(s, dmalen); 219 } 220 221 static void esp_set_pdma_cb(ESPState *s, enum pdma_cb cb) 222 { 223 s->pdma_cb = cb; 224 } 225 226 static int esp_select(ESPState *s) 227 { 228 int target; 229 230 target = s->wregs[ESP_WBUSID] & BUSID_DID; 231 232 s->ti_size = 0; 233 234 if (s->current_req) { 235 /* Started a new command before the old one finished. Cancel it. */ 236 scsi_req_cancel(s->current_req); 237 } 238 239 s->current_dev = scsi_device_find(&s->bus, 0, target, 0); 240 if (!s->current_dev) { 241 /* No such drive */ 242 s->rregs[ESP_RSTAT] = 0; 243 s->rregs[ESP_RINTR] = INTR_DC; 244 s->rregs[ESP_RSEQ] = SEQ_0; 245 esp_raise_irq(s); 246 return -1; 247 } 248 249 /* 250 * Note that we deliberately don't raise the IRQ here: this will be done 251 * either in do_command_phase() for DATA OUT transfers or by the deferred 252 * IRQ mechanism in esp_transfer_data() for DATA IN transfers 253 */ 254 s->rregs[ESP_RINTR] |= INTR_FC; 255 s->rregs[ESP_RSEQ] = SEQ_CD; 256 return 0; 257 } 258 259 static uint32_t get_cmd(ESPState *s, uint32_t maxlen) 260 { 261 uint8_t buf[ESP_CMDFIFO_SZ]; 262 uint32_t dmalen, n; 263 int target; 264 265 target = s->wregs[ESP_WBUSID] & BUSID_DID; 266 if (s->dma) { 267 dmalen = MIN(esp_get_tc(s), maxlen); 268 if (dmalen == 0) { 269 return 0; 270 } 271 if (s->dma_memory_read) { 272 s->dma_memory_read(s->dma_opaque, buf, dmalen); 273 dmalen = MIN(fifo8_num_free(&s->cmdfifo), dmalen); 274 fifo8_push_all(&s->cmdfifo, buf, dmalen); 275 esp_set_tc(s, esp_get_tc(s) - dmalen); 276 } else { 277 return 0; 278 } 279 } else { 280 dmalen = MIN(fifo8_num_used(&s->fifo), maxlen); 281 if (dmalen == 0) { 282 return 0; 283 } 284 n = esp_fifo_pop_buf(&s->fifo, buf, dmalen); 285 n = MIN(fifo8_num_free(&s->cmdfifo), n); 286 fifo8_push_all(&s->cmdfifo, buf, n); 287 } 288 trace_esp_get_cmd(dmalen, target); 289 290 return dmalen; 291 } 292 293 static void do_command_phase(ESPState *s) 294 { 295 uint32_t cmdlen; 296 int32_t datalen; 297 SCSIDevice *current_lun; 298 uint8_t buf[ESP_CMDFIFO_SZ]; 299 300 trace_esp_do_command_phase(s->lun); 301 cmdlen = fifo8_num_used(&s->cmdfifo); 302 if (!cmdlen || !s->current_dev) { 303 return; 304 } 305 esp_fifo_pop_buf(&s->cmdfifo, buf, cmdlen); 306 307 current_lun = scsi_device_find(&s->bus, 0, s->current_dev->id, s->lun); 308 if (!current_lun) { 309 /* No such drive */ 310 s->rregs[ESP_RSTAT] = 0; 311 s->rregs[ESP_RINTR] = INTR_DC; 312 s->rregs[ESP_RSEQ] = SEQ_0; 313 esp_raise_irq(s); 314 return; 315 } 316 317 s->current_req = scsi_req_new(current_lun, 0, s->lun, buf, cmdlen, s); 318 datalen = scsi_req_enqueue(s->current_req); 319 s->ti_size = datalen; 320 fifo8_reset(&s->cmdfifo); 321 if (datalen != 0) { 322 s->ti_cmd = 0; 323 if (datalen > 0) { 324 /* 325 * Switch to DATA IN phase but wait until initial data xfer is 326 * complete before raising the command completion interrupt 327 */ 328 s->data_in_ready = false; 329 esp_set_phase(s, STAT_DI); 330 } else { 331 esp_set_phase(s, STAT_DO); 332 s->rregs[ESP_RINTR] |= INTR_BS | INTR_FC; 333 esp_raise_irq(s); 334 esp_lower_drq(s); 335 } 336 scsi_req_continue(s->current_req); 337 return; 338 } 339 } 340 341 static void do_message_phase(ESPState *s) 342 { 343 if (s->cmdfifo_cdb_offset) { 344 uint8_t message = esp_fifo_pop(&s->cmdfifo); 345 346 trace_esp_do_identify(message); 347 s->lun = message & 7; 348 s->cmdfifo_cdb_offset--; 349 } 350 351 /* Ignore extended messages for now */ 352 if (s->cmdfifo_cdb_offset) { 353 int len = MIN(s->cmdfifo_cdb_offset, fifo8_num_used(&s->cmdfifo)); 354 esp_fifo_pop_buf(&s->cmdfifo, NULL, len); 355 s->cmdfifo_cdb_offset = 0; 356 } 357 } 358 359 static void do_cmd(ESPState *s) 360 { 361 do_message_phase(s); 362 assert(s->cmdfifo_cdb_offset == 0); 363 do_command_phase(s); 364 } 365 366 static void satn_pdma_cb(ESPState *s) 367 { 368 uint8_t buf[ESP_FIFO_SZ]; 369 int n; 370 371 /* Copy FIFO into cmdfifo */ 372 n = esp_fifo_pop_buf(&s->fifo, buf, fifo8_num_used(&s->fifo)); 373 n = MIN(fifo8_num_free(&s->cmdfifo), n); 374 fifo8_push_all(&s->cmdfifo, buf, n); 375 376 if (!esp_get_tc(s) && !fifo8_is_empty(&s->cmdfifo)) { 377 s->cmdfifo_cdb_offset = 1; 378 s->do_cmd = 0; 379 do_cmd(s); 380 } 381 } 382 383 static void handle_satn(ESPState *s) 384 { 385 int32_t cmdlen; 386 387 if (s->dma && !s->dma_enabled) { 388 s->dma_cb = handle_satn; 389 return; 390 } 391 esp_set_pdma_cb(s, SATN_PDMA_CB); 392 if (esp_select(s) < 0) { 393 return; 394 } 395 cmdlen = get_cmd(s, ESP_CMDFIFO_SZ); 396 if (cmdlen > 0) { 397 s->cmdfifo_cdb_offset = 1; 398 s->do_cmd = 0; 399 do_cmd(s); 400 } else if (cmdlen == 0) { 401 if (s->dma) { 402 esp_raise_drq(s); 403 } 404 s->do_cmd = 1; 405 /* Target present, but no cmd yet - switch to command phase */ 406 s->rregs[ESP_RSEQ] = SEQ_CD; 407 esp_set_phase(s, STAT_CD); 408 } 409 } 410 411 static void s_without_satn_pdma_cb(ESPState *s) 412 { 413 uint8_t buf[ESP_FIFO_SZ]; 414 int n; 415 416 /* Copy FIFO into cmdfifo */ 417 n = esp_fifo_pop_buf(&s->fifo, buf, fifo8_num_used(&s->fifo)); 418 n = MIN(fifo8_num_free(&s->cmdfifo), n); 419 fifo8_push_all(&s->cmdfifo, buf, n); 420 421 if (!esp_get_tc(s) && !fifo8_is_empty(&s->cmdfifo)) { 422 s->cmdfifo_cdb_offset = 0; 423 s->do_cmd = 0; 424 do_cmd(s); 425 } 426 } 427 428 static void handle_s_without_atn(ESPState *s) 429 { 430 int32_t cmdlen; 431 432 if (s->dma && !s->dma_enabled) { 433 s->dma_cb = handle_s_without_atn; 434 return; 435 } 436 esp_set_pdma_cb(s, S_WITHOUT_SATN_PDMA_CB); 437 if (esp_select(s) < 0) { 438 return; 439 } 440 cmdlen = get_cmd(s, ESP_CMDFIFO_SZ); 441 if (cmdlen > 0) { 442 s->cmdfifo_cdb_offset = 0; 443 s->do_cmd = 0; 444 do_cmd(s); 445 } else if (cmdlen == 0) { 446 if (s->dma) { 447 esp_raise_drq(s); 448 } 449 s->do_cmd = 1; 450 /* Target present, but no cmd yet - switch to command phase */ 451 s->rregs[ESP_RSEQ] = SEQ_CD; 452 esp_set_phase(s, STAT_CD); 453 } 454 } 455 456 static void satn_stop_pdma_cb(ESPState *s) 457 { 458 uint8_t buf[ESP_FIFO_SZ]; 459 int n; 460 461 /* Copy FIFO into cmdfifo */ 462 n = esp_fifo_pop_buf(&s->fifo, buf, fifo8_num_used(&s->fifo)); 463 n = MIN(fifo8_num_free(&s->cmdfifo), n); 464 fifo8_push_all(&s->cmdfifo, buf, n); 465 466 if (!esp_get_tc(s) && !fifo8_is_empty(&s->cmdfifo)) { 467 trace_esp_handle_satn_stop(fifo8_num_used(&s->cmdfifo)); 468 s->do_cmd = 1; 469 s->cmdfifo_cdb_offset = 1; 470 esp_set_phase(s, STAT_CD); 471 s->rregs[ESP_RSTAT] |= STAT_TC; 472 s->rregs[ESP_RINTR] |= INTR_BS | INTR_FC; 473 s->rregs[ESP_RSEQ] = SEQ_CD; 474 esp_raise_irq(s); 475 } 476 } 477 478 static void handle_satn_stop(ESPState *s) 479 { 480 int32_t cmdlen; 481 482 if (s->dma && !s->dma_enabled) { 483 s->dma_cb = handle_satn_stop; 484 return; 485 } 486 esp_set_pdma_cb(s, SATN_STOP_PDMA_CB); 487 if (esp_select(s) < 0) { 488 return; 489 } 490 cmdlen = get_cmd(s, 1); 491 if (cmdlen > 0) { 492 trace_esp_handle_satn_stop(fifo8_num_used(&s->cmdfifo)); 493 s->do_cmd = 1; 494 s->cmdfifo_cdb_offset = 1; 495 esp_set_phase(s, STAT_MO); 496 s->rregs[ESP_RINTR] |= INTR_BS | INTR_FC; 497 s->rregs[ESP_RSEQ] = SEQ_MO; 498 esp_raise_irq(s); 499 } else if (cmdlen == 0) { 500 if (s->dma) { 501 esp_raise_drq(s); 502 } 503 s->do_cmd = 1; 504 /* Target present, switch to message out phase */ 505 s->rregs[ESP_RSEQ] = SEQ_MO; 506 esp_set_phase(s, STAT_MO); 507 } 508 } 509 510 static void write_response_pdma_cb(ESPState *s) 511 { 512 esp_set_phase(s, STAT_ST); 513 s->rregs[ESP_RINTR] |= INTR_BS | INTR_FC; 514 s->rregs[ESP_RSEQ] = SEQ_CD; 515 esp_raise_irq(s); 516 } 517 518 static void write_response(ESPState *s) 519 { 520 uint8_t buf[2]; 521 522 trace_esp_write_response(s->status); 523 524 buf[0] = s->status; 525 buf[1] = 0; 526 527 if (s->dma) { 528 if (s->dma_memory_write) { 529 s->dma_memory_write(s->dma_opaque, buf, 2); 530 esp_set_phase(s, STAT_ST); 531 s->rregs[ESP_RINTR] |= INTR_BS | INTR_FC; 532 s->rregs[ESP_RSEQ] = SEQ_CD; 533 } else { 534 esp_set_pdma_cb(s, WRITE_RESPONSE_PDMA_CB); 535 esp_raise_drq(s); 536 return; 537 } 538 } else { 539 fifo8_reset(&s->fifo); 540 fifo8_push_all(&s->fifo, buf, 2); 541 s->rregs[ESP_RFLAGS] = 2; 542 } 543 esp_raise_irq(s); 544 } 545 546 static void esp_dma_done(ESPState *s) 547 { 548 s->rregs[ESP_RINTR] |= INTR_BS; 549 s->rregs[ESP_RFLAGS] = 0; 550 esp_raise_irq(s); 551 } 552 553 static void do_dma_pdma_cb(ESPState *s) 554 { 555 int to_device = ((s->rregs[ESP_RSTAT] & 7) == STAT_DO); 556 uint8_t buf[ESP_CMDFIFO_SZ]; 557 int len; 558 uint32_t n; 559 560 if (s->do_cmd) { 561 /* Copy FIFO into cmdfifo */ 562 n = esp_fifo_pop_buf(&s->fifo, buf, fifo8_num_used(&s->fifo)); 563 n = MIN(fifo8_num_free(&s->cmdfifo), n); 564 fifo8_push_all(&s->cmdfifo, buf, n); 565 566 /* Ensure we have received complete command after SATN and stop */ 567 if (esp_get_tc(s) || fifo8_is_empty(&s->cmdfifo)) { 568 return; 569 } 570 571 s->ti_size = 0; 572 if ((s->rregs[ESP_RSTAT] & 7) == STAT_CD) { 573 /* No command received */ 574 if (s->cmdfifo_cdb_offset == fifo8_num_used(&s->cmdfifo)) { 575 return; 576 } 577 578 /* Command has been received */ 579 s->do_cmd = 0; 580 do_cmd(s); 581 } else { 582 /* 583 * Extra message out bytes received: update cmdfifo_cdb_offset 584 * and then switch to command phase 585 */ 586 s->cmdfifo_cdb_offset = fifo8_num_used(&s->cmdfifo); 587 esp_set_phase(s, STAT_CD); 588 s->rregs[ESP_RSEQ] = SEQ_CD; 589 s->rregs[ESP_RINTR] |= INTR_BS; 590 esp_raise_irq(s); 591 } 592 return; 593 } 594 595 if (!s->current_req) { 596 return; 597 } 598 599 if (to_device) { 600 /* Copy FIFO data to device */ 601 len = MIN(s->async_len, ESP_FIFO_SZ); 602 len = MIN(len, fifo8_num_used(&s->fifo)); 603 n = esp_fifo_pop_buf(&s->fifo, s->async_buf, len); 604 s->async_buf += n; 605 s->async_len -= n; 606 s->ti_size += n; 607 608 if (n < len) { 609 /* Unaligned accesses can cause FIFO wraparound */ 610 len = len - n; 611 n = esp_fifo_pop_buf(&s->fifo, s->async_buf, len); 612 s->async_buf += n; 613 s->async_len -= n; 614 s->ti_size += n; 615 } 616 617 if (s->async_len == 0) { 618 scsi_req_continue(s->current_req); 619 return; 620 } 621 622 if (esp_get_tc(s) == 0) { 623 esp_lower_drq(s); 624 esp_dma_done(s); 625 } 626 627 return; 628 } else { 629 if (s->async_len == 0) { 630 /* Defer until the scsi layer has completed */ 631 scsi_req_continue(s->current_req); 632 s->data_in_ready = false; 633 return; 634 } 635 636 if (esp_get_tc(s) == 0) { 637 esp_lower_drq(s); 638 esp_dma_done(s); 639 } 640 641 /* Copy device data to FIFO */ 642 len = MIN(s->async_len, esp_get_tc(s)); 643 len = MIN(len, fifo8_num_free(&s->fifo)); 644 fifo8_push_all(&s->fifo, s->async_buf, len); 645 s->async_buf += len; 646 s->async_len -= len; 647 s->ti_size -= len; 648 esp_set_tc(s, esp_get_tc(s) - len); 649 } 650 } 651 652 static void esp_do_dma(ESPState *s) 653 { 654 uint32_t len, cmdlen; 655 int to_device = ((s->rregs[ESP_RSTAT] & 7) == STAT_DO); 656 uint8_t buf[ESP_CMDFIFO_SZ]; 657 658 len = esp_get_tc(s); 659 if (s->do_cmd) { 660 /* 661 * handle_ti_cmd() case: esp_do_dma() is called only from 662 * handle_ti_cmd() with do_cmd != NULL (see the assert()) 663 */ 664 cmdlen = fifo8_num_used(&s->cmdfifo); 665 trace_esp_do_dma(cmdlen, len); 666 if (s->dma_memory_read) { 667 len = MIN(len, fifo8_num_free(&s->cmdfifo)); 668 s->dma_memory_read(s->dma_opaque, buf, len); 669 fifo8_push_all(&s->cmdfifo, buf, len); 670 esp_set_tc(s, esp_get_tc(s) - len); 671 } else { 672 esp_set_pdma_cb(s, DO_DMA_PDMA_CB); 673 esp_raise_drq(s); 674 return; 675 } 676 trace_esp_handle_ti_cmd(cmdlen); 677 s->ti_size = 0; 678 if ((s->rregs[ESP_RSTAT] & 7) == STAT_CD) { 679 /* No command received */ 680 if (s->cmdfifo_cdb_offset == fifo8_num_used(&s->cmdfifo)) { 681 return; 682 } 683 684 /* Command has been received */ 685 s->do_cmd = 0; 686 do_cmd(s); 687 } else { 688 /* 689 * Extra message out bytes received: update cmdfifo_cdb_offset 690 * and then switch to command phase 691 */ 692 s->cmdfifo_cdb_offset = fifo8_num_used(&s->cmdfifo); 693 esp_set_phase(s, STAT_CD); 694 s->rregs[ESP_RSEQ] = SEQ_CD; 695 s->rregs[ESP_RINTR] |= INTR_BS; 696 esp_raise_irq(s); 697 } 698 return; 699 } 700 if (!s->current_req) { 701 return; 702 } 703 if (s->async_len == 0) { 704 /* Defer until data is available. */ 705 return; 706 } 707 if (len > s->async_len) { 708 len = s->async_len; 709 } 710 if (to_device) { 711 if (s->dma_memory_read) { 712 s->dma_memory_read(s->dma_opaque, s->async_buf, len); 713 714 esp_set_tc(s, esp_get_tc(s) - len); 715 s->async_buf += len; 716 s->async_len -= len; 717 s->ti_size += len; 718 719 if (s->async_len == 0) { 720 scsi_req_continue(s->current_req); 721 /* 722 * If there is still data to be read from the device then 723 * complete the DMA operation immediately. Otherwise defer 724 * until the scsi layer has completed. 725 */ 726 return; 727 } 728 729 /* Partially filled a scsi buffer. Complete immediately. */ 730 esp_dma_done(s); 731 esp_lower_drq(s); 732 } else { 733 esp_set_pdma_cb(s, DO_DMA_PDMA_CB); 734 esp_raise_drq(s); 735 } 736 } else { 737 if (s->dma_memory_write) { 738 s->dma_memory_write(s->dma_opaque, s->async_buf, len); 739 740 esp_set_tc(s, esp_get_tc(s) - len); 741 s->async_buf += len; 742 s->async_len -= len; 743 s->ti_size -= len; 744 745 if (s->async_len == 0) { 746 scsi_req_continue(s->current_req); 747 /* 748 * If there is still data to be read from the device then 749 * complete the DMA operation immediately. Otherwise defer 750 * until the scsi layer has completed. 751 */ 752 if (esp_get_tc(s) != 0 || s->ti_size == 0) { 753 return; 754 } 755 } 756 757 /* Partially filled a scsi buffer. Complete immediately. */ 758 esp_dma_done(s); 759 esp_lower_drq(s); 760 } else { 761 /* Adjust TC for any leftover data in the FIFO */ 762 if (!fifo8_is_empty(&s->fifo)) { 763 esp_set_tc(s, esp_get_tc(s) - fifo8_num_used(&s->fifo)); 764 } 765 766 /* Copy device data to FIFO */ 767 len = MIN(len, fifo8_num_free(&s->fifo)); 768 fifo8_push_all(&s->fifo, s->async_buf, len); 769 s->async_buf += len; 770 s->async_len -= len; 771 s->ti_size -= len; 772 esp_set_tc(s, esp_get_tc(s) - len); 773 esp_set_pdma_cb(s, DO_DMA_PDMA_CB); 774 esp_raise_drq(s); 775 } 776 } 777 } 778 779 static void esp_do_nodma(ESPState *s) 780 { 781 int to_device = ((s->rregs[ESP_RSTAT] & 7) == STAT_DO); 782 uint8_t buf[ESP_FIFO_SZ]; 783 uint32_t cmdlen; 784 int len, n; 785 786 if (s->do_cmd) { 787 /* Copy FIFO into cmdfifo */ 788 n = esp_fifo_pop_buf(&s->fifo, buf, fifo8_num_used(&s->fifo)); 789 n = MIN(fifo8_num_free(&s->cmdfifo), n); 790 fifo8_push_all(&s->cmdfifo, buf, n); 791 792 cmdlen = fifo8_num_used(&s->cmdfifo); 793 trace_esp_handle_ti_cmd(cmdlen); 794 s->ti_size = 0; 795 if ((s->rregs[ESP_RSTAT] & 7) == STAT_CD) { 796 /* No command received */ 797 if (s->cmdfifo_cdb_offset == fifo8_num_used(&s->cmdfifo)) { 798 return; 799 } 800 801 /* Command has been received */ 802 s->do_cmd = 0; 803 do_cmd(s); 804 } else { 805 /* 806 * Extra message out bytes received: update cmdfifo_cdb_offset 807 * and then switch to command phase 808 */ 809 s->cmdfifo_cdb_offset = fifo8_num_used(&s->cmdfifo); 810 esp_set_phase(s, STAT_CD); 811 s->rregs[ESP_RSEQ] = SEQ_CD; 812 s->rregs[ESP_RINTR] |= INTR_BS; 813 esp_raise_irq(s); 814 } 815 return; 816 } 817 818 if (!s->current_req) { 819 return; 820 } 821 822 if (s->async_len == 0) { 823 /* Defer until data is available. */ 824 return; 825 } 826 827 if (to_device) { 828 len = MIN(s->async_len, ESP_FIFO_SZ); 829 len = MIN(len, fifo8_num_used(&s->fifo)); 830 esp_fifo_pop_buf(&s->fifo, s->async_buf, len); 831 s->async_buf += len; 832 s->async_len -= len; 833 s->ti_size += len; 834 } else { 835 if (fifo8_is_empty(&s->fifo)) { 836 fifo8_push(&s->fifo, s->async_buf[0]); 837 s->async_buf++; 838 s->async_len--; 839 s->ti_size--; 840 } 841 } 842 843 if (s->async_len == 0) { 844 scsi_req_continue(s->current_req); 845 return; 846 } 847 848 s->rregs[ESP_RINTR] |= INTR_BS; 849 esp_raise_irq(s); 850 } 851 852 static void esp_pdma_cb(ESPState *s) 853 { 854 switch (s->pdma_cb) { 855 case SATN_PDMA_CB: 856 satn_pdma_cb(s); 857 break; 858 case S_WITHOUT_SATN_PDMA_CB: 859 s_without_satn_pdma_cb(s); 860 break; 861 case SATN_STOP_PDMA_CB: 862 satn_stop_pdma_cb(s); 863 break; 864 case WRITE_RESPONSE_PDMA_CB: 865 write_response_pdma_cb(s); 866 break; 867 case DO_DMA_PDMA_CB: 868 do_dma_pdma_cb(s); 869 break; 870 default: 871 g_assert_not_reached(); 872 } 873 } 874 875 void esp_command_complete(SCSIRequest *req, size_t resid) 876 { 877 ESPState *s = req->hba_private; 878 int to_device = ((s->rregs[ESP_RSTAT] & 7) == STAT_DO); 879 880 trace_esp_command_complete(); 881 882 /* 883 * Non-DMA transfers from the target will leave the last byte in 884 * the FIFO so don't reset ti_size in this case 885 */ 886 if (s->dma || to_device) { 887 if (s->ti_size != 0) { 888 trace_esp_command_complete_unexpected(); 889 } 890 s->ti_size = 0; 891 } 892 893 s->async_len = 0; 894 if (req->status) { 895 trace_esp_command_complete_fail(); 896 } 897 s->status = req->status; 898 899 /* 900 * If the transfer is finished, switch to status phase. For non-DMA 901 * transfers from the target the last byte is still in the FIFO 902 */ 903 if (s->ti_size == 0) { 904 esp_set_phase(s, STAT_ST); 905 esp_dma_done(s); 906 esp_lower_drq(s); 907 } 908 909 if (s->current_req) { 910 scsi_req_unref(s->current_req); 911 s->current_req = NULL; 912 s->current_dev = NULL; 913 } 914 } 915 916 void esp_transfer_data(SCSIRequest *req, uint32_t len) 917 { 918 ESPState *s = req->hba_private; 919 int to_device = ((s->rregs[ESP_RSTAT] & 7) == STAT_DO); 920 uint32_t dmalen = esp_get_tc(s); 921 922 assert(!s->do_cmd); 923 trace_esp_transfer_data(dmalen, s->ti_size); 924 s->async_len = len; 925 s->async_buf = scsi_req_get_buf(req); 926 927 if (!to_device && !s->data_in_ready) { 928 /* 929 * Initial incoming data xfer is complete so raise command 930 * completion interrupt 931 */ 932 s->data_in_ready = true; 933 s->rregs[ESP_RINTR] |= INTR_BS; 934 esp_raise_irq(s); 935 } 936 937 if (s->ti_cmd == 0) { 938 /* 939 * Always perform the initial transfer upon reception of the next TI 940 * command to ensure the DMA/non-DMA status of the command is correct. 941 * It is not possible to use s->dma directly in the section below as 942 * some OSs send non-DMA NOP commands after a DMA transfer. Hence if the 943 * async data transfer is delayed then s->dma is set incorrectly. 944 */ 945 return; 946 } 947 948 if (s->ti_cmd == (CMD_TI | CMD_DMA)) { 949 if (dmalen) { 950 esp_do_dma(s); 951 } else if (s->ti_size <= 0) { 952 /* 953 * If this was the last part of a DMA transfer then the 954 * completion interrupt is deferred to here. 955 */ 956 esp_dma_done(s); 957 esp_lower_drq(s); 958 } 959 } else if (s->ti_cmd == CMD_TI) { 960 esp_do_nodma(s); 961 } 962 } 963 964 static void handle_ti(ESPState *s) 965 { 966 uint32_t dmalen; 967 968 if (s->dma && !s->dma_enabled) { 969 s->dma_cb = handle_ti; 970 return; 971 } 972 973 s->ti_cmd = s->rregs[ESP_CMD]; 974 if (s->dma) { 975 dmalen = esp_get_tc(s); 976 trace_esp_handle_ti(dmalen); 977 esp_do_dma(s); 978 } else { 979 trace_esp_handle_ti(s->ti_size); 980 esp_do_nodma(s); 981 } 982 } 983 984 void esp_hard_reset(ESPState *s) 985 { 986 memset(s->rregs, 0, ESP_REGS); 987 memset(s->wregs, 0, ESP_REGS); 988 s->tchi_written = 0; 989 s->ti_size = 0; 990 s->async_len = 0; 991 fifo8_reset(&s->fifo); 992 fifo8_reset(&s->cmdfifo); 993 s->dma = 0; 994 s->do_cmd = 0; 995 s->dma_cb = NULL; 996 997 s->rregs[ESP_CFG1] = 7; 998 } 999 1000 static void esp_soft_reset(ESPState *s) 1001 { 1002 qemu_irq_lower(s->irq); 1003 qemu_irq_lower(s->irq_data); 1004 esp_hard_reset(s); 1005 } 1006 1007 static void esp_bus_reset(ESPState *s) 1008 { 1009 bus_cold_reset(BUS(&s->bus)); 1010 } 1011 1012 static void parent_esp_reset(ESPState *s, int irq, int level) 1013 { 1014 if (level) { 1015 esp_soft_reset(s); 1016 } 1017 } 1018 1019 static void esp_run_cmd(ESPState *s) 1020 { 1021 uint8_t cmd = s->rregs[ESP_CMD]; 1022 1023 if (cmd & CMD_DMA) { 1024 s->dma = 1; 1025 /* Reload DMA counter. */ 1026 if (esp_get_stc(s) == 0) { 1027 esp_set_tc(s, 0x10000); 1028 } else { 1029 esp_set_tc(s, esp_get_stc(s)); 1030 } 1031 } else { 1032 s->dma = 0; 1033 } 1034 switch (cmd & CMD_CMD) { 1035 case CMD_NOP: 1036 trace_esp_mem_writeb_cmd_nop(cmd); 1037 break; 1038 case CMD_FLUSH: 1039 trace_esp_mem_writeb_cmd_flush(cmd); 1040 fifo8_reset(&s->fifo); 1041 break; 1042 case CMD_RESET: 1043 trace_esp_mem_writeb_cmd_reset(cmd); 1044 esp_soft_reset(s); 1045 break; 1046 case CMD_BUSRESET: 1047 trace_esp_mem_writeb_cmd_bus_reset(cmd); 1048 esp_bus_reset(s); 1049 if (!(s->wregs[ESP_CFG1] & CFG1_RESREPT)) { 1050 s->rregs[ESP_RINTR] |= INTR_RST; 1051 esp_raise_irq(s); 1052 } 1053 break; 1054 case CMD_TI: 1055 trace_esp_mem_writeb_cmd_ti(cmd); 1056 handle_ti(s); 1057 break; 1058 case CMD_ICCS: 1059 trace_esp_mem_writeb_cmd_iccs(cmd); 1060 write_response(s); 1061 s->rregs[ESP_RINTR] |= INTR_FC; 1062 esp_set_phase(s, STAT_MI); 1063 break; 1064 case CMD_MSGACC: 1065 trace_esp_mem_writeb_cmd_msgacc(cmd); 1066 s->rregs[ESP_RINTR] |= INTR_DC; 1067 s->rregs[ESP_RSEQ] = 0; 1068 s->rregs[ESP_RFLAGS] = 0; 1069 esp_raise_irq(s); 1070 break; 1071 case CMD_PAD: 1072 trace_esp_mem_writeb_cmd_pad(cmd); 1073 s->rregs[ESP_RSTAT] = STAT_TC; 1074 s->rregs[ESP_RINTR] |= INTR_FC; 1075 s->rregs[ESP_RSEQ] = 0; 1076 break; 1077 case CMD_SATN: 1078 trace_esp_mem_writeb_cmd_satn(cmd); 1079 break; 1080 case CMD_RSTATN: 1081 trace_esp_mem_writeb_cmd_rstatn(cmd); 1082 break; 1083 case CMD_SEL: 1084 trace_esp_mem_writeb_cmd_sel(cmd); 1085 handle_s_without_atn(s); 1086 break; 1087 case CMD_SELATN: 1088 trace_esp_mem_writeb_cmd_selatn(cmd); 1089 handle_satn(s); 1090 break; 1091 case CMD_SELATNS: 1092 trace_esp_mem_writeb_cmd_selatns(cmd); 1093 handle_satn_stop(s); 1094 break; 1095 case CMD_ENSEL: 1096 trace_esp_mem_writeb_cmd_ensel(cmd); 1097 s->rregs[ESP_RINTR] = 0; 1098 break; 1099 case CMD_DISSEL: 1100 trace_esp_mem_writeb_cmd_dissel(cmd); 1101 s->rregs[ESP_RINTR] = 0; 1102 esp_raise_irq(s); 1103 break; 1104 default: 1105 trace_esp_error_unhandled_command(cmd); 1106 break; 1107 } 1108 } 1109 1110 uint64_t esp_reg_read(ESPState *s, uint32_t saddr) 1111 { 1112 uint32_t val; 1113 1114 switch (saddr) { 1115 case ESP_FIFO: 1116 if (s->dma_memory_read && s->dma_memory_write && 1117 (s->rregs[ESP_RSTAT] & STAT_PIO_MASK) == 0) { 1118 /* Data out. */ 1119 qemu_log_mask(LOG_UNIMP, "esp: PIO data read not implemented\n"); 1120 s->rregs[ESP_FIFO] = 0; 1121 } else { 1122 if ((s->rregs[ESP_RSTAT] & 0x7) == STAT_DI) { 1123 if (s->ti_size) { 1124 esp_do_nodma(s); 1125 } else { 1126 /* 1127 * The last byte of a non-DMA transfer has been read out 1128 * of the FIFO so switch to status phase 1129 */ 1130 esp_set_phase(s, STAT_ST); 1131 } 1132 } 1133 s->rregs[ESP_FIFO] = esp_fifo_pop(&s->fifo); 1134 } 1135 val = s->rregs[ESP_FIFO]; 1136 break; 1137 case ESP_RINTR: 1138 /* 1139 * Clear sequence step, interrupt register and all status bits 1140 * except TC 1141 */ 1142 val = s->rregs[ESP_RINTR]; 1143 s->rregs[ESP_RINTR] = 0; 1144 s->rregs[ESP_RSTAT] &= ~STAT_TC; 1145 /* 1146 * According to the datasheet ESP_RSEQ should be cleared, but as the 1147 * emulation currently defers information transfers to the next TI 1148 * command leave it for now so that pedantic guests such as the old 1149 * Linux 2.6 driver see the correct flags before the next SCSI phase 1150 * transition. 1151 * 1152 * s->rregs[ESP_RSEQ] = SEQ_0; 1153 */ 1154 esp_lower_irq(s); 1155 break; 1156 case ESP_TCHI: 1157 /* Return the unique id if the value has never been written */ 1158 if (!s->tchi_written) { 1159 val = s->chip_id; 1160 } else { 1161 val = s->rregs[saddr]; 1162 } 1163 break; 1164 case ESP_RFLAGS: 1165 /* Bottom 5 bits indicate number of bytes in FIFO */ 1166 val = fifo8_num_used(&s->fifo); 1167 break; 1168 default: 1169 val = s->rregs[saddr]; 1170 break; 1171 } 1172 1173 trace_esp_mem_readb(saddr, val); 1174 return val; 1175 } 1176 1177 void esp_reg_write(ESPState *s, uint32_t saddr, uint64_t val) 1178 { 1179 trace_esp_mem_writeb(saddr, s->wregs[saddr], val); 1180 switch (saddr) { 1181 case ESP_TCHI: 1182 s->tchi_written = true; 1183 /* fall through */ 1184 case ESP_TCLO: 1185 case ESP_TCMID: 1186 s->rregs[ESP_RSTAT] &= ~STAT_TC; 1187 break; 1188 case ESP_FIFO: 1189 if (s->do_cmd) { 1190 if (!fifo8_is_full(&s->fifo)) { 1191 esp_fifo_push(&s->fifo, val); 1192 esp_fifo_push(&s->cmdfifo, fifo8_pop(&s->fifo)); 1193 } 1194 1195 /* 1196 * If any unexpected message out/command phase data is 1197 * transferred using non-DMA, raise the interrupt 1198 */ 1199 if (s->rregs[ESP_CMD] == CMD_TI) { 1200 s->rregs[ESP_RINTR] |= INTR_BS; 1201 esp_raise_irq(s); 1202 } 1203 } else { 1204 esp_fifo_push(&s->fifo, val); 1205 } 1206 break; 1207 case ESP_CMD: 1208 s->rregs[saddr] = val; 1209 esp_run_cmd(s); 1210 break; 1211 case ESP_WBUSID ... ESP_WSYNO: 1212 break; 1213 case ESP_CFG1: 1214 case ESP_CFG2: case ESP_CFG3: 1215 case ESP_RES3: case ESP_RES4: 1216 s->rregs[saddr] = val; 1217 break; 1218 case ESP_WCCF ... ESP_WTEST: 1219 break; 1220 default: 1221 trace_esp_error_invalid_write(val, saddr); 1222 return; 1223 } 1224 s->wregs[saddr] = val; 1225 } 1226 1227 static bool esp_mem_accepts(void *opaque, hwaddr addr, 1228 unsigned size, bool is_write, 1229 MemTxAttrs attrs) 1230 { 1231 return (size == 1) || (is_write && size == 4); 1232 } 1233 1234 static bool esp_is_before_version_5(void *opaque, int version_id) 1235 { 1236 ESPState *s = ESP(opaque); 1237 1238 version_id = MIN(version_id, s->mig_version_id); 1239 return version_id < 5; 1240 } 1241 1242 static bool esp_is_version_5(void *opaque, int version_id) 1243 { 1244 ESPState *s = ESP(opaque); 1245 1246 version_id = MIN(version_id, s->mig_version_id); 1247 return version_id >= 5; 1248 } 1249 1250 static bool esp_is_version_6(void *opaque, int version_id) 1251 { 1252 ESPState *s = ESP(opaque); 1253 1254 version_id = MIN(version_id, s->mig_version_id); 1255 return version_id >= 6; 1256 } 1257 1258 int esp_pre_save(void *opaque) 1259 { 1260 ESPState *s = ESP(object_resolve_path_component( 1261 OBJECT(opaque), "esp")); 1262 1263 s->mig_version_id = vmstate_esp.version_id; 1264 return 0; 1265 } 1266 1267 static int esp_post_load(void *opaque, int version_id) 1268 { 1269 ESPState *s = ESP(opaque); 1270 int len, i; 1271 1272 version_id = MIN(version_id, s->mig_version_id); 1273 1274 if (version_id < 5) { 1275 esp_set_tc(s, s->mig_dma_left); 1276 1277 /* Migrate ti_buf to fifo */ 1278 len = s->mig_ti_wptr - s->mig_ti_rptr; 1279 for (i = 0; i < len; i++) { 1280 fifo8_push(&s->fifo, s->mig_ti_buf[i]); 1281 } 1282 1283 /* Migrate cmdbuf to cmdfifo */ 1284 for (i = 0; i < s->mig_cmdlen; i++) { 1285 fifo8_push(&s->cmdfifo, s->mig_cmdbuf[i]); 1286 } 1287 } 1288 1289 s->mig_version_id = vmstate_esp.version_id; 1290 return 0; 1291 } 1292 1293 /* 1294 * PDMA (or pseudo-DMA) is only used on the Macintosh and requires the 1295 * guest CPU to perform the transfers between the SCSI bus and memory 1296 * itself. This is indicated by the dma_memory_read and dma_memory_write 1297 * functions being NULL (in contrast to the ESP PCI device) whilst 1298 * dma_enabled is still set. 1299 */ 1300 1301 static bool esp_pdma_needed(void *opaque) 1302 { 1303 ESPState *s = ESP(opaque); 1304 1305 return s->dma_memory_read == NULL && s->dma_memory_write == NULL && 1306 s->dma_enabled; 1307 } 1308 1309 static const VMStateDescription vmstate_esp_pdma = { 1310 .name = "esp/pdma", 1311 .version_id = 0, 1312 .minimum_version_id = 0, 1313 .needed = esp_pdma_needed, 1314 .fields = (const VMStateField[]) { 1315 VMSTATE_UINT8(pdma_cb, ESPState), 1316 VMSTATE_END_OF_LIST() 1317 } 1318 }; 1319 1320 const VMStateDescription vmstate_esp = { 1321 .name = "esp", 1322 .version_id = 6, 1323 .minimum_version_id = 3, 1324 .post_load = esp_post_load, 1325 .fields = (const VMStateField[]) { 1326 VMSTATE_BUFFER(rregs, ESPState), 1327 VMSTATE_BUFFER(wregs, ESPState), 1328 VMSTATE_INT32(ti_size, ESPState), 1329 VMSTATE_UINT32_TEST(mig_ti_rptr, ESPState, esp_is_before_version_5), 1330 VMSTATE_UINT32_TEST(mig_ti_wptr, ESPState, esp_is_before_version_5), 1331 VMSTATE_BUFFER_TEST(mig_ti_buf, ESPState, esp_is_before_version_5), 1332 VMSTATE_UINT32(status, ESPState), 1333 VMSTATE_UINT32_TEST(mig_deferred_status, ESPState, 1334 esp_is_before_version_5), 1335 VMSTATE_BOOL_TEST(mig_deferred_complete, ESPState, 1336 esp_is_before_version_5), 1337 VMSTATE_UINT32(dma, ESPState), 1338 VMSTATE_STATIC_BUFFER(mig_cmdbuf, ESPState, 0, 1339 esp_is_before_version_5, 0, 16), 1340 VMSTATE_STATIC_BUFFER(mig_cmdbuf, ESPState, 4, 1341 esp_is_before_version_5, 16, 1342 sizeof(typeof_field(ESPState, mig_cmdbuf))), 1343 VMSTATE_UINT32_TEST(mig_cmdlen, ESPState, esp_is_before_version_5), 1344 VMSTATE_UINT32(do_cmd, ESPState), 1345 VMSTATE_UINT32_TEST(mig_dma_left, ESPState, esp_is_before_version_5), 1346 VMSTATE_BOOL_TEST(data_in_ready, ESPState, esp_is_version_5), 1347 VMSTATE_UINT8_TEST(cmdfifo_cdb_offset, ESPState, esp_is_version_5), 1348 VMSTATE_FIFO8_TEST(fifo, ESPState, esp_is_version_5), 1349 VMSTATE_FIFO8_TEST(cmdfifo, ESPState, esp_is_version_5), 1350 VMSTATE_UINT8_TEST(ti_cmd, ESPState, esp_is_version_5), 1351 VMSTATE_UINT8_TEST(lun, ESPState, esp_is_version_6), 1352 VMSTATE_END_OF_LIST() 1353 }, 1354 .subsections = (const VMStateDescription * const []) { 1355 &vmstate_esp_pdma, 1356 NULL 1357 } 1358 }; 1359 1360 static void sysbus_esp_mem_write(void *opaque, hwaddr addr, 1361 uint64_t val, unsigned int size) 1362 { 1363 SysBusESPState *sysbus = opaque; 1364 ESPState *s = ESP(&sysbus->esp); 1365 uint32_t saddr; 1366 1367 saddr = addr >> sysbus->it_shift; 1368 esp_reg_write(s, saddr, val); 1369 } 1370 1371 static uint64_t sysbus_esp_mem_read(void *opaque, hwaddr addr, 1372 unsigned int size) 1373 { 1374 SysBusESPState *sysbus = opaque; 1375 ESPState *s = ESP(&sysbus->esp); 1376 uint32_t saddr; 1377 1378 saddr = addr >> sysbus->it_shift; 1379 return esp_reg_read(s, saddr); 1380 } 1381 1382 static const MemoryRegionOps sysbus_esp_mem_ops = { 1383 .read = sysbus_esp_mem_read, 1384 .write = sysbus_esp_mem_write, 1385 .endianness = DEVICE_NATIVE_ENDIAN, 1386 .valid.accepts = esp_mem_accepts, 1387 }; 1388 1389 static void sysbus_esp_pdma_write(void *opaque, hwaddr addr, 1390 uint64_t val, unsigned int size) 1391 { 1392 SysBusESPState *sysbus = opaque; 1393 ESPState *s = ESP(&sysbus->esp); 1394 1395 trace_esp_pdma_write(size); 1396 1397 switch (size) { 1398 case 1: 1399 esp_pdma_write(s, val); 1400 break; 1401 case 2: 1402 esp_pdma_write(s, val >> 8); 1403 esp_pdma_write(s, val); 1404 break; 1405 } 1406 esp_pdma_cb(s); 1407 } 1408 1409 static uint64_t sysbus_esp_pdma_read(void *opaque, hwaddr addr, 1410 unsigned int size) 1411 { 1412 SysBusESPState *sysbus = opaque; 1413 ESPState *s = ESP(&sysbus->esp); 1414 uint64_t val = 0; 1415 1416 trace_esp_pdma_read(size); 1417 1418 switch (size) { 1419 case 1: 1420 val = esp_pdma_read(s); 1421 break; 1422 case 2: 1423 val = esp_pdma_read(s); 1424 val = (val << 8) | esp_pdma_read(s); 1425 break; 1426 } 1427 if (fifo8_num_used(&s->fifo) < 2) { 1428 esp_pdma_cb(s); 1429 } 1430 return val; 1431 } 1432 1433 static void *esp_load_request(QEMUFile *f, SCSIRequest *req) 1434 { 1435 ESPState *s = container_of(req->bus, ESPState, bus); 1436 1437 scsi_req_ref(req); 1438 s->current_req = req; 1439 return s; 1440 } 1441 1442 static const MemoryRegionOps sysbus_esp_pdma_ops = { 1443 .read = sysbus_esp_pdma_read, 1444 .write = sysbus_esp_pdma_write, 1445 .endianness = DEVICE_NATIVE_ENDIAN, 1446 .valid.min_access_size = 1, 1447 .valid.max_access_size = 4, 1448 .impl.min_access_size = 1, 1449 .impl.max_access_size = 2, 1450 }; 1451 1452 static const struct SCSIBusInfo esp_scsi_info = { 1453 .tcq = false, 1454 .max_target = ESP_MAX_DEVS, 1455 .max_lun = 7, 1456 1457 .load_request = esp_load_request, 1458 .transfer_data = esp_transfer_data, 1459 .complete = esp_command_complete, 1460 .cancel = esp_request_cancelled 1461 }; 1462 1463 static void sysbus_esp_gpio_demux(void *opaque, int irq, int level) 1464 { 1465 SysBusESPState *sysbus = SYSBUS_ESP(opaque); 1466 ESPState *s = ESP(&sysbus->esp); 1467 1468 switch (irq) { 1469 case 0: 1470 parent_esp_reset(s, irq, level); 1471 break; 1472 case 1: 1473 esp_dma_enable(s, irq, level); 1474 break; 1475 } 1476 } 1477 1478 static void sysbus_esp_realize(DeviceState *dev, Error **errp) 1479 { 1480 SysBusDevice *sbd = SYS_BUS_DEVICE(dev); 1481 SysBusESPState *sysbus = SYSBUS_ESP(dev); 1482 ESPState *s = ESP(&sysbus->esp); 1483 1484 if (!qdev_realize(DEVICE(s), NULL, errp)) { 1485 return; 1486 } 1487 1488 sysbus_init_irq(sbd, &s->irq); 1489 sysbus_init_irq(sbd, &s->irq_data); 1490 assert(sysbus->it_shift != -1); 1491 1492 s->chip_id = TCHI_FAS100A; 1493 memory_region_init_io(&sysbus->iomem, OBJECT(sysbus), &sysbus_esp_mem_ops, 1494 sysbus, "esp-regs", ESP_REGS << sysbus->it_shift); 1495 sysbus_init_mmio(sbd, &sysbus->iomem); 1496 memory_region_init_io(&sysbus->pdma, OBJECT(sysbus), &sysbus_esp_pdma_ops, 1497 sysbus, "esp-pdma", 4); 1498 sysbus_init_mmio(sbd, &sysbus->pdma); 1499 1500 qdev_init_gpio_in(dev, sysbus_esp_gpio_demux, 2); 1501 1502 scsi_bus_init(&s->bus, sizeof(s->bus), dev, &esp_scsi_info); 1503 } 1504 1505 static void sysbus_esp_hard_reset(DeviceState *dev) 1506 { 1507 SysBusESPState *sysbus = SYSBUS_ESP(dev); 1508 ESPState *s = ESP(&sysbus->esp); 1509 1510 esp_hard_reset(s); 1511 } 1512 1513 static void sysbus_esp_init(Object *obj) 1514 { 1515 SysBusESPState *sysbus = SYSBUS_ESP(obj); 1516 1517 object_initialize_child(obj, "esp", &sysbus->esp, TYPE_ESP); 1518 } 1519 1520 static const VMStateDescription vmstate_sysbus_esp_scsi = { 1521 .name = "sysbusespscsi", 1522 .version_id = 2, 1523 .minimum_version_id = 1, 1524 .pre_save = esp_pre_save, 1525 .fields = (const VMStateField[]) { 1526 VMSTATE_UINT8_V(esp.mig_version_id, SysBusESPState, 2), 1527 VMSTATE_STRUCT(esp, SysBusESPState, 0, vmstate_esp, ESPState), 1528 VMSTATE_END_OF_LIST() 1529 } 1530 }; 1531 1532 static void sysbus_esp_class_init(ObjectClass *klass, void *data) 1533 { 1534 DeviceClass *dc = DEVICE_CLASS(klass); 1535 1536 dc->realize = sysbus_esp_realize; 1537 dc->reset = sysbus_esp_hard_reset; 1538 dc->vmsd = &vmstate_sysbus_esp_scsi; 1539 set_bit(DEVICE_CATEGORY_STORAGE, dc->categories); 1540 } 1541 1542 static const TypeInfo sysbus_esp_info = { 1543 .name = TYPE_SYSBUS_ESP, 1544 .parent = TYPE_SYS_BUS_DEVICE, 1545 .instance_init = sysbus_esp_init, 1546 .instance_size = sizeof(SysBusESPState), 1547 .class_init = sysbus_esp_class_init, 1548 }; 1549 1550 static void esp_finalize(Object *obj) 1551 { 1552 ESPState *s = ESP(obj); 1553 1554 fifo8_destroy(&s->fifo); 1555 fifo8_destroy(&s->cmdfifo); 1556 } 1557 1558 static void esp_init(Object *obj) 1559 { 1560 ESPState *s = ESP(obj); 1561 1562 fifo8_create(&s->fifo, ESP_FIFO_SZ); 1563 fifo8_create(&s->cmdfifo, ESP_CMDFIFO_SZ); 1564 } 1565 1566 static void esp_class_init(ObjectClass *klass, void *data) 1567 { 1568 DeviceClass *dc = DEVICE_CLASS(klass); 1569 1570 /* internal device for sysbusesp/pciespscsi, not user-creatable */ 1571 dc->user_creatable = false; 1572 set_bit(DEVICE_CATEGORY_STORAGE, dc->categories); 1573 } 1574 1575 static const TypeInfo esp_info = { 1576 .name = TYPE_ESP, 1577 .parent = TYPE_DEVICE, 1578 .instance_init = esp_init, 1579 .instance_finalize = esp_finalize, 1580 .instance_size = sizeof(ESPState), 1581 .class_init = esp_class_init, 1582 }; 1583 1584 static void esp_register_types(void) 1585 { 1586 type_register_static(&sysbus_esp_info); 1587 type_register_static(&esp_info); 1588 } 1589 1590 type_init(esp_register_types) 1591