1 /* 2 * QEMU ESP/NCR53C9x emulation 3 * 4 * Copyright (c) 2005-2006 Fabrice Bellard 5 * Copyright (c) 2012 Herve Poussineau 6 * 7 * Permission is hereby granted, free of charge, to any person obtaining a copy 8 * of this software and associated documentation files (the "Software"), to deal 9 * in the Software without restriction, including without limitation the rights 10 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 11 * copies of the Software, and to permit persons to whom the Software is 12 * furnished to do so, subject to the following conditions: 13 * 14 * The above copyright notice and this permission notice shall be included in 15 * all copies or substantial portions of the Software. 16 * 17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 22 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 23 * THE SOFTWARE. 24 */ 25 26 #include "qemu/osdep.h" 27 #include "hw/sysbus.h" 28 #include "migration/vmstate.h" 29 #include "hw/irq.h" 30 #include "hw/scsi/esp.h" 31 #include "trace.h" 32 #include "qemu/log.h" 33 #include "qemu/module.h" 34 35 /* 36 * On Sparc32, this is the ESP (NCR53C90) part of chip STP2000 (Master I/O), 37 * also produced as NCR89C100. See 38 * http://www.ibiblio.org/pub/historic-linux/early-ports/Sparc/NCR/NCR89C100.txt 39 * and 40 * http://www.ibiblio.org/pub/historic-linux/early-ports/Sparc/NCR/NCR53C9X.txt 41 * 42 * On Macintosh Quadra it is a NCR53C96. 43 */ 44 45 static void esp_raise_irq(ESPState *s) 46 { 47 if (!(s->rregs[ESP_RSTAT] & STAT_INT)) { 48 s->rregs[ESP_RSTAT] |= STAT_INT; 49 qemu_irq_raise(s->irq); 50 trace_esp_raise_irq(); 51 } 52 } 53 54 static void esp_lower_irq(ESPState *s) 55 { 56 if (s->rregs[ESP_RSTAT] & STAT_INT) { 57 s->rregs[ESP_RSTAT] &= ~STAT_INT; 58 qemu_irq_lower(s->irq); 59 trace_esp_lower_irq(); 60 } 61 } 62 63 static void esp_raise_drq(ESPState *s) 64 { 65 qemu_irq_raise(s->irq_data); 66 trace_esp_raise_drq(); 67 } 68 69 static void esp_lower_drq(ESPState *s) 70 { 71 qemu_irq_lower(s->irq_data); 72 trace_esp_lower_drq(); 73 } 74 75 void esp_dma_enable(ESPState *s, int irq, int level) 76 { 77 if (level) { 78 s->dma_enabled = 1; 79 trace_esp_dma_enable(); 80 if (s->dma_cb) { 81 s->dma_cb(s); 82 s->dma_cb = NULL; 83 } 84 } else { 85 trace_esp_dma_disable(); 86 s->dma_enabled = 0; 87 } 88 } 89 90 void esp_request_cancelled(SCSIRequest *req) 91 { 92 ESPState *s = req->hba_private; 93 94 if (req == s->current_req) { 95 scsi_req_unref(s->current_req); 96 s->current_req = NULL; 97 s->current_dev = NULL; 98 s->async_len = 0; 99 } 100 } 101 102 static void esp_fifo_push(Fifo8 *fifo, uint8_t val) 103 { 104 if (fifo8_num_used(fifo) == fifo->capacity) { 105 trace_esp_error_fifo_overrun(); 106 return; 107 } 108 109 fifo8_push(fifo, val); 110 } 111 112 static uint8_t esp_fifo_pop(Fifo8 *fifo) 113 { 114 if (fifo8_is_empty(fifo)) { 115 return 0; 116 } 117 118 return fifo8_pop(fifo); 119 } 120 121 static uint32_t esp_fifo_pop_buf(Fifo8 *fifo, uint8_t *dest, int maxlen) 122 { 123 const uint8_t *buf; 124 uint32_t n; 125 126 if (maxlen == 0) { 127 return 0; 128 } 129 130 buf = fifo8_pop_buf(fifo, maxlen, &n); 131 if (dest) { 132 memcpy(dest, buf, n); 133 } 134 135 return n; 136 } 137 138 static uint32_t esp_get_tc(ESPState *s) 139 { 140 uint32_t dmalen; 141 142 dmalen = s->rregs[ESP_TCLO]; 143 dmalen |= s->rregs[ESP_TCMID] << 8; 144 dmalen |= s->rregs[ESP_TCHI] << 16; 145 146 return dmalen; 147 } 148 149 static void esp_set_tc(ESPState *s, uint32_t dmalen) 150 { 151 s->rregs[ESP_TCLO] = dmalen; 152 s->rregs[ESP_TCMID] = dmalen >> 8; 153 s->rregs[ESP_TCHI] = dmalen >> 16; 154 } 155 156 static uint32_t esp_get_stc(ESPState *s) 157 { 158 uint32_t dmalen; 159 160 dmalen = s->wregs[ESP_TCLO]; 161 dmalen |= s->wregs[ESP_TCMID] << 8; 162 dmalen |= s->wregs[ESP_TCHI] << 16; 163 164 return dmalen; 165 } 166 167 static uint8_t esp_pdma_read(ESPState *s) 168 { 169 uint8_t val; 170 171 if (s->do_cmd) { 172 val = esp_fifo_pop(&s->cmdfifo); 173 } else { 174 val = esp_fifo_pop(&s->fifo); 175 } 176 177 return val; 178 } 179 180 static void esp_pdma_write(ESPState *s, uint8_t val) 181 { 182 uint32_t dmalen = esp_get_tc(s); 183 184 if (dmalen == 0) { 185 return; 186 } 187 188 if (s->do_cmd) { 189 esp_fifo_push(&s->cmdfifo, val); 190 } else { 191 esp_fifo_push(&s->fifo, val); 192 } 193 194 dmalen--; 195 esp_set_tc(s, dmalen); 196 } 197 198 static int esp_select(ESPState *s) 199 { 200 int target; 201 202 target = s->wregs[ESP_WBUSID] & BUSID_DID; 203 204 s->ti_size = 0; 205 fifo8_reset(&s->fifo); 206 207 if (s->current_req) { 208 /* Started a new command before the old one finished. Cancel it. */ 209 scsi_req_cancel(s->current_req); 210 } 211 212 s->current_dev = scsi_device_find(&s->bus, 0, target, 0); 213 if (!s->current_dev) { 214 /* No such drive */ 215 s->rregs[ESP_RSTAT] = 0; 216 s->rregs[ESP_RINTR] = INTR_DC; 217 s->rregs[ESP_RSEQ] = SEQ_0; 218 esp_raise_irq(s); 219 return -1; 220 } 221 222 /* 223 * Note that we deliberately don't raise the IRQ here: this will be done 224 * either in do_busid_cmd() for DATA OUT transfers or by the deferred 225 * IRQ mechanism in esp_transfer_data() for DATA IN transfers 226 */ 227 s->rregs[ESP_RINTR] |= INTR_FC; 228 s->rregs[ESP_RSEQ] = SEQ_CD; 229 return 0; 230 } 231 232 static uint32_t get_cmd(ESPState *s, uint32_t maxlen) 233 { 234 uint8_t buf[ESP_CMDFIFO_SZ]; 235 uint32_t dmalen, n; 236 int target; 237 238 target = s->wregs[ESP_WBUSID] & BUSID_DID; 239 if (s->dma) { 240 dmalen = MIN(esp_get_tc(s), maxlen); 241 if (dmalen == 0) { 242 return 0; 243 } 244 if (s->dma_memory_read) { 245 s->dma_memory_read(s->dma_opaque, buf, dmalen); 246 dmalen = MIN(fifo8_num_free(&s->cmdfifo), dmalen); 247 fifo8_push_all(&s->cmdfifo, buf, dmalen); 248 } else { 249 if (esp_select(s) < 0) { 250 fifo8_reset(&s->cmdfifo); 251 return -1; 252 } 253 esp_raise_drq(s); 254 fifo8_reset(&s->cmdfifo); 255 return 0; 256 } 257 } else { 258 dmalen = MIN(fifo8_num_used(&s->fifo), maxlen); 259 if (dmalen == 0) { 260 return 0; 261 } 262 n = esp_fifo_pop_buf(&s->fifo, buf, dmalen); 263 if (n >= 3) { 264 buf[0] = buf[2] >> 5; 265 } 266 n = MIN(fifo8_num_free(&s->cmdfifo), n); 267 fifo8_push_all(&s->cmdfifo, buf, n); 268 } 269 trace_esp_get_cmd(dmalen, target); 270 271 if (esp_select(s) < 0) { 272 fifo8_reset(&s->cmdfifo); 273 return -1; 274 } 275 return dmalen; 276 } 277 278 static void do_busid_cmd(ESPState *s, uint8_t busid) 279 { 280 uint32_t cmdlen; 281 int32_t datalen; 282 int lun; 283 SCSIDevice *current_lun; 284 uint8_t buf[ESP_CMDFIFO_SZ]; 285 286 trace_esp_do_busid_cmd(busid); 287 lun = busid & 7; 288 cmdlen = fifo8_num_used(&s->cmdfifo); 289 if (!cmdlen || !s->current_dev) { 290 return; 291 } 292 esp_fifo_pop_buf(&s->cmdfifo, buf, cmdlen); 293 294 current_lun = scsi_device_find(&s->bus, 0, s->current_dev->id, lun); 295 s->current_req = scsi_req_new(current_lun, 0, lun, buf, s); 296 datalen = scsi_req_enqueue(s->current_req); 297 s->ti_size = datalen; 298 fifo8_reset(&s->cmdfifo); 299 if (datalen != 0) { 300 s->rregs[ESP_RSTAT] = STAT_TC; 301 s->rregs[ESP_RSEQ] = SEQ_CD; 302 s->ti_cmd = 0; 303 esp_set_tc(s, 0); 304 if (datalen > 0) { 305 /* 306 * Switch to DATA IN phase but wait until initial data xfer is 307 * complete before raising the command completion interrupt 308 */ 309 s->data_in_ready = false; 310 s->rregs[ESP_RSTAT] |= STAT_DI; 311 } else { 312 s->rregs[ESP_RSTAT] |= STAT_DO; 313 s->rregs[ESP_RINTR] |= INTR_BS | INTR_FC; 314 esp_raise_irq(s); 315 esp_lower_drq(s); 316 } 317 scsi_req_continue(s->current_req); 318 return; 319 } 320 } 321 322 static void do_cmd(ESPState *s) 323 { 324 uint8_t busid = esp_fifo_pop(&s->cmdfifo); 325 int len; 326 327 s->cmdfifo_cdb_offset--; 328 329 /* Ignore extended messages for now */ 330 if (s->cmdfifo_cdb_offset) { 331 len = MIN(s->cmdfifo_cdb_offset, fifo8_num_used(&s->cmdfifo)); 332 esp_fifo_pop_buf(&s->cmdfifo, NULL, len); 333 s->cmdfifo_cdb_offset = 0; 334 } 335 336 do_busid_cmd(s, busid); 337 } 338 339 static void satn_pdma_cb(ESPState *s) 340 { 341 if (!esp_get_tc(s) && !fifo8_is_empty(&s->cmdfifo)) { 342 s->cmdfifo_cdb_offset = 1; 343 s->do_cmd = 0; 344 do_cmd(s); 345 } 346 } 347 348 static void handle_satn(ESPState *s) 349 { 350 int32_t cmdlen; 351 352 if (s->dma && !s->dma_enabled) { 353 s->dma_cb = handle_satn; 354 return; 355 } 356 s->pdma_cb = satn_pdma_cb; 357 cmdlen = get_cmd(s, ESP_CMDFIFO_SZ); 358 if (cmdlen > 0) { 359 s->cmdfifo_cdb_offset = 1; 360 s->do_cmd = 0; 361 do_cmd(s); 362 } else if (cmdlen == 0) { 363 s->do_cmd = 1; 364 /* Target present, but no cmd yet - switch to command phase */ 365 s->rregs[ESP_RSEQ] = SEQ_CD; 366 s->rregs[ESP_RSTAT] = STAT_CD; 367 } 368 } 369 370 static void s_without_satn_pdma_cb(ESPState *s) 371 { 372 if (!esp_get_tc(s) && !fifo8_is_empty(&s->cmdfifo)) { 373 s->cmdfifo_cdb_offset = 0; 374 s->do_cmd = 0; 375 do_busid_cmd(s, 0); 376 } 377 } 378 379 static void handle_s_without_atn(ESPState *s) 380 { 381 int32_t cmdlen; 382 383 if (s->dma && !s->dma_enabled) { 384 s->dma_cb = handle_s_without_atn; 385 return; 386 } 387 s->pdma_cb = s_without_satn_pdma_cb; 388 cmdlen = get_cmd(s, ESP_CMDFIFO_SZ); 389 if (cmdlen > 0) { 390 s->cmdfifo_cdb_offset = 0; 391 s->do_cmd = 0; 392 do_busid_cmd(s, 0); 393 } else if (cmdlen == 0) { 394 s->do_cmd = 1; 395 /* Target present, but no cmd yet - switch to command phase */ 396 s->rregs[ESP_RSEQ] = SEQ_CD; 397 s->rregs[ESP_RSTAT] = STAT_CD; 398 } 399 } 400 401 static void satn_stop_pdma_cb(ESPState *s) 402 { 403 if (!esp_get_tc(s) && !fifo8_is_empty(&s->cmdfifo)) { 404 trace_esp_handle_satn_stop(fifo8_num_used(&s->cmdfifo)); 405 s->do_cmd = 1; 406 s->cmdfifo_cdb_offset = 1; 407 s->rregs[ESP_RSTAT] = STAT_TC | STAT_CD; 408 s->rregs[ESP_RINTR] |= INTR_BS | INTR_FC; 409 s->rregs[ESP_RSEQ] = SEQ_CD; 410 esp_raise_irq(s); 411 } 412 } 413 414 static void handle_satn_stop(ESPState *s) 415 { 416 int32_t cmdlen; 417 418 if (s->dma && !s->dma_enabled) { 419 s->dma_cb = handle_satn_stop; 420 return; 421 } 422 s->pdma_cb = satn_stop_pdma_cb; 423 cmdlen = get_cmd(s, 1); 424 if (cmdlen > 0) { 425 trace_esp_handle_satn_stop(fifo8_num_used(&s->cmdfifo)); 426 s->do_cmd = 1; 427 s->cmdfifo_cdb_offset = 1; 428 s->rregs[ESP_RSTAT] = STAT_MO; 429 s->rregs[ESP_RINTR] |= INTR_BS | INTR_FC; 430 s->rregs[ESP_RSEQ] = SEQ_MO; 431 esp_raise_irq(s); 432 } else if (cmdlen == 0) { 433 s->do_cmd = 1; 434 /* Target present, switch to message out phase */ 435 s->rregs[ESP_RSEQ] = SEQ_MO; 436 s->rregs[ESP_RSTAT] = STAT_MO; 437 } 438 } 439 440 static void write_response_pdma_cb(ESPState *s) 441 { 442 s->rregs[ESP_RSTAT] = STAT_TC | STAT_ST; 443 s->rregs[ESP_RINTR] |= INTR_BS | INTR_FC; 444 s->rregs[ESP_RSEQ] = SEQ_CD; 445 esp_raise_irq(s); 446 } 447 448 static void write_response(ESPState *s) 449 { 450 uint8_t buf[2]; 451 452 trace_esp_write_response(s->status); 453 454 buf[0] = s->status; 455 buf[1] = 0; 456 457 if (s->dma) { 458 if (s->dma_memory_write) { 459 s->dma_memory_write(s->dma_opaque, buf, 2); 460 s->rregs[ESP_RSTAT] = STAT_TC | STAT_ST; 461 s->rregs[ESP_RINTR] |= INTR_BS | INTR_FC; 462 s->rregs[ESP_RSEQ] = SEQ_CD; 463 } else { 464 s->pdma_cb = write_response_pdma_cb; 465 esp_raise_drq(s); 466 return; 467 } 468 } else { 469 fifo8_reset(&s->fifo); 470 fifo8_push_all(&s->fifo, buf, 2); 471 s->rregs[ESP_RFLAGS] = 2; 472 } 473 esp_raise_irq(s); 474 } 475 476 static void esp_dma_done(ESPState *s) 477 { 478 s->rregs[ESP_RSTAT] |= STAT_TC; 479 s->rregs[ESP_RINTR] |= INTR_BS; 480 s->rregs[ESP_RFLAGS] = 0; 481 esp_set_tc(s, 0); 482 esp_raise_irq(s); 483 } 484 485 static void do_dma_pdma_cb(ESPState *s) 486 { 487 int to_device = ((s->rregs[ESP_RSTAT] & 7) == STAT_DO); 488 int len; 489 uint32_t n; 490 491 if (s->do_cmd) { 492 /* Ensure we have received complete command after SATN and stop */ 493 if (esp_get_tc(s) || fifo8_is_empty(&s->cmdfifo)) { 494 return; 495 } 496 497 s->ti_size = 0; 498 s->do_cmd = 0; 499 do_cmd(s); 500 esp_lower_drq(s); 501 return; 502 } 503 504 if (!s->current_req) { 505 return; 506 } 507 508 if (to_device) { 509 /* Copy FIFO data to device */ 510 len = MIN(s->async_len, ESP_FIFO_SZ); 511 len = MIN(len, fifo8_num_used(&s->fifo)); 512 n = esp_fifo_pop_buf(&s->fifo, s->async_buf, len); 513 s->async_buf += n; 514 s->async_len -= n; 515 s->ti_size += n; 516 517 if (n < len) { 518 /* Unaligned accesses can cause FIFO wraparound */ 519 len = len - n; 520 n = esp_fifo_pop_buf(&s->fifo, s->async_buf, len); 521 s->async_buf += n; 522 s->async_len -= n; 523 s->ti_size += n; 524 } 525 526 if (s->async_len == 0) { 527 scsi_req_continue(s->current_req); 528 return; 529 } 530 531 if (esp_get_tc(s) == 0) { 532 esp_lower_drq(s); 533 esp_dma_done(s); 534 } 535 536 return; 537 } else { 538 if (s->async_len == 0) { 539 /* Defer until the scsi layer has completed */ 540 scsi_req_continue(s->current_req); 541 s->data_in_ready = false; 542 return; 543 } 544 545 if (esp_get_tc(s) != 0) { 546 /* Copy device data to FIFO */ 547 len = MIN(s->async_len, esp_get_tc(s)); 548 len = MIN(len, fifo8_num_free(&s->fifo)); 549 fifo8_push_all(&s->fifo, s->async_buf, len); 550 s->async_buf += len; 551 s->async_len -= len; 552 s->ti_size -= len; 553 esp_set_tc(s, esp_get_tc(s) - len); 554 555 if (esp_get_tc(s) == 0) { 556 /* Indicate transfer to FIFO is complete */ 557 s->rregs[ESP_RSTAT] |= STAT_TC; 558 } 559 return; 560 } 561 562 /* Partially filled a scsi buffer. Complete immediately. */ 563 esp_lower_drq(s); 564 esp_dma_done(s); 565 } 566 } 567 568 static void esp_do_dma(ESPState *s) 569 { 570 uint32_t len, cmdlen; 571 int to_device = ((s->rregs[ESP_RSTAT] & 7) == STAT_DO); 572 uint8_t buf[ESP_CMDFIFO_SZ]; 573 574 len = esp_get_tc(s); 575 if (s->do_cmd) { 576 /* 577 * handle_ti_cmd() case: esp_do_dma() is called only from 578 * handle_ti_cmd() with do_cmd != NULL (see the assert()) 579 */ 580 cmdlen = fifo8_num_used(&s->cmdfifo); 581 trace_esp_do_dma(cmdlen, len); 582 if (s->dma_memory_read) { 583 len = MIN(len, fifo8_num_free(&s->cmdfifo)); 584 s->dma_memory_read(s->dma_opaque, buf, len); 585 fifo8_push_all(&s->cmdfifo, buf, len); 586 } else { 587 s->pdma_cb = do_dma_pdma_cb; 588 esp_raise_drq(s); 589 return; 590 } 591 trace_esp_handle_ti_cmd(cmdlen); 592 s->ti_size = 0; 593 if ((s->rregs[ESP_RSTAT] & 7) == STAT_CD) { 594 /* No command received */ 595 if (s->cmdfifo_cdb_offset == fifo8_num_used(&s->cmdfifo)) { 596 return; 597 } 598 599 /* Command has been received */ 600 s->do_cmd = 0; 601 do_cmd(s); 602 } else { 603 /* 604 * Extra message out bytes received: update cmdfifo_cdb_offset 605 * and then switch to commmand phase 606 */ 607 s->cmdfifo_cdb_offset = fifo8_num_used(&s->cmdfifo); 608 s->rregs[ESP_RSTAT] = STAT_TC | STAT_CD; 609 s->rregs[ESP_RSEQ] = SEQ_CD; 610 s->rregs[ESP_RINTR] |= INTR_BS; 611 esp_raise_irq(s); 612 } 613 return; 614 } 615 if (!s->current_req) { 616 return; 617 } 618 if (s->async_len == 0) { 619 /* Defer until data is available. */ 620 return; 621 } 622 if (len > s->async_len) { 623 len = s->async_len; 624 } 625 if (to_device) { 626 if (s->dma_memory_read) { 627 s->dma_memory_read(s->dma_opaque, s->async_buf, len); 628 } else { 629 s->pdma_cb = do_dma_pdma_cb; 630 esp_raise_drq(s); 631 return; 632 } 633 } else { 634 if (s->dma_memory_write) { 635 s->dma_memory_write(s->dma_opaque, s->async_buf, len); 636 } else { 637 /* Adjust TC for any leftover data in the FIFO */ 638 if (!fifo8_is_empty(&s->fifo)) { 639 esp_set_tc(s, esp_get_tc(s) - fifo8_num_used(&s->fifo)); 640 } 641 642 /* Copy device data to FIFO */ 643 len = MIN(len, fifo8_num_free(&s->fifo)); 644 fifo8_push_all(&s->fifo, s->async_buf, len); 645 s->async_buf += len; 646 s->async_len -= len; 647 s->ti_size -= len; 648 649 /* 650 * MacOS toolbox uses a TI length of 16 bytes for all commands, so 651 * commands shorter than this must be padded accordingly 652 */ 653 if (len < esp_get_tc(s) && esp_get_tc(s) <= ESP_FIFO_SZ) { 654 while (fifo8_num_used(&s->fifo) < ESP_FIFO_SZ) { 655 esp_fifo_push(&s->fifo, 0); 656 len++; 657 } 658 } 659 660 esp_set_tc(s, esp_get_tc(s) - len); 661 s->pdma_cb = do_dma_pdma_cb; 662 esp_raise_drq(s); 663 664 /* Indicate transfer to FIFO is complete */ 665 s->rregs[ESP_RSTAT] |= STAT_TC; 666 return; 667 } 668 } 669 esp_set_tc(s, esp_get_tc(s) - len); 670 s->async_buf += len; 671 s->async_len -= len; 672 if (to_device) { 673 s->ti_size += len; 674 } else { 675 s->ti_size -= len; 676 } 677 if (s->async_len == 0) { 678 scsi_req_continue(s->current_req); 679 /* 680 * If there is still data to be read from the device then 681 * complete the DMA operation immediately. Otherwise defer 682 * until the scsi layer has completed. 683 */ 684 if (to_device || esp_get_tc(s) != 0 || s->ti_size == 0) { 685 return; 686 } 687 } 688 689 /* Partially filled a scsi buffer. Complete immediately. */ 690 esp_dma_done(s); 691 esp_lower_drq(s); 692 } 693 694 static void esp_do_nodma(ESPState *s) 695 { 696 int to_device = ((s->rregs[ESP_RSTAT] & 7) == STAT_DO); 697 uint32_t cmdlen; 698 int len; 699 700 if (s->do_cmd) { 701 cmdlen = fifo8_num_used(&s->cmdfifo); 702 trace_esp_handle_ti_cmd(cmdlen); 703 s->ti_size = 0; 704 if ((s->rregs[ESP_RSTAT] & 7) == STAT_CD) { 705 /* No command received */ 706 if (s->cmdfifo_cdb_offset == fifo8_num_used(&s->cmdfifo)) { 707 return; 708 } 709 710 /* Command has been received */ 711 s->do_cmd = 0; 712 do_cmd(s); 713 } else { 714 /* 715 * Extra message out bytes received: update cmdfifo_cdb_offset 716 * and then switch to commmand phase 717 */ 718 s->cmdfifo_cdb_offset = fifo8_num_used(&s->cmdfifo); 719 s->rregs[ESP_RSTAT] = STAT_TC | STAT_CD; 720 s->rregs[ESP_RSEQ] = SEQ_CD; 721 s->rregs[ESP_RINTR] |= INTR_BS; 722 esp_raise_irq(s); 723 } 724 return; 725 } 726 727 if (!s->current_req) { 728 return; 729 } 730 731 if (s->async_len == 0) { 732 /* Defer until data is available. */ 733 return; 734 } 735 736 if (to_device) { 737 len = MIN(fifo8_num_used(&s->fifo), ESP_FIFO_SZ); 738 esp_fifo_pop_buf(&s->fifo, s->async_buf, len); 739 s->async_buf += len; 740 s->async_len -= len; 741 s->ti_size += len; 742 } else { 743 if (fifo8_is_empty(&s->fifo)) { 744 fifo8_push(&s->fifo, s->async_buf[0]); 745 s->async_buf++; 746 s->async_len--; 747 s->ti_size--; 748 } 749 } 750 751 if (s->async_len == 0) { 752 scsi_req_continue(s->current_req); 753 return; 754 } 755 756 s->rregs[ESP_RINTR] |= INTR_BS; 757 esp_raise_irq(s); 758 } 759 760 void esp_command_complete(SCSIRequest *req, size_t resid) 761 { 762 ESPState *s = req->hba_private; 763 int to_device = ((s->rregs[ESP_RSTAT] & 7) == STAT_DO); 764 765 trace_esp_command_complete(); 766 767 /* 768 * Non-DMA transfers from the target will leave the last byte in 769 * the FIFO so don't reset ti_size in this case 770 */ 771 if (s->dma || to_device) { 772 if (s->ti_size != 0) { 773 trace_esp_command_complete_unexpected(); 774 } 775 s->ti_size = 0; 776 } 777 778 s->async_len = 0; 779 if (req->status) { 780 trace_esp_command_complete_fail(); 781 } 782 s->status = req->status; 783 784 /* 785 * If the transfer is finished, switch to status phase. For non-DMA 786 * transfers from the target the last byte is still in the FIFO 787 */ 788 if (s->ti_size == 0) { 789 s->rregs[ESP_RSTAT] = STAT_TC | STAT_ST; 790 esp_dma_done(s); 791 esp_lower_drq(s); 792 } 793 794 if (s->current_req) { 795 scsi_req_unref(s->current_req); 796 s->current_req = NULL; 797 s->current_dev = NULL; 798 } 799 } 800 801 void esp_transfer_data(SCSIRequest *req, uint32_t len) 802 { 803 ESPState *s = req->hba_private; 804 int to_device = ((s->rregs[ESP_RSTAT] & 7) == STAT_DO); 805 uint32_t dmalen = esp_get_tc(s); 806 807 assert(!s->do_cmd); 808 trace_esp_transfer_data(dmalen, s->ti_size); 809 s->async_len = len; 810 s->async_buf = scsi_req_get_buf(req); 811 812 if (!to_device && !s->data_in_ready) { 813 /* 814 * Initial incoming data xfer is complete so raise command 815 * completion interrupt 816 */ 817 s->data_in_ready = true; 818 s->rregs[ESP_RSTAT] |= STAT_TC; 819 s->rregs[ESP_RINTR] |= INTR_BS; 820 esp_raise_irq(s); 821 } 822 823 if (s->ti_cmd == 0) { 824 /* 825 * Always perform the initial transfer upon reception of the next TI 826 * command to ensure the DMA/non-DMA status of the command is correct. 827 * It is not possible to use s->dma directly in the section below as 828 * some OSs send non-DMA NOP commands after a DMA transfer. Hence if the 829 * async data transfer is delayed then s->dma is set incorrectly. 830 */ 831 return; 832 } 833 834 if (s->ti_cmd == (CMD_TI | CMD_DMA)) { 835 if (dmalen) { 836 esp_do_dma(s); 837 } else if (s->ti_size <= 0) { 838 /* 839 * If this was the last part of a DMA transfer then the 840 * completion interrupt is deferred to here. 841 */ 842 esp_dma_done(s); 843 esp_lower_drq(s); 844 } 845 } else if (s->ti_cmd == CMD_TI) { 846 esp_do_nodma(s); 847 } 848 } 849 850 static void handle_ti(ESPState *s) 851 { 852 uint32_t dmalen; 853 854 if (s->dma && !s->dma_enabled) { 855 s->dma_cb = handle_ti; 856 return; 857 } 858 859 s->ti_cmd = s->rregs[ESP_CMD]; 860 if (s->dma) { 861 dmalen = esp_get_tc(s); 862 trace_esp_handle_ti(dmalen); 863 s->rregs[ESP_RSTAT] &= ~STAT_TC; 864 esp_do_dma(s); 865 } else { 866 trace_esp_handle_ti(s->ti_size); 867 esp_do_nodma(s); 868 } 869 } 870 871 void esp_hard_reset(ESPState *s) 872 { 873 memset(s->rregs, 0, ESP_REGS); 874 memset(s->wregs, 0, ESP_REGS); 875 s->tchi_written = 0; 876 s->ti_size = 0; 877 fifo8_reset(&s->fifo); 878 fifo8_reset(&s->cmdfifo); 879 s->dma = 0; 880 s->do_cmd = 0; 881 s->dma_cb = NULL; 882 883 s->rregs[ESP_CFG1] = 7; 884 } 885 886 static void esp_soft_reset(ESPState *s) 887 { 888 qemu_irq_lower(s->irq); 889 qemu_irq_lower(s->irq_data); 890 esp_hard_reset(s); 891 } 892 893 static void parent_esp_reset(ESPState *s, int irq, int level) 894 { 895 if (level) { 896 esp_soft_reset(s); 897 } 898 } 899 900 uint64_t esp_reg_read(ESPState *s, uint32_t saddr) 901 { 902 uint32_t val; 903 904 switch (saddr) { 905 case ESP_FIFO: 906 if (s->dma_memory_read && s->dma_memory_write && 907 (s->rregs[ESP_RSTAT] & STAT_PIO_MASK) == 0) { 908 /* Data out. */ 909 qemu_log_mask(LOG_UNIMP, "esp: PIO data read not implemented\n"); 910 s->rregs[ESP_FIFO] = 0; 911 } else { 912 if ((s->rregs[ESP_RSTAT] & 0x7) == STAT_DI) { 913 if (s->ti_size) { 914 esp_do_nodma(s); 915 } else { 916 /* 917 * The last byte of a non-DMA transfer has been read out 918 * of the FIFO so switch to status phase 919 */ 920 s->rregs[ESP_RSTAT] = STAT_TC | STAT_ST; 921 } 922 } 923 s->rregs[ESP_FIFO] = esp_fifo_pop(&s->fifo); 924 } 925 val = s->rregs[ESP_FIFO]; 926 break; 927 case ESP_RINTR: 928 /* 929 * Clear sequence step, interrupt register and all status bits 930 * except TC 931 */ 932 val = s->rregs[ESP_RINTR]; 933 s->rregs[ESP_RINTR] = 0; 934 s->rregs[ESP_RSTAT] &= ~STAT_TC; 935 /* 936 * According to the datasheet ESP_RSEQ should be cleared, but as the 937 * emulation currently defers information transfers to the next TI 938 * command leave it for now so that pedantic guests such as the old 939 * Linux 2.6 driver see the correct flags before the next SCSI phase 940 * transition. 941 * 942 * s->rregs[ESP_RSEQ] = SEQ_0; 943 */ 944 esp_lower_irq(s); 945 break; 946 case ESP_TCHI: 947 /* Return the unique id if the value has never been written */ 948 if (!s->tchi_written) { 949 val = s->chip_id; 950 } else { 951 val = s->rregs[saddr]; 952 } 953 break; 954 case ESP_RFLAGS: 955 /* Bottom 5 bits indicate number of bytes in FIFO */ 956 val = fifo8_num_used(&s->fifo); 957 break; 958 default: 959 val = s->rregs[saddr]; 960 break; 961 } 962 963 trace_esp_mem_readb(saddr, val); 964 return val; 965 } 966 967 void esp_reg_write(ESPState *s, uint32_t saddr, uint64_t val) 968 { 969 trace_esp_mem_writeb(saddr, s->wregs[saddr], val); 970 switch (saddr) { 971 case ESP_TCHI: 972 s->tchi_written = true; 973 /* fall through */ 974 case ESP_TCLO: 975 case ESP_TCMID: 976 s->rregs[ESP_RSTAT] &= ~STAT_TC; 977 break; 978 case ESP_FIFO: 979 if (s->do_cmd) { 980 esp_fifo_push(&s->cmdfifo, val); 981 982 /* 983 * If any unexpected message out/command phase data is 984 * transferred using non-DMA, raise the interrupt 985 */ 986 if (s->rregs[ESP_CMD] == CMD_TI) { 987 s->rregs[ESP_RINTR] |= INTR_BS; 988 esp_raise_irq(s); 989 } 990 } else { 991 esp_fifo_push(&s->fifo, val); 992 } 993 break; 994 case ESP_CMD: 995 s->rregs[saddr] = val; 996 if (val & CMD_DMA) { 997 s->dma = 1; 998 /* Reload DMA counter. */ 999 if (esp_get_stc(s) == 0) { 1000 esp_set_tc(s, 0x10000); 1001 } else { 1002 esp_set_tc(s, esp_get_stc(s)); 1003 } 1004 } else { 1005 s->dma = 0; 1006 } 1007 switch (val & CMD_CMD) { 1008 case CMD_NOP: 1009 trace_esp_mem_writeb_cmd_nop(val); 1010 break; 1011 case CMD_FLUSH: 1012 trace_esp_mem_writeb_cmd_flush(val); 1013 fifo8_reset(&s->fifo); 1014 break; 1015 case CMD_RESET: 1016 trace_esp_mem_writeb_cmd_reset(val); 1017 esp_soft_reset(s); 1018 break; 1019 case CMD_BUSRESET: 1020 trace_esp_mem_writeb_cmd_bus_reset(val); 1021 if (!(s->wregs[ESP_CFG1] & CFG1_RESREPT)) { 1022 s->rregs[ESP_RINTR] |= INTR_RST; 1023 esp_raise_irq(s); 1024 } 1025 break; 1026 case CMD_TI: 1027 trace_esp_mem_writeb_cmd_ti(val); 1028 handle_ti(s); 1029 break; 1030 case CMD_ICCS: 1031 trace_esp_mem_writeb_cmd_iccs(val); 1032 write_response(s); 1033 s->rregs[ESP_RINTR] |= INTR_FC; 1034 s->rregs[ESP_RSTAT] |= STAT_MI; 1035 break; 1036 case CMD_MSGACC: 1037 trace_esp_mem_writeb_cmd_msgacc(val); 1038 s->rregs[ESP_RINTR] |= INTR_DC; 1039 s->rregs[ESP_RSEQ] = 0; 1040 s->rregs[ESP_RFLAGS] = 0; 1041 esp_raise_irq(s); 1042 break; 1043 case CMD_PAD: 1044 trace_esp_mem_writeb_cmd_pad(val); 1045 s->rregs[ESP_RSTAT] = STAT_TC; 1046 s->rregs[ESP_RINTR] |= INTR_FC; 1047 s->rregs[ESP_RSEQ] = 0; 1048 break; 1049 case CMD_SATN: 1050 trace_esp_mem_writeb_cmd_satn(val); 1051 break; 1052 case CMD_RSTATN: 1053 trace_esp_mem_writeb_cmd_rstatn(val); 1054 break; 1055 case CMD_SEL: 1056 trace_esp_mem_writeb_cmd_sel(val); 1057 handle_s_without_atn(s); 1058 break; 1059 case CMD_SELATN: 1060 trace_esp_mem_writeb_cmd_selatn(val); 1061 handle_satn(s); 1062 break; 1063 case CMD_SELATNS: 1064 trace_esp_mem_writeb_cmd_selatns(val); 1065 handle_satn_stop(s); 1066 break; 1067 case CMD_ENSEL: 1068 trace_esp_mem_writeb_cmd_ensel(val); 1069 s->rregs[ESP_RINTR] = 0; 1070 break; 1071 case CMD_DISSEL: 1072 trace_esp_mem_writeb_cmd_dissel(val); 1073 s->rregs[ESP_RINTR] = 0; 1074 esp_raise_irq(s); 1075 break; 1076 default: 1077 trace_esp_error_unhandled_command(val); 1078 break; 1079 } 1080 break; 1081 case ESP_WBUSID ... ESP_WSYNO: 1082 break; 1083 case ESP_CFG1: 1084 case ESP_CFG2: case ESP_CFG3: 1085 case ESP_RES3: case ESP_RES4: 1086 s->rregs[saddr] = val; 1087 break; 1088 case ESP_WCCF ... ESP_WTEST: 1089 break; 1090 default: 1091 trace_esp_error_invalid_write(val, saddr); 1092 return; 1093 } 1094 s->wregs[saddr] = val; 1095 } 1096 1097 static bool esp_mem_accepts(void *opaque, hwaddr addr, 1098 unsigned size, bool is_write, 1099 MemTxAttrs attrs) 1100 { 1101 return (size == 1) || (is_write && size == 4); 1102 } 1103 1104 static bool esp_is_before_version_5(void *opaque, int version_id) 1105 { 1106 ESPState *s = ESP(opaque); 1107 1108 version_id = MIN(version_id, s->mig_version_id); 1109 return version_id < 5; 1110 } 1111 1112 static bool esp_is_version_5(void *opaque, int version_id) 1113 { 1114 ESPState *s = ESP(opaque); 1115 1116 version_id = MIN(version_id, s->mig_version_id); 1117 return version_id == 5; 1118 } 1119 1120 int esp_pre_save(void *opaque) 1121 { 1122 ESPState *s = ESP(object_resolve_path_component( 1123 OBJECT(opaque), "esp")); 1124 1125 s->mig_version_id = vmstate_esp.version_id; 1126 return 0; 1127 } 1128 1129 static int esp_post_load(void *opaque, int version_id) 1130 { 1131 ESPState *s = ESP(opaque); 1132 int len, i; 1133 1134 version_id = MIN(version_id, s->mig_version_id); 1135 1136 if (version_id < 5) { 1137 esp_set_tc(s, s->mig_dma_left); 1138 1139 /* Migrate ti_buf to fifo */ 1140 len = s->mig_ti_wptr - s->mig_ti_rptr; 1141 for (i = 0; i < len; i++) { 1142 fifo8_push(&s->fifo, s->mig_ti_buf[i]); 1143 } 1144 1145 /* Migrate cmdbuf to cmdfifo */ 1146 for (i = 0; i < s->mig_cmdlen; i++) { 1147 fifo8_push(&s->cmdfifo, s->mig_cmdbuf[i]); 1148 } 1149 } 1150 1151 s->mig_version_id = vmstate_esp.version_id; 1152 return 0; 1153 } 1154 1155 const VMStateDescription vmstate_esp = { 1156 .name = "esp", 1157 .version_id = 5, 1158 .minimum_version_id = 3, 1159 .post_load = esp_post_load, 1160 .fields = (VMStateField[]) { 1161 VMSTATE_BUFFER(rregs, ESPState), 1162 VMSTATE_BUFFER(wregs, ESPState), 1163 VMSTATE_INT32(ti_size, ESPState), 1164 VMSTATE_UINT32_TEST(mig_ti_rptr, ESPState, esp_is_before_version_5), 1165 VMSTATE_UINT32_TEST(mig_ti_wptr, ESPState, esp_is_before_version_5), 1166 VMSTATE_BUFFER_TEST(mig_ti_buf, ESPState, esp_is_before_version_5), 1167 VMSTATE_UINT32(status, ESPState), 1168 VMSTATE_UINT32_TEST(mig_deferred_status, ESPState, 1169 esp_is_before_version_5), 1170 VMSTATE_BOOL_TEST(mig_deferred_complete, ESPState, 1171 esp_is_before_version_5), 1172 VMSTATE_UINT32(dma, ESPState), 1173 VMSTATE_STATIC_BUFFER(mig_cmdbuf, ESPState, 0, 1174 esp_is_before_version_5, 0, 16), 1175 VMSTATE_STATIC_BUFFER(mig_cmdbuf, ESPState, 4, 1176 esp_is_before_version_5, 16, 1177 sizeof(typeof_field(ESPState, mig_cmdbuf))), 1178 VMSTATE_UINT32_TEST(mig_cmdlen, ESPState, esp_is_before_version_5), 1179 VMSTATE_UINT32(do_cmd, ESPState), 1180 VMSTATE_UINT32_TEST(mig_dma_left, ESPState, esp_is_before_version_5), 1181 VMSTATE_BOOL_TEST(data_in_ready, ESPState, esp_is_version_5), 1182 VMSTATE_UINT8_TEST(cmdfifo_cdb_offset, ESPState, esp_is_version_5), 1183 VMSTATE_FIFO8_TEST(fifo, ESPState, esp_is_version_5), 1184 VMSTATE_FIFO8_TEST(cmdfifo, ESPState, esp_is_version_5), 1185 VMSTATE_UINT8_TEST(ti_cmd, ESPState, esp_is_version_5), 1186 VMSTATE_END_OF_LIST() 1187 }, 1188 }; 1189 1190 static void sysbus_esp_mem_write(void *opaque, hwaddr addr, 1191 uint64_t val, unsigned int size) 1192 { 1193 SysBusESPState *sysbus = opaque; 1194 ESPState *s = ESP(&sysbus->esp); 1195 uint32_t saddr; 1196 1197 saddr = addr >> sysbus->it_shift; 1198 esp_reg_write(s, saddr, val); 1199 } 1200 1201 static uint64_t sysbus_esp_mem_read(void *opaque, hwaddr addr, 1202 unsigned int size) 1203 { 1204 SysBusESPState *sysbus = opaque; 1205 ESPState *s = ESP(&sysbus->esp); 1206 uint32_t saddr; 1207 1208 saddr = addr >> sysbus->it_shift; 1209 return esp_reg_read(s, saddr); 1210 } 1211 1212 static const MemoryRegionOps sysbus_esp_mem_ops = { 1213 .read = sysbus_esp_mem_read, 1214 .write = sysbus_esp_mem_write, 1215 .endianness = DEVICE_NATIVE_ENDIAN, 1216 .valid.accepts = esp_mem_accepts, 1217 }; 1218 1219 static void sysbus_esp_pdma_write(void *opaque, hwaddr addr, 1220 uint64_t val, unsigned int size) 1221 { 1222 SysBusESPState *sysbus = opaque; 1223 ESPState *s = ESP(&sysbus->esp); 1224 1225 trace_esp_pdma_write(size); 1226 1227 switch (size) { 1228 case 1: 1229 esp_pdma_write(s, val); 1230 break; 1231 case 2: 1232 esp_pdma_write(s, val >> 8); 1233 esp_pdma_write(s, val); 1234 break; 1235 } 1236 s->pdma_cb(s); 1237 } 1238 1239 static uint64_t sysbus_esp_pdma_read(void *opaque, hwaddr addr, 1240 unsigned int size) 1241 { 1242 SysBusESPState *sysbus = opaque; 1243 ESPState *s = ESP(&sysbus->esp); 1244 uint64_t val = 0; 1245 1246 trace_esp_pdma_read(size); 1247 1248 switch (size) { 1249 case 1: 1250 val = esp_pdma_read(s); 1251 break; 1252 case 2: 1253 val = esp_pdma_read(s); 1254 val = (val << 8) | esp_pdma_read(s); 1255 break; 1256 } 1257 if (fifo8_num_used(&s->fifo) < 2) { 1258 s->pdma_cb(s); 1259 } 1260 return val; 1261 } 1262 1263 static const MemoryRegionOps sysbus_esp_pdma_ops = { 1264 .read = sysbus_esp_pdma_read, 1265 .write = sysbus_esp_pdma_write, 1266 .endianness = DEVICE_NATIVE_ENDIAN, 1267 .valid.min_access_size = 1, 1268 .valid.max_access_size = 4, 1269 .impl.min_access_size = 1, 1270 .impl.max_access_size = 2, 1271 }; 1272 1273 static const struct SCSIBusInfo esp_scsi_info = { 1274 .tcq = false, 1275 .max_target = ESP_MAX_DEVS, 1276 .max_lun = 7, 1277 1278 .transfer_data = esp_transfer_data, 1279 .complete = esp_command_complete, 1280 .cancel = esp_request_cancelled 1281 }; 1282 1283 static void sysbus_esp_gpio_demux(void *opaque, int irq, int level) 1284 { 1285 SysBusESPState *sysbus = SYSBUS_ESP(opaque); 1286 ESPState *s = ESP(&sysbus->esp); 1287 1288 switch (irq) { 1289 case 0: 1290 parent_esp_reset(s, irq, level); 1291 break; 1292 case 1: 1293 esp_dma_enable(opaque, irq, level); 1294 break; 1295 } 1296 } 1297 1298 static void sysbus_esp_realize(DeviceState *dev, Error **errp) 1299 { 1300 SysBusDevice *sbd = SYS_BUS_DEVICE(dev); 1301 SysBusESPState *sysbus = SYSBUS_ESP(dev); 1302 ESPState *s = ESP(&sysbus->esp); 1303 1304 if (!qdev_realize(DEVICE(s), NULL, errp)) { 1305 return; 1306 } 1307 1308 sysbus_init_irq(sbd, &s->irq); 1309 sysbus_init_irq(sbd, &s->irq_data); 1310 assert(sysbus->it_shift != -1); 1311 1312 s->chip_id = TCHI_FAS100A; 1313 memory_region_init_io(&sysbus->iomem, OBJECT(sysbus), &sysbus_esp_mem_ops, 1314 sysbus, "esp-regs", ESP_REGS << sysbus->it_shift); 1315 sysbus_init_mmio(sbd, &sysbus->iomem); 1316 memory_region_init_io(&sysbus->pdma, OBJECT(sysbus), &sysbus_esp_pdma_ops, 1317 sysbus, "esp-pdma", 4); 1318 sysbus_init_mmio(sbd, &sysbus->pdma); 1319 1320 qdev_init_gpio_in(dev, sysbus_esp_gpio_demux, 2); 1321 1322 scsi_bus_new(&s->bus, sizeof(s->bus), dev, &esp_scsi_info, NULL); 1323 } 1324 1325 static void sysbus_esp_hard_reset(DeviceState *dev) 1326 { 1327 SysBusESPState *sysbus = SYSBUS_ESP(dev); 1328 ESPState *s = ESP(&sysbus->esp); 1329 1330 esp_hard_reset(s); 1331 } 1332 1333 static void sysbus_esp_init(Object *obj) 1334 { 1335 SysBusESPState *sysbus = SYSBUS_ESP(obj); 1336 1337 object_initialize_child(obj, "esp", &sysbus->esp, TYPE_ESP); 1338 } 1339 1340 static const VMStateDescription vmstate_sysbus_esp_scsi = { 1341 .name = "sysbusespscsi", 1342 .version_id = 2, 1343 .minimum_version_id = 1, 1344 .pre_save = esp_pre_save, 1345 .fields = (VMStateField[]) { 1346 VMSTATE_UINT8_V(esp.mig_version_id, SysBusESPState, 2), 1347 VMSTATE_STRUCT(esp, SysBusESPState, 0, vmstate_esp, ESPState), 1348 VMSTATE_END_OF_LIST() 1349 } 1350 }; 1351 1352 static void sysbus_esp_class_init(ObjectClass *klass, void *data) 1353 { 1354 DeviceClass *dc = DEVICE_CLASS(klass); 1355 1356 dc->realize = sysbus_esp_realize; 1357 dc->reset = sysbus_esp_hard_reset; 1358 dc->vmsd = &vmstate_sysbus_esp_scsi; 1359 set_bit(DEVICE_CATEGORY_STORAGE, dc->categories); 1360 } 1361 1362 static const TypeInfo sysbus_esp_info = { 1363 .name = TYPE_SYSBUS_ESP, 1364 .parent = TYPE_SYS_BUS_DEVICE, 1365 .instance_init = sysbus_esp_init, 1366 .instance_size = sizeof(SysBusESPState), 1367 .class_init = sysbus_esp_class_init, 1368 }; 1369 1370 static void esp_finalize(Object *obj) 1371 { 1372 ESPState *s = ESP(obj); 1373 1374 fifo8_destroy(&s->fifo); 1375 fifo8_destroy(&s->cmdfifo); 1376 } 1377 1378 static void esp_init(Object *obj) 1379 { 1380 ESPState *s = ESP(obj); 1381 1382 fifo8_create(&s->fifo, ESP_FIFO_SZ); 1383 fifo8_create(&s->cmdfifo, ESP_CMDFIFO_SZ); 1384 } 1385 1386 static void esp_class_init(ObjectClass *klass, void *data) 1387 { 1388 DeviceClass *dc = DEVICE_CLASS(klass); 1389 1390 /* internal device for sysbusesp/pciespscsi, not user-creatable */ 1391 dc->user_creatable = false; 1392 set_bit(DEVICE_CATEGORY_STORAGE, dc->categories); 1393 } 1394 1395 static const TypeInfo esp_info = { 1396 .name = TYPE_ESP, 1397 .parent = TYPE_DEVICE, 1398 .instance_init = esp_init, 1399 .instance_finalize = esp_finalize, 1400 .instance_size = sizeof(ESPState), 1401 .class_init = esp_class_init, 1402 }; 1403 1404 static void esp_register_types(void) 1405 { 1406 type_register_static(&sysbus_esp_info); 1407 type_register_static(&esp_info); 1408 } 1409 1410 type_init(esp_register_types) 1411