1 /* 2 * QEMU ESP/NCR53C9x emulation 3 * 4 * Copyright (c) 2005-2006 Fabrice Bellard 5 * Copyright (c) 2012 Herve Poussineau 6 * 7 * Permission is hereby granted, free of charge, to any person obtaining a copy 8 * of this software and associated documentation files (the "Software"), to deal 9 * in the Software without restriction, including without limitation the rights 10 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 11 * copies of the Software, and to permit persons to whom the Software is 12 * furnished to do so, subject to the following conditions: 13 * 14 * The above copyright notice and this permission notice shall be included in 15 * all copies or substantial portions of the Software. 16 * 17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 22 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 23 * THE SOFTWARE. 24 */ 25 26 #include "qemu/osdep.h" 27 #include "hw/sysbus.h" 28 #include "migration/vmstate.h" 29 #include "hw/irq.h" 30 #include "hw/scsi/esp.h" 31 #include "trace.h" 32 #include "qemu/log.h" 33 #include "qemu/module.h" 34 35 /* 36 * On Sparc32, this is the ESP (NCR53C90) part of chip STP2000 (Master I/O), 37 * also produced as NCR89C100. See 38 * http://www.ibiblio.org/pub/historic-linux/early-ports/Sparc/NCR/NCR89C100.txt 39 * and 40 * http://www.ibiblio.org/pub/historic-linux/early-ports/Sparc/NCR/NCR53C9X.txt 41 * 42 * On Macintosh Quadra it is a NCR53C96. 43 */ 44 45 static void esp_raise_irq(ESPState *s) 46 { 47 if (!(s->rregs[ESP_RSTAT] & STAT_INT)) { 48 s->rregs[ESP_RSTAT] |= STAT_INT; 49 qemu_irq_raise(s->irq); 50 trace_esp_raise_irq(); 51 } 52 } 53 54 static void esp_lower_irq(ESPState *s) 55 { 56 if (s->rregs[ESP_RSTAT] & STAT_INT) { 57 s->rregs[ESP_RSTAT] &= ~STAT_INT; 58 qemu_irq_lower(s->irq); 59 trace_esp_lower_irq(); 60 } 61 } 62 63 static void esp_raise_drq(ESPState *s) 64 { 65 qemu_irq_raise(s->irq_data); 66 trace_esp_raise_drq(); 67 } 68 69 static void esp_lower_drq(ESPState *s) 70 { 71 qemu_irq_lower(s->irq_data); 72 trace_esp_lower_drq(); 73 } 74 75 void esp_dma_enable(ESPState *s, int irq, int level) 76 { 77 if (level) { 78 s->dma_enabled = 1; 79 trace_esp_dma_enable(); 80 if (s->dma_cb) { 81 s->dma_cb(s); 82 s->dma_cb = NULL; 83 } 84 } else { 85 trace_esp_dma_disable(); 86 s->dma_enabled = 0; 87 } 88 } 89 90 void esp_request_cancelled(SCSIRequest *req) 91 { 92 ESPState *s = req->hba_private; 93 94 if (req == s->current_req) { 95 scsi_req_unref(s->current_req); 96 s->current_req = NULL; 97 s->current_dev = NULL; 98 s->async_len = 0; 99 } 100 } 101 102 static void esp_fifo_push(Fifo8 *fifo, uint8_t val) 103 { 104 if (fifo8_num_used(fifo) == fifo->capacity) { 105 trace_esp_error_fifo_overrun(); 106 return; 107 } 108 109 fifo8_push(fifo, val); 110 } 111 112 static uint8_t esp_fifo_pop(Fifo8 *fifo) 113 { 114 if (fifo8_is_empty(fifo)) { 115 return 0; 116 } 117 118 return fifo8_pop(fifo); 119 } 120 121 static uint32_t esp_fifo_pop_buf(Fifo8 *fifo, uint8_t *dest, int maxlen) 122 { 123 const uint8_t *buf; 124 uint32_t n, n2; 125 int len; 126 127 if (maxlen == 0) { 128 return 0; 129 } 130 131 len = maxlen; 132 buf = fifo8_pop_buf(fifo, len, &n); 133 if (dest) { 134 memcpy(dest, buf, n); 135 } 136 137 /* Add FIFO wraparound if needed */ 138 len -= n; 139 len = MIN(len, fifo8_num_used(fifo)); 140 if (len) { 141 buf = fifo8_pop_buf(fifo, len, &n2); 142 if (dest) { 143 memcpy(&dest[n], buf, n2); 144 } 145 n += n2; 146 } 147 148 return n; 149 } 150 151 static uint32_t esp_get_tc(ESPState *s) 152 { 153 uint32_t dmalen; 154 155 dmalen = s->rregs[ESP_TCLO]; 156 dmalen |= s->rregs[ESP_TCMID] << 8; 157 dmalen |= s->rregs[ESP_TCHI] << 16; 158 159 return dmalen; 160 } 161 162 static void esp_set_tc(ESPState *s, uint32_t dmalen) 163 { 164 uint32_t old_tc = esp_get_tc(s); 165 166 s->rregs[ESP_TCLO] = dmalen; 167 s->rregs[ESP_TCMID] = dmalen >> 8; 168 s->rregs[ESP_TCHI] = dmalen >> 16; 169 170 if (old_tc && dmalen == 0) { 171 s->rregs[ESP_RSTAT] |= STAT_TC; 172 } 173 } 174 175 static uint32_t esp_get_stc(ESPState *s) 176 { 177 uint32_t dmalen; 178 179 dmalen = s->wregs[ESP_TCLO]; 180 dmalen |= s->wregs[ESP_TCMID] << 8; 181 dmalen |= s->wregs[ESP_TCHI] << 16; 182 183 return dmalen; 184 } 185 186 static const char *esp_phase_names[8] = { 187 "DATA OUT", "DATA IN", "COMMAND", "STATUS", 188 "(reserved)", "(reserved)", "MESSAGE OUT", "MESSAGE IN" 189 }; 190 191 static void esp_set_phase(ESPState *s, uint8_t phase) 192 { 193 s->rregs[ESP_RSTAT] &= ~7; 194 s->rregs[ESP_RSTAT] |= phase; 195 196 trace_esp_set_phase(esp_phase_names[phase]); 197 } 198 199 static uint8_t esp_get_phase(ESPState *s) 200 { 201 return s->rregs[ESP_RSTAT] & 7; 202 } 203 204 static uint8_t esp_pdma_read(ESPState *s) 205 { 206 uint8_t val; 207 208 val = esp_fifo_pop(&s->fifo); 209 return val; 210 } 211 212 static void esp_pdma_write(ESPState *s, uint8_t val) 213 { 214 uint32_t dmalen = esp_get_tc(s); 215 216 if (dmalen == 0) { 217 return; 218 } 219 220 esp_fifo_push(&s->fifo, val); 221 222 dmalen--; 223 esp_set_tc(s, dmalen); 224 } 225 226 static void esp_set_pdma_cb(ESPState *s, enum pdma_cb cb) 227 { 228 s->pdma_cb = cb; 229 } 230 231 static int esp_select(ESPState *s) 232 { 233 int target; 234 235 target = s->wregs[ESP_WBUSID] & BUSID_DID; 236 237 s->ti_size = 0; 238 239 if (s->current_req) { 240 /* Started a new command before the old one finished. Cancel it. */ 241 scsi_req_cancel(s->current_req); 242 } 243 244 s->current_dev = scsi_device_find(&s->bus, 0, target, 0); 245 if (!s->current_dev) { 246 /* No such drive */ 247 s->rregs[ESP_RSTAT] = 0; 248 s->rregs[ESP_RINTR] = INTR_DC; 249 s->rregs[ESP_RSEQ] = SEQ_0; 250 esp_raise_irq(s); 251 return -1; 252 } 253 254 /* 255 * Note that we deliberately don't raise the IRQ here: this will be done 256 * either in do_command_phase() for DATA OUT transfers or by the deferred 257 * IRQ mechanism in esp_transfer_data() for DATA IN transfers 258 */ 259 s->rregs[ESP_RINTR] |= INTR_FC; 260 s->rregs[ESP_RSEQ] = SEQ_CD; 261 return 0; 262 } 263 264 static uint32_t get_cmd(ESPState *s, uint32_t maxlen) 265 { 266 uint8_t buf[ESP_CMDFIFO_SZ]; 267 uint32_t dmalen, n; 268 int target; 269 270 target = s->wregs[ESP_WBUSID] & BUSID_DID; 271 if (s->dma) { 272 dmalen = MIN(esp_get_tc(s), maxlen); 273 if (dmalen == 0) { 274 return 0; 275 } 276 if (s->dma_memory_read) { 277 s->dma_memory_read(s->dma_opaque, buf, dmalen); 278 dmalen = MIN(fifo8_num_free(&s->cmdfifo), dmalen); 279 fifo8_push_all(&s->cmdfifo, buf, dmalen); 280 esp_set_tc(s, esp_get_tc(s) - dmalen); 281 } else { 282 return 0; 283 } 284 } else { 285 dmalen = MIN(fifo8_num_used(&s->fifo), maxlen); 286 if (dmalen == 0) { 287 return 0; 288 } 289 n = esp_fifo_pop_buf(&s->fifo, buf, dmalen); 290 n = MIN(fifo8_num_free(&s->cmdfifo), n); 291 fifo8_push_all(&s->cmdfifo, buf, n); 292 } 293 trace_esp_get_cmd(dmalen, target); 294 295 return dmalen; 296 } 297 298 static void do_command_phase(ESPState *s) 299 { 300 uint32_t cmdlen; 301 int32_t datalen; 302 SCSIDevice *current_lun; 303 uint8_t buf[ESP_CMDFIFO_SZ]; 304 305 trace_esp_do_command_phase(s->lun); 306 cmdlen = fifo8_num_used(&s->cmdfifo); 307 if (!cmdlen || !s->current_dev) { 308 return; 309 } 310 esp_fifo_pop_buf(&s->cmdfifo, buf, cmdlen); 311 312 current_lun = scsi_device_find(&s->bus, 0, s->current_dev->id, s->lun); 313 if (!current_lun) { 314 /* No such drive */ 315 s->rregs[ESP_RSTAT] = 0; 316 s->rregs[ESP_RINTR] = INTR_DC; 317 s->rregs[ESP_RSEQ] = SEQ_0; 318 esp_raise_irq(s); 319 return; 320 } 321 322 s->current_req = scsi_req_new(current_lun, 0, s->lun, buf, cmdlen, s); 323 datalen = scsi_req_enqueue(s->current_req); 324 s->ti_size = datalen; 325 fifo8_reset(&s->cmdfifo); 326 if (datalen != 0) { 327 s->ti_cmd = 0; 328 if (datalen > 0) { 329 /* 330 * Switch to DATA IN phase but wait until initial data xfer is 331 * complete before raising the command completion interrupt 332 */ 333 s->data_in_ready = false; 334 esp_set_phase(s, STAT_DI); 335 } else { 336 esp_set_phase(s, STAT_DO); 337 s->rregs[ESP_RINTR] |= INTR_BS | INTR_FC; 338 esp_raise_irq(s); 339 esp_lower_drq(s); 340 } 341 scsi_req_continue(s->current_req); 342 return; 343 } 344 } 345 346 static void do_message_phase(ESPState *s) 347 { 348 if (s->cmdfifo_cdb_offset) { 349 uint8_t message = esp_fifo_pop(&s->cmdfifo); 350 351 trace_esp_do_identify(message); 352 s->lun = message & 7; 353 s->cmdfifo_cdb_offset--; 354 } 355 356 /* Ignore extended messages for now */ 357 if (s->cmdfifo_cdb_offset) { 358 int len = MIN(s->cmdfifo_cdb_offset, fifo8_num_used(&s->cmdfifo)); 359 esp_fifo_pop_buf(&s->cmdfifo, NULL, len); 360 s->cmdfifo_cdb_offset = 0; 361 } 362 } 363 364 static void do_cmd(ESPState *s) 365 { 366 do_message_phase(s); 367 assert(s->cmdfifo_cdb_offset == 0); 368 do_command_phase(s); 369 } 370 371 static void satn_pdma_cb(ESPState *s) 372 { 373 uint8_t buf[ESP_FIFO_SZ]; 374 int n; 375 376 /* Copy FIFO into cmdfifo */ 377 n = esp_fifo_pop_buf(&s->fifo, buf, fifo8_num_used(&s->fifo)); 378 n = MIN(fifo8_num_free(&s->cmdfifo), n); 379 fifo8_push_all(&s->cmdfifo, buf, n); 380 381 if (!esp_get_tc(s) && !fifo8_is_empty(&s->cmdfifo)) { 382 s->cmdfifo_cdb_offset = 1; 383 s->do_cmd = 0; 384 do_cmd(s); 385 } 386 } 387 388 static void handle_satn(ESPState *s) 389 { 390 int32_t cmdlen; 391 392 if (s->dma && !s->dma_enabled) { 393 s->dma_cb = handle_satn; 394 return; 395 } 396 esp_set_pdma_cb(s, SATN_PDMA_CB); 397 if (esp_select(s) < 0) { 398 return; 399 } 400 cmdlen = get_cmd(s, ESP_CMDFIFO_SZ); 401 if (cmdlen > 0) { 402 s->cmdfifo_cdb_offset = 1; 403 s->do_cmd = 0; 404 do_cmd(s); 405 } else if (cmdlen == 0) { 406 if (s->dma) { 407 esp_raise_drq(s); 408 } 409 s->do_cmd = 1; 410 /* Target present, but no cmd yet - switch to command phase */ 411 s->rregs[ESP_RSEQ] = SEQ_CD; 412 esp_set_phase(s, STAT_CD); 413 } 414 } 415 416 static void handle_s_without_atn(ESPState *s) 417 { 418 int32_t cmdlen; 419 420 if (s->dma && !s->dma_enabled) { 421 s->dma_cb = handle_s_without_atn; 422 return; 423 } 424 esp_set_pdma_cb(s, DO_DMA_PDMA_CB); 425 if (esp_select(s) < 0) { 426 return; 427 } 428 cmdlen = get_cmd(s, ESP_CMDFIFO_SZ); 429 if (cmdlen > 0) { 430 s->cmdfifo_cdb_offset = 0; 431 s->do_cmd = 0; 432 do_cmd(s); 433 } else if (cmdlen == 0) { 434 if (s->dma) { 435 esp_raise_drq(s); 436 } 437 s->do_cmd = 1; 438 /* Target present, but no cmd yet - switch to command phase */ 439 s->rregs[ESP_RSEQ] = SEQ_CD; 440 esp_set_phase(s, STAT_CD); 441 } 442 } 443 444 static void satn_stop_pdma_cb(ESPState *s) 445 { 446 uint8_t buf[ESP_FIFO_SZ]; 447 int n; 448 449 /* Copy FIFO into cmdfifo */ 450 n = esp_fifo_pop_buf(&s->fifo, buf, fifo8_num_used(&s->fifo)); 451 n = MIN(fifo8_num_free(&s->cmdfifo), n); 452 fifo8_push_all(&s->cmdfifo, buf, n); 453 454 if (!esp_get_tc(s) && !fifo8_is_empty(&s->cmdfifo)) { 455 trace_esp_handle_satn_stop(fifo8_num_used(&s->cmdfifo)); 456 s->do_cmd = 1; 457 s->cmdfifo_cdb_offset = 1; 458 esp_set_phase(s, STAT_CD); 459 s->rregs[ESP_RSTAT] |= STAT_TC; 460 s->rregs[ESP_RINTR] |= INTR_BS | INTR_FC; 461 s->rregs[ESP_RSEQ] = SEQ_CD; 462 esp_raise_irq(s); 463 } 464 } 465 466 static void handle_satn_stop(ESPState *s) 467 { 468 int32_t cmdlen; 469 470 if (s->dma && !s->dma_enabled) { 471 s->dma_cb = handle_satn_stop; 472 return; 473 } 474 esp_set_pdma_cb(s, SATN_STOP_PDMA_CB); 475 if (esp_select(s) < 0) { 476 return; 477 } 478 cmdlen = get_cmd(s, 1); 479 if (cmdlen > 0) { 480 trace_esp_handle_satn_stop(fifo8_num_used(&s->cmdfifo)); 481 s->do_cmd = 1; 482 s->cmdfifo_cdb_offset = 1; 483 esp_set_phase(s, STAT_MO); 484 s->rregs[ESP_RINTR] |= INTR_BS | INTR_FC; 485 s->rregs[ESP_RSEQ] = SEQ_MO; 486 esp_raise_irq(s); 487 } else if (cmdlen == 0) { 488 if (s->dma) { 489 esp_raise_drq(s); 490 } 491 s->do_cmd = 1; 492 /* Target present, switch to message out phase */ 493 s->rregs[ESP_RSEQ] = SEQ_MO; 494 esp_set_phase(s, STAT_MO); 495 } 496 } 497 498 static void write_response_pdma_cb(ESPState *s) 499 { 500 esp_set_phase(s, STAT_ST); 501 s->rregs[ESP_RINTR] |= INTR_BS | INTR_FC; 502 s->rregs[ESP_RSEQ] = SEQ_CD; 503 esp_raise_irq(s); 504 } 505 506 static void write_response(ESPState *s) 507 { 508 uint8_t buf[2]; 509 510 trace_esp_write_response(s->status); 511 512 buf[0] = s->status; 513 buf[1] = 0; 514 515 if (s->dma) { 516 if (s->dma_memory_write) { 517 s->dma_memory_write(s->dma_opaque, buf, 2); 518 esp_set_phase(s, STAT_ST); 519 s->rregs[ESP_RINTR] |= INTR_BS | INTR_FC; 520 s->rregs[ESP_RSEQ] = SEQ_CD; 521 } else { 522 esp_set_pdma_cb(s, WRITE_RESPONSE_PDMA_CB); 523 esp_raise_drq(s); 524 return; 525 } 526 } else { 527 fifo8_reset(&s->fifo); 528 fifo8_push_all(&s->fifo, buf, 2); 529 s->rregs[ESP_RFLAGS] = 2; 530 } 531 esp_raise_irq(s); 532 } 533 534 static void esp_dma_ti_check(ESPState *s) 535 { 536 if (esp_get_tc(s) == 0 && fifo8_num_used(&s->fifo) < 2) { 537 s->rregs[ESP_RINTR] |= INTR_BS; 538 esp_raise_irq(s); 539 esp_lower_drq(s); 540 } 541 } 542 543 static void do_dma_pdma_cb(ESPState *s) 544 { 545 uint8_t buf[ESP_CMDFIFO_SZ]; 546 int len; 547 uint32_t n; 548 549 switch (esp_get_phase(s)) { 550 case STAT_MO: 551 case STAT_CD: 552 /* Copy FIFO into cmdfifo */ 553 n = esp_fifo_pop_buf(&s->fifo, buf, fifo8_num_used(&s->fifo)); 554 n = MIN(fifo8_num_free(&s->cmdfifo), n); 555 fifo8_push_all(&s->cmdfifo, buf, n); 556 557 /* Ensure we have received complete command after SATN and stop */ 558 if (esp_get_tc(s) || fifo8_is_empty(&s->cmdfifo)) { 559 return; 560 } 561 562 s->ti_size = 0; 563 if (esp_get_phase(s) == STAT_CD) { 564 /* No command received */ 565 if (s->cmdfifo_cdb_offset == fifo8_num_used(&s->cmdfifo)) { 566 return; 567 } 568 569 /* Command has been received */ 570 s->do_cmd = 0; 571 do_cmd(s); 572 } else { 573 /* 574 * Extra message out bytes received: update cmdfifo_cdb_offset 575 * and then switch to command phase 576 */ 577 s->cmdfifo_cdb_offset = fifo8_num_used(&s->cmdfifo); 578 esp_set_phase(s, STAT_CD); 579 s->rregs[ESP_RSEQ] = SEQ_CD; 580 s->rregs[ESP_RINTR] |= INTR_BS; 581 esp_raise_irq(s); 582 } 583 break; 584 585 case STAT_DO: 586 if (!s->current_req) { 587 return; 588 } 589 /* Copy FIFO data to device */ 590 len = MIN(s->async_len, ESP_FIFO_SZ); 591 len = MIN(len, fifo8_num_used(&s->fifo)); 592 n = esp_fifo_pop_buf(&s->fifo, s->async_buf, len); 593 s->async_buf += n; 594 s->async_len -= n; 595 s->ti_size += n; 596 597 if (s->async_len == 0 && fifo8_num_used(&s->fifo) < 2) { 598 /* Defer until the scsi layer has completed */ 599 scsi_req_continue(s->current_req); 600 return; 601 } 602 603 esp_dma_ti_check(s); 604 break; 605 606 case STAT_DI: 607 if (!s->current_req) { 608 return; 609 } 610 /* Copy device data to FIFO */ 611 len = MIN(s->async_len, esp_get_tc(s)); 612 len = MIN(len, fifo8_num_free(&s->fifo)); 613 fifo8_push_all(&s->fifo, s->async_buf, len); 614 s->async_buf += len; 615 s->async_len -= len; 616 s->ti_size -= len; 617 esp_set_tc(s, esp_get_tc(s) - len); 618 619 if (s->async_len == 0 && fifo8_num_used(&s->fifo) < 2) { 620 /* Defer until the scsi layer has completed */ 621 scsi_req_continue(s->current_req); 622 s->data_in_ready = false; 623 return; 624 } 625 626 esp_dma_ti_check(s); 627 break; 628 } 629 } 630 631 static void esp_do_dma(ESPState *s) 632 { 633 uint32_t len, cmdlen; 634 uint8_t buf[ESP_CMDFIFO_SZ]; 635 int n; 636 637 len = esp_get_tc(s); 638 639 switch (esp_get_phase(s)) { 640 case STAT_MO: 641 case STAT_CD: 642 cmdlen = fifo8_num_used(&s->cmdfifo); 643 trace_esp_do_dma(cmdlen, len); 644 if (s->dma_memory_read) { 645 len = MIN(len, fifo8_num_free(&s->cmdfifo)); 646 s->dma_memory_read(s->dma_opaque, buf, len); 647 fifo8_push_all(&s->cmdfifo, buf, len); 648 esp_set_tc(s, esp_get_tc(s) - len); 649 } else { 650 n = esp_fifo_pop_buf(&s->fifo, buf, fifo8_num_used(&s->fifo)); 651 n = MIN(fifo8_num_free(&s->cmdfifo), n); 652 fifo8_push_all(&s->cmdfifo, buf, n); 653 esp_set_tc(s, esp_get_tc(s) - n); 654 655 esp_set_pdma_cb(s, DO_DMA_PDMA_CB); 656 esp_raise_drq(s); 657 658 /* Ensure we have received complete command after SATN and stop */ 659 if (esp_get_tc(s) || fifo8_is_empty(&s->cmdfifo)) { 660 return; 661 } 662 } 663 trace_esp_handle_ti_cmd(cmdlen); 664 s->ti_size = 0; 665 if (esp_get_phase(s) == STAT_CD) { 666 /* No command received */ 667 if (s->cmdfifo_cdb_offset == fifo8_num_used(&s->cmdfifo)) { 668 return; 669 } 670 671 /* Command has been received */ 672 s->do_cmd = 0; 673 do_cmd(s); 674 } else { 675 /* 676 * Extra message out bytes received: update cmdfifo_cdb_offset 677 * and then switch to command phase 678 */ 679 s->cmdfifo_cdb_offset = fifo8_num_used(&s->cmdfifo); 680 esp_set_phase(s, STAT_CD); 681 s->rregs[ESP_RSEQ] = SEQ_CD; 682 s->rregs[ESP_RINTR] |= INTR_BS; 683 esp_raise_irq(s); 684 } 685 break; 686 687 case STAT_DO: 688 if (!s->current_req) { 689 return; 690 } 691 if (s->async_len == 0 && esp_get_tc(s) && s->ti_size) { 692 /* Defer until data is available. */ 693 return; 694 } 695 if (len > s->async_len) { 696 len = s->async_len; 697 } 698 if (s->dma_memory_read) { 699 s->dma_memory_read(s->dma_opaque, s->async_buf, len); 700 701 esp_set_tc(s, esp_get_tc(s) - len); 702 s->async_buf += len; 703 s->async_len -= len; 704 s->ti_size += len; 705 706 if (s->async_len == 0 && fifo8_num_used(&s->fifo) < 2) { 707 /* Defer until the scsi layer has completed */ 708 scsi_req_continue(s->current_req); 709 return; 710 } 711 712 esp_dma_ti_check(s); 713 } else { 714 /* Copy FIFO data to device */ 715 len = MIN(s->async_len, ESP_FIFO_SZ); 716 len = MIN(len, fifo8_num_used(&s->fifo)); 717 n = esp_fifo_pop_buf(&s->fifo, s->async_buf, len); 718 s->async_buf += n; 719 s->async_len -= n; 720 s->ti_size += n; 721 722 esp_set_pdma_cb(s, DO_DMA_PDMA_CB); 723 esp_raise_drq(s); 724 725 if (s->async_len == 0 && fifo8_num_used(&s->fifo) < 2) { 726 /* Defer until the scsi layer has completed */ 727 scsi_req_continue(s->current_req); 728 return; 729 } 730 731 esp_dma_ti_check(s); 732 } 733 break; 734 735 case STAT_DI: 736 if (!s->current_req) { 737 return; 738 } 739 if (s->async_len == 0 && esp_get_tc(s) && s->ti_size) { 740 /* Defer until data is available. */ 741 return; 742 } 743 if (len > s->async_len) { 744 len = s->async_len; 745 } 746 if (s->dma_memory_write) { 747 s->dma_memory_write(s->dma_opaque, s->async_buf, len); 748 749 esp_set_tc(s, esp_get_tc(s) - len); 750 s->async_buf += len; 751 s->async_len -= len; 752 s->ti_size -= len; 753 754 if (s->async_len == 0 && fifo8_num_used(&s->fifo) < 2) { 755 /* Defer until the scsi layer has completed */ 756 scsi_req_continue(s->current_req); 757 return; 758 } 759 760 esp_dma_ti_check(s); 761 } else { 762 /* Copy device data to FIFO */ 763 len = MIN(len, fifo8_num_free(&s->fifo)); 764 fifo8_push_all(&s->fifo, s->async_buf, len); 765 s->async_buf += len; 766 s->async_len -= len; 767 s->ti_size -= len; 768 esp_set_tc(s, esp_get_tc(s) - len); 769 esp_set_pdma_cb(s, DO_DMA_PDMA_CB); 770 esp_raise_drq(s); 771 772 if (s->async_len == 0 && fifo8_num_used(&s->fifo) < 2) { 773 /* Defer until the scsi layer has completed */ 774 scsi_req_continue(s->current_req); 775 return; 776 } 777 778 esp_dma_ti_check(s); 779 } 780 break; 781 } 782 } 783 784 static void esp_do_nodma(ESPState *s) 785 { 786 uint8_t buf[ESP_FIFO_SZ]; 787 uint32_t cmdlen; 788 int len, n; 789 790 switch (esp_get_phase(s)) { 791 case STAT_MO: 792 case STAT_CD: 793 /* Copy FIFO into cmdfifo */ 794 n = esp_fifo_pop_buf(&s->fifo, buf, fifo8_num_used(&s->fifo)); 795 n = MIN(fifo8_num_free(&s->cmdfifo), n); 796 fifo8_push_all(&s->cmdfifo, buf, n); 797 798 cmdlen = fifo8_num_used(&s->cmdfifo); 799 trace_esp_handle_ti_cmd(cmdlen); 800 s->ti_size = 0; 801 if (esp_get_phase(s) == STAT_CD) { 802 /* No command received */ 803 if (s->cmdfifo_cdb_offset == fifo8_num_used(&s->cmdfifo)) { 804 return; 805 } 806 807 /* Command has been received */ 808 s->do_cmd = 0; 809 do_cmd(s); 810 } else { 811 /* 812 * Extra message out bytes received: update cmdfifo_cdb_offset 813 * and then switch to command phase 814 */ 815 s->cmdfifo_cdb_offset = fifo8_num_used(&s->cmdfifo); 816 esp_set_phase(s, STAT_CD); 817 s->rregs[ESP_RSEQ] = SEQ_CD; 818 s->rregs[ESP_RINTR] |= INTR_BS; 819 esp_raise_irq(s); 820 } 821 break; 822 823 case STAT_DO: 824 if (!s->current_req) { 825 return; 826 } 827 if (s->async_len == 0) { 828 /* Defer until data is available. */ 829 return; 830 } 831 len = MIN(s->async_len, ESP_FIFO_SZ); 832 len = MIN(len, fifo8_num_used(&s->fifo)); 833 esp_fifo_pop_buf(&s->fifo, s->async_buf, len); 834 s->async_buf += len; 835 s->async_len -= len; 836 s->ti_size += len; 837 838 if (s->async_len == 0) { 839 scsi_req_continue(s->current_req); 840 return; 841 } 842 843 s->rregs[ESP_RINTR] |= INTR_BS; 844 esp_raise_irq(s); 845 break; 846 847 case STAT_DI: 848 if (!s->current_req) { 849 return; 850 } 851 if (s->async_len == 0) { 852 /* Defer until data is available. */ 853 return; 854 } 855 if (fifo8_is_empty(&s->fifo)) { 856 fifo8_push(&s->fifo, s->async_buf[0]); 857 s->async_buf++; 858 s->async_len--; 859 s->ti_size--; 860 } 861 862 if (s->async_len == 0) { 863 scsi_req_continue(s->current_req); 864 return; 865 } 866 867 s->rregs[ESP_RINTR] |= INTR_BS; 868 esp_raise_irq(s); 869 break; 870 } 871 } 872 873 static void esp_pdma_cb(ESPState *s) 874 { 875 switch (s->pdma_cb) { 876 case SATN_PDMA_CB: 877 satn_pdma_cb(s); 878 break; 879 case SATN_STOP_PDMA_CB: 880 satn_stop_pdma_cb(s); 881 break; 882 case WRITE_RESPONSE_PDMA_CB: 883 write_response_pdma_cb(s); 884 break; 885 case DO_DMA_PDMA_CB: 886 do_dma_pdma_cb(s); 887 break; 888 default: 889 g_assert_not_reached(); 890 } 891 } 892 893 void esp_command_complete(SCSIRequest *req, size_t resid) 894 { 895 ESPState *s = req->hba_private; 896 int to_device = (esp_get_phase(s) == STAT_DO); 897 898 trace_esp_command_complete(); 899 900 /* 901 * Non-DMA transfers from the target will leave the last byte in 902 * the FIFO so don't reset ti_size in this case 903 */ 904 if (s->dma || to_device) { 905 if (s->ti_size != 0) { 906 trace_esp_command_complete_unexpected(); 907 } 908 } 909 910 s->async_len = 0; 911 if (req->status) { 912 trace_esp_command_complete_fail(); 913 } 914 s->status = req->status; 915 916 /* 917 * Switch to status phase. For non-DMA transfers from the target the last 918 * byte is still in the FIFO 919 */ 920 esp_set_phase(s, STAT_ST); 921 if (s->ti_size == 0) { 922 /* 923 * Transfer complete: force TC to zero just in case a TI command was 924 * requested for more data than the command returns (Solaris 8 does 925 * this) 926 */ 927 esp_set_tc(s, 0); 928 esp_dma_ti_check(s); 929 } else { 930 /* 931 * Transfer truncated: raise INTR_BS to indicate early change of 932 * phase 933 */ 934 s->rregs[ESP_RINTR] |= INTR_BS; 935 esp_raise_irq(s); 936 s->ti_size = 0; 937 } 938 939 if (s->current_req) { 940 scsi_req_unref(s->current_req); 941 s->current_req = NULL; 942 s->current_dev = NULL; 943 } 944 } 945 946 void esp_transfer_data(SCSIRequest *req, uint32_t len) 947 { 948 ESPState *s = req->hba_private; 949 int to_device = (esp_get_phase(s) == STAT_DO); 950 uint32_t dmalen = esp_get_tc(s); 951 952 assert(!s->do_cmd); 953 trace_esp_transfer_data(dmalen, s->ti_size); 954 s->async_len = len; 955 s->async_buf = scsi_req_get_buf(req); 956 957 if (!to_device && !s->data_in_ready) { 958 /* 959 * Initial incoming data xfer is complete so raise command 960 * completion interrupt 961 */ 962 s->data_in_ready = true; 963 s->rregs[ESP_RINTR] |= INTR_BS; 964 esp_raise_irq(s); 965 } 966 967 /* 968 * Always perform the initial transfer upon reception of the next TI 969 * command to ensure the DMA/non-DMA status of the command is correct. 970 * It is not possible to use s->dma directly in the section below as 971 * some OSs send non-DMA NOP commands after a DMA transfer. Hence if the 972 * async data transfer is delayed then s->dma is set incorrectly. 973 */ 974 975 if (s->ti_cmd == (CMD_TI | CMD_DMA)) { 976 /* When the SCSI layer returns more data, raise deferred INTR_BS */ 977 esp_dma_ti_check(s); 978 979 esp_do_dma(s); 980 } else if (s->ti_cmd == CMD_TI) { 981 esp_do_nodma(s); 982 } 983 } 984 985 static void handle_ti(ESPState *s) 986 { 987 uint32_t dmalen; 988 989 if (s->dma && !s->dma_enabled) { 990 s->dma_cb = handle_ti; 991 return; 992 } 993 994 s->ti_cmd = s->rregs[ESP_CMD]; 995 if (s->dma) { 996 dmalen = esp_get_tc(s); 997 trace_esp_handle_ti(dmalen); 998 esp_do_dma(s); 999 } else { 1000 trace_esp_handle_ti(s->ti_size); 1001 esp_do_nodma(s); 1002 } 1003 } 1004 1005 void esp_hard_reset(ESPState *s) 1006 { 1007 memset(s->rregs, 0, ESP_REGS); 1008 memset(s->wregs, 0, ESP_REGS); 1009 s->tchi_written = 0; 1010 s->ti_size = 0; 1011 s->async_len = 0; 1012 fifo8_reset(&s->fifo); 1013 fifo8_reset(&s->cmdfifo); 1014 s->dma = 0; 1015 s->do_cmd = 0; 1016 s->dma_cb = NULL; 1017 1018 s->rregs[ESP_CFG1] = 7; 1019 } 1020 1021 static void esp_soft_reset(ESPState *s) 1022 { 1023 qemu_irq_lower(s->irq); 1024 qemu_irq_lower(s->irq_data); 1025 esp_hard_reset(s); 1026 } 1027 1028 static void esp_bus_reset(ESPState *s) 1029 { 1030 bus_cold_reset(BUS(&s->bus)); 1031 } 1032 1033 static void parent_esp_reset(ESPState *s, int irq, int level) 1034 { 1035 if (level) { 1036 esp_soft_reset(s); 1037 } 1038 } 1039 1040 static void esp_run_cmd(ESPState *s) 1041 { 1042 uint8_t cmd = s->rregs[ESP_CMD]; 1043 1044 if (cmd & CMD_DMA) { 1045 s->dma = 1; 1046 /* Reload DMA counter. */ 1047 if (esp_get_stc(s) == 0) { 1048 esp_set_tc(s, 0x10000); 1049 } else { 1050 esp_set_tc(s, esp_get_stc(s)); 1051 } 1052 } else { 1053 s->dma = 0; 1054 } 1055 switch (cmd & CMD_CMD) { 1056 case CMD_NOP: 1057 trace_esp_mem_writeb_cmd_nop(cmd); 1058 break; 1059 case CMD_FLUSH: 1060 trace_esp_mem_writeb_cmd_flush(cmd); 1061 fifo8_reset(&s->fifo); 1062 break; 1063 case CMD_RESET: 1064 trace_esp_mem_writeb_cmd_reset(cmd); 1065 esp_soft_reset(s); 1066 break; 1067 case CMD_BUSRESET: 1068 trace_esp_mem_writeb_cmd_bus_reset(cmd); 1069 esp_bus_reset(s); 1070 if (!(s->wregs[ESP_CFG1] & CFG1_RESREPT)) { 1071 s->rregs[ESP_RINTR] |= INTR_RST; 1072 esp_raise_irq(s); 1073 } 1074 break; 1075 case CMD_TI: 1076 trace_esp_mem_writeb_cmd_ti(cmd); 1077 handle_ti(s); 1078 break; 1079 case CMD_ICCS: 1080 trace_esp_mem_writeb_cmd_iccs(cmd); 1081 write_response(s); 1082 s->rregs[ESP_RINTR] |= INTR_FC; 1083 esp_set_phase(s, STAT_MI); 1084 break; 1085 case CMD_MSGACC: 1086 trace_esp_mem_writeb_cmd_msgacc(cmd); 1087 s->rregs[ESP_RINTR] |= INTR_DC; 1088 s->rregs[ESP_RSEQ] = 0; 1089 s->rregs[ESP_RFLAGS] = 0; 1090 esp_raise_irq(s); 1091 break; 1092 case CMD_PAD: 1093 trace_esp_mem_writeb_cmd_pad(cmd); 1094 s->rregs[ESP_RSTAT] = STAT_TC; 1095 s->rregs[ESP_RINTR] |= INTR_FC; 1096 s->rregs[ESP_RSEQ] = 0; 1097 break; 1098 case CMD_SATN: 1099 trace_esp_mem_writeb_cmd_satn(cmd); 1100 break; 1101 case CMD_RSTATN: 1102 trace_esp_mem_writeb_cmd_rstatn(cmd); 1103 break; 1104 case CMD_SEL: 1105 trace_esp_mem_writeb_cmd_sel(cmd); 1106 handle_s_without_atn(s); 1107 break; 1108 case CMD_SELATN: 1109 trace_esp_mem_writeb_cmd_selatn(cmd); 1110 handle_satn(s); 1111 break; 1112 case CMD_SELATNS: 1113 trace_esp_mem_writeb_cmd_selatns(cmd); 1114 handle_satn_stop(s); 1115 break; 1116 case CMD_ENSEL: 1117 trace_esp_mem_writeb_cmd_ensel(cmd); 1118 s->rregs[ESP_RINTR] = 0; 1119 break; 1120 case CMD_DISSEL: 1121 trace_esp_mem_writeb_cmd_dissel(cmd); 1122 s->rregs[ESP_RINTR] = 0; 1123 esp_raise_irq(s); 1124 break; 1125 default: 1126 trace_esp_error_unhandled_command(cmd); 1127 break; 1128 } 1129 } 1130 1131 uint64_t esp_reg_read(ESPState *s, uint32_t saddr) 1132 { 1133 uint32_t val; 1134 1135 switch (saddr) { 1136 case ESP_FIFO: 1137 if (s->dma_memory_read && s->dma_memory_write && 1138 (s->rregs[ESP_RSTAT] & STAT_PIO_MASK) == 0) { 1139 /* Data out. */ 1140 qemu_log_mask(LOG_UNIMP, "esp: PIO data read not implemented\n"); 1141 s->rregs[ESP_FIFO] = 0; 1142 } else { 1143 if (esp_get_phase(s) == STAT_DI) { 1144 if (s->ti_size) { 1145 esp_do_nodma(s); 1146 } else { 1147 /* 1148 * The last byte of a non-DMA transfer has been read out 1149 * of the FIFO so switch to status phase 1150 */ 1151 esp_set_phase(s, STAT_ST); 1152 } 1153 } 1154 s->rregs[ESP_FIFO] = esp_fifo_pop(&s->fifo); 1155 } 1156 val = s->rregs[ESP_FIFO]; 1157 break; 1158 case ESP_RINTR: 1159 /* 1160 * Clear sequence step, interrupt register and all status bits 1161 * except TC 1162 */ 1163 val = s->rregs[ESP_RINTR]; 1164 s->rregs[ESP_RINTR] = 0; 1165 s->rregs[ESP_RSTAT] &= ~STAT_TC; 1166 /* 1167 * According to the datasheet ESP_RSEQ should be cleared, but as the 1168 * emulation currently defers information transfers to the next TI 1169 * command leave it for now so that pedantic guests such as the old 1170 * Linux 2.6 driver see the correct flags before the next SCSI phase 1171 * transition. 1172 * 1173 * s->rregs[ESP_RSEQ] = SEQ_0; 1174 */ 1175 esp_lower_irq(s); 1176 break; 1177 case ESP_TCHI: 1178 /* Return the unique id if the value has never been written */ 1179 if (!s->tchi_written) { 1180 val = s->chip_id; 1181 } else { 1182 val = s->rregs[saddr]; 1183 } 1184 break; 1185 case ESP_RFLAGS: 1186 /* Bottom 5 bits indicate number of bytes in FIFO */ 1187 val = fifo8_num_used(&s->fifo); 1188 break; 1189 default: 1190 val = s->rregs[saddr]; 1191 break; 1192 } 1193 1194 trace_esp_mem_readb(saddr, val); 1195 return val; 1196 } 1197 1198 void esp_reg_write(ESPState *s, uint32_t saddr, uint64_t val) 1199 { 1200 trace_esp_mem_writeb(saddr, s->wregs[saddr], val); 1201 switch (saddr) { 1202 case ESP_TCHI: 1203 s->tchi_written = true; 1204 /* fall through */ 1205 case ESP_TCLO: 1206 case ESP_TCMID: 1207 s->rregs[ESP_RSTAT] &= ~STAT_TC; 1208 break; 1209 case ESP_FIFO: 1210 if (esp_get_phase(s) == STAT_MO || esp_get_phase(s) == STAT_CD) { 1211 if (!fifo8_is_full(&s->fifo)) { 1212 esp_fifo_push(&s->fifo, val); 1213 esp_fifo_push(&s->cmdfifo, fifo8_pop(&s->fifo)); 1214 } 1215 1216 /* 1217 * If any unexpected message out/command phase data is 1218 * transferred using non-DMA, raise the interrupt 1219 */ 1220 if (s->rregs[ESP_CMD] == CMD_TI) { 1221 s->rregs[ESP_RINTR] |= INTR_BS; 1222 esp_raise_irq(s); 1223 } 1224 } else { 1225 esp_fifo_push(&s->fifo, val); 1226 } 1227 break; 1228 case ESP_CMD: 1229 s->rregs[saddr] = val; 1230 esp_run_cmd(s); 1231 break; 1232 case ESP_WBUSID ... ESP_WSYNO: 1233 break; 1234 case ESP_CFG1: 1235 case ESP_CFG2: case ESP_CFG3: 1236 case ESP_RES3: case ESP_RES4: 1237 s->rregs[saddr] = val; 1238 break; 1239 case ESP_WCCF ... ESP_WTEST: 1240 break; 1241 default: 1242 trace_esp_error_invalid_write(val, saddr); 1243 return; 1244 } 1245 s->wregs[saddr] = val; 1246 } 1247 1248 static bool esp_mem_accepts(void *opaque, hwaddr addr, 1249 unsigned size, bool is_write, 1250 MemTxAttrs attrs) 1251 { 1252 return (size == 1) || (is_write && size == 4); 1253 } 1254 1255 static bool esp_is_before_version_5(void *opaque, int version_id) 1256 { 1257 ESPState *s = ESP(opaque); 1258 1259 version_id = MIN(version_id, s->mig_version_id); 1260 return version_id < 5; 1261 } 1262 1263 static bool esp_is_version_5(void *opaque, int version_id) 1264 { 1265 ESPState *s = ESP(opaque); 1266 1267 version_id = MIN(version_id, s->mig_version_id); 1268 return version_id >= 5; 1269 } 1270 1271 static bool esp_is_version_6(void *opaque, int version_id) 1272 { 1273 ESPState *s = ESP(opaque); 1274 1275 version_id = MIN(version_id, s->mig_version_id); 1276 return version_id >= 6; 1277 } 1278 1279 int esp_pre_save(void *opaque) 1280 { 1281 ESPState *s = ESP(object_resolve_path_component( 1282 OBJECT(opaque), "esp")); 1283 1284 s->mig_version_id = vmstate_esp.version_id; 1285 return 0; 1286 } 1287 1288 static int esp_post_load(void *opaque, int version_id) 1289 { 1290 ESPState *s = ESP(opaque); 1291 int len, i; 1292 1293 version_id = MIN(version_id, s->mig_version_id); 1294 1295 if (version_id < 5) { 1296 esp_set_tc(s, s->mig_dma_left); 1297 1298 /* Migrate ti_buf to fifo */ 1299 len = s->mig_ti_wptr - s->mig_ti_rptr; 1300 for (i = 0; i < len; i++) { 1301 fifo8_push(&s->fifo, s->mig_ti_buf[i]); 1302 } 1303 1304 /* Migrate cmdbuf to cmdfifo */ 1305 for (i = 0; i < s->mig_cmdlen; i++) { 1306 fifo8_push(&s->cmdfifo, s->mig_cmdbuf[i]); 1307 } 1308 } 1309 1310 s->mig_version_id = vmstate_esp.version_id; 1311 return 0; 1312 } 1313 1314 /* 1315 * PDMA (or pseudo-DMA) is only used on the Macintosh and requires the 1316 * guest CPU to perform the transfers between the SCSI bus and memory 1317 * itself. This is indicated by the dma_memory_read and dma_memory_write 1318 * functions being NULL (in contrast to the ESP PCI device) whilst 1319 * dma_enabled is still set. 1320 */ 1321 1322 static bool esp_pdma_needed(void *opaque) 1323 { 1324 ESPState *s = ESP(opaque); 1325 1326 return s->dma_memory_read == NULL && s->dma_memory_write == NULL && 1327 s->dma_enabled; 1328 } 1329 1330 static const VMStateDescription vmstate_esp_pdma = { 1331 .name = "esp/pdma", 1332 .version_id = 0, 1333 .minimum_version_id = 0, 1334 .needed = esp_pdma_needed, 1335 .fields = (const VMStateField[]) { 1336 VMSTATE_UINT8(pdma_cb, ESPState), 1337 VMSTATE_END_OF_LIST() 1338 } 1339 }; 1340 1341 const VMStateDescription vmstate_esp = { 1342 .name = "esp", 1343 .version_id = 6, 1344 .minimum_version_id = 3, 1345 .post_load = esp_post_load, 1346 .fields = (const VMStateField[]) { 1347 VMSTATE_BUFFER(rregs, ESPState), 1348 VMSTATE_BUFFER(wregs, ESPState), 1349 VMSTATE_INT32(ti_size, ESPState), 1350 VMSTATE_UINT32_TEST(mig_ti_rptr, ESPState, esp_is_before_version_5), 1351 VMSTATE_UINT32_TEST(mig_ti_wptr, ESPState, esp_is_before_version_5), 1352 VMSTATE_BUFFER_TEST(mig_ti_buf, ESPState, esp_is_before_version_5), 1353 VMSTATE_UINT32(status, ESPState), 1354 VMSTATE_UINT32_TEST(mig_deferred_status, ESPState, 1355 esp_is_before_version_5), 1356 VMSTATE_BOOL_TEST(mig_deferred_complete, ESPState, 1357 esp_is_before_version_5), 1358 VMSTATE_UINT32(dma, ESPState), 1359 VMSTATE_STATIC_BUFFER(mig_cmdbuf, ESPState, 0, 1360 esp_is_before_version_5, 0, 16), 1361 VMSTATE_STATIC_BUFFER(mig_cmdbuf, ESPState, 4, 1362 esp_is_before_version_5, 16, 1363 sizeof(typeof_field(ESPState, mig_cmdbuf))), 1364 VMSTATE_UINT32_TEST(mig_cmdlen, ESPState, esp_is_before_version_5), 1365 VMSTATE_UINT32(do_cmd, ESPState), 1366 VMSTATE_UINT32_TEST(mig_dma_left, ESPState, esp_is_before_version_5), 1367 VMSTATE_BOOL_TEST(data_in_ready, ESPState, esp_is_version_5), 1368 VMSTATE_UINT8_TEST(cmdfifo_cdb_offset, ESPState, esp_is_version_5), 1369 VMSTATE_FIFO8_TEST(fifo, ESPState, esp_is_version_5), 1370 VMSTATE_FIFO8_TEST(cmdfifo, ESPState, esp_is_version_5), 1371 VMSTATE_UINT8_TEST(ti_cmd, ESPState, esp_is_version_5), 1372 VMSTATE_UINT8_TEST(lun, ESPState, esp_is_version_6), 1373 VMSTATE_END_OF_LIST() 1374 }, 1375 .subsections = (const VMStateDescription * const []) { 1376 &vmstate_esp_pdma, 1377 NULL 1378 } 1379 }; 1380 1381 static void sysbus_esp_mem_write(void *opaque, hwaddr addr, 1382 uint64_t val, unsigned int size) 1383 { 1384 SysBusESPState *sysbus = opaque; 1385 ESPState *s = ESP(&sysbus->esp); 1386 uint32_t saddr; 1387 1388 saddr = addr >> sysbus->it_shift; 1389 esp_reg_write(s, saddr, val); 1390 } 1391 1392 static uint64_t sysbus_esp_mem_read(void *opaque, hwaddr addr, 1393 unsigned int size) 1394 { 1395 SysBusESPState *sysbus = opaque; 1396 ESPState *s = ESP(&sysbus->esp); 1397 uint32_t saddr; 1398 1399 saddr = addr >> sysbus->it_shift; 1400 return esp_reg_read(s, saddr); 1401 } 1402 1403 static const MemoryRegionOps sysbus_esp_mem_ops = { 1404 .read = sysbus_esp_mem_read, 1405 .write = sysbus_esp_mem_write, 1406 .endianness = DEVICE_NATIVE_ENDIAN, 1407 .valid.accepts = esp_mem_accepts, 1408 }; 1409 1410 static void sysbus_esp_pdma_write(void *opaque, hwaddr addr, 1411 uint64_t val, unsigned int size) 1412 { 1413 SysBusESPState *sysbus = opaque; 1414 ESPState *s = ESP(&sysbus->esp); 1415 1416 trace_esp_pdma_write(size); 1417 1418 switch (size) { 1419 case 1: 1420 esp_pdma_write(s, val); 1421 break; 1422 case 2: 1423 esp_pdma_write(s, val >> 8); 1424 esp_pdma_write(s, val); 1425 break; 1426 } 1427 esp_pdma_cb(s); 1428 } 1429 1430 static uint64_t sysbus_esp_pdma_read(void *opaque, hwaddr addr, 1431 unsigned int size) 1432 { 1433 SysBusESPState *sysbus = opaque; 1434 ESPState *s = ESP(&sysbus->esp); 1435 uint64_t val = 0; 1436 1437 trace_esp_pdma_read(size); 1438 1439 switch (size) { 1440 case 1: 1441 val = esp_pdma_read(s); 1442 break; 1443 case 2: 1444 val = esp_pdma_read(s); 1445 val = (val << 8) | esp_pdma_read(s); 1446 break; 1447 } 1448 esp_pdma_cb(s); 1449 return val; 1450 } 1451 1452 static void *esp_load_request(QEMUFile *f, SCSIRequest *req) 1453 { 1454 ESPState *s = container_of(req->bus, ESPState, bus); 1455 1456 scsi_req_ref(req); 1457 s->current_req = req; 1458 return s; 1459 } 1460 1461 static const MemoryRegionOps sysbus_esp_pdma_ops = { 1462 .read = sysbus_esp_pdma_read, 1463 .write = sysbus_esp_pdma_write, 1464 .endianness = DEVICE_NATIVE_ENDIAN, 1465 .valid.min_access_size = 1, 1466 .valid.max_access_size = 4, 1467 .impl.min_access_size = 1, 1468 .impl.max_access_size = 2, 1469 }; 1470 1471 static const struct SCSIBusInfo esp_scsi_info = { 1472 .tcq = false, 1473 .max_target = ESP_MAX_DEVS, 1474 .max_lun = 7, 1475 1476 .load_request = esp_load_request, 1477 .transfer_data = esp_transfer_data, 1478 .complete = esp_command_complete, 1479 .cancel = esp_request_cancelled 1480 }; 1481 1482 static void sysbus_esp_gpio_demux(void *opaque, int irq, int level) 1483 { 1484 SysBusESPState *sysbus = SYSBUS_ESP(opaque); 1485 ESPState *s = ESP(&sysbus->esp); 1486 1487 switch (irq) { 1488 case 0: 1489 parent_esp_reset(s, irq, level); 1490 break; 1491 case 1: 1492 esp_dma_enable(s, irq, level); 1493 break; 1494 } 1495 } 1496 1497 static void sysbus_esp_realize(DeviceState *dev, Error **errp) 1498 { 1499 SysBusDevice *sbd = SYS_BUS_DEVICE(dev); 1500 SysBusESPState *sysbus = SYSBUS_ESP(dev); 1501 ESPState *s = ESP(&sysbus->esp); 1502 1503 if (!qdev_realize(DEVICE(s), NULL, errp)) { 1504 return; 1505 } 1506 1507 sysbus_init_irq(sbd, &s->irq); 1508 sysbus_init_irq(sbd, &s->irq_data); 1509 assert(sysbus->it_shift != -1); 1510 1511 s->chip_id = TCHI_FAS100A; 1512 memory_region_init_io(&sysbus->iomem, OBJECT(sysbus), &sysbus_esp_mem_ops, 1513 sysbus, "esp-regs", ESP_REGS << sysbus->it_shift); 1514 sysbus_init_mmio(sbd, &sysbus->iomem); 1515 memory_region_init_io(&sysbus->pdma, OBJECT(sysbus), &sysbus_esp_pdma_ops, 1516 sysbus, "esp-pdma", 4); 1517 sysbus_init_mmio(sbd, &sysbus->pdma); 1518 1519 qdev_init_gpio_in(dev, sysbus_esp_gpio_demux, 2); 1520 1521 scsi_bus_init(&s->bus, sizeof(s->bus), dev, &esp_scsi_info); 1522 } 1523 1524 static void sysbus_esp_hard_reset(DeviceState *dev) 1525 { 1526 SysBusESPState *sysbus = SYSBUS_ESP(dev); 1527 ESPState *s = ESP(&sysbus->esp); 1528 1529 esp_hard_reset(s); 1530 } 1531 1532 static void sysbus_esp_init(Object *obj) 1533 { 1534 SysBusESPState *sysbus = SYSBUS_ESP(obj); 1535 1536 object_initialize_child(obj, "esp", &sysbus->esp, TYPE_ESP); 1537 } 1538 1539 static const VMStateDescription vmstate_sysbus_esp_scsi = { 1540 .name = "sysbusespscsi", 1541 .version_id = 2, 1542 .minimum_version_id = 1, 1543 .pre_save = esp_pre_save, 1544 .fields = (const VMStateField[]) { 1545 VMSTATE_UINT8_V(esp.mig_version_id, SysBusESPState, 2), 1546 VMSTATE_STRUCT(esp, SysBusESPState, 0, vmstate_esp, ESPState), 1547 VMSTATE_END_OF_LIST() 1548 } 1549 }; 1550 1551 static void sysbus_esp_class_init(ObjectClass *klass, void *data) 1552 { 1553 DeviceClass *dc = DEVICE_CLASS(klass); 1554 1555 dc->realize = sysbus_esp_realize; 1556 dc->reset = sysbus_esp_hard_reset; 1557 dc->vmsd = &vmstate_sysbus_esp_scsi; 1558 set_bit(DEVICE_CATEGORY_STORAGE, dc->categories); 1559 } 1560 1561 static const TypeInfo sysbus_esp_info = { 1562 .name = TYPE_SYSBUS_ESP, 1563 .parent = TYPE_SYS_BUS_DEVICE, 1564 .instance_init = sysbus_esp_init, 1565 .instance_size = sizeof(SysBusESPState), 1566 .class_init = sysbus_esp_class_init, 1567 }; 1568 1569 static void esp_finalize(Object *obj) 1570 { 1571 ESPState *s = ESP(obj); 1572 1573 fifo8_destroy(&s->fifo); 1574 fifo8_destroy(&s->cmdfifo); 1575 } 1576 1577 static void esp_init(Object *obj) 1578 { 1579 ESPState *s = ESP(obj); 1580 1581 fifo8_create(&s->fifo, ESP_FIFO_SZ); 1582 fifo8_create(&s->cmdfifo, ESP_CMDFIFO_SZ); 1583 } 1584 1585 static void esp_class_init(ObjectClass *klass, void *data) 1586 { 1587 DeviceClass *dc = DEVICE_CLASS(klass); 1588 1589 /* internal device for sysbusesp/pciespscsi, not user-creatable */ 1590 dc->user_creatable = false; 1591 set_bit(DEVICE_CATEGORY_STORAGE, dc->categories); 1592 } 1593 1594 static const TypeInfo esp_info = { 1595 .name = TYPE_ESP, 1596 .parent = TYPE_DEVICE, 1597 .instance_init = esp_init, 1598 .instance_finalize = esp_finalize, 1599 .instance_size = sizeof(ESPState), 1600 .class_init = esp_class_init, 1601 }; 1602 1603 static void esp_register_types(void) 1604 { 1605 type_register_static(&sysbus_esp_info); 1606 type_register_static(&esp_info); 1607 } 1608 1609 type_init(esp_register_types) 1610