1 /* 2 * QEMU ESP/NCR53C9x emulation 3 * 4 * Copyright (c) 2005-2006 Fabrice Bellard 5 * Copyright (c) 2012 Herve Poussineau 6 * 7 * Permission is hereby granted, free of charge, to any person obtaining a copy 8 * of this software and associated documentation files (the "Software"), to deal 9 * in the Software without restriction, including without limitation the rights 10 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 11 * copies of the Software, and to permit persons to whom the Software is 12 * furnished to do so, subject to the following conditions: 13 * 14 * The above copyright notice and this permission notice shall be included in 15 * all copies or substantial portions of the Software. 16 * 17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 22 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 23 * THE SOFTWARE. 24 */ 25 26 #include "qemu/osdep.h" 27 #include "hw/sysbus.h" 28 #include "migration/vmstate.h" 29 #include "hw/irq.h" 30 #include "hw/scsi/esp.h" 31 #include "trace.h" 32 #include "qemu/log.h" 33 #include "qemu/module.h" 34 35 /* 36 * On Sparc32, this is the ESP (NCR53C90) part of chip STP2000 (Master I/O), 37 * also produced as NCR89C100. See 38 * http://www.ibiblio.org/pub/historic-linux/early-ports/Sparc/NCR/NCR89C100.txt 39 * and 40 * http://www.ibiblio.org/pub/historic-linux/early-ports/Sparc/NCR/NCR53C9X.txt 41 * 42 * On Macintosh Quadra it is a NCR53C96. 43 */ 44 45 static void esp_raise_irq(ESPState *s) 46 { 47 if (!(s->rregs[ESP_RSTAT] & STAT_INT)) { 48 s->rregs[ESP_RSTAT] |= STAT_INT; 49 qemu_irq_raise(s->irq); 50 trace_esp_raise_irq(); 51 } 52 } 53 54 static void esp_lower_irq(ESPState *s) 55 { 56 if (s->rregs[ESP_RSTAT] & STAT_INT) { 57 s->rregs[ESP_RSTAT] &= ~STAT_INT; 58 qemu_irq_lower(s->irq); 59 trace_esp_lower_irq(); 60 } 61 } 62 63 static void esp_raise_drq(ESPState *s) 64 { 65 qemu_irq_raise(s->irq_data); 66 trace_esp_raise_drq(); 67 } 68 69 static void esp_lower_drq(ESPState *s) 70 { 71 qemu_irq_lower(s->irq_data); 72 trace_esp_lower_drq(); 73 } 74 75 void esp_dma_enable(ESPState *s, int irq, int level) 76 { 77 if (level) { 78 s->dma_enabled = 1; 79 trace_esp_dma_enable(); 80 if (s->dma_cb) { 81 s->dma_cb(s); 82 s->dma_cb = NULL; 83 } 84 } else { 85 trace_esp_dma_disable(); 86 s->dma_enabled = 0; 87 } 88 } 89 90 void esp_request_cancelled(SCSIRequest *req) 91 { 92 ESPState *s = req->hba_private; 93 94 if (req == s->current_req) { 95 scsi_req_unref(s->current_req); 96 s->current_req = NULL; 97 s->current_dev = NULL; 98 s->async_len = 0; 99 } 100 } 101 102 static void esp_fifo_push(Fifo8 *fifo, uint8_t val) 103 { 104 if (fifo8_num_used(fifo) == fifo->capacity) { 105 trace_esp_error_fifo_overrun(); 106 return; 107 } 108 109 fifo8_push(fifo, val); 110 } 111 112 static uint8_t esp_fifo_pop(Fifo8 *fifo) 113 { 114 if (fifo8_is_empty(fifo)) { 115 return 0; 116 } 117 118 return fifo8_pop(fifo); 119 } 120 121 static uint32_t esp_fifo_pop_buf(Fifo8 *fifo, uint8_t *dest, int maxlen) 122 { 123 const uint8_t *buf; 124 uint32_t n, n2; 125 int len; 126 127 if (maxlen == 0) { 128 return 0; 129 } 130 131 len = maxlen; 132 buf = fifo8_pop_buf(fifo, len, &n); 133 if (dest) { 134 memcpy(dest, buf, n); 135 } 136 137 /* Add FIFO wraparound if needed */ 138 len -= n; 139 len = MIN(len, fifo8_num_used(fifo)); 140 if (len) { 141 buf = fifo8_pop_buf(fifo, len, &n2); 142 if (dest) { 143 memcpy(&dest[n], buf, n2); 144 } 145 n += n2; 146 } 147 148 return n; 149 } 150 151 static uint32_t esp_get_tc(ESPState *s) 152 { 153 uint32_t dmalen; 154 155 dmalen = s->rregs[ESP_TCLO]; 156 dmalen |= s->rregs[ESP_TCMID] << 8; 157 dmalen |= s->rregs[ESP_TCHI] << 16; 158 159 return dmalen; 160 } 161 162 static void esp_set_tc(ESPState *s, uint32_t dmalen) 163 { 164 uint32_t old_tc = esp_get_tc(s); 165 166 s->rregs[ESP_TCLO] = dmalen; 167 s->rregs[ESP_TCMID] = dmalen >> 8; 168 s->rregs[ESP_TCHI] = dmalen >> 16; 169 170 if (old_tc && dmalen == 0) { 171 s->rregs[ESP_RSTAT] |= STAT_TC; 172 } 173 } 174 175 static uint32_t esp_get_stc(ESPState *s) 176 { 177 uint32_t dmalen; 178 179 dmalen = s->wregs[ESP_TCLO]; 180 dmalen |= s->wregs[ESP_TCMID] << 8; 181 dmalen |= s->wregs[ESP_TCHI] << 16; 182 183 return dmalen; 184 } 185 186 static const char *esp_phase_names[8] = { 187 "DATA OUT", "DATA IN", "COMMAND", "STATUS", 188 "(reserved)", "(reserved)", "MESSAGE OUT", "MESSAGE IN" 189 }; 190 191 static void esp_set_phase(ESPState *s, uint8_t phase) 192 { 193 s->rregs[ESP_RSTAT] &= ~7; 194 s->rregs[ESP_RSTAT] |= phase; 195 196 trace_esp_set_phase(esp_phase_names[phase]); 197 } 198 199 static uint8_t esp_pdma_read(ESPState *s) 200 { 201 uint8_t val; 202 203 val = esp_fifo_pop(&s->fifo); 204 return val; 205 } 206 207 static void esp_pdma_write(ESPState *s, uint8_t val) 208 { 209 uint32_t dmalen = esp_get_tc(s); 210 211 if (dmalen == 0) { 212 return; 213 } 214 215 esp_fifo_push(&s->fifo, val); 216 217 dmalen--; 218 esp_set_tc(s, dmalen); 219 } 220 221 static void esp_set_pdma_cb(ESPState *s, enum pdma_cb cb) 222 { 223 s->pdma_cb = cb; 224 } 225 226 static int esp_select(ESPState *s) 227 { 228 int target; 229 230 target = s->wregs[ESP_WBUSID] & BUSID_DID; 231 232 s->ti_size = 0; 233 234 if (s->current_req) { 235 /* Started a new command before the old one finished. Cancel it. */ 236 scsi_req_cancel(s->current_req); 237 } 238 239 s->current_dev = scsi_device_find(&s->bus, 0, target, 0); 240 if (!s->current_dev) { 241 /* No such drive */ 242 s->rregs[ESP_RSTAT] = 0; 243 s->rregs[ESP_RINTR] = INTR_DC; 244 s->rregs[ESP_RSEQ] = SEQ_0; 245 esp_raise_irq(s); 246 return -1; 247 } 248 249 /* 250 * Note that we deliberately don't raise the IRQ here: this will be done 251 * either in do_command_phase() for DATA OUT transfers or by the deferred 252 * IRQ mechanism in esp_transfer_data() for DATA IN transfers 253 */ 254 s->rregs[ESP_RINTR] |= INTR_FC; 255 s->rregs[ESP_RSEQ] = SEQ_CD; 256 return 0; 257 } 258 259 static uint32_t get_cmd(ESPState *s, uint32_t maxlen) 260 { 261 uint8_t buf[ESP_CMDFIFO_SZ]; 262 uint32_t dmalen, n; 263 int target; 264 265 target = s->wregs[ESP_WBUSID] & BUSID_DID; 266 if (s->dma) { 267 dmalen = MIN(esp_get_tc(s), maxlen); 268 if (dmalen == 0) { 269 return 0; 270 } 271 if (s->dma_memory_read) { 272 s->dma_memory_read(s->dma_opaque, buf, dmalen); 273 dmalen = MIN(fifo8_num_free(&s->cmdfifo), dmalen); 274 fifo8_push_all(&s->cmdfifo, buf, dmalen); 275 esp_set_tc(s, esp_get_tc(s) - dmalen); 276 } else { 277 return 0; 278 } 279 } else { 280 dmalen = MIN(fifo8_num_used(&s->fifo), maxlen); 281 if (dmalen == 0) { 282 return 0; 283 } 284 n = esp_fifo_pop_buf(&s->fifo, buf, dmalen); 285 n = MIN(fifo8_num_free(&s->cmdfifo), n); 286 fifo8_push_all(&s->cmdfifo, buf, n); 287 } 288 trace_esp_get_cmd(dmalen, target); 289 290 return dmalen; 291 } 292 293 static void do_command_phase(ESPState *s) 294 { 295 uint32_t cmdlen; 296 int32_t datalen; 297 SCSIDevice *current_lun; 298 uint8_t buf[ESP_CMDFIFO_SZ]; 299 300 trace_esp_do_command_phase(s->lun); 301 cmdlen = fifo8_num_used(&s->cmdfifo); 302 if (!cmdlen || !s->current_dev) { 303 return; 304 } 305 esp_fifo_pop_buf(&s->cmdfifo, buf, cmdlen); 306 307 current_lun = scsi_device_find(&s->bus, 0, s->current_dev->id, s->lun); 308 if (!current_lun) { 309 /* No such drive */ 310 s->rregs[ESP_RSTAT] = 0; 311 s->rregs[ESP_RINTR] = INTR_DC; 312 s->rregs[ESP_RSEQ] = SEQ_0; 313 esp_raise_irq(s); 314 return; 315 } 316 317 s->current_req = scsi_req_new(current_lun, 0, s->lun, buf, cmdlen, s); 318 datalen = scsi_req_enqueue(s->current_req); 319 s->ti_size = datalen; 320 fifo8_reset(&s->cmdfifo); 321 if (datalen != 0) { 322 s->ti_cmd = 0; 323 if (datalen > 0) { 324 /* 325 * Switch to DATA IN phase but wait until initial data xfer is 326 * complete before raising the command completion interrupt 327 */ 328 s->data_in_ready = false; 329 esp_set_phase(s, STAT_DI); 330 } else { 331 esp_set_phase(s, STAT_DO); 332 s->rregs[ESP_RINTR] |= INTR_BS | INTR_FC; 333 esp_raise_irq(s); 334 esp_lower_drq(s); 335 } 336 scsi_req_continue(s->current_req); 337 return; 338 } 339 } 340 341 static void do_message_phase(ESPState *s) 342 { 343 if (s->cmdfifo_cdb_offset) { 344 uint8_t message = esp_fifo_pop(&s->cmdfifo); 345 346 trace_esp_do_identify(message); 347 s->lun = message & 7; 348 s->cmdfifo_cdb_offset--; 349 } 350 351 /* Ignore extended messages for now */ 352 if (s->cmdfifo_cdb_offset) { 353 int len = MIN(s->cmdfifo_cdb_offset, fifo8_num_used(&s->cmdfifo)); 354 esp_fifo_pop_buf(&s->cmdfifo, NULL, len); 355 s->cmdfifo_cdb_offset = 0; 356 } 357 } 358 359 static void do_cmd(ESPState *s) 360 { 361 do_message_phase(s); 362 assert(s->cmdfifo_cdb_offset == 0); 363 do_command_phase(s); 364 } 365 366 static void satn_pdma_cb(ESPState *s) 367 { 368 uint8_t buf[ESP_FIFO_SZ]; 369 int n; 370 371 /* Copy FIFO into cmdfifo */ 372 n = esp_fifo_pop_buf(&s->fifo, buf, fifo8_num_used(&s->fifo)); 373 n = MIN(fifo8_num_free(&s->cmdfifo), n); 374 fifo8_push_all(&s->cmdfifo, buf, n); 375 376 if (!esp_get_tc(s) && !fifo8_is_empty(&s->cmdfifo)) { 377 s->cmdfifo_cdb_offset = 1; 378 s->do_cmd = 0; 379 do_cmd(s); 380 } 381 } 382 383 static void handle_satn(ESPState *s) 384 { 385 int32_t cmdlen; 386 387 if (s->dma && !s->dma_enabled) { 388 s->dma_cb = handle_satn; 389 return; 390 } 391 esp_set_pdma_cb(s, SATN_PDMA_CB); 392 if (esp_select(s) < 0) { 393 return; 394 } 395 cmdlen = get_cmd(s, ESP_CMDFIFO_SZ); 396 if (cmdlen > 0) { 397 s->cmdfifo_cdb_offset = 1; 398 s->do_cmd = 0; 399 do_cmd(s); 400 } else if (cmdlen == 0) { 401 if (s->dma) { 402 esp_raise_drq(s); 403 } 404 s->do_cmd = 1; 405 /* Target present, but no cmd yet - switch to command phase */ 406 s->rregs[ESP_RSEQ] = SEQ_CD; 407 esp_set_phase(s, STAT_CD); 408 } 409 } 410 411 static void s_without_satn_pdma_cb(ESPState *s) 412 { 413 uint8_t buf[ESP_FIFO_SZ]; 414 int n; 415 416 /* Copy FIFO into cmdfifo */ 417 n = esp_fifo_pop_buf(&s->fifo, buf, fifo8_num_used(&s->fifo)); 418 n = MIN(fifo8_num_free(&s->cmdfifo), n); 419 fifo8_push_all(&s->cmdfifo, buf, n); 420 421 if (!esp_get_tc(s) && !fifo8_is_empty(&s->cmdfifo)) { 422 s->cmdfifo_cdb_offset = 0; 423 s->do_cmd = 0; 424 do_cmd(s); 425 } 426 } 427 428 static void handle_s_without_atn(ESPState *s) 429 { 430 int32_t cmdlen; 431 432 if (s->dma && !s->dma_enabled) { 433 s->dma_cb = handle_s_without_atn; 434 return; 435 } 436 esp_set_pdma_cb(s, S_WITHOUT_SATN_PDMA_CB); 437 if (esp_select(s) < 0) { 438 return; 439 } 440 cmdlen = get_cmd(s, ESP_CMDFIFO_SZ); 441 if (cmdlen > 0) { 442 s->cmdfifo_cdb_offset = 0; 443 s->do_cmd = 0; 444 do_cmd(s); 445 } else if (cmdlen == 0) { 446 if (s->dma) { 447 esp_raise_drq(s); 448 } 449 s->do_cmd = 1; 450 /* Target present, but no cmd yet - switch to command phase */ 451 s->rregs[ESP_RSEQ] = SEQ_CD; 452 esp_set_phase(s, STAT_CD); 453 } 454 } 455 456 static void satn_stop_pdma_cb(ESPState *s) 457 { 458 uint8_t buf[ESP_FIFO_SZ]; 459 int n; 460 461 /* Copy FIFO into cmdfifo */ 462 n = esp_fifo_pop_buf(&s->fifo, buf, fifo8_num_used(&s->fifo)); 463 n = MIN(fifo8_num_free(&s->cmdfifo), n); 464 fifo8_push_all(&s->cmdfifo, buf, n); 465 466 if (!esp_get_tc(s) && !fifo8_is_empty(&s->cmdfifo)) { 467 trace_esp_handle_satn_stop(fifo8_num_used(&s->cmdfifo)); 468 s->do_cmd = 1; 469 s->cmdfifo_cdb_offset = 1; 470 esp_set_phase(s, STAT_CD); 471 s->rregs[ESP_RSTAT] |= STAT_TC; 472 s->rregs[ESP_RINTR] |= INTR_BS | INTR_FC; 473 s->rregs[ESP_RSEQ] = SEQ_CD; 474 esp_raise_irq(s); 475 } 476 } 477 478 static void handle_satn_stop(ESPState *s) 479 { 480 int32_t cmdlen; 481 482 if (s->dma && !s->dma_enabled) { 483 s->dma_cb = handle_satn_stop; 484 return; 485 } 486 esp_set_pdma_cb(s, SATN_STOP_PDMA_CB); 487 if (esp_select(s) < 0) { 488 return; 489 } 490 cmdlen = get_cmd(s, 1); 491 if (cmdlen > 0) { 492 trace_esp_handle_satn_stop(fifo8_num_used(&s->cmdfifo)); 493 s->do_cmd = 1; 494 s->cmdfifo_cdb_offset = 1; 495 esp_set_phase(s, STAT_MO); 496 s->rregs[ESP_RINTR] |= INTR_BS | INTR_FC; 497 s->rregs[ESP_RSEQ] = SEQ_MO; 498 esp_raise_irq(s); 499 } else if (cmdlen == 0) { 500 if (s->dma) { 501 esp_raise_drq(s); 502 } 503 s->do_cmd = 1; 504 /* Target present, switch to message out phase */ 505 s->rregs[ESP_RSEQ] = SEQ_MO; 506 esp_set_phase(s, STAT_MO); 507 } 508 } 509 510 static void write_response_pdma_cb(ESPState *s) 511 { 512 esp_set_phase(s, STAT_ST); 513 s->rregs[ESP_RINTR] |= INTR_BS | INTR_FC; 514 s->rregs[ESP_RSEQ] = SEQ_CD; 515 esp_raise_irq(s); 516 } 517 518 static void write_response(ESPState *s) 519 { 520 uint8_t buf[2]; 521 522 trace_esp_write_response(s->status); 523 524 buf[0] = s->status; 525 buf[1] = 0; 526 527 if (s->dma) { 528 if (s->dma_memory_write) { 529 s->dma_memory_write(s->dma_opaque, buf, 2); 530 esp_set_phase(s, STAT_ST); 531 s->rregs[ESP_RINTR] |= INTR_BS | INTR_FC; 532 s->rregs[ESP_RSEQ] = SEQ_CD; 533 } else { 534 esp_set_pdma_cb(s, WRITE_RESPONSE_PDMA_CB); 535 esp_raise_drq(s); 536 return; 537 } 538 } else { 539 fifo8_reset(&s->fifo); 540 fifo8_push_all(&s->fifo, buf, 2); 541 s->rregs[ESP_RFLAGS] = 2; 542 } 543 esp_raise_irq(s); 544 } 545 546 static void esp_dma_done(ESPState *s) 547 { 548 s->rregs[ESP_RINTR] |= INTR_BS; 549 esp_raise_irq(s); 550 } 551 552 static void do_dma_pdma_cb(ESPState *s) 553 { 554 int to_device = ((s->rregs[ESP_RSTAT] & 7) == STAT_DO); 555 uint8_t buf[ESP_CMDFIFO_SZ]; 556 int len; 557 uint32_t n; 558 559 if (s->do_cmd) { 560 /* Copy FIFO into cmdfifo */ 561 n = esp_fifo_pop_buf(&s->fifo, buf, fifo8_num_used(&s->fifo)); 562 n = MIN(fifo8_num_free(&s->cmdfifo), n); 563 fifo8_push_all(&s->cmdfifo, buf, n); 564 565 /* Ensure we have received complete command after SATN and stop */ 566 if (esp_get_tc(s) || fifo8_is_empty(&s->cmdfifo)) { 567 return; 568 } 569 570 s->ti_size = 0; 571 if ((s->rregs[ESP_RSTAT] & 7) == STAT_CD) { 572 /* No command received */ 573 if (s->cmdfifo_cdb_offset == fifo8_num_used(&s->cmdfifo)) { 574 return; 575 } 576 577 /* Command has been received */ 578 s->do_cmd = 0; 579 do_cmd(s); 580 } else { 581 /* 582 * Extra message out bytes received: update cmdfifo_cdb_offset 583 * and then switch to command phase 584 */ 585 s->cmdfifo_cdb_offset = fifo8_num_used(&s->cmdfifo); 586 esp_set_phase(s, STAT_CD); 587 s->rregs[ESP_RSEQ] = SEQ_CD; 588 s->rregs[ESP_RINTR] |= INTR_BS; 589 esp_raise_irq(s); 590 } 591 return; 592 } 593 594 if (!s->current_req) { 595 return; 596 } 597 598 if (to_device) { 599 /* Copy FIFO data to device */ 600 len = MIN(s->async_len, ESP_FIFO_SZ); 601 len = MIN(len, fifo8_num_used(&s->fifo)); 602 n = esp_fifo_pop_buf(&s->fifo, s->async_buf, len); 603 s->async_buf += n; 604 s->async_len -= n; 605 s->ti_size += n; 606 607 if (s->async_len == 0 && fifo8_num_used(&s->fifo) < 2) { 608 /* Defer until the scsi layer has completed */ 609 scsi_req_continue(s->current_req); 610 return; 611 } 612 613 if (esp_get_tc(s) == 0 && fifo8_num_used(&s->fifo) < 2) { 614 esp_lower_drq(s); 615 esp_dma_done(s); 616 } 617 618 return; 619 } else { 620 if (s->async_len == 0 && fifo8_num_used(&s->fifo) < 2) { 621 /* Defer until the scsi layer has completed */ 622 scsi_req_continue(s->current_req); 623 s->data_in_ready = false; 624 return; 625 } 626 627 if (esp_get_tc(s) == 0 && fifo8_num_used(&s->fifo) < 2) { 628 esp_lower_drq(s); 629 esp_dma_done(s); 630 } 631 632 /* Copy device data to FIFO */ 633 len = MIN(s->async_len, esp_get_tc(s)); 634 len = MIN(len, fifo8_num_free(&s->fifo)); 635 fifo8_push_all(&s->fifo, s->async_buf, len); 636 s->async_buf += len; 637 s->async_len -= len; 638 s->ti_size -= len; 639 esp_set_tc(s, esp_get_tc(s) - len); 640 } 641 } 642 643 static void esp_do_dma(ESPState *s) 644 { 645 uint32_t len, cmdlen; 646 int to_device = ((s->rregs[ESP_RSTAT] & 7) == STAT_DO); 647 uint8_t buf[ESP_CMDFIFO_SZ]; 648 649 len = esp_get_tc(s); 650 if (s->do_cmd) { 651 /* 652 * handle_ti_cmd() case: esp_do_dma() is called only from 653 * handle_ti_cmd() with do_cmd != NULL (see the assert()) 654 */ 655 cmdlen = fifo8_num_used(&s->cmdfifo); 656 trace_esp_do_dma(cmdlen, len); 657 if (s->dma_memory_read) { 658 len = MIN(len, fifo8_num_free(&s->cmdfifo)); 659 s->dma_memory_read(s->dma_opaque, buf, len); 660 fifo8_push_all(&s->cmdfifo, buf, len); 661 esp_set_tc(s, esp_get_tc(s) - len); 662 } else { 663 esp_set_pdma_cb(s, DO_DMA_PDMA_CB); 664 esp_raise_drq(s); 665 return; 666 } 667 trace_esp_handle_ti_cmd(cmdlen); 668 s->ti_size = 0; 669 if ((s->rregs[ESP_RSTAT] & 7) == STAT_CD) { 670 /* No command received */ 671 if (s->cmdfifo_cdb_offset == fifo8_num_used(&s->cmdfifo)) { 672 return; 673 } 674 675 /* Command has been received */ 676 s->do_cmd = 0; 677 do_cmd(s); 678 } else { 679 /* 680 * Extra message out bytes received: update cmdfifo_cdb_offset 681 * and then switch to command phase 682 */ 683 s->cmdfifo_cdb_offset = fifo8_num_used(&s->cmdfifo); 684 esp_set_phase(s, STAT_CD); 685 s->rregs[ESP_RSEQ] = SEQ_CD; 686 s->rregs[ESP_RINTR] |= INTR_BS; 687 esp_raise_irq(s); 688 } 689 return; 690 } 691 if (!s->current_req) { 692 return; 693 } 694 if (s->async_len == 0) { 695 /* Defer until data is available. */ 696 return; 697 } 698 if (len > s->async_len) { 699 len = s->async_len; 700 } 701 if (to_device) { 702 if (s->dma_memory_read) { 703 s->dma_memory_read(s->dma_opaque, s->async_buf, len); 704 705 esp_set_tc(s, esp_get_tc(s) - len); 706 s->async_buf += len; 707 s->async_len -= len; 708 s->ti_size += len; 709 710 if (s->async_len == 0 && fifo8_num_used(&s->fifo) < 2) { 711 /* Defer until the scsi layer has completed */ 712 scsi_req_continue(s->current_req); 713 return; 714 } 715 716 if (esp_get_tc(s) == 0 && fifo8_num_used(&s->fifo) < 2) { 717 esp_dma_done(s); 718 esp_lower_drq(s); 719 } 720 } else { 721 esp_set_pdma_cb(s, DO_DMA_PDMA_CB); 722 esp_raise_drq(s); 723 724 if (s->async_len == 0 && fifo8_num_used(&s->fifo) < 2) { 725 /* Defer until the scsi layer has completed */ 726 scsi_req_continue(s->current_req); 727 return; 728 } 729 730 if (esp_get_tc(s) == 0 && fifo8_num_used(&s->fifo) < 2) { 731 esp_dma_done(s); 732 esp_lower_drq(s); 733 } 734 } 735 } else { 736 if (s->dma_memory_write) { 737 s->dma_memory_write(s->dma_opaque, s->async_buf, len); 738 739 esp_set_tc(s, esp_get_tc(s) - len); 740 s->async_buf += len; 741 s->async_len -= len; 742 s->ti_size -= len; 743 744 if (s->async_len == 0 && fifo8_num_used(&s->fifo) < 2) { 745 /* Defer until the scsi layer has completed */ 746 scsi_req_continue(s->current_req); 747 return; 748 } 749 750 if (esp_get_tc(s) == 0 && fifo8_num_used(&s->fifo) < 2) { 751 esp_dma_done(s); 752 esp_lower_drq(s); 753 } 754 } else { 755 /* Copy device data to FIFO */ 756 len = MIN(len, fifo8_num_free(&s->fifo)); 757 fifo8_push_all(&s->fifo, s->async_buf, len); 758 s->async_buf += len; 759 s->async_len -= len; 760 s->ti_size -= len; 761 esp_set_tc(s, esp_get_tc(s) - len); 762 esp_set_pdma_cb(s, DO_DMA_PDMA_CB); 763 esp_raise_drq(s); 764 765 if (s->async_len == 0 && fifo8_num_used(&s->fifo) < 2) { 766 /* Defer until the scsi layer has completed */ 767 scsi_req_continue(s->current_req); 768 return; 769 } 770 771 if (esp_get_tc(s) == 0 && fifo8_num_used(&s->fifo) < 2) { 772 esp_lower_drq(s); 773 esp_dma_done(s); 774 } 775 } 776 } 777 } 778 779 static void esp_do_nodma(ESPState *s) 780 { 781 int to_device = ((s->rregs[ESP_RSTAT] & 7) == STAT_DO); 782 uint8_t buf[ESP_FIFO_SZ]; 783 uint32_t cmdlen; 784 int len, n; 785 786 if (s->do_cmd) { 787 /* Copy FIFO into cmdfifo */ 788 n = esp_fifo_pop_buf(&s->fifo, buf, fifo8_num_used(&s->fifo)); 789 n = MIN(fifo8_num_free(&s->cmdfifo), n); 790 fifo8_push_all(&s->cmdfifo, buf, n); 791 792 cmdlen = fifo8_num_used(&s->cmdfifo); 793 trace_esp_handle_ti_cmd(cmdlen); 794 s->ti_size = 0; 795 if ((s->rregs[ESP_RSTAT] & 7) == STAT_CD) { 796 /* No command received */ 797 if (s->cmdfifo_cdb_offset == fifo8_num_used(&s->cmdfifo)) { 798 return; 799 } 800 801 /* Command has been received */ 802 s->do_cmd = 0; 803 do_cmd(s); 804 } else { 805 /* 806 * Extra message out bytes received: update cmdfifo_cdb_offset 807 * and then switch to command phase 808 */ 809 s->cmdfifo_cdb_offset = fifo8_num_used(&s->cmdfifo); 810 esp_set_phase(s, STAT_CD); 811 s->rregs[ESP_RSEQ] = SEQ_CD; 812 s->rregs[ESP_RINTR] |= INTR_BS; 813 esp_raise_irq(s); 814 } 815 return; 816 } 817 818 if (!s->current_req) { 819 return; 820 } 821 822 if (s->async_len == 0) { 823 /* Defer until data is available. */ 824 return; 825 } 826 827 if (to_device) { 828 len = MIN(s->async_len, ESP_FIFO_SZ); 829 len = MIN(len, fifo8_num_used(&s->fifo)); 830 esp_fifo_pop_buf(&s->fifo, s->async_buf, len); 831 s->async_buf += len; 832 s->async_len -= len; 833 s->ti_size += len; 834 } else { 835 if (fifo8_is_empty(&s->fifo)) { 836 fifo8_push(&s->fifo, s->async_buf[0]); 837 s->async_buf++; 838 s->async_len--; 839 s->ti_size--; 840 } 841 } 842 843 if (s->async_len == 0) { 844 scsi_req_continue(s->current_req); 845 return; 846 } 847 848 s->rregs[ESP_RINTR] |= INTR_BS; 849 esp_raise_irq(s); 850 } 851 852 static void esp_pdma_cb(ESPState *s) 853 { 854 switch (s->pdma_cb) { 855 case SATN_PDMA_CB: 856 satn_pdma_cb(s); 857 break; 858 case S_WITHOUT_SATN_PDMA_CB: 859 s_without_satn_pdma_cb(s); 860 break; 861 case SATN_STOP_PDMA_CB: 862 satn_stop_pdma_cb(s); 863 break; 864 case WRITE_RESPONSE_PDMA_CB: 865 write_response_pdma_cb(s); 866 break; 867 case DO_DMA_PDMA_CB: 868 do_dma_pdma_cb(s); 869 break; 870 default: 871 g_assert_not_reached(); 872 } 873 } 874 875 void esp_command_complete(SCSIRequest *req, size_t resid) 876 { 877 ESPState *s = req->hba_private; 878 int to_device = ((s->rregs[ESP_RSTAT] & 7) == STAT_DO); 879 880 trace_esp_command_complete(); 881 882 /* 883 * Non-DMA transfers from the target will leave the last byte in 884 * the FIFO so don't reset ti_size in this case 885 */ 886 if (s->dma || to_device) { 887 if (s->ti_size != 0) { 888 trace_esp_command_complete_unexpected(); 889 } 890 } 891 892 s->async_len = 0; 893 if (req->status) { 894 trace_esp_command_complete_fail(); 895 } 896 s->status = req->status; 897 898 /* 899 * Switch to status phase. For non-DMA transfers from the target the last 900 * byte is still in the FIFO 901 */ 902 esp_set_phase(s, STAT_ST); 903 if (s->ti_size == 0) { 904 /* 905 * Transfer complete: force TC to zero just in case a TI command was 906 * requested for more data than the command returns (Solaris 8 does 907 * this) 908 */ 909 esp_set_tc(s, 0); 910 esp_dma_done(s); 911 } else { 912 /* 913 * Transfer truncated: raise INTR_BS to indicate early change of 914 * phase 915 */ 916 s->rregs[ESP_RINTR] |= INTR_BS; 917 esp_raise_irq(s); 918 s->ti_size = 0; 919 } 920 921 if (s->current_req) { 922 scsi_req_unref(s->current_req); 923 s->current_req = NULL; 924 s->current_dev = NULL; 925 } 926 } 927 928 void esp_transfer_data(SCSIRequest *req, uint32_t len) 929 { 930 ESPState *s = req->hba_private; 931 int to_device = ((s->rregs[ESP_RSTAT] & 7) == STAT_DO); 932 uint32_t dmalen = esp_get_tc(s); 933 934 assert(!s->do_cmd); 935 trace_esp_transfer_data(dmalen, s->ti_size); 936 s->async_len = len; 937 s->async_buf = scsi_req_get_buf(req); 938 939 if (!to_device && !s->data_in_ready) { 940 /* 941 * Initial incoming data xfer is complete so raise command 942 * completion interrupt 943 */ 944 s->data_in_ready = true; 945 s->rregs[ESP_RINTR] |= INTR_BS; 946 esp_raise_irq(s); 947 } 948 949 /* 950 * Always perform the initial transfer upon reception of the next TI 951 * command to ensure the DMA/non-DMA status of the command is correct. 952 * It is not possible to use s->dma directly in the section below as 953 * some OSs send non-DMA NOP commands after a DMA transfer. Hence if the 954 * async data transfer is delayed then s->dma is set incorrectly. 955 */ 956 957 if (s->ti_cmd == (CMD_TI | CMD_DMA)) { 958 /* When the SCSI layer returns more data, raise deferred INTR_BS */ 959 esp_dma_done(s); 960 961 esp_do_dma(s); 962 } else if (s->ti_cmd == CMD_TI) { 963 esp_do_nodma(s); 964 } 965 } 966 967 static void handle_ti(ESPState *s) 968 { 969 uint32_t dmalen; 970 971 if (s->dma && !s->dma_enabled) { 972 s->dma_cb = handle_ti; 973 return; 974 } 975 976 s->ti_cmd = s->rregs[ESP_CMD]; 977 if (s->dma) { 978 dmalen = esp_get_tc(s); 979 trace_esp_handle_ti(dmalen); 980 esp_do_dma(s); 981 } else { 982 trace_esp_handle_ti(s->ti_size); 983 esp_do_nodma(s); 984 } 985 } 986 987 void esp_hard_reset(ESPState *s) 988 { 989 memset(s->rregs, 0, ESP_REGS); 990 memset(s->wregs, 0, ESP_REGS); 991 s->tchi_written = 0; 992 s->ti_size = 0; 993 s->async_len = 0; 994 fifo8_reset(&s->fifo); 995 fifo8_reset(&s->cmdfifo); 996 s->dma = 0; 997 s->do_cmd = 0; 998 s->dma_cb = NULL; 999 1000 s->rregs[ESP_CFG1] = 7; 1001 } 1002 1003 static void esp_soft_reset(ESPState *s) 1004 { 1005 qemu_irq_lower(s->irq); 1006 qemu_irq_lower(s->irq_data); 1007 esp_hard_reset(s); 1008 } 1009 1010 static void esp_bus_reset(ESPState *s) 1011 { 1012 bus_cold_reset(BUS(&s->bus)); 1013 } 1014 1015 static void parent_esp_reset(ESPState *s, int irq, int level) 1016 { 1017 if (level) { 1018 esp_soft_reset(s); 1019 } 1020 } 1021 1022 static void esp_run_cmd(ESPState *s) 1023 { 1024 uint8_t cmd = s->rregs[ESP_CMD]; 1025 1026 if (cmd & CMD_DMA) { 1027 s->dma = 1; 1028 /* Reload DMA counter. */ 1029 if (esp_get_stc(s) == 0) { 1030 esp_set_tc(s, 0x10000); 1031 } else { 1032 esp_set_tc(s, esp_get_stc(s)); 1033 } 1034 } else { 1035 s->dma = 0; 1036 } 1037 switch (cmd & CMD_CMD) { 1038 case CMD_NOP: 1039 trace_esp_mem_writeb_cmd_nop(cmd); 1040 break; 1041 case CMD_FLUSH: 1042 trace_esp_mem_writeb_cmd_flush(cmd); 1043 fifo8_reset(&s->fifo); 1044 break; 1045 case CMD_RESET: 1046 trace_esp_mem_writeb_cmd_reset(cmd); 1047 esp_soft_reset(s); 1048 break; 1049 case CMD_BUSRESET: 1050 trace_esp_mem_writeb_cmd_bus_reset(cmd); 1051 esp_bus_reset(s); 1052 if (!(s->wregs[ESP_CFG1] & CFG1_RESREPT)) { 1053 s->rregs[ESP_RINTR] |= INTR_RST; 1054 esp_raise_irq(s); 1055 } 1056 break; 1057 case CMD_TI: 1058 trace_esp_mem_writeb_cmd_ti(cmd); 1059 handle_ti(s); 1060 break; 1061 case CMD_ICCS: 1062 trace_esp_mem_writeb_cmd_iccs(cmd); 1063 write_response(s); 1064 s->rregs[ESP_RINTR] |= INTR_FC; 1065 esp_set_phase(s, STAT_MI); 1066 break; 1067 case CMD_MSGACC: 1068 trace_esp_mem_writeb_cmd_msgacc(cmd); 1069 s->rregs[ESP_RINTR] |= INTR_DC; 1070 s->rregs[ESP_RSEQ] = 0; 1071 s->rregs[ESP_RFLAGS] = 0; 1072 esp_raise_irq(s); 1073 break; 1074 case CMD_PAD: 1075 trace_esp_mem_writeb_cmd_pad(cmd); 1076 s->rregs[ESP_RSTAT] = STAT_TC; 1077 s->rregs[ESP_RINTR] |= INTR_FC; 1078 s->rregs[ESP_RSEQ] = 0; 1079 break; 1080 case CMD_SATN: 1081 trace_esp_mem_writeb_cmd_satn(cmd); 1082 break; 1083 case CMD_RSTATN: 1084 trace_esp_mem_writeb_cmd_rstatn(cmd); 1085 break; 1086 case CMD_SEL: 1087 trace_esp_mem_writeb_cmd_sel(cmd); 1088 handle_s_without_atn(s); 1089 break; 1090 case CMD_SELATN: 1091 trace_esp_mem_writeb_cmd_selatn(cmd); 1092 handle_satn(s); 1093 break; 1094 case CMD_SELATNS: 1095 trace_esp_mem_writeb_cmd_selatns(cmd); 1096 handle_satn_stop(s); 1097 break; 1098 case CMD_ENSEL: 1099 trace_esp_mem_writeb_cmd_ensel(cmd); 1100 s->rregs[ESP_RINTR] = 0; 1101 break; 1102 case CMD_DISSEL: 1103 trace_esp_mem_writeb_cmd_dissel(cmd); 1104 s->rregs[ESP_RINTR] = 0; 1105 esp_raise_irq(s); 1106 break; 1107 default: 1108 trace_esp_error_unhandled_command(cmd); 1109 break; 1110 } 1111 } 1112 1113 uint64_t esp_reg_read(ESPState *s, uint32_t saddr) 1114 { 1115 uint32_t val; 1116 1117 switch (saddr) { 1118 case ESP_FIFO: 1119 if (s->dma_memory_read && s->dma_memory_write && 1120 (s->rregs[ESP_RSTAT] & STAT_PIO_MASK) == 0) { 1121 /* Data out. */ 1122 qemu_log_mask(LOG_UNIMP, "esp: PIO data read not implemented\n"); 1123 s->rregs[ESP_FIFO] = 0; 1124 } else { 1125 if ((s->rregs[ESP_RSTAT] & 0x7) == STAT_DI) { 1126 if (s->ti_size) { 1127 esp_do_nodma(s); 1128 } else { 1129 /* 1130 * The last byte of a non-DMA transfer has been read out 1131 * of the FIFO so switch to status phase 1132 */ 1133 esp_set_phase(s, STAT_ST); 1134 } 1135 } 1136 s->rregs[ESP_FIFO] = esp_fifo_pop(&s->fifo); 1137 } 1138 val = s->rregs[ESP_FIFO]; 1139 break; 1140 case ESP_RINTR: 1141 /* 1142 * Clear sequence step, interrupt register and all status bits 1143 * except TC 1144 */ 1145 val = s->rregs[ESP_RINTR]; 1146 s->rregs[ESP_RINTR] = 0; 1147 s->rregs[ESP_RSTAT] &= ~STAT_TC; 1148 /* 1149 * According to the datasheet ESP_RSEQ should be cleared, but as the 1150 * emulation currently defers information transfers to the next TI 1151 * command leave it for now so that pedantic guests such as the old 1152 * Linux 2.6 driver see the correct flags before the next SCSI phase 1153 * transition. 1154 * 1155 * s->rregs[ESP_RSEQ] = SEQ_0; 1156 */ 1157 esp_lower_irq(s); 1158 break; 1159 case ESP_TCHI: 1160 /* Return the unique id if the value has never been written */ 1161 if (!s->tchi_written) { 1162 val = s->chip_id; 1163 } else { 1164 val = s->rregs[saddr]; 1165 } 1166 break; 1167 case ESP_RFLAGS: 1168 /* Bottom 5 bits indicate number of bytes in FIFO */ 1169 val = fifo8_num_used(&s->fifo); 1170 break; 1171 default: 1172 val = s->rregs[saddr]; 1173 break; 1174 } 1175 1176 trace_esp_mem_readb(saddr, val); 1177 return val; 1178 } 1179 1180 void esp_reg_write(ESPState *s, uint32_t saddr, uint64_t val) 1181 { 1182 trace_esp_mem_writeb(saddr, s->wregs[saddr], val); 1183 switch (saddr) { 1184 case ESP_TCHI: 1185 s->tchi_written = true; 1186 /* fall through */ 1187 case ESP_TCLO: 1188 case ESP_TCMID: 1189 s->rregs[ESP_RSTAT] &= ~STAT_TC; 1190 break; 1191 case ESP_FIFO: 1192 if (s->do_cmd) { 1193 if (!fifo8_is_full(&s->fifo)) { 1194 esp_fifo_push(&s->fifo, val); 1195 esp_fifo_push(&s->cmdfifo, fifo8_pop(&s->fifo)); 1196 } 1197 1198 /* 1199 * If any unexpected message out/command phase data is 1200 * transferred using non-DMA, raise the interrupt 1201 */ 1202 if (s->rregs[ESP_CMD] == CMD_TI) { 1203 s->rregs[ESP_RINTR] |= INTR_BS; 1204 esp_raise_irq(s); 1205 } 1206 } else { 1207 esp_fifo_push(&s->fifo, val); 1208 } 1209 break; 1210 case ESP_CMD: 1211 s->rregs[saddr] = val; 1212 esp_run_cmd(s); 1213 break; 1214 case ESP_WBUSID ... ESP_WSYNO: 1215 break; 1216 case ESP_CFG1: 1217 case ESP_CFG2: case ESP_CFG3: 1218 case ESP_RES3: case ESP_RES4: 1219 s->rregs[saddr] = val; 1220 break; 1221 case ESP_WCCF ... ESP_WTEST: 1222 break; 1223 default: 1224 trace_esp_error_invalid_write(val, saddr); 1225 return; 1226 } 1227 s->wregs[saddr] = val; 1228 } 1229 1230 static bool esp_mem_accepts(void *opaque, hwaddr addr, 1231 unsigned size, bool is_write, 1232 MemTxAttrs attrs) 1233 { 1234 return (size == 1) || (is_write && size == 4); 1235 } 1236 1237 static bool esp_is_before_version_5(void *opaque, int version_id) 1238 { 1239 ESPState *s = ESP(opaque); 1240 1241 version_id = MIN(version_id, s->mig_version_id); 1242 return version_id < 5; 1243 } 1244 1245 static bool esp_is_version_5(void *opaque, int version_id) 1246 { 1247 ESPState *s = ESP(opaque); 1248 1249 version_id = MIN(version_id, s->mig_version_id); 1250 return version_id >= 5; 1251 } 1252 1253 static bool esp_is_version_6(void *opaque, int version_id) 1254 { 1255 ESPState *s = ESP(opaque); 1256 1257 version_id = MIN(version_id, s->mig_version_id); 1258 return version_id >= 6; 1259 } 1260 1261 int esp_pre_save(void *opaque) 1262 { 1263 ESPState *s = ESP(object_resolve_path_component( 1264 OBJECT(opaque), "esp")); 1265 1266 s->mig_version_id = vmstate_esp.version_id; 1267 return 0; 1268 } 1269 1270 static int esp_post_load(void *opaque, int version_id) 1271 { 1272 ESPState *s = ESP(opaque); 1273 int len, i; 1274 1275 version_id = MIN(version_id, s->mig_version_id); 1276 1277 if (version_id < 5) { 1278 esp_set_tc(s, s->mig_dma_left); 1279 1280 /* Migrate ti_buf to fifo */ 1281 len = s->mig_ti_wptr - s->mig_ti_rptr; 1282 for (i = 0; i < len; i++) { 1283 fifo8_push(&s->fifo, s->mig_ti_buf[i]); 1284 } 1285 1286 /* Migrate cmdbuf to cmdfifo */ 1287 for (i = 0; i < s->mig_cmdlen; i++) { 1288 fifo8_push(&s->cmdfifo, s->mig_cmdbuf[i]); 1289 } 1290 } 1291 1292 s->mig_version_id = vmstate_esp.version_id; 1293 return 0; 1294 } 1295 1296 /* 1297 * PDMA (or pseudo-DMA) is only used on the Macintosh and requires the 1298 * guest CPU to perform the transfers between the SCSI bus and memory 1299 * itself. This is indicated by the dma_memory_read and dma_memory_write 1300 * functions being NULL (in contrast to the ESP PCI device) whilst 1301 * dma_enabled is still set. 1302 */ 1303 1304 static bool esp_pdma_needed(void *opaque) 1305 { 1306 ESPState *s = ESP(opaque); 1307 1308 return s->dma_memory_read == NULL && s->dma_memory_write == NULL && 1309 s->dma_enabled; 1310 } 1311 1312 static const VMStateDescription vmstate_esp_pdma = { 1313 .name = "esp/pdma", 1314 .version_id = 0, 1315 .minimum_version_id = 0, 1316 .needed = esp_pdma_needed, 1317 .fields = (const VMStateField[]) { 1318 VMSTATE_UINT8(pdma_cb, ESPState), 1319 VMSTATE_END_OF_LIST() 1320 } 1321 }; 1322 1323 const VMStateDescription vmstate_esp = { 1324 .name = "esp", 1325 .version_id = 6, 1326 .minimum_version_id = 3, 1327 .post_load = esp_post_load, 1328 .fields = (const VMStateField[]) { 1329 VMSTATE_BUFFER(rregs, ESPState), 1330 VMSTATE_BUFFER(wregs, ESPState), 1331 VMSTATE_INT32(ti_size, ESPState), 1332 VMSTATE_UINT32_TEST(mig_ti_rptr, ESPState, esp_is_before_version_5), 1333 VMSTATE_UINT32_TEST(mig_ti_wptr, ESPState, esp_is_before_version_5), 1334 VMSTATE_BUFFER_TEST(mig_ti_buf, ESPState, esp_is_before_version_5), 1335 VMSTATE_UINT32(status, ESPState), 1336 VMSTATE_UINT32_TEST(mig_deferred_status, ESPState, 1337 esp_is_before_version_5), 1338 VMSTATE_BOOL_TEST(mig_deferred_complete, ESPState, 1339 esp_is_before_version_5), 1340 VMSTATE_UINT32(dma, ESPState), 1341 VMSTATE_STATIC_BUFFER(mig_cmdbuf, ESPState, 0, 1342 esp_is_before_version_5, 0, 16), 1343 VMSTATE_STATIC_BUFFER(mig_cmdbuf, ESPState, 4, 1344 esp_is_before_version_5, 16, 1345 sizeof(typeof_field(ESPState, mig_cmdbuf))), 1346 VMSTATE_UINT32_TEST(mig_cmdlen, ESPState, esp_is_before_version_5), 1347 VMSTATE_UINT32(do_cmd, ESPState), 1348 VMSTATE_UINT32_TEST(mig_dma_left, ESPState, esp_is_before_version_5), 1349 VMSTATE_BOOL_TEST(data_in_ready, ESPState, esp_is_version_5), 1350 VMSTATE_UINT8_TEST(cmdfifo_cdb_offset, ESPState, esp_is_version_5), 1351 VMSTATE_FIFO8_TEST(fifo, ESPState, esp_is_version_5), 1352 VMSTATE_FIFO8_TEST(cmdfifo, ESPState, esp_is_version_5), 1353 VMSTATE_UINT8_TEST(ti_cmd, ESPState, esp_is_version_5), 1354 VMSTATE_UINT8_TEST(lun, ESPState, esp_is_version_6), 1355 VMSTATE_END_OF_LIST() 1356 }, 1357 .subsections = (const VMStateDescription * const []) { 1358 &vmstate_esp_pdma, 1359 NULL 1360 } 1361 }; 1362 1363 static void sysbus_esp_mem_write(void *opaque, hwaddr addr, 1364 uint64_t val, unsigned int size) 1365 { 1366 SysBusESPState *sysbus = opaque; 1367 ESPState *s = ESP(&sysbus->esp); 1368 uint32_t saddr; 1369 1370 saddr = addr >> sysbus->it_shift; 1371 esp_reg_write(s, saddr, val); 1372 } 1373 1374 static uint64_t sysbus_esp_mem_read(void *opaque, hwaddr addr, 1375 unsigned int size) 1376 { 1377 SysBusESPState *sysbus = opaque; 1378 ESPState *s = ESP(&sysbus->esp); 1379 uint32_t saddr; 1380 1381 saddr = addr >> sysbus->it_shift; 1382 return esp_reg_read(s, saddr); 1383 } 1384 1385 static const MemoryRegionOps sysbus_esp_mem_ops = { 1386 .read = sysbus_esp_mem_read, 1387 .write = sysbus_esp_mem_write, 1388 .endianness = DEVICE_NATIVE_ENDIAN, 1389 .valid.accepts = esp_mem_accepts, 1390 }; 1391 1392 static void sysbus_esp_pdma_write(void *opaque, hwaddr addr, 1393 uint64_t val, unsigned int size) 1394 { 1395 SysBusESPState *sysbus = opaque; 1396 ESPState *s = ESP(&sysbus->esp); 1397 1398 trace_esp_pdma_write(size); 1399 1400 switch (size) { 1401 case 1: 1402 esp_pdma_write(s, val); 1403 break; 1404 case 2: 1405 esp_pdma_write(s, val >> 8); 1406 esp_pdma_write(s, val); 1407 break; 1408 } 1409 esp_pdma_cb(s); 1410 } 1411 1412 static uint64_t sysbus_esp_pdma_read(void *opaque, hwaddr addr, 1413 unsigned int size) 1414 { 1415 SysBusESPState *sysbus = opaque; 1416 ESPState *s = ESP(&sysbus->esp); 1417 uint64_t val = 0; 1418 1419 trace_esp_pdma_read(size); 1420 1421 switch (size) { 1422 case 1: 1423 val = esp_pdma_read(s); 1424 break; 1425 case 2: 1426 val = esp_pdma_read(s); 1427 val = (val << 8) | esp_pdma_read(s); 1428 break; 1429 } 1430 esp_pdma_cb(s); 1431 return val; 1432 } 1433 1434 static void *esp_load_request(QEMUFile *f, SCSIRequest *req) 1435 { 1436 ESPState *s = container_of(req->bus, ESPState, bus); 1437 1438 scsi_req_ref(req); 1439 s->current_req = req; 1440 return s; 1441 } 1442 1443 static const MemoryRegionOps sysbus_esp_pdma_ops = { 1444 .read = sysbus_esp_pdma_read, 1445 .write = sysbus_esp_pdma_write, 1446 .endianness = DEVICE_NATIVE_ENDIAN, 1447 .valid.min_access_size = 1, 1448 .valid.max_access_size = 4, 1449 .impl.min_access_size = 1, 1450 .impl.max_access_size = 2, 1451 }; 1452 1453 static const struct SCSIBusInfo esp_scsi_info = { 1454 .tcq = false, 1455 .max_target = ESP_MAX_DEVS, 1456 .max_lun = 7, 1457 1458 .load_request = esp_load_request, 1459 .transfer_data = esp_transfer_data, 1460 .complete = esp_command_complete, 1461 .cancel = esp_request_cancelled 1462 }; 1463 1464 static void sysbus_esp_gpio_demux(void *opaque, int irq, int level) 1465 { 1466 SysBusESPState *sysbus = SYSBUS_ESP(opaque); 1467 ESPState *s = ESP(&sysbus->esp); 1468 1469 switch (irq) { 1470 case 0: 1471 parent_esp_reset(s, irq, level); 1472 break; 1473 case 1: 1474 esp_dma_enable(s, irq, level); 1475 break; 1476 } 1477 } 1478 1479 static void sysbus_esp_realize(DeviceState *dev, Error **errp) 1480 { 1481 SysBusDevice *sbd = SYS_BUS_DEVICE(dev); 1482 SysBusESPState *sysbus = SYSBUS_ESP(dev); 1483 ESPState *s = ESP(&sysbus->esp); 1484 1485 if (!qdev_realize(DEVICE(s), NULL, errp)) { 1486 return; 1487 } 1488 1489 sysbus_init_irq(sbd, &s->irq); 1490 sysbus_init_irq(sbd, &s->irq_data); 1491 assert(sysbus->it_shift != -1); 1492 1493 s->chip_id = TCHI_FAS100A; 1494 memory_region_init_io(&sysbus->iomem, OBJECT(sysbus), &sysbus_esp_mem_ops, 1495 sysbus, "esp-regs", ESP_REGS << sysbus->it_shift); 1496 sysbus_init_mmio(sbd, &sysbus->iomem); 1497 memory_region_init_io(&sysbus->pdma, OBJECT(sysbus), &sysbus_esp_pdma_ops, 1498 sysbus, "esp-pdma", 4); 1499 sysbus_init_mmio(sbd, &sysbus->pdma); 1500 1501 qdev_init_gpio_in(dev, sysbus_esp_gpio_demux, 2); 1502 1503 scsi_bus_init(&s->bus, sizeof(s->bus), dev, &esp_scsi_info); 1504 } 1505 1506 static void sysbus_esp_hard_reset(DeviceState *dev) 1507 { 1508 SysBusESPState *sysbus = SYSBUS_ESP(dev); 1509 ESPState *s = ESP(&sysbus->esp); 1510 1511 esp_hard_reset(s); 1512 } 1513 1514 static void sysbus_esp_init(Object *obj) 1515 { 1516 SysBusESPState *sysbus = SYSBUS_ESP(obj); 1517 1518 object_initialize_child(obj, "esp", &sysbus->esp, TYPE_ESP); 1519 } 1520 1521 static const VMStateDescription vmstate_sysbus_esp_scsi = { 1522 .name = "sysbusespscsi", 1523 .version_id = 2, 1524 .minimum_version_id = 1, 1525 .pre_save = esp_pre_save, 1526 .fields = (const VMStateField[]) { 1527 VMSTATE_UINT8_V(esp.mig_version_id, SysBusESPState, 2), 1528 VMSTATE_STRUCT(esp, SysBusESPState, 0, vmstate_esp, ESPState), 1529 VMSTATE_END_OF_LIST() 1530 } 1531 }; 1532 1533 static void sysbus_esp_class_init(ObjectClass *klass, void *data) 1534 { 1535 DeviceClass *dc = DEVICE_CLASS(klass); 1536 1537 dc->realize = sysbus_esp_realize; 1538 dc->reset = sysbus_esp_hard_reset; 1539 dc->vmsd = &vmstate_sysbus_esp_scsi; 1540 set_bit(DEVICE_CATEGORY_STORAGE, dc->categories); 1541 } 1542 1543 static const TypeInfo sysbus_esp_info = { 1544 .name = TYPE_SYSBUS_ESP, 1545 .parent = TYPE_SYS_BUS_DEVICE, 1546 .instance_init = sysbus_esp_init, 1547 .instance_size = sizeof(SysBusESPState), 1548 .class_init = sysbus_esp_class_init, 1549 }; 1550 1551 static void esp_finalize(Object *obj) 1552 { 1553 ESPState *s = ESP(obj); 1554 1555 fifo8_destroy(&s->fifo); 1556 fifo8_destroy(&s->cmdfifo); 1557 } 1558 1559 static void esp_init(Object *obj) 1560 { 1561 ESPState *s = ESP(obj); 1562 1563 fifo8_create(&s->fifo, ESP_FIFO_SZ); 1564 fifo8_create(&s->cmdfifo, ESP_CMDFIFO_SZ); 1565 } 1566 1567 static void esp_class_init(ObjectClass *klass, void *data) 1568 { 1569 DeviceClass *dc = DEVICE_CLASS(klass); 1570 1571 /* internal device for sysbusesp/pciespscsi, not user-creatable */ 1572 dc->user_creatable = false; 1573 set_bit(DEVICE_CATEGORY_STORAGE, dc->categories); 1574 } 1575 1576 static const TypeInfo esp_info = { 1577 .name = TYPE_ESP, 1578 .parent = TYPE_DEVICE, 1579 .instance_init = esp_init, 1580 .instance_finalize = esp_finalize, 1581 .instance_size = sizeof(ESPState), 1582 .class_init = esp_class_init, 1583 }; 1584 1585 static void esp_register_types(void) 1586 { 1587 type_register_static(&sysbus_esp_info); 1588 type_register_static(&esp_info); 1589 } 1590 1591 type_init(esp_register_types) 1592