1 /* 2 * QEMU ESP/NCR53C9x emulation 3 * 4 * Copyright (c) 2005-2006 Fabrice Bellard 5 * Copyright (c) 2012 Herve Poussineau 6 * 7 * Permission is hereby granted, free of charge, to any person obtaining a copy 8 * of this software and associated documentation files (the "Software"), to deal 9 * in the Software without restriction, including without limitation the rights 10 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 11 * copies of the Software, and to permit persons to whom the Software is 12 * furnished to do so, subject to the following conditions: 13 * 14 * The above copyright notice and this permission notice shall be included in 15 * all copies or substantial portions of the Software. 16 * 17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 22 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 23 * THE SOFTWARE. 24 */ 25 26 #include "qemu/osdep.h" 27 #include "hw/sysbus.h" 28 #include "migration/vmstate.h" 29 #include "hw/irq.h" 30 #include "hw/scsi/esp.h" 31 #include "trace.h" 32 #include "qemu/log.h" 33 #include "qemu/module.h" 34 35 /* 36 * On Sparc32, this is the ESP (NCR53C90) part of chip STP2000 (Master I/O), 37 * also produced as NCR89C100. See 38 * http://www.ibiblio.org/pub/historic-linux/early-ports/Sparc/NCR/NCR89C100.txt 39 * and 40 * http://www.ibiblio.org/pub/historic-linux/early-ports/Sparc/NCR/NCR53C9X.txt 41 * 42 * On Macintosh Quadra it is a NCR53C96. 43 */ 44 45 static void esp_raise_irq(ESPState *s) 46 { 47 if (!(s->rregs[ESP_RSTAT] & STAT_INT)) { 48 s->rregs[ESP_RSTAT] |= STAT_INT; 49 qemu_irq_raise(s->irq); 50 trace_esp_raise_irq(); 51 } 52 } 53 54 static void esp_lower_irq(ESPState *s) 55 { 56 if (s->rregs[ESP_RSTAT] & STAT_INT) { 57 s->rregs[ESP_RSTAT] &= ~STAT_INT; 58 qemu_irq_lower(s->irq); 59 trace_esp_lower_irq(); 60 } 61 } 62 63 static void esp_raise_drq(ESPState *s) 64 { 65 qemu_irq_raise(s->irq_data); 66 trace_esp_raise_drq(); 67 } 68 69 static void esp_lower_drq(ESPState *s) 70 { 71 qemu_irq_lower(s->irq_data); 72 trace_esp_lower_drq(); 73 } 74 75 void esp_dma_enable(ESPState *s, int irq, int level) 76 { 77 if (level) { 78 s->dma_enabled = 1; 79 trace_esp_dma_enable(); 80 if (s->dma_cb) { 81 s->dma_cb(s); 82 s->dma_cb = NULL; 83 } 84 } else { 85 trace_esp_dma_disable(); 86 s->dma_enabled = 0; 87 } 88 } 89 90 void esp_request_cancelled(SCSIRequest *req) 91 { 92 ESPState *s = req->hba_private; 93 94 if (req == s->current_req) { 95 scsi_req_unref(s->current_req); 96 s->current_req = NULL; 97 s->current_dev = NULL; 98 s->async_len = 0; 99 } 100 } 101 102 static void esp_fifo_push(Fifo8 *fifo, uint8_t val) 103 { 104 if (fifo8_num_used(fifo) == fifo->capacity) { 105 trace_esp_error_fifo_overrun(); 106 return; 107 } 108 109 fifo8_push(fifo, val); 110 } 111 112 static uint8_t esp_fifo_pop(Fifo8 *fifo) 113 { 114 if (fifo8_is_empty(fifo)) { 115 return 0; 116 } 117 118 return fifo8_pop(fifo); 119 } 120 121 static uint32_t esp_fifo_pop_buf(Fifo8 *fifo, uint8_t *dest, int maxlen) 122 { 123 const uint8_t *buf; 124 uint32_t n, n2; 125 int len; 126 127 if (maxlen == 0) { 128 return 0; 129 } 130 131 len = maxlen; 132 buf = fifo8_pop_buf(fifo, len, &n); 133 if (dest) { 134 memcpy(dest, buf, n); 135 } 136 137 /* Add FIFO wraparound if needed */ 138 len -= n; 139 len = MIN(len, fifo8_num_used(fifo)); 140 if (len) { 141 buf = fifo8_pop_buf(fifo, len, &n2); 142 if (dest) { 143 memcpy(&dest[n], buf, n2); 144 } 145 n += n2; 146 } 147 148 return n; 149 } 150 151 static uint32_t esp_get_tc(ESPState *s) 152 { 153 uint32_t dmalen; 154 155 dmalen = s->rregs[ESP_TCLO]; 156 dmalen |= s->rregs[ESP_TCMID] << 8; 157 dmalen |= s->rregs[ESP_TCHI] << 16; 158 159 return dmalen; 160 } 161 162 static void esp_set_tc(ESPState *s, uint32_t dmalen) 163 { 164 uint32_t old_tc = esp_get_tc(s); 165 166 s->rregs[ESP_TCLO] = dmalen; 167 s->rregs[ESP_TCMID] = dmalen >> 8; 168 s->rregs[ESP_TCHI] = dmalen >> 16; 169 170 if (old_tc && dmalen == 0) { 171 s->rregs[ESP_RSTAT] |= STAT_TC; 172 } 173 } 174 175 static uint32_t esp_get_stc(ESPState *s) 176 { 177 uint32_t dmalen; 178 179 dmalen = s->wregs[ESP_TCLO]; 180 dmalen |= s->wregs[ESP_TCMID] << 8; 181 dmalen |= s->wregs[ESP_TCHI] << 16; 182 183 return dmalen; 184 } 185 186 static const char *esp_phase_names[8] = { 187 "DATA OUT", "DATA IN", "COMMAND", "STATUS", 188 "(reserved)", "(reserved)", "MESSAGE OUT", "MESSAGE IN" 189 }; 190 191 static void esp_set_phase(ESPState *s, uint8_t phase) 192 { 193 s->rregs[ESP_RSTAT] &= ~7; 194 s->rregs[ESP_RSTAT] |= phase; 195 196 trace_esp_set_phase(esp_phase_names[phase]); 197 } 198 199 static uint8_t esp_pdma_read(ESPState *s) 200 { 201 uint8_t val; 202 203 val = esp_fifo_pop(&s->fifo); 204 return val; 205 } 206 207 static void esp_pdma_write(ESPState *s, uint8_t val) 208 { 209 uint32_t dmalen = esp_get_tc(s); 210 211 if (dmalen == 0) { 212 return; 213 } 214 215 esp_fifo_push(&s->fifo, val); 216 217 dmalen--; 218 esp_set_tc(s, dmalen); 219 } 220 221 static void esp_set_pdma_cb(ESPState *s, enum pdma_cb cb) 222 { 223 s->pdma_cb = cb; 224 } 225 226 static int esp_select(ESPState *s) 227 { 228 int target; 229 230 target = s->wregs[ESP_WBUSID] & BUSID_DID; 231 232 s->ti_size = 0; 233 234 if (s->current_req) { 235 /* Started a new command before the old one finished. Cancel it. */ 236 scsi_req_cancel(s->current_req); 237 } 238 239 s->current_dev = scsi_device_find(&s->bus, 0, target, 0); 240 if (!s->current_dev) { 241 /* No such drive */ 242 s->rregs[ESP_RSTAT] = 0; 243 s->rregs[ESP_RINTR] = INTR_DC; 244 s->rregs[ESP_RSEQ] = SEQ_0; 245 esp_raise_irq(s); 246 return -1; 247 } 248 249 /* 250 * Note that we deliberately don't raise the IRQ here: this will be done 251 * either in do_command_phase() for DATA OUT transfers or by the deferred 252 * IRQ mechanism in esp_transfer_data() for DATA IN transfers 253 */ 254 s->rregs[ESP_RINTR] |= INTR_FC; 255 s->rregs[ESP_RSEQ] = SEQ_CD; 256 return 0; 257 } 258 259 static uint32_t get_cmd(ESPState *s, uint32_t maxlen) 260 { 261 uint8_t buf[ESP_CMDFIFO_SZ]; 262 uint32_t dmalen, n; 263 int target; 264 265 target = s->wregs[ESP_WBUSID] & BUSID_DID; 266 if (s->dma) { 267 dmalen = MIN(esp_get_tc(s), maxlen); 268 if (dmalen == 0) { 269 return 0; 270 } 271 if (s->dma_memory_read) { 272 s->dma_memory_read(s->dma_opaque, buf, dmalen); 273 dmalen = MIN(fifo8_num_free(&s->cmdfifo), dmalen); 274 fifo8_push_all(&s->cmdfifo, buf, dmalen); 275 esp_set_tc(s, esp_get_tc(s) - dmalen); 276 } else { 277 return 0; 278 } 279 } else { 280 dmalen = MIN(fifo8_num_used(&s->fifo), maxlen); 281 if (dmalen == 0) { 282 return 0; 283 } 284 n = esp_fifo_pop_buf(&s->fifo, buf, dmalen); 285 n = MIN(fifo8_num_free(&s->cmdfifo), n); 286 fifo8_push_all(&s->cmdfifo, buf, n); 287 } 288 trace_esp_get_cmd(dmalen, target); 289 290 return dmalen; 291 } 292 293 static void do_command_phase(ESPState *s) 294 { 295 uint32_t cmdlen; 296 int32_t datalen; 297 SCSIDevice *current_lun; 298 uint8_t buf[ESP_CMDFIFO_SZ]; 299 300 trace_esp_do_command_phase(s->lun); 301 cmdlen = fifo8_num_used(&s->cmdfifo); 302 if (!cmdlen || !s->current_dev) { 303 return; 304 } 305 esp_fifo_pop_buf(&s->cmdfifo, buf, cmdlen); 306 307 current_lun = scsi_device_find(&s->bus, 0, s->current_dev->id, s->lun); 308 if (!current_lun) { 309 /* No such drive */ 310 s->rregs[ESP_RSTAT] = 0; 311 s->rregs[ESP_RINTR] = INTR_DC; 312 s->rregs[ESP_RSEQ] = SEQ_0; 313 esp_raise_irq(s); 314 return; 315 } 316 317 s->current_req = scsi_req_new(current_lun, 0, s->lun, buf, cmdlen, s); 318 datalen = scsi_req_enqueue(s->current_req); 319 s->ti_size = datalen; 320 fifo8_reset(&s->cmdfifo); 321 if (datalen != 0) { 322 s->ti_cmd = 0; 323 if (datalen > 0) { 324 /* 325 * Switch to DATA IN phase but wait until initial data xfer is 326 * complete before raising the command completion interrupt 327 */ 328 s->data_in_ready = false; 329 esp_set_phase(s, STAT_DI); 330 } else { 331 esp_set_phase(s, STAT_DO); 332 s->rregs[ESP_RINTR] |= INTR_BS | INTR_FC; 333 esp_raise_irq(s); 334 esp_lower_drq(s); 335 } 336 scsi_req_continue(s->current_req); 337 return; 338 } 339 } 340 341 static void do_message_phase(ESPState *s) 342 { 343 if (s->cmdfifo_cdb_offset) { 344 uint8_t message = esp_fifo_pop(&s->cmdfifo); 345 346 trace_esp_do_identify(message); 347 s->lun = message & 7; 348 s->cmdfifo_cdb_offset--; 349 } 350 351 /* Ignore extended messages for now */ 352 if (s->cmdfifo_cdb_offset) { 353 int len = MIN(s->cmdfifo_cdb_offset, fifo8_num_used(&s->cmdfifo)); 354 esp_fifo_pop_buf(&s->cmdfifo, NULL, len); 355 s->cmdfifo_cdb_offset = 0; 356 } 357 } 358 359 static void do_cmd(ESPState *s) 360 { 361 do_message_phase(s); 362 assert(s->cmdfifo_cdb_offset == 0); 363 do_command_phase(s); 364 } 365 366 static void satn_pdma_cb(ESPState *s) 367 { 368 uint8_t buf[ESP_FIFO_SZ]; 369 int n; 370 371 /* Copy FIFO into cmdfifo */ 372 n = esp_fifo_pop_buf(&s->fifo, buf, fifo8_num_used(&s->fifo)); 373 n = MIN(fifo8_num_free(&s->cmdfifo), n); 374 fifo8_push_all(&s->cmdfifo, buf, n); 375 376 if (!esp_get_tc(s) && !fifo8_is_empty(&s->cmdfifo)) { 377 s->cmdfifo_cdb_offset = 1; 378 s->do_cmd = 0; 379 do_cmd(s); 380 } 381 } 382 383 static void handle_satn(ESPState *s) 384 { 385 int32_t cmdlen; 386 387 if (s->dma && !s->dma_enabled) { 388 s->dma_cb = handle_satn; 389 return; 390 } 391 esp_set_pdma_cb(s, SATN_PDMA_CB); 392 if (esp_select(s) < 0) { 393 return; 394 } 395 cmdlen = get_cmd(s, ESP_CMDFIFO_SZ); 396 if (cmdlen > 0) { 397 s->cmdfifo_cdb_offset = 1; 398 s->do_cmd = 0; 399 do_cmd(s); 400 } else if (cmdlen == 0) { 401 if (s->dma) { 402 esp_raise_drq(s); 403 } 404 s->do_cmd = 1; 405 /* Target present, but no cmd yet - switch to command phase */ 406 s->rregs[ESP_RSEQ] = SEQ_CD; 407 esp_set_phase(s, STAT_CD); 408 } 409 } 410 411 static void s_without_satn_pdma_cb(ESPState *s) 412 { 413 uint8_t buf[ESP_FIFO_SZ]; 414 int n; 415 416 /* Copy FIFO into cmdfifo */ 417 n = esp_fifo_pop_buf(&s->fifo, buf, fifo8_num_used(&s->fifo)); 418 n = MIN(fifo8_num_free(&s->cmdfifo), n); 419 fifo8_push_all(&s->cmdfifo, buf, n); 420 421 if (!esp_get_tc(s) && !fifo8_is_empty(&s->cmdfifo)) { 422 s->cmdfifo_cdb_offset = 0; 423 s->do_cmd = 0; 424 do_cmd(s); 425 } 426 } 427 428 static void handle_s_without_atn(ESPState *s) 429 { 430 int32_t cmdlen; 431 432 if (s->dma && !s->dma_enabled) { 433 s->dma_cb = handle_s_without_atn; 434 return; 435 } 436 esp_set_pdma_cb(s, S_WITHOUT_SATN_PDMA_CB); 437 if (esp_select(s) < 0) { 438 return; 439 } 440 cmdlen = get_cmd(s, ESP_CMDFIFO_SZ); 441 if (cmdlen > 0) { 442 s->cmdfifo_cdb_offset = 0; 443 s->do_cmd = 0; 444 do_cmd(s); 445 } else if (cmdlen == 0) { 446 if (s->dma) { 447 esp_raise_drq(s); 448 } 449 s->do_cmd = 1; 450 /* Target present, but no cmd yet - switch to command phase */ 451 s->rregs[ESP_RSEQ] = SEQ_CD; 452 esp_set_phase(s, STAT_CD); 453 } 454 } 455 456 static void satn_stop_pdma_cb(ESPState *s) 457 { 458 uint8_t buf[ESP_FIFO_SZ]; 459 int n; 460 461 /* Copy FIFO into cmdfifo */ 462 n = esp_fifo_pop_buf(&s->fifo, buf, fifo8_num_used(&s->fifo)); 463 n = MIN(fifo8_num_free(&s->cmdfifo), n); 464 fifo8_push_all(&s->cmdfifo, buf, n); 465 466 if (!esp_get_tc(s) && !fifo8_is_empty(&s->cmdfifo)) { 467 trace_esp_handle_satn_stop(fifo8_num_used(&s->cmdfifo)); 468 s->do_cmd = 1; 469 s->cmdfifo_cdb_offset = 1; 470 esp_set_phase(s, STAT_CD); 471 s->rregs[ESP_RSTAT] |= STAT_TC; 472 s->rregs[ESP_RINTR] |= INTR_BS | INTR_FC; 473 s->rregs[ESP_RSEQ] = SEQ_CD; 474 esp_raise_irq(s); 475 } 476 } 477 478 static void handle_satn_stop(ESPState *s) 479 { 480 int32_t cmdlen; 481 482 if (s->dma && !s->dma_enabled) { 483 s->dma_cb = handle_satn_stop; 484 return; 485 } 486 esp_set_pdma_cb(s, SATN_STOP_PDMA_CB); 487 if (esp_select(s) < 0) { 488 return; 489 } 490 cmdlen = get_cmd(s, 1); 491 if (cmdlen > 0) { 492 trace_esp_handle_satn_stop(fifo8_num_used(&s->cmdfifo)); 493 s->do_cmd = 1; 494 s->cmdfifo_cdb_offset = 1; 495 esp_set_phase(s, STAT_MO); 496 s->rregs[ESP_RINTR] |= INTR_BS | INTR_FC; 497 s->rregs[ESP_RSEQ] = SEQ_MO; 498 esp_raise_irq(s); 499 } else if (cmdlen == 0) { 500 if (s->dma) { 501 esp_raise_drq(s); 502 } 503 s->do_cmd = 1; 504 /* Target present, switch to message out phase */ 505 s->rregs[ESP_RSEQ] = SEQ_MO; 506 esp_set_phase(s, STAT_MO); 507 } 508 } 509 510 static void write_response_pdma_cb(ESPState *s) 511 { 512 esp_set_phase(s, STAT_ST); 513 s->rregs[ESP_RINTR] |= INTR_BS | INTR_FC; 514 s->rregs[ESP_RSEQ] = SEQ_CD; 515 esp_raise_irq(s); 516 } 517 518 static void write_response(ESPState *s) 519 { 520 uint8_t buf[2]; 521 522 trace_esp_write_response(s->status); 523 524 buf[0] = s->status; 525 buf[1] = 0; 526 527 if (s->dma) { 528 if (s->dma_memory_write) { 529 s->dma_memory_write(s->dma_opaque, buf, 2); 530 esp_set_phase(s, STAT_ST); 531 s->rregs[ESP_RINTR] |= INTR_BS | INTR_FC; 532 s->rregs[ESP_RSEQ] = SEQ_CD; 533 } else { 534 esp_set_pdma_cb(s, WRITE_RESPONSE_PDMA_CB); 535 esp_raise_drq(s); 536 return; 537 } 538 } else { 539 fifo8_reset(&s->fifo); 540 fifo8_push_all(&s->fifo, buf, 2); 541 s->rregs[ESP_RFLAGS] = 2; 542 } 543 esp_raise_irq(s); 544 } 545 546 static void esp_dma_done(ESPState *s) 547 { 548 s->rregs[ESP_RINTR] |= INTR_BS; 549 esp_raise_irq(s); 550 } 551 552 static void do_dma_pdma_cb(ESPState *s) 553 { 554 int to_device = ((s->rregs[ESP_RSTAT] & 7) == STAT_DO); 555 uint8_t buf[ESP_CMDFIFO_SZ]; 556 int len; 557 uint32_t n; 558 559 if (s->do_cmd) { 560 /* Copy FIFO into cmdfifo */ 561 n = esp_fifo_pop_buf(&s->fifo, buf, fifo8_num_used(&s->fifo)); 562 n = MIN(fifo8_num_free(&s->cmdfifo), n); 563 fifo8_push_all(&s->cmdfifo, buf, n); 564 565 /* Ensure we have received complete command after SATN and stop */ 566 if (esp_get_tc(s) || fifo8_is_empty(&s->cmdfifo)) { 567 return; 568 } 569 570 s->ti_size = 0; 571 if ((s->rregs[ESP_RSTAT] & 7) == STAT_CD) { 572 /* No command received */ 573 if (s->cmdfifo_cdb_offset == fifo8_num_used(&s->cmdfifo)) { 574 return; 575 } 576 577 /* Command has been received */ 578 s->do_cmd = 0; 579 do_cmd(s); 580 } else { 581 /* 582 * Extra message out bytes received: update cmdfifo_cdb_offset 583 * and then switch to command phase 584 */ 585 s->cmdfifo_cdb_offset = fifo8_num_used(&s->cmdfifo); 586 esp_set_phase(s, STAT_CD); 587 s->rregs[ESP_RSEQ] = SEQ_CD; 588 s->rregs[ESP_RINTR] |= INTR_BS; 589 esp_raise_irq(s); 590 } 591 return; 592 } 593 594 if (!s->current_req) { 595 return; 596 } 597 598 if (to_device) { 599 /* Copy FIFO data to device */ 600 len = MIN(s->async_len, ESP_FIFO_SZ); 601 len = MIN(len, fifo8_num_used(&s->fifo)); 602 n = esp_fifo_pop_buf(&s->fifo, s->async_buf, len); 603 s->async_buf += n; 604 s->async_len -= n; 605 s->ti_size += n; 606 607 if (n < len) { 608 /* Unaligned accesses can cause FIFO wraparound */ 609 len = len - n; 610 n = esp_fifo_pop_buf(&s->fifo, s->async_buf, len); 611 s->async_buf += n; 612 s->async_len -= n; 613 s->ti_size += n; 614 } 615 616 if (s->async_len == 0) { 617 scsi_req_continue(s->current_req); 618 return; 619 } 620 621 if (esp_get_tc(s) == 0) { 622 esp_lower_drq(s); 623 esp_dma_done(s); 624 } 625 626 return; 627 } else { 628 if (s->async_len == 0) { 629 /* Defer until the scsi layer has completed */ 630 scsi_req_continue(s->current_req); 631 s->data_in_ready = false; 632 return; 633 } 634 635 if (esp_get_tc(s) == 0) { 636 esp_lower_drq(s); 637 esp_dma_done(s); 638 } 639 640 /* Copy device data to FIFO */ 641 len = MIN(s->async_len, esp_get_tc(s)); 642 len = MIN(len, fifo8_num_free(&s->fifo)); 643 fifo8_push_all(&s->fifo, s->async_buf, len); 644 s->async_buf += len; 645 s->async_len -= len; 646 s->ti_size -= len; 647 esp_set_tc(s, esp_get_tc(s) - len); 648 } 649 } 650 651 static void esp_do_dma(ESPState *s) 652 { 653 uint32_t len, cmdlen; 654 int to_device = ((s->rregs[ESP_RSTAT] & 7) == STAT_DO); 655 uint8_t buf[ESP_CMDFIFO_SZ]; 656 657 len = esp_get_tc(s); 658 if (s->do_cmd) { 659 /* 660 * handle_ti_cmd() case: esp_do_dma() is called only from 661 * handle_ti_cmd() with do_cmd != NULL (see the assert()) 662 */ 663 cmdlen = fifo8_num_used(&s->cmdfifo); 664 trace_esp_do_dma(cmdlen, len); 665 if (s->dma_memory_read) { 666 len = MIN(len, fifo8_num_free(&s->cmdfifo)); 667 s->dma_memory_read(s->dma_opaque, buf, len); 668 fifo8_push_all(&s->cmdfifo, buf, len); 669 esp_set_tc(s, esp_get_tc(s) - len); 670 } else { 671 esp_set_pdma_cb(s, DO_DMA_PDMA_CB); 672 esp_raise_drq(s); 673 return; 674 } 675 trace_esp_handle_ti_cmd(cmdlen); 676 s->ti_size = 0; 677 if ((s->rregs[ESP_RSTAT] & 7) == STAT_CD) { 678 /* No command received */ 679 if (s->cmdfifo_cdb_offset == fifo8_num_used(&s->cmdfifo)) { 680 return; 681 } 682 683 /* Command has been received */ 684 s->do_cmd = 0; 685 do_cmd(s); 686 } else { 687 /* 688 * Extra message out bytes received: update cmdfifo_cdb_offset 689 * and then switch to command phase 690 */ 691 s->cmdfifo_cdb_offset = fifo8_num_used(&s->cmdfifo); 692 esp_set_phase(s, STAT_CD); 693 s->rregs[ESP_RSEQ] = SEQ_CD; 694 s->rregs[ESP_RINTR] |= INTR_BS; 695 esp_raise_irq(s); 696 } 697 return; 698 } 699 if (!s->current_req) { 700 return; 701 } 702 if (s->async_len == 0) { 703 /* Defer until data is available. */ 704 return; 705 } 706 if (len > s->async_len) { 707 len = s->async_len; 708 } 709 if (to_device) { 710 if (s->dma_memory_read) { 711 s->dma_memory_read(s->dma_opaque, s->async_buf, len); 712 713 esp_set_tc(s, esp_get_tc(s) - len); 714 s->async_buf += len; 715 s->async_len -= len; 716 s->ti_size += len; 717 718 if (s->async_len == 0) { 719 scsi_req_continue(s->current_req); 720 /* 721 * If there is still data to be read from the device then 722 * complete the DMA operation immediately. Otherwise defer 723 * until the scsi layer has completed. 724 */ 725 return; 726 } 727 728 if (esp_get_tc(s) == 0) { 729 /* Partially filled a scsi buffer. Complete immediately. */ 730 esp_dma_done(s); 731 esp_lower_drq(s); 732 } 733 } else { 734 esp_set_pdma_cb(s, DO_DMA_PDMA_CB); 735 esp_raise_drq(s); 736 } 737 } else { 738 if (s->dma_memory_write) { 739 s->dma_memory_write(s->dma_opaque, s->async_buf, len); 740 741 esp_set_tc(s, esp_get_tc(s) - len); 742 s->async_buf += len; 743 s->async_len -= len; 744 s->ti_size -= len; 745 746 if (s->async_len == 0) { 747 scsi_req_continue(s->current_req); 748 } 749 750 if (esp_get_tc(s) == 0) { 751 /* Partially filled a scsi buffer. Complete immediately. */ 752 esp_dma_done(s); 753 esp_lower_drq(s); 754 } 755 } else { 756 /* Adjust TC for any leftover data in the FIFO */ 757 if (!fifo8_is_empty(&s->fifo)) { 758 esp_set_tc(s, esp_get_tc(s) - fifo8_num_used(&s->fifo)); 759 } 760 761 /* Copy device data to FIFO */ 762 len = MIN(len, fifo8_num_free(&s->fifo)); 763 fifo8_push_all(&s->fifo, s->async_buf, len); 764 s->async_buf += len; 765 s->async_len -= len; 766 s->ti_size -= len; 767 esp_set_tc(s, esp_get_tc(s) - len); 768 esp_set_pdma_cb(s, DO_DMA_PDMA_CB); 769 esp_raise_drq(s); 770 } 771 } 772 } 773 774 static void esp_do_nodma(ESPState *s) 775 { 776 int to_device = ((s->rregs[ESP_RSTAT] & 7) == STAT_DO); 777 uint8_t buf[ESP_FIFO_SZ]; 778 uint32_t cmdlen; 779 int len, n; 780 781 if (s->do_cmd) { 782 /* Copy FIFO into cmdfifo */ 783 n = esp_fifo_pop_buf(&s->fifo, buf, fifo8_num_used(&s->fifo)); 784 n = MIN(fifo8_num_free(&s->cmdfifo), n); 785 fifo8_push_all(&s->cmdfifo, buf, n); 786 787 cmdlen = fifo8_num_used(&s->cmdfifo); 788 trace_esp_handle_ti_cmd(cmdlen); 789 s->ti_size = 0; 790 if ((s->rregs[ESP_RSTAT] & 7) == STAT_CD) { 791 /* No command received */ 792 if (s->cmdfifo_cdb_offset == fifo8_num_used(&s->cmdfifo)) { 793 return; 794 } 795 796 /* Command has been received */ 797 s->do_cmd = 0; 798 do_cmd(s); 799 } else { 800 /* 801 * Extra message out bytes received: update cmdfifo_cdb_offset 802 * and then switch to command phase 803 */ 804 s->cmdfifo_cdb_offset = fifo8_num_used(&s->cmdfifo); 805 esp_set_phase(s, STAT_CD); 806 s->rregs[ESP_RSEQ] = SEQ_CD; 807 s->rregs[ESP_RINTR] |= INTR_BS; 808 esp_raise_irq(s); 809 } 810 return; 811 } 812 813 if (!s->current_req) { 814 return; 815 } 816 817 if (s->async_len == 0) { 818 /* Defer until data is available. */ 819 return; 820 } 821 822 if (to_device) { 823 len = MIN(s->async_len, ESP_FIFO_SZ); 824 len = MIN(len, fifo8_num_used(&s->fifo)); 825 esp_fifo_pop_buf(&s->fifo, s->async_buf, len); 826 s->async_buf += len; 827 s->async_len -= len; 828 s->ti_size += len; 829 } else { 830 if (fifo8_is_empty(&s->fifo)) { 831 fifo8_push(&s->fifo, s->async_buf[0]); 832 s->async_buf++; 833 s->async_len--; 834 s->ti_size--; 835 } 836 } 837 838 if (s->async_len == 0) { 839 scsi_req_continue(s->current_req); 840 return; 841 } 842 843 s->rregs[ESP_RINTR] |= INTR_BS; 844 esp_raise_irq(s); 845 } 846 847 static void esp_pdma_cb(ESPState *s) 848 { 849 switch (s->pdma_cb) { 850 case SATN_PDMA_CB: 851 satn_pdma_cb(s); 852 break; 853 case S_WITHOUT_SATN_PDMA_CB: 854 s_without_satn_pdma_cb(s); 855 break; 856 case SATN_STOP_PDMA_CB: 857 satn_stop_pdma_cb(s); 858 break; 859 case WRITE_RESPONSE_PDMA_CB: 860 write_response_pdma_cb(s); 861 break; 862 case DO_DMA_PDMA_CB: 863 do_dma_pdma_cb(s); 864 break; 865 default: 866 g_assert_not_reached(); 867 } 868 } 869 870 void esp_command_complete(SCSIRequest *req, size_t resid) 871 { 872 ESPState *s = req->hba_private; 873 int to_device = ((s->rregs[ESP_RSTAT] & 7) == STAT_DO); 874 875 trace_esp_command_complete(); 876 877 /* 878 * Non-DMA transfers from the target will leave the last byte in 879 * the FIFO so don't reset ti_size in this case 880 */ 881 if (s->dma || to_device) { 882 if (s->ti_size != 0) { 883 trace_esp_command_complete_unexpected(); 884 } 885 s->ti_size = 0; 886 } 887 888 s->async_len = 0; 889 if (req->status) { 890 trace_esp_command_complete_fail(); 891 } 892 s->status = req->status; 893 894 /* 895 * If the transfer is finished, switch to status phase. For non-DMA 896 * transfers from the target the last byte is still in the FIFO 897 */ 898 if (s->ti_size == 0) { 899 esp_set_phase(s, STAT_ST); 900 esp_dma_done(s); 901 esp_lower_drq(s); 902 } 903 904 if (s->current_req) { 905 scsi_req_unref(s->current_req); 906 s->current_req = NULL; 907 s->current_dev = NULL; 908 } 909 } 910 911 void esp_transfer_data(SCSIRequest *req, uint32_t len) 912 { 913 ESPState *s = req->hba_private; 914 int to_device = ((s->rregs[ESP_RSTAT] & 7) == STAT_DO); 915 uint32_t dmalen = esp_get_tc(s); 916 917 assert(!s->do_cmd); 918 trace_esp_transfer_data(dmalen, s->ti_size); 919 s->async_len = len; 920 s->async_buf = scsi_req_get_buf(req); 921 922 if (!to_device && !s->data_in_ready) { 923 /* 924 * Initial incoming data xfer is complete so raise command 925 * completion interrupt 926 */ 927 s->data_in_ready = true; 928 s->rregs[ESP_RINTR] |= INTR_BS; 929 esp_raise_irq(s); 930 } 931 932 if (s->ti_cmd == 0) { 933 /* 934 * Always perform the initial transfer upon reception of the next TI 935 * command to ensure the DMA/non-DMA status of the command is correct. 936 * It is not possible to use s->dma directly in the section below as 937 * some OSs send non-DMA NOP commands after a DMA transfer. Hence if the 938 * async data transfer is delayed then s->dma is set incorrectly. 939 */ 940 return; 941 } 942 943 if (s->ti_cmd == (CMD_TI | CMD_DMA)) { 944 if (dmalen) { 945 esp_do_dma(s); 946 } else if (s->ti_size <= 0) { 947 /* 948 * If this was the last part of a DMA transfer then the 949 * completion interrupt is deferred to here. 950 */ 951 esp_dma_done(s); 952 esp_lower_drq(s); 953 } 954 } else if (s->ti_cmd == CMD_TI) { 955 esp_do_nodma(s); 956 } 957 } 958 959 static void handle_ti(ESPState *s) 960 { 961 uint32_t dmalen; 962 963 if (s->dma && !s->dma_enabled) { 964 s->dma_cb = handle_ti; 965 return; 966 } 967 968 s->ti_cmd = s->rregs[ESP_CMD]; 969 if (s->dma) { 970 dmalen = esp_get_tc(s); 971 trace_esp_handle_ti(dmalen); 972 esp_do_dma(s); 973 } else { 974 trace_esp_handle_ti(s->ti_size); 975 esp_do_nodma(s); 976 } 977 } 978 979 void esp_hard_reset(ESPState *s) 980 { 981 memset(s->rregs, 0, ESP_REGS); 982 memset(s->wregs, 0, ESP_REGS); 983 s->tchi_written = 0; 984 s->ti_size = 0; 985 s->async_len = 0; 986 fifo8_reset(&s->fifo); 987 fifo8_reset(&s->cmdfifo); 988 s->dma = 0; 989 s->do_cmd = 0; 990 s->dma_cb = NULL; 991 992 s->rregs[ESP_CFG1] = 7; 993 } 994 995 static void esp_soft_reset(ESPState *s) 996 { 997 qemu_irq_lower(s->irq); 998 qemu_irq_lower(s->irq_data); 999 esp_hard_reset(s); 1000 } 1001 1002 static void esp_bus_reset(ESPState *s) 1003 { 1004 bus_cold_reset(BUS(&s->bus)); 1005 } 1006 1007 static void parent_esp_reset(ESPState *s, int irq, int level) 1008 { 1009 if (level) { 1010 esp_soft_reset(s); 1011 } 1012 } 1013 1014 static void esp_run_cmd(ESPState *s) 1015 { 1016 uint8_t cmd = s->rregs[ESP_CMD]; 1017 1018 if (cmd & CMD_DMA) { 1019 s->dma = 1; 1020 /* Reload DMA counter. */ 1021 if (esp_get_stc(s) == 0) { 1022 esp_set_tc(s, 0x10000); 1023 } else { 1024 esp_set_tc(s, esp_get_stc(s)); 1025 } 1026 } else { 1027 s->dma = 0; 1028 } 1029 switch (cmd & CMD_CMD) { 1030 case CMD_NOP: 1031 trace_esp_mem_writeb_cmd_nop(cmd); 1032 break; 1033 case CMD_FLUSH: 1034 trace_esp_mem_writeb_cmd_flush(cmd); 1035 fifo8_reset(&s->fifo); 1036 break; 1037 case CMD_RESET: 1038 trace_esp_mem_writeb_cmd_reset(cmd); 1039 esp_soft_reset(s); 1040 break; 1041 case CMD_BUSRESET: 1042 trace_esp_mem_writeb_cmd_bus_reset(cmd); 1043 esp_bus_reset(s); 1044 if (!(s->wregs[ESP_CFG1] & CFG1_RESREPT)) { 1045 s->rregs[ESP_RINTR] |= INTR_RST; 1046 esp_raise_irq(s); 1047 } 1048 break; 1049 case CMD_TI: 1050 trace_esp_mem_writeb_cmd_ti(cmd); 1051 handle_ti(s); 1052 break; 1053 case CMD_ICCS: 1054 trace_esp_mem_writeb_cmd_iccs(cmd); 1055 write_response(s); 1056 s->rregs[ESP_RINTR] |= INTR_FC; 1057 esp_set_phase(s, STAT_MI); 1058 break; 1059 case CMD_MSGACC: 1060 trace_esp_mem_writeb_cmd_msgacc(cmd); 1061 s->rregs[ESP_RINTR] |= INTR_DC; 1062 s->rregs[ESP_RSEQ] = 0; 1063 s->rregs[ESP_RFLAGS] = 0; 1064 esp_raise_irq(s); 1065 break; 1066 case CMD_PAD: 1067 trace_esp_mem_writeb_cmd_pad(cmd); 1068 s->rregs[ESP_RSTAT] = STAT_TC; 1069 s->rregs[ESP_RINTR] |= INTR_FC; 1070 s->rregs[ESP_RSEQ] = 0; 1071 break; 1072 case CMD_SATN: 1073 trace_esp_mem_writeb_cmd_satn(cmd); 1074 break; 1075 case CMD_RSTATN: 1076 trace_esp_mem_writeb_cmd_rstatn(cmd); 1077 break; 1078 case CMD_SEL: 1079 trace_esp_mem_writeb_cmd_sel(cmd); 1080 handle_s_without_atn(s); 1081 break; 1082 case CMD_SELATN: 1083 trace_esp_mem_writeb_cmd_selatn(cmd); 1084 handle_satn(s); 1085 break; 1086 case CMD_SELATNS: 1087 trace_esp_mem_writeb_cmd_selatns(cmd); 1088 handle_satn_stop(s); 1089 break; 1090 case CMD_ENSEL: 1091 trace_esp_mem_writeb_cmd_ensel(cmd); 1092 s->rregs[ESP_RINTR] = 0; 1093 break; 1094 case CMD_DISSEL: 1095 trace_esp_mem_writeb_cmd_dissel(cmd); 1096 s->rregs[ESP_RINTR] = 0; 1097 esp_raise_irq(s); 1098 break; 1099 default: 1100 trace_esp_error_unhandled_command(cmd); 1101 break; 1102 } 1103 } 1104 1105 uint64_t esp_reg_read(ESPState *s, uint32_t saddr) 1106 { 1107 uint32_t val; 1108 1109 switch (saddr) { 1110 case ESP_FIFO: 1111 if (s->dma_memory_read && s->dma_memory_write && 1112 (s->rregs[ESP_RSTAT] & STAT_PIO_MASK) == 0) { 1113 /* Data out. */ 1114 qemu_log_mask(LOG_UNIMP, "esp: PIO data read not implemented\n"); 1115 s->rregs[ESP_FIFO] = 0; 1116 } else { 1117 if ((s->rregs[ESP_RSTAT] & 0x7) == STAT_DI) { 1118 if (s->ti_size) { 1119 esp_do_nodma(s); 1120 } else { 1121 /* 1122 * The last byte of a non-DMA transfer has been read out 1123 * of the FIFO so switch to status phase 1124 */ 1125 esp_set_phase(s, STAT_ST); 1126 } 1127 } 1128 s->rregs[ESP_FIFO] = esp_fifo_pop(&s->fifo); 1129 } 1130 val = s->rregs[ESP_FIFO]; 1131 break; 1132 case ESP_RINTR: 1133 /* 1134 * Clear sequence step, interrupt register and all status bits 1135 * except TC 1136 */ 1137 val = s->rregs[ESP_RINTR]; 1138 s->rregs[ESP_RINTR] = 0; 1139 s->rregs[ESP_RSTAT] &= ~STAT_TC; 1140 /* 1141 * According to the datasheet ESP_RSEQ should be cleared, but as the 1142 * emulation currently defers information transfers to the next TI 1143 * command leave it for now so that pedantic guests such as the old 1144 * Linux 2.6 driver see the correct flags before the next SCSI phase 1145 * transition. 1146 * 1147 * s->rregs[ESP_RSEQ] = SEQ_0; 1148 */ 1149 esp_lower_irq(s); 1150 break; 1151 case ESP_TCHI: 1152 /* Return the unique id if the value has never been written */ 1153 if (!s->tchi_written) { 1154 val = s->chip_id; 1155 } else { 1156 val = s->rregs[saddr]; 1157 } 1158 break; 1159 case ESP_RFLAGS: 1160 /* Bottom 5 bits indicate number of bytes in FIFO */ 1161 val = fifo8_num_used(&s->fifo); 1162 break; 1163 default: 1164 val = s->rregs[saddr]; 1165 break; 1166 } 1167 1168 trace_esp_mem_readb(saddr, val); 1169 return val; 1170 } 1171 1172 void esp_reg_write(ESPState *s, uint32_t saddr, uint64_t val) 1173 { 1174 trace_esp_mem_writeb(saddr, s->wregs[saddr], val); 1175 switch (saddr) { 1176 case ESP_TCHI: 1177 s->tchi_written = true; 1178 /* fall through */ 1179 case ESP_TCLO: 1180 case ESP_TCMID: 1181 s->rregs[ESP_RSTAT] &= ~STAT_TC; 1182 break; 1183 case ESP_FIFO: 1184 if (s->do_cmd) { 1185 if (!fifo8_is_full(&s->fifo)) { 1186 esp_fifo_push(&s->fifo, val); 1187 esp_fifo_push(&s->cmdfifo, fifo8_pop(&s->fifo)); 1188 } 1189 1190 /* 1191 * If any unexpected message out/command phase data is 1192 * transferred using non-DMA, raise the interrupt 1193 */ 1194 if (s->rregs[ESP_CMD] == CMD_TI) { 1195 s->rregs[ESP_RINTR] |= INTR_BS; 1196 esp_raise_irq(s); 1197 } 1198 } else { 1199 esp_fifo_push(&s->fifo, val); 1200 } 1201 break; 1202 case ESP_CMD: 1203 s->rregs[saddr] = val; 1204 esp_run_cmd(s); 1205 break; 1206 case ESP_WBUSID ... ESP_WSYNO: 1207 break; 1208 case ESP_CFG1: 1209 case ESP_CFG2: case ESP_CFG3: 1210 case ESP_RES3: case ESP_RES4: 1211 s->rregs[saddr] = val; 1212 break; 1213 case ESP_WCCF ... ESP_WTEST: 1214 break; 1215 default: 1216 trace_esp_error_invalid_write(val, saddr); 1217 return; 1218 } 1219 s->wregs[saddr] = val; 1220 } 1221 1222 static bool esp_mem_accepts(void *opaque, hwaddr addr, 1223 unsigned size, bool is_write, 1224 MemTxAttrs attrs) 1225 { 1226 return (size == 1) || (is_write && size == 4); 1227 } 1228 1229 static bool esp_is_before_version_5(void *opaque, int version_id) 1230 { 1231 ESPState *s = ESP(opaque); 1232 1233 version_id = MIN(version_id, s->mig_version_id); 1234 return version_id < 5; 1235 } 1236 1237 static bool esp_is_version_5(void *opaque, int version_id) 1238 { 1239 ESPState *s = ESP(opaque); 1240 1241 version_id = MIN(version_id, s->mig_version_id); 1242 return version_id >= 5; 1243 } 1244 1245 static bool esp_is_version_6(void *opaque, int version_id) 1246 { 1247 ESPState *s = ESP(opaque); 1248 1249 version_id = MIN(version_id, s->mig_version_id); 1250 return version_id >= 6; 1251 } 1252 1253 int esp_pre_save(void *opaque) 1254 { 1255 ESPState *s = ESP(object_resolve_path_component( 1256 OBJECT(opaque), "esp")); 1257 1258 s->mig_version_id = vmstate_esp.version_id; 1259 return 0; 1260 } 1261 1262 static int esp_post_load(void *opaque, int version_id) 1263 { 1264 ESPState *s = ESP(opaque); 1265 int len, i; 1266 1267 version_id = MIN(version_id, s->mig_version_id); 1268 1269 if (version_id < 5) { 1270 esp_set_tc(s, s->mig_dma_left); 1271 1272 /* Migrate ti_buf to fifo */ 1273 len = s->mig_ti_wptr - s->mig_ti_rptr; 1274 for (i = 0; i < len; i++) { 1275 fifo8_push(&s->fifo, s->mig_ti_buf[i]); 1276 } 1277 1278 /* Migrate cmdbuf to cmdfifo */ 1279 for (i = 0; i < s->mig_cmdlen; i++) { 1280 fifo8_push(&s->cmdfifo, s->mig_cmdbuf[i]); 1281 } 1282 } 1283 1284 s->mig_version_id = vmstate_esp.version_id; 1285 return 0; 1286 } 1287 1288 /* 1289 * PDMA (or pseudo-DMA) is only used on the Macintosh and requires the 1290 * guest CPU to perform the transfers between the SCSI bus and memory 1291 * itself. This is indicated by the dma_memory_read and dma_memory_write 1292 * functions being NULL (in contrast to the ESP PCI device) whilst 1293 * dma_enabled is still set. 1294 */ 1295 1296 static bool esp_pdma_needed(void *opaque) 1297 { 1298 ESPState *s = ESP(opaque); 1299 1300 return s->dma_memory_read == NULL && s->dma_memory_write == NULL && 1301 s->dma_enabled; 1302 } 1303 1304 static const VMStateDescription vmstate_esp_pdma = { 1305 .name = "esp/pdma", 1306 .version_id = 0, 1307 .minimum_version_id = 0, 1308 .needed = esp_pdma_needed, 1309 .fields = (const VMStateField[]) { 1310 VMSTATE_UINT8(pdma_cb, ESPState), 1311 VMSTATE_END_OF_LIST() 1312 } 1313 }; 1314 1315 const VMStateDescription vmstate_esp = { 1316 .name = "esp", 1317 .version_id = 6, 1318 .minimum_version_id = 3, 1319 .post_load = esp_post_load, 1320 .fields = (const VMStateField[]) { 1321 VMSTATE_BUFFER(rregs, ESPState), 1322 VMSTATE_BUFFER(wregs, ESPState), 1323 VMSTATE_INT32(ti_size, ESPState), 1324 VMSTATE_UINT32_TEST(mig_ti_rptr, ESPState, esp_is_before_version_5), 1325 VMSTATE_UINT32_TEST(mig_ti_wptr, ESPState, esp_is_before_version_5), 1326 VMSTATE_BUFFER_TEST(mig_ti_buf, ESPState, esp_is_before_version_5), 1327 VMSTATE_UINT32(status, ESPState), 1328 VMSTATE_UINT32_TEST(mig_deferred_status, ESPState, 1329 esp_is_before_version_5), 1330 VMSTATE_BOOL_TEST(mig_deferred_complete, ESPState, 1331 esp_is_before_version_5), 1332 VMSTATE_UINT32(dma, ESPState), 1333 VMSTATE_STATIC_BUFFER(mig_cmdbuf, ESPState, 0, 1334 esp_is_before_version_5, 0, 16), 1335 VMSTATE_STATIC_BUFFER(mig_cmdbuf, ESPState, 4, 1336 esp_is_before_version_5, 16, 1337 sizeof(typeof_field(ESPState, mig_cmdbuf))), 1338 VMSTATE_UINT32_TEST(mig_cmdlen, ESPState, esp_is_before_version_5), 1339 VMSTATE_UINT32(do_cmd, ESPState), 1340 VMSTATE_UINT32_TEST(mig_dma_left, ESPState, esp_is_before_version_5), 1341 VMSTATE_BOOL_TEST(data_in_ready, ESPState, esp_is_version_5), 1342 VMSTATE_UINT8_TEST(cmdfifo_cdb_offset, ESPState, esp_is_version_5), 1343 VMSTATE_FIFO8_TEST(fifo, ESPState, esp_is_version_5), 1344 VMSTATE_FIFO8_TEST(cmdfifo, ESPState, esp_is_version_5), 1345 VMSTATE_UINT8_TEST(ti_cmd, ESPState, esp_is_version_5), 1346 VMSTATE_UINT8_TEST(lun, ESPState, esp_is_version_6), 1347 VMSTATE_END_OF_LIST() 1348 }, 1349 .subsections = (const VMStateDescription * const []) { 1350 &vmstate_esp_pdma, 1351 NULL 1352 } 1353 }; 1354 1355 static void sysbus_esp_mem_write(void *opaque, hwaddr addr, 1356 uint64_t val, unsigned int size) 1357 { 1358 SysBusESPState *sysbus = opaque; 1359 ESPState *s = ESP(&sysbus->esp); 1360 uint32_t saddr; 1361 1362 saddr = addr >> sysbus->it_shift; 1363 esp_reg_write(s, saddr, val); 1364 } 1365 1366 static uint64_t sysbus_esp_mem_read(void *opaque, hwaddr addr, 1367 unsigned int size) 1368 { 1369 SysBusESPState *sysbus = opaque; 1370 ESPState *s = ESP(&sysbus->esp); 1371 uint32_t saddr; 1372 1373 saddr = addr >> sysbus->it_shift; 1374 return esp_reg_read(s, saddr); 1375 } 1376 1377 static const MemoryRegionOps sysbus_esp_mem_ops = { 1378 .read = sysbus_esp_mem_read, 1379 .write = sysbus_esp_mem_write, 1380 .endianness = DEVICE_NATIVE_ENDIAN, 1381 .valid.accepts = esp_mem_accepts, 1382 }; 1383 1384 static void sysbus_esp_pdma_write(void *opaque, hwaddr addr, 1385 uint64_t val, unsigned int size) 1386 { 1387 SysBusESPState *sysbus = opaque; 1388 ESPState *s = ESP(&sysbus->esp); 1389 1390 trace_esp_pdma_write(size); 1391 1392 switch (size) { 1393 case 1: 1394 esp_pdma_write(s, val); 1395 break; 1396 case 2: 1397 esp_pdma_write(s, val >> 8); 1398 esp_pdma_write(s, val); 1399 break; 1400 } 1401 esp_pdma_cb(s); 1402 } 1403 1404 static uint64_t sysbus_esp_pdma_read(void *opaque, hwaddr addr, 1405 unsigned int size) 1406 { 1407 SysBusESPState *sysbus = opaque; 1408 ESPState *s = ESP(&sysbus->esp); 1409 uint64_t val = 0; 1410 1411 trace_esp_pdma_read(size); 1412 1413 switch (size) { 1414 case 1: 1415 val = esp_pdma_read(s); 1416 break; 1417 case 2: 1418 val = esp_pdma_read(s); 1419 val = (val << 8) | esp_pdma_read(s); 1420 break; 1421 } 1422 if (fifo8_num_used(&s->fifo) < 2) { 1423 esp_pdma_cb(s); 1424 } 1425 return val; 1426 } 1427 1428 static void *esp_load_request(QEMUFile *f, SCSIRequest *req) 1429 { 1430 ESPState *s = container_of(req->bus, ESPState, bus); 1431 1432 scsi_req_ref(req); 1433 s->current_req = req; 1434 return s; 1435 } 1436 1437 static const MemoryRegionOps sysbus_esp_pdma_ops = { 1438 .read = sysbus_esp_pdma_read, 1439 .write = sysbus_esp_pdma_write, 1440 .endianness = DEVICE_NATIVE_ENDIAN, 1441 .valid.min_access_size = 1, 1442 .valid.max_access_size = 4, 1443 .impl.min_access_size = 1, 1444 .impl.max_access_size = 2, 1445 }; 1446 1447 static const struct SCSIBusInfo esp_scsi_info = { 1448 .tcq = false, 1449 .max_target = ESP_MAX_DEVS, 1450 .max_lun = 7, 1451 1452 .load_request = esp_load_request, 1453 .transfer_data = esp_transfer_data, 1454 .complete = esp_command_complete, 1455 .cancel = esp_request_cancelled 1456 }; 1457 1458 static void sysbus_esp_gpio_demux(void *opaque, int irq, int level) 1459 { 1460 SysBusESPState *sysbus = SYSBUS_ESP(opaque); 1461 ESPState *s = ESP(&sysbus->esp); 1462 1463 switch (irq) { 1464 case 0: 1465 parent_esp_reset(s, irq, level); 1466 break; 1467 case 1: 1468 esp_dma_enable(s, irq, level); 1469 break; 1470 } 1471 } 1472 1473 static void sysbus_esp_realize(DeviceState *dev, Error **errp) 1474 { 1475 SysBusDevice *sbd = SYS_BUS_DEVICE(dev); 1476 SysBusESPState *sysbus = SYSBUS_ESP(dev); 1477 ESPState *s = ESP(&sysbus->esp); 1478 1479 if (!qdev_realize(DEVICE(s), NULL, errp)) { 1480 return; 1481 } 1482 1483 sysbus_init_irq(sbd, &s->irq); 1484 sysbus_init_irq(sbd, &s->irq_data); 1485 assert(sysbus->it_shift != -1); 1486 1487 s->chip_id = TCHI_FAS100A; 1488 memory_region_init_io(&sysbus->iomem, OBJECT(sysbus), &sysbus_esp_mem_ops, 1489 sysbus, "esp-regs", ESP_REGS << sysbus->it_shift); 1490 sysbus_init_mmio(sbd, &sysbus->iomem); 1491 memory_region_init_io(&sysbus->pdma, OBJECT(sysbus), &sysbus_esp_pdma_ops, 1492 sysbus, "esp-pdma", 4); 1493 sysbus_init_mmio(sbd, &sysbus->pdma); 1494 1495 qdev_init_gpio_in(dev, sysbus_esp_gpio_demux, 2); 1496 1497 scsi_bus_init(&s->bus, sizeof(s->bus), dev, &esp_scsi_info); 1498 } 1499 1500 static void sysbus_esp_hard_reset(DeviceState *dev) 1501 { 1502 SysBusESPState *sysbus = SYSBUS_ESP(dev); 1503 ESPState *s = ESP(&sysbus->esp); 1504 1505 esp_hard_reset(s); 1506 } 1507 1508 static void sysbus_esp_init(Object *obj) 1509 { 1510 SysBusESPState *sysbus = SYSBUS_ESP(obj); 1511 1512 object_initialize_child(obj, "esp", &sysbus->esp, TYPE_ESP); 1513 } 1514 1515 static const VMStateDescription vmstate_sysbus_esp_scsi = { 1516 .name = "sysbusespscsi", 1517 .version_id = 2, 1518 .minimum_version_id = 1, 1519 .pre_save = esp_pre_save, 1520 .fields = (const VMStateField[]) { 1521 VMSTATE_UINT8_V(esp.mig_version_id, SysBusESPState, 2), 1522 VMSTATE_STRUCT(esp, SysBusESPState, 0, vmstate_esp, ESPState), 1523 VMSTATE_END_OF_LIST() 1524 } 1525 }; 1526 1527 static void sysbus_esp_class_init(ObjectClass *klass, void *data) 1528 { 1529 DeviceClass *dc = DEVICE_CLASS(klass); 1530 1531 dc->realize = sysbus_esp_realize; 1532 dc->reset = sysbus_esp_hard_reset; 1533 dc->vmsd = &vmstate_sysbus_esp_scsi; 1534 set_bit(DEVICE_CATEGORY_STORAGE, dc->categories); 1535 } 1536 1537 static const TypeInfo sysbus_esp_info = { 1538 .name = TYPE_SYSBUS_ESP, 1539 .parent = TYPE_SYS_BUS_DEVICE, 1540 .instance_init = sysbus_esp_init, 1541 .instance_size = sizeof(SysBusESPState), 1542 .class_init = sysbus_esp_class_init, 1543 }; 1544 1545 static void esp_finalize(Object *obj) 1546 { 1547 ESPState *s = ESP(obj); 1548 1549 fifo8_destroy(&s->fifo); 1550 fifo8_destroy(&s->cmdfifo); 1551 } 1552 1553 static void esp_init(Object *obj) 1554 { 1555 ESPState *s = ESP(obj); 1556 1557 fifo8_create(&s->fifo, ESP_FIFO_SZ); 1558 fifo8_create(&s->cmdfifo, ESP_CMDFIFO_SZ); 1559 } 1560 1561 static void esp_class_init(ObjectClass *klass, void *data) 1562 { 1563 DeviceClass *dc = DEVICE_CLASS(klass); 1564 1565 /* internal device for sysbusesp/pciespscsi, not user-creatable */ 1566 dc->user_creatable = false; 1567 set_bit(DEVICE_CATEGORY_STORAGE, dc->categories); 1568 } 1569 1570 static const TypeInfo esp_info = { 1571 .name = TYPE_ESP, 1572 .parent = TYPE_DEVICE, 1573 .instance_init = esp_init, 1574 .instance_finalize = esp_finalize, 1575 .instance_size = sizeof(ESPState), 1576 .class_init = esp_class_init, 1577 }; 1578 1579 static void esp_register_types(void) 1580 { 1581 type_register_static(&sysbus_esp_info); 1582 type_register_static(&esp_info); 1583 } 1584 1585 type_init(esp_register_types) 1586