1 /* 2 * QEMU ESP/NCR53C9x emulation 3 * 4 * Copyright (c) 2005-2006 Fabrice Bellard 5 * Copyright (c) 2012 Herve Poussineau 6 * 7 * Permission is hereby granted, free of charge, to any person obtaining a copy 8 * of this software and associated documentation files (the "Software"), to deal 9 * in the Software without restriction, including without limitation the rights 10 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 11 * copies of the Software, and to permit persons to whom the Software is 12 * furnished to do so, subject to the following conditions: 13 * 14 * The above copyright notice and this permission notice shall be included in 15 * all copies or substantial portions of the Software. 16 * 17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 22 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 23 * THE SOFTWARE. 24 */ 25 26 #include "qemu/osdep.h" 27 #include "hw/sysbus.h" 28 #include "migration/vmstate.h" 29 #include "hw/irq.h" 30 #include "hw/scsi/esp.h" 31 #include "trace.h" 32 #include "qemu/log.h" 33 #include "qemu/module.h" 34 35 /* 36 * On Sparc32, this is the ESP (NCR53C90) part of chip STP2000 (Master I/O), 37 * also produced as NCR89C100. See 38 * http://www.ibiblio.org/pub/historic-linux/early-ports/Sparc/NCR/NCR89C100.txt 39 * and 40 * http://www.ibiblio.org/pub/historic-linux/early-ports/Sparc/NCR/NCR53C9X.txt 41 * 42 * On Macintosh Quadra it is a NCR53C96. 43 */ 44 45 static void esp_raise_irq(ESPState *s) 46 { 47 if (!(s->rregs[ESP_RSTAT] & STAT_INT)) { 48 s->rregs[ESP_RSTAT] |= STAT_INT; 49 qemu_irq_raise(s->irq); 50 trace_esp_raise_irq(); 51 } 52 } 53 54 static void esp_lower_irq(ESPState *s) 55 { 56 if (s->rregs[ESP_RSTAT] & STAT_INT) { 57 s->rregs[ESP_RSTAT] &= ~STAT_INT; 58 qemu_irq_lower(s->irq); 59 trace_esp_lower_irq(); 60 } 61 } 62 63 static void esp_raise_drq(ESPState *s) 64 { 65 qemu_irq_raise(s->irq_data); 66 trace_esp_raise_drq(); 67 } 68 69 static void esp_lower_drq(ESPState *s) 70 { 71 qemu_irq_lower(s->irq_data); 72 trace_esp_lower_drq(); 73 } 74 75 void esp_dma_enable(ESPState *s, int irq, int level) 76 { 77 if (level) { 78 s->dma_enabled = 1; 79 trace_esp_dma_enable(); 80 if (s->dma_cb) { 81 s->dma_cb(s); 82 s->dma_cb = NULL; 83 } 84 } else { 85 trace_esp_dma_disable(); 86 s->dma_enabled = 0; 87 } 88 } 89 90 void esp_request_cancelled(SCSIRequest *req) 91 { 92 ESPState *s = req->hba_private; 93 94 if (req == s->current_req) { 95 scsi_req_unref(s->current_req); 96 s->current_req = NULL; 97 s->current_dev = NULL; 98 } 99 } 100 101 static uint32_t esp_get_tc(ESPState *s) 102 { 103 uint32_t dmalen; 104 105 dmalen = s->rregs[ESP_TCLO]; 106 dmalen |= s->rregs[ESP_TCMID] << 8; 107 dmalen |= s->rregs[ESP_TCHI] << 16; 108 109 return dmalen; 110 } 111 112 static void esp_set_tc(ESPState *s, uint32_t dmalen) 113 { 114 s->rregs[ESP_TCLO] = dmalen; 115 s->rregs[ESP_TCMID] = dmalen >> 8; 116 s->rregs[ESP_TCHI] = dmalen >> 16; 117 } 118 119 static uint32_t esp_get_stc(ESPState *s) 120 { 121 uint32_t dmalen; 122 123 dmalen = s->wregs[ESP_TCLO]; 124 dmalen |= s->wregs[ESP_TCMID] << 8; 125 dmalen |= s->wregs[ESP_TCHI] << 16; 126 127 return dmalen; 128 } 129 130 static void set_pdma(ESPState *s, enum pdma_origin_id origin, 131 uint32_t index, uint32_t len) 132 { 133 s->pdma_origin = origin; 134 s->pdma_start = index; 135 s->pdma_cur = index; 136 s->pdma_len = len; 137 } 138 139 static uint8_t *get_pdma_buf(ESPState *s) 140 { 141 switch (s->pdma_origin) { 142 case PDMA: 143 return s->pdma_buf; 144 case TI: 145 return s->ti_buf; 146 case CMD: 147 return s->cmdbuf; 148 case ASYNC: 149 return s->async_buf; 150 } 151 return NULL; 152 } 153 154 static int get_cmd_cb(ESPState *s) 155 { 156 int target; 157 158 target = s->wregs[ESP_WBUSID] & BUSID_DID; 159 160 s->ti_size = 0; 161 s->ti_rptr = 0; 162 s->ti_wptr = 0; 163 164 if (s->current_req) { 165 /* Started a new command before the old one finished. Cancel it. */ 166 scsi_req_cancel(s->current_req); 167 s->async_len = 0; 168 } 169 170 s->current_dev = scsi_device_find(&s->bus, 0, target, 0); 171 if (!s->current_dev) { 172 /* No such drive */ 173 s->rregs[ESP_RSTAT] = 0; 174 s->rregs[ESP_RINTR] = INTR_DC; 175 s->rregs[ESP_RSEQ] = SEQ_0; 176 esp_raise_irq(s); 177 return -1; 178 } 179 return 0; 180 } 181 182 static uint32_t get_cmd(ESPState *s, uint8_t *buf, uint8_t buflen) 183 { 184 uint32_t dmalen; 185 int target; 186 187 target = s->wregs[ESP_WBUSID] & BUSID_DID; 188 if (s->dma) { 189 dmalen = esp_get_tc(s); 190 if (dmalen > buflen) { 191 return 0; 192 } 193 if (s->dma_memory_read) { 194 s->dma_memory_read(s->dma_opaque, buf, dmalen); 195 } else { 196 memcpy(s->pdma_buf, buf, dmalen); 197 set_pdma(s, PDMA, 0, dmalen); 198 esp_raise_drq(s); 199 return 0; 200 } 201 } else { 202 dmalen = s->ti_size; 203 if (dmalen > TI_BUFSZ) { 204 return 0; 205 } 206 memcpy(buf, s->ti_buf, dmalen); 207 buf[0] = buf[2] >> 5; 208 } 209 trace_esp_get_cmd(dmalen, target); 210 211 if (get_cmd_cb(s) < 0) { 212 return 0; 213 } 214 return dmalen; 215 } 216 217 static void do_busid_cmd(ESPState *s, uint8_t *buf, uint8_t busid) 218 { 219 int32_t datalen; 220 int lun; 221 SCSIDevice *current_lun; 222 223 trace_esp_do_busid_cmd(busid); 224 lun = busid & 7; 225 current_lun = scsi_device_find(&s->bus, 0, s->current_dev->id, lun); 226 s->current_req = scsi_req_new(current_lun, 0, lun, buf, s); 227 datalen = scsi_req_enqueue(s->current_req); 228 s->ti_size = datalen; 229 if (datalen != 0) { 230 s->rregs[ESP_RSTAT] = STAT_TC; 231 s->dma_left = 0; 232 s->dma_counter = 0; 233 if (datalen > 0) { 234 s->rregs[ESP_RSTAT] |= STAT_DI; 235 } else { 236 s->rregs[ESP_RSTAT] |= STAT_DO; 237 } 238 scsi_req_continue(s->current_req); 239 } 240 s->rregs[ESP_RINTR] = INTR_BS | INTR_FC; 241 s->rregs[ESP_RSEQ] = SEQ_CD; 242 esp_raise_irq(s); 243 } 244 245 static void do_cmd(ESPState *s, uint8_t *buf) 246 { 247 uint8_t busid = buf[0]; 248 249 do_busid_cmd(s, &buf[1], busid); 250 } 251 252 static void satn_pdma_cb(ESPState *s) 253 { 254 if (get_cmd_cb(s) < 0) { 255 return; 256 } 257 if (s->pdma_cur != s->pdma_start) { 258 do_cmd(s, get_pdma_buf(s) + s->pdma_start); 259 } 260 } 261 262 static void handle_satn(ESPState *s) 263 { 264 uint8_t buf[32]; 265 int len; 266 267 if (s->dma && !s->dma_enabled) { 268 s->dma_cb = handle_satn; 269 return; 270 } 271 s->pdma_cb = satn_pdma_cb; 272 len = get_cmd(s, buf, sizeof(buf)); 273 if (len) { 274 do_cmd(s, buf); 275 } 276 } 277 278 static void s_without_satn_pdma_cb(ESPState *s) 279 { 280 if (get_cmd_cb(s) < 0) { 281 return; 282 } 283 if (s->pdma_cur != s->pdma_start) { 284 do_busid_cmd(s, get_pdma_buf(s) + s->pdma_start, 0); 285 } 286 } 287 288 static void handle_s_without_atn(ESPState *s) 289 { 290 uint8_t buf[32]; 291 int len; 292 293 if (s->dma && !s->dma_enabled) { 294 s->dma_cb = handle_s_without_atn; 295 return; 296 } 297 s->pdma_cb = s_without_satn_pdma_cb; 298 len = get_cmd(s, buf, sizeof(buf)); 299 if (len) { 300 do_busid_cmd(s, buf, 0); 301 } 302 } 303 304 static void satn_stop_pdma_cb(ESPState *s) 305 { 306 if (get_cmd_cb(s) < 0) { 307 return; 308 } 309 s->cmdlen = s->pdma_cur - s->pdma_start; 310 if (s->cmdlen) { 311 trace_esp_handle_satn_stop(s->cmdlen); 312 s->do_cmd = 1; 313 s->rregs[ESP_RSTAT] = STAT_TC | STAT_CD; 314 s->rregs[ESP_RINTR] = INTR_BS | INTR_FC; 315 s->rregs[ESP_RSEQ] = SEQ_CD; 316 esp_raise_irq(s); 317 } 318 } 319 320 static void handle_satn_stop(ESPState *s) 321 { 322 if (s->dma && !s->dma_enabled) { 323 s->dma_cb = handle_satn_stop; 324 return; 325 } 326 s->pdma_cb = satn_stop_pdma_cb; 327 s->cmdlen = get_cmd(s, s->cmdbuf, sizeof(s->cmdbuf)); 328 if (s->cmdlen) { 329 trace_esp_handle_satn_stop(s->cmdlen); 330 s->do_cmd = 1; 331 s->rregs[ESP_RSTAT] = STAT_TC | STAT_CD; 332 s->rregs[ESP_RINTR] = INTR_BS | INTR_FC; 333 s->rregs[ESP_RSEQ] = SEQ_CD; 334 esp_raise_irq(s); 335 } 336 } 337 338 static void write_response_pdma_cb(ESPState *s) 339 { 340 s->rregs[ESP_RSTAT] = STAT_TC | STAT_ST; 341 s->rregs[ESP_RINTR] = INTR_BS | INTR_FC; 342 s->rregs[ESP_RSEQ] = SEQ_CD; 343 esp_raise_irq(s); 344 } 345 346 static void write_response(ESPState *s) 347 { 348 trace_esp_write_response(s->status); 349 s->ti_buf[0] = s->status; 350 s->ti_buf[1] = 0; 351 if (s->dma) { 352 if (s->dma_memory_write) { 353 s->dma_memory_write(s->dma_opaque, s->ti_buf, 2); 354 s->rregs[ESP_RSTAT] = STAT_TC | STAT_ST; 355 s->rregs[ESP_RINTR] = INTR_BS | INTR_FC; 356 s->rregs[ESP_RSEQ] = SEQ_CD; 357 } else { 358 set_pdma(s, TI, 0, 2); 359 s->pdma_cb = write_response_pdma_cb; 360 esp_raise_drq(s); 361 return; 362 } 363 } else { 364 s->ti_size = 2; 365 s->ti_rptr = 0; 366 s->ti_wptr = 2; 367 s->rregs[ESP_RFLAGS] = 2; 368 } 369 esp_raise_irq(s); 370 } 371 372 static void esp_dma_done(ESPState *s) 373 { 374 s->rregs[ESP_RSTAT] |= STAT_TC; 375 s->rregs[ESP_RINTR] = INTR_BS; 376 s->rregs[ESP_RSEQ] = 0; 377 s->rregs[ESP_RFLAGS] = 0; 378 esp_set_tc(s, 0); 379 esp_raise_irq(s); 380 } 381 382 static void do_dma_pdma_cb(ESPState *s) 383 { 384 int to_device = ((s->rregs[ESP_RSTAT] & 7) == STAT_DO); 385 int len = s->pdma_cur - s->pdma_start; 386 if (s->do_cmd) { 387 s->ti_size = 0; 388 s->cmdlen = 0; 389 s->do_cmd = 0; 390 do_cmd(s, s->cmdbuf); 391 return; 392 } 393 s->dma_left -= len; 394 s->async_buf += len; 395 s->async_len -= len; 396 if (to_device) { 397 s->ti_size += len; 398 } else { 399 s->ti_size -= len; 400 } 401 if (s->async_len == 0) { 402 scsi_req_continue(s->current_req); 403 /* 404 * If there is still data to be read from the device then 405 * complete the DMA operation immediately. Otherwise defer 406 * until the scsi layer has completed. 407 */ 408 if (to_device || s->dma_left != 0 || s->ti_size == 0) { 409 return; 410 } 411 } 412 413 /* Partially filled a scsi buffer. Complete immediately. */ 414 esp_dma_done(s); 415 } 416 417 static void esp_do_dma(ESPState *s) 418 { 419 uint32_t len; 420 int to_device = ((s->rregs[ESP_RSTAT] & 7) == STAT_DO); 421 422 len = s->dma_left; 423 if (s->do_cmd) { 424 /* 425 * handle_ti_cmd() case: esp_do_dma() is called only from 426 * handle_ti_cmd() with do_cmd != NULL (see the assert()) 427 */ 428 trace_esp_do_dma(s->cmdlen, len); 429 assert(s->cmdlen <= sizeof(s->cmdbuf) && 430 len <= sizeof(s->cmdbuf) - s->cmdlen); 431 if (s->dma_memory_read) { 432 s->dma_memory_read(s->dma_opaque, &s->cmdbuf[s->cmdlen], len); 433 } else { 434 set_pdma(s, CMD, s->cmdlen, len); 435 s->pdma_cb = do_dma_pdma_cb; 436 esp_raise_drq(s); 437 return; 438 } 439 trace_esp_handle_ti_cmd(s->cmdlen); 440 s->ti_size = 0; 441 s->cmdlen = 0; 442 s->do_cmd = 0; 443 do_cmd(s, s->cmdbuf); 444 return; 445 } 446 if (s->async_len == 0) { 447 /* Defer until data is available. */ 448 return; 449 } 450 if (len > s->async_len) { 451 len = s->async_len; 452 } 453 if (to_device) { 454 if (s->dma_memory_read) { 455 s->dma_memory_read(s->dma_opaque, s->async_buf, len); 456 } else { 457 set_pdma(s, ASYNC, 0, len); 458 s->pdma_cb = do_dma_pdma_cb; 459 esp_raise_drq(s); 460 return; 461 } 462 } else { 463 if (s->dma_memory_write) { 464 s->dma_memory_write(s->dma_opaque, s->async_buf, len); 465 } else { 466 set_pdma(s, ASYNC, 0, len); 467 s->pdma_cb = do_dma_pdma_cb; 468 esp_raise_drq(s); 469 return; 470 } 471 } 472 s->dma_left -= len; 473 s->async_buf += len; 474 s->async_len -= len; 475 if (to_device) { 476 s->ti_size += len; 477 } else { 478 s->ti_size -= len; 479 } 480 if (s->async_len == 0) { 481 scsi_req_continue(s->current_req); 482 /* 483 * If there is still data to be read from the device then 484 * complete the DMA operation immediately. Otherwise defer 485 * until the scsi layer has completed. 486 */ 487 if (to_device || s->dma_left != 0 || s->ti_size == 0) { 488 return; 489 } 490 } 491 492 /* Partially filled a scsi buffer. Complete immediately. */ 493 esp_dma_done(s); 494 } 495 496 static void esp_report_command_complete(ESPState *s, uint32_t status) 497 { 498 trace_esp_command_complete(); 499 if (s->ti_size != 0) { 500 trace_esp_command_complete_unexpected(); 501 } 502 s->ti_size = 0; 503 s->dma_left = 0; 504 s->async_len = 0; 505 if (status) { 506 trace_esp_command_complete_fail(); 507 } 508 s->status = status; 509 s->rregs[ESP_RSTAT] = STAT_ST; 510 esp_dma_done(s); 511 if (s->current_req) { 512 scsi_req_unref(s->current_req); 513 s->current_req = NULL; 514 s->current_dev = NULL; 515 } 516 } 517 518 void esp_command_complete(SCSIRequest *req, size_t resid) 519 { 520 ESPState *s = req->hba_private; 521 522 if (s->rregs[ESP_RSTAT] & STAT_INT) { 523 /* 524 * Defer handling command complete until the previous 525 * interrupt has been handled. 526 */ 527 trace_esp_command_complete_deferred(); 528 s->deferred_status = req->status; 529 s->deferred_complete = true; 530 return; 531 } 532 esp_report_command_complete(s, req->status); 533 } 534 535 void esp_transfer_data(SCSIRequest *req, uint32_t len) 536 { 537 ESPState *s = req->hba_private; 538 539 assert(!s->do_cmd); 540 trace_esp_transfer_data(s->dma_left, s->ti_size); 541 s->async_len = len; 542 s->async_buf = scsi_req_get_buf(req); 543 if (s->dma_left) { 544 esp_do_dma(s); 545 } else if (s->dma_counter != 0 && s->ti_size <= 0) { 546 /* 547 * If this was the last part of a DMA transfer then the 548 * completion interrupt is deferred to here. 549 */ 550 esp_dma_done(s); 551 } 552 } 553 554 static void handle_ti(ESPState *s) 555 { 556 uint32_t dmalen, minlen; 557 558 if (s->dma && !s->dma_enabled) { 559 s->dma_cb = handle_ti; 560 return; 561 } 562 563 dmalen = esp_get_tc(s); 564 if (dmalen == 0) { 565 dmalen = 0x10000; 566 } 567 s->dma_counter = dmalen; 568 569 if (s->do_cmd) { 570 minlen = (dmalen < ESP_CMDBUF_SZ) ? dmalen : ESP_CMDBUF_SZ; 571 } else if (s->ti_size < 0) { 572 minlen = (dmalen < -s->ti_size) ? dmalen : -s->ti_size; 573 } else { 574 minlen = (dmalen < s->ti_size) ? dmalen : s->ti_size; 575 } 576 trace_esp_handle_ti(minlen); 577 if (s->dma) { 578 s->dma_left = minlen; 579 s->rregs[ESP_RSTAT] &= ~STAT_TC; 580 esp_do_dma(s); 581 } else if (s->do_cmd) { 582 trace_esp_handle_ti_cmd(s->cmdlen); 583 s->ti_size = 0; 584 s->cmdlen = 0; 585 s->do_cmd = 0; 586 do_cmd(s, s->cmdbuf); 587 } 588 } 589 590 void esp_hard_reset(ESPState *s) 591 { 592 memset(s->rregs, 0, ESP_REGS); 593 memset(s->wregs, 0, ESP_REGS); 594 s->tchi_written = 0; 595 s->ti_size = 0; 596 s->ti_rptr = 0; 597 s->ti_wptr = 0; 598 s->dma = 0; 599 s->do_cmd = 0; 600 s->dma_cb = NULL; 601 602 s->rregs[ESP_CFG1] = 7; 603 } 604 605 static void esp_soft_reset(ESPState *s) 606 { 607 qemu_irq_lower(s->irq); 608 qemu_irq_lower(s->irq_data); 609 esp_hard_reset(s); 610 } 611 612 static void parent_esp_reset(ESPState *s, int irq, int level) 613 { 614 if (level) { 615 esp_soft_reset(s); 616 } 617 } 618 619 uint64_t esp_reg_read(ESPState *s, uint32_t saddr) 620 { 621 uint32_t val; 622 623 switch (saddr) { 624 case ESP_FIFO: 625 if ((s->rregs[ESP_RSTAT] & STAT_PIO_MASK) == 0) { 626 /* Data out. */ 627 qemu_log_mask(LOG_UNIMP, "esp: PIO data read not implemented\n"); 628 s->rregs[ESP_FIFO] = 0; 629 } else if (s->ti_rptr < s->ti_wptr) { 630 s->ti_size--; 631 s->rregs[ESP_FIFO] = s->ti_buf[s->ti_rptr++]; 632 } 633 if (s->ti_rptr == s->ti_wptr) { 634 s->ti_rptr = 0; 635 s->ti_wptr = 0; 636 } 637 val = s->rregs[ESP_FIFO]; 638 break; 639 case ESP_RINTR: 640 /* 641 * Clear sequence step, interrupt register and all status bits 642 * except TC 643 */ 644 val = s->rregs[ESP_RINTR]; 645 s->rregs[ESP_RINTR] = 0; 646 s->rregs[ESP_RSTAT] &= ~STAT_TC; 647 s->rregs[ESP_RSEQ] = SEQ_CD; 648 esp_lower_irq(s); 649 if (s->deferred_complete) { 650 esp_report_command_complete(s, s->deferred_status); 651 s->deferred_complete = false; 652 } 653 break; 654 case ESP_TCHI: 655 /* Return the unique id if the value has never been written */ 656 if (!s->tchi_written) { 657 val = s->chip_id; 658 } else { 659 val = s->rregs[saddr]; 660 } 661 break; 662 default: 663 val = s->rregs[saddr]; 664 break; 665 } 666 667 trace_esp_mem_readb(saddr, val); 668 return val; 669 } 670 671 void esp_reg_write(ESPState *s, uint32_t saddr, uint64_t val) 672 { 673 trace_esp_mem_writeb(saddr, s->wregs[saddr], val); 674 switch (saddr) { 675 case ESP_TCHI: 676 s->tchi_written = true; 677 /* fall through */ 678 case ESP_TCLO: 679 case ESP_TCMID: 680 s->rregs[ESP_RSTAT] &= ~STAT_TC; 681 break; 682 case ESP_FIFO: 683 if (s->do_cmd) { 684 if (s->cmdlen < ESP_CMDBUF_SZ) { 685 s->cmdbuf[s->cmdlen++] = val & 0xff; 686 } else { 687 trace_esp_error_fifo_overrun(); 688 } 689 } else if (s->ti_wptr == TI_BUFSZ - 1) { 690 trace_esp_error_fifo_overrun(); 691 } else { 692 s->ti_size++; 693 s->ti_buf[s->ti_wptr++] = val & 0xff; 694 } 695 break; 696 case ESP_CMD: 697 s->rregs[saddr] = val; 698 if (val & CMD_DMA) { 699 s->dma = 1; 700 /* Reload DMA counter. */ 701 esp_set_tc(s, esp_get_stc(s)); 702 } else { 703 s->dma = 0; 704 } 705 switch (val & CMD_CMD) { 706 case CMD_NOP: 707 trace_esp_mem_writeb_cmd_nop(val); 708 break; 709 case CMD_FLUSH: 710 trace_esp_mem_writeb_cmd_flush(val); 711 /*s->ti_size = 0;*/ 712 s->rregs[ESP_RINTR] = INTR_FC; 713 s->rregs[ESP_RSEQ] = 0; 714 s->rregs[ESP_RFLAGS] = 0; 715 break; 716 case CMD_RESET: 717 trace_esp_mem_writeb_cmd_reset(val); 718 esp_soft_reset(s); 719 break; 720 case CMD_BUSRESET: 721 trace_esp_mem_writeb_cmd_bus_reset(val); 722 s->rregs[ESP_RINTR] = INTR_RST; 723 if (!(s->wregs[ESP_CFG1] & CFG1_RESREPT)) { 724 esp_raise_irq(s); 725 } 726 break; 727 case CMD_TI: 728 trace_esp_mem_writeb_cmd_ti(val); 729 handle_ti(s); 730 break; 731 case CMD_ICCS: 732 trace_esp_mem_writeb_cmd_iccs(val); 733 write_response(s); 734 s->rregs[ESP_RINTR] = INTR_FC; 735 s->rregs[ESP_RSTAT] |= STAT_MI; 736 break; 737 case CMD_MSGACC: 738 trace_esp_mem_writeb_cmd_msgacc(val); 739 s->rregs[ESP_RINTR] = INTR_DC; 740 s->rregs[ESP_RSEQ] = 0; 741 s->rregs[ESP_RFLAGS] = 0; 742 esp_raise_irq(s); 743 break; 744 case CMD_PAD: 745 trace_esp_mem_writeb_cmd_pad(val); 746 s->rregs[ESP_RSTAT] = STAT_TC; 747 s->rregs[ESP_RINTR] = INTR_FC; 748 s->rregs[ESP_RSEQ] = 0; 749 break; 750 case CMD_SATN: 751 trace_esp_mem_writeb_cmd_satn(val); 752 break; 753 case CMD_RSTATN: 754 trace_esp_mem_writeb_cmd_rstatn(val); 755 break; 756 case CMD_SEL: 757 trace_esp_mem_writeb_cmd_sel(val); 758 handle_s_without_atn(s); 759 break; 760 case CMD_SELATN: 761 trace_esp_mem_writeb_cmd_selatn(val); 762 handle_satn(s); 763 break; 764 case CMD_SELATNS: 765 trace_esp_mem_writeb_cmd_selatns(val); 766 handle_satn_stop(s); 767 break; 768 case CMD_ENSEL: 769 trace_esp_mem_writeb_cmd_ensel(val); 770 s->rregs[ESP_RINTR] = 0; 771 break; 772 case CMD_DISSEL: 773 trace_esp_mem_writeb_cmd_dissel(val); 774 s->rregs[ESP_RINTR] = 0; 775 esp_raise_irq(s); 776 break; 777 default: 778 trace_esp_error_unhandled_command(val); 779 break; 780 } 781 break; 782 case ESP_WBUSID ... ESP_WSYNO: 783 break; 784 case ESP_CFG1: 785 case ESP_CFG2: case ESP_CFG3: 786 case ESP_RES3: case ESP_RES4: 787 s->rregs[saddr] = val; 788 break; 789 case ESP_WCCF ... ESP_WTEST: 790 break; 791 default: 792 trace_esp_error_invalid_write(val, saddr); 793 return; 794 } 795 s->wregs[saddr] = val; 796 } 797 798 static bool esp_mem_accepts(void *opaque, hwaddr addr, 799 unsigned size, bool is_write, 800 MemTxAttrs attrs) 801 { 802 return (size == 1) || (is_write && size == 4); 803 } 804 805 static bool esp_pdma_needed(void *opaque) 806 { 807 ESPState *s = opaque; 808 return s->dma_memory_read == NULL && s->dma_memory_write == NULL && 809 s->dma_enabled; 810 } 811 812 static const VMStateDescription vmstate_esp_pdma = { 813 .name = "esp/pdma", 814 .version_id = 1, 815 .minimum_version_id = 1, 816 .needed = esp_pdma_needed, 817 .fields = (VMStateField[]) { 818 VMSTATE_BUFFER(pdma_buf, ESPState), 819 VMSTATE_INT32(pdma_origin, ESPState), 820 VMSTATE_UINT32(pdma_len, ESPState), 821 VMSTATE_UINT32(pdma_start, ESPState), 822 VMSTATE_UINT32(pdma_cur, ESPState), 823 VMSTATE_END_OF_LIST() 824 } 825 }; 826 827 static int esp_pre_save(void *opaque) 828 { 829 ESPState *s = ESP(opaque); 830 831 s->mig_version_id = vmstate_esp.version_id; 832 return 0; 833 } 834 835 static int esp_post_load(void *opaque, int version_id) 836 { 837 ESPState *s = ESP(opaque); 838 839 s->mig_version_id = vmstate_esp.version_id; 840 return 0; 841 } 842 843 const VMStateDescription vmstate_esp = { 844 .name = "esp", 845 .version_id = 5, 846 .minimum_version_id = 3, 847 .pre_save = esp_pre_save, 848 .post_load = esp_post_load, 849 .fields = (VMStateField[]) { 850 VMSTATE_BUFFER(rregs, ESPState), 851 VMSTATE_BUFFER(wregs, ESPState), 852 VMSTATE_INT32(ti_size, ESPState), 853 VMSTATE_UINT32(ti_rptr, ESPState), 854 VMSTATE_UINT32(ti_wptr, ESPState), 855 VMSTATE_BUFFER(ti_buf, ESPState), 856 VMSTATE_UINT32(status, ESPState), 857 VMSTATE_UINT32(deferred_status, ESPState), 858 VMSTATE_BOOL(deferred_complete, ESPState), 859 VMSTATE_UINT32(dma, ESPState), 860 VMSTATE_PARTIAL_BUFFER(cmdbuf, ESPState, 16), 861 VMSTATE_BUFFER_START_MIDDLE_V(cmdbuf, ESPState, 16, 4), 862 VMSTATE_UINT32(cmdlen, ESPState), 863 VMSTATE_UINT32(do_cmd, ESPState), 864 VMSTATE_UINT32(dma_left, ESPState), 865 VMSTATE_END_OF_LIST() 866 }, 867 .subsections = (const VMStateDescription * []) { 868 &vmstate_esp_pdma, 869 NULL 870 } 871 }; 872 873 static void sysbus_esp_mem_write(void *opaque, hwaddr addr, 874 uint64_t val, unsigned int size) 875 { 876 SysBusESPState *sysbus = opaque; 877 ESPState *s = ESP(&sysbus->esp); 878 uint32_t saddr; 879 880 saddr = addr >> sysbus->it_shift; 881 esp_reg_write(s, saddr, val); 882 } 883 884 static uint64_t sysbus_esp_mem_read(void *opaque, hwaddr addr, 885 unsigned int size) 886 { 887 SysBusESPState *sysbus = opaque; 888 ESPState *s = ESP(&sysbus->esp); 889 uint32_t saddr; 890 891 saddr = addr >> sysbus->it_shift; 892 return esp_reg_read(s, saddr); 893 } 894 895 static const MemoryRegionOps sysbus_esp_mem_ops = { 896 .read = sysbus_esp_mem_read, 897 .write = sysbus_esp_mem_write, 898 .endianness = DEVICE_NATIVE_ENDIAN, 899 .valid.accepts = esp_mem_accepts, 900 }; 901 902 static void sysbus_esp_pdma_write(void *opaque, hwaddr addr, 903 uint64_t val, unsigned int size) 904 { 905 SysBusESPState *sysbus = opaque; 906 ESPState *s = ESP(&sysbus->esp); 907 uint32_t dmalen; 908 uint8_t *buf = get_pdma_buf(s); 909 910 trace_esp_pdma_write(size); 911 912 dmalen = esp_get_tc(s); 913 if (dmalen == 0 || s->pdma_len == 0) { 914 return; 915 } 916 switch (size) { 917 case 1: 918 buf[s->pdma_cur++] = val; 919 s->pdma_len--; 920 dmalen--; 921 break; 922 case 2: 923 buf[s->pdma_cur++] = val >> 8; 924 buf[s->pdma_cur++] = val; 925 s->pdma_len -= 2; 926 dmalen -= 2; 927 break; 928 } 929 esp_set_tc(s, dmalen); 930 if (s->pdma_len == 0 && s->pdma_cb) { 931 esp_lower_drq(s); 932 s->pdma_cb(s); 933 s->pdma_cb = NULL; 934 } 935 } 936 937 static uint64_t sysbus_esp_pdma_read(void *opaque, hwaddr addr, 938 unsigned int size) 939 { 940 SysBusESPState *sysbus = opaque; 941 ESPState *s = ESP(&sysbus->esp); 942 uint8_t *buf = get_pdma_buf(s); 943 uint64_t val = 0; 944 945 trace_esp_pdma_read(size); 946 947 if (s->pdma_len == 0) { 948 return 0; 949 } 950 switch (size) { 951 case 1: 952 val = buf[s->pdma_cur++]; 953 s->pdma_len--; 954 break; 955 case 2: 956 val = buf[s->pdma_cur++]; 957 val = (val << 8) | buf[s->pdma_cur++]; 958 s->pdma_len -= 2; 959 break; 960 } 961 962 if (s->pdma_len == 0 && s->pdma_cb) { 963 esp_lower_drq(s); 964 s->pdma_cb(s); 965 s->pdma_cb = NULL; 966 } 967 return val; 968 } 969 970 static const MemoryRegionOps sysbus_esp_pdma_ops = { 971 .read = sysbus_esp_pdma_read, 972 .write = sysbus_esp_pdma_write, 973 .endianness = DEVICE_NATIVE_ENDIAN, 974 .valid.min_access_size = 1, 975 .valid.max_access_size = 2, 976 }; 977 978 static const struct SCSIBusInfo esp_scsi_info = { 979 .tcq = false, 980 .max_target = ESP_MAX_DEVS, 981 .max_lun = 7, 982 983 .transfer_data = esp_transfer_data, 984 .complete = esp_command_complete, 985 .cancel = esp_request_cancelled 986 }; 987 988 static void sysbus_esp_gpio_demux(void *opaque, int irq, int level) 989 { 990 SysBusESPState *sysbus = SYSBUS_ESP(opaque); 991 ESPState *s = ESP(&sysbus->esp); 992 993 switch (irq) { 994 case 0: 995 parent_esp_reset(s, irq, level); 996 break; 997 case 1: 998 esp_dma_enable(opaque, irq, level); 999 break; 1000 } 1001 } 1002 1003 static void sysbus_esp_realize(DeviceState *dev, Error **errp) 1004 { 1005 SysBusDevice *sbd = SYS_BUS_DEVICE(dev); 1006 SysBusESPState *sysbus = SYSBUS_ESP(dev); 1007 ESPState *s = ESP(&sysbus->esp); 1008 1009 if (!qdev_realize(DEVICE(s), NULL, errp)) { 1010 return; 1011 } 1012 1013 sysbus_init_irq(sbd, &s->irq); 1014 sysbus_init_irq(sbd, &s->irq_data); 1015 assert(sysbus->it_shift != -1); 1016 1017 s->chip_id = TCHI_FAS100A; 1018 memory_region_init_io(&sysbus->iomem, OBJECT(sysbus), &sysbus_esp_mem_ops, 1019 sysbus, "esp-regs", ESP_REGS << sysbus->it_shift); 1020 sysbus_init_mmio(sbd, &sysbus->iomem); 1021 memory_region_init_io(&sysbus->pdma, OBJECT(sysbus), &sysbus_esp_pdma_ops, 1022 sysbus, "esp-pdma", 2); 1023 sysbus_init_mmio(sbd, &sysbus->pdma); 1024 1025 qdev_init_gpio_in(dev, sysbus_esp_gpio_demux, 2); 1026 1027 scsi_bus_new(&s->bus, sizeof(s->bus), dev, &esp_scsi_info, NULL); 1028 } 1029 1030 static void sysbus_esp_hard_reset(DeviceState *dev) 1031 { 1032 SysBusESPState *sysbus = SYSBUS_ESP(dev); 1033 ESPState *s = ESP(&sysbus->esp); 1034 1035 esp_hard_reset(s); 1036 } 1037 1038 static void sysbus_esp_init(Object *obj) 1039 { 1040 SysBusESPState *sysbus = SYSBUS_ESP(obj); 1041 1042 object_initialize_child(obj, "esp", &sysbus->esp, TYPE_ESP); 1043 } 1044 1045 static const VMStateDescription vmstate_sysbus_esp_scsi = { 1046 .name = "sysbusespscsi", 1047 .version_id = 2, 1048 .minimum_version_id = 1, 1049 .fields = (VMStateField[]) { 1050 VMSTATE_UINT8_V(esp.mig_version_id, SysBusESPState, 2), 1051 VMSTATE_STRUCT(esp, SysBusESPState, 0, vmstate_esp, ESPState), 1052 VMSTATE_END_OF_LIST() 1053 } 1054 }; 1055 1056 static void sysbus_esp_class_init(ObjectClass *klass, void *data) 1057 { 1058 DeviceClass *dc = DEVICE_CLASS(klass); 1059 1060 dc->realize = sysbus_esp_realize; 1061 dc->reset = sysbus_esp_hard_reset; 1062 dc->vmsd = &vmstate_sysbus_esp_scsi; 1063 set_bit(DEVICE_CATEGORY_STORAGE, dc->categories); 1064 } 1065 1066 static const TypeInfo sysbus_esp_info = { 1067 .name = TYPE_SYSBUS_ESP, 1068 .parent = TYPE_SYS_BUS_DEVICE, 1069 .instance_init = sysbus_esp_init, 1070 .instance_size = sizeof(SysBusESPState), 1071 .class_init = sysbus_esp_class_init, 1072 }; 1073 1074 static void esp_class_init(ObjectClass *klass, void *data) 1075 { 1076 DeviceClass *dc = DEVICE_CLASS(klass); 1077 1078 /* internal device for sysbusesp/pciespscsi, not user-creatable */ 1079 dc->user_creatable = false; 1080 set_bit(DEVICE_CATEGORY_STORAGE, dc->categories); 1081 } 1082 1083 static const TypeInfo esp_info = { 1084 .name = TYPE_ESP, 1085 .parent = TYPE_DEVICE, 1086 .instance_size = sizeof(ESPState), 1087 .class_init = esp_class_init, 1088 }; 1089 1090 static void esp_register_types(void) 1091 { 1092 type_register_static(&sysbus_esp_info); 1093 type_register_static(&esp_info); 1094 } 1095 1096 type_init(esp_register_types) 1097