1 /* 2 * QEMU ESP/NCR53C9x emulation 3 * 4 * Copyright (c) 2005-2006 Fabrice Bellard 5 * Copyright (c) 2012 Herve Poussineau 6 * 7 * Permission is hereby granted, free of charge, to any person obtaining a copy 8 * of this software and associated documentation files (the "Software"), to deal 9 * in the Software without restriction, including without limitation the rights 10 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 11 * copies of the Software, and to permit persons to whom the Software is 12 * furnished to do so, subject to the following conditions: 13 * 14 * The above copyright notice and this permission notice shall be included in 15 * all copies or substantial portions of the Software. 16 * 17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 22 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 23 * THE SOFTWARE. 24 */ 25 26 #include "qemu/osdep.h" 27 #include "hw/sysbus.h" 28 #include "migration/vmstate.h" 29 #include "hw/irq.h" 30 #include "hw/scsi/esp.h" 31 #include "trace.h" 32 #include "qemu/log.h" 33 #include "qemu/module.h" 34 35 /* 36 * On Sparc32, this is the ESP (NCR53C90) part of chip STP2000 (Master I/O), 37 * also produced as NCR89C100. See 38 * http://www.ibiblio.org/pub/historic-linux/early-ports/Sparc/NCR/NCR89C100.txt 39 * and 40 * http://www.ibiblio.org/pub/historic-linux/early-ports/Sparc/NCR/NCR53C9X.txt 41 * 42 * On Macintosh Quadra it is a NCR53C96. 43 */ 44 45 static void esp_raise_irq(ESPState *s) 46 { 47 if (!(s->rregs[ESP_RSTAT] & STAT_INT)) { 48 s->rregs[ESP_RSTAT] |= STAT_INT; 49 qemu_irq_raise(s->irq); 50 trace_esp_raise_irq(); 51 } 52 } 53 54 static void esp_lower_irq(ESPState *s) 55 { 56 if (s->rregs[ESP_RSTAT] & STAT_INT) { 57 s->rregs[ESP_RSTAT] &= ~STAT_INT; 58 qemu_irq_lower(s->irq); 59 trace_esp_lower_irq(); 60 } 61 } 62 63 static void esp_raise_drq(ESPState *s) 64 { 65 qemu_irq_raise(s->irq_data); 66 trace_esp_raise_drq(); 67 } 68 69 static void esp_lower_drq(ESPState *s) 70 { 71 qemu_irq_lower(s->irq_data); 72 trace_esp_lower_drq(); 73 } 74 75 void esp_dma_enable(ESPState *s, int irq, int level) 76 { 77 if (level) { 78 s->dma_enabled = 1; 79 trace_esp_dma_enable(); 80 if (s->dma_cb) { 81 s->dma_cb(s); 82 s->dma_cb = NULL; 83 } 84 } else { 85 trace_esp_dma_disable(); 86 s->dma_enabled = 0; 87 } 88 } 89 90 void esp_request_cancelled(SCSIRequest *req) 91 { 92 ESPState *s = req->hba_private; 93 94 if (req == s->current_req) { 95 scsi_req_unref(s->current_req); 96 s->current_req = NULL; 97 s->current_dev = NULL; 98 s->async_len = 0; 99 } 100 } 101 102 static void esp_fifo_push(Fifo8 *fifo, uint8_t val) 103 { 104 if (fifo8_num_used(fifo) == fifo->capacity) { 105 trace_esp_error_fifo_overrun(); 106 return; 107 } 108 109 fifo8_push(fifo, val); 110 } 111 112 static uint8_t esp_fifo_pop(Fifo8 *fifo) 113 { 114 if (fifo8_is_empty(fifo)) { 115 return 0; 116 } 117 118 return fifo8_pop(fifo); 119 } 120 121 static uint32_t esp_fifo_pop_buf(Fifo8 *fifo, uint8_t *dest, int maxlen) 122 { 123 const uint8_t *buf; 124 uint32_t n, n2; 125 int len; 126 127 if (maxlen == 0) { 128 return 0; 129 } 130 131 len = maxlen; 132 buf = fifo8_pop_buf(fifo, len, &n); 133 if (dest) { 134 memcpy(dest, buf, n); 135 } 136 137 /* Add FIFO wraparound if needed */ 138 len -= n; 139 len = MIN(len, fifo8_num_used(fifo)); 140 if (len) { 141 buf = fifo8_pop_buf(fifo, len, &n2); 142 if (dest) { 143 memcpy(&dest[n], buf, n2); 144 } 145 n += n2; 146 } 147 148 return n; 149 } 150 151 static uint32_t esp_get_tc(ESPState *s) 152 { 153 uint32_t dmalen; 154 155 dmalen = s->rregs[ESP_TCLO]; 156 dmalen |= s->rregs[ESP_TCMID] << 8; 157 dmalen |= s->rregs[ESP_TCHI] << 16; 158 159 return dmalen; 160 } 161 162 static void esp_set_tc(ESPState *s, uint32_t dmalen) 163 { 164 uint32_t old_tc = esp_get_tc(s); 165 166 s->rregs[ESP_TCLO] = dmalen; 167 s->rregs[ESP_TCMID] = dmalen >> 8; 168 s->rregs[ESP_TCHI] = dmalen >> 16; 169 170 if (old_tc && dmalen == 0) { 171 s->rregs[ESP_RSTAT] |= STAT_TC; 172 } 173 } 174 175 static uint32_t esp_get_stc(ESPState *s) 176 { 177 uint32_t dmalen; 178 179 dmalen = s->wregs[ESP_TCLO]; 180 dmalen |= s->wregs[ESP_TCMID] << 8; 181 dmalen |= s->wregs[ESP_TCHI] << 16; 182 183 return dmalen; 184 } 185 186 static const char *esp_phase_names[8] = { 187 "DATA OUT", "DATA IN", "COMMAND", "STATUS", 188 "(reserved)", "(reserved)", "MESSAGE OUT", "MESSAGE IN" 189 }; 190 191 static void esp_set_phase(ESPState *s, uint8_t phase) 192 { 193 s->rregs[ESP_RSTAT] &= ~7; 194 s->rregs[ESP_RSTAT] |= phase; 195 196 trace_esp_set_phase(esp_phase_names[phase]); 197 } 198 199 static uint8_t esp_pdma_read(ESPState *s) 200 { 201 uint8_t val; 202 203 val = esp_fifo_pop(&s->fifo); 204 return val; 205 } 206 207 static void esp_pdma_write(ESPState *s, uint8_t val) 208 { 209 uint32_t dmalen = esp_get_tc(s); 210 211 if (dmalen == 0) { 212 return; 213 } 214 215 esp_fifo_push(&s->fifo, val); 216 217 dmalen--; 218 esp_set_tc(s, dmalen); 219 } 220 221 static void esp_set_pdma_cb(ESPState *s, enum pdma_cb cb) 222 { 223 s->pdma_cb = cb; 224 } 225 226 static int esp_select(ESPState *s) 227 { 228 int target; 229 230 target = s->wregs[ESP_WBUSID] & BUSID_DID; 231 232 s->ti_size = 0; 233 234 if (s->current_req) { 235 /* Started a new command before the old one finished. Cancel it. */ 236 scsi_req_cancel(s->current_req); 237 } 238 239 s->current_dev = scsi_device_find(&s->bus, 0, target, 0); 240 if (!s->current_dev) { 241 /* No such drive */ 242 s->rregs[ESP_RSTAT] = 0; 243 s->rregs[ESP_RINTR] = INTR_DC; 244 s->rregs[ESP_RSEQ] = SEQ_0; 245 esp_raise_irq(s); 246 return -1; 247 } 248 249 /* 250 * Note that we deliberately don't raise the IRQ here: this will be done 251 * either in do_command_phase() for DATA OUT transfers or by the deferred 252 * IRQ mechanism in esp_transfer_data() for DATA IN transfers 253 */ 254 s->rregs[ESP_RINTR] |= INTR_FC; 255 s->rregs[ESP_RSEQ] = SEQ_CD; 256 return 0; 257 } 258 259 static uint32_t get_cmd(ESPState *s, uint32_t maxlen) 260 { 261 uint8_t buf[ESP_CMDFIFO_SZ]; 262 uint32_t dmalen, n; 263 int target; 264 265 target = s->wregs[ESP_WBUSID] & BUSID_DID; 266 if (s->dma) { 267 dmalen = MIN(esp_get_tc(s), maxlen); 268 if (dmalen == 0) { 269 return 0; 270 } 271 if (s->dma_memory_read) { 272 s->dma_memory_read(s->dma_opaque, buf, dmalen); 273 dmalen = MIN(fifo8_num_free(&s->cmdfifo), dmalen); 274 fifo8_push_all(&s->cmdfifo, buf, dmalen); 275 esp_set_tc(s, esp_get_tc(s) - dmalen); 276 } else { 277 return 0; 278 } 279 } else { 280 dmalen = MIN(fifo8_num_used(&s->fifo), maxlen); 281 if (dmalen == 0) { 282 return 0; 283 } 284 n = esp_fifo_pop_buf(&s->fifo, buf, dmalen); 285 n = MIN(fifo8_num_free(&s->cmdfifo), n); 286 fifo8_push_all(&s->cmdfifo, buf, n); 287 } 288 trace_esp_get_cmd(dmalen, target); 289 290 return dmalen; 291 } 292 293 static void do_command_phase(ESPState *s) 294 { 295 uint32_t cmdlen; 296 int32_t datalen; 297 SCSIDevice *current_lun; 298 uint8_t buf[ESP_CMDFIFO_SZ]; 299 300 trace_esp_do_command_phase(s->lun); 301 cmdlen = fifo8_num_used(&s->cmdfifo); 302 if (!cmdlen || !s->current_dev) { 303 return; 304 } 305 esp_fifo_pop_buf(&s->cmdfifo, buf, cmdlen); 306 307 current_lun = scsi_device_find(&s->bus, 0, s->current_dev->id, s->lun); 308 if (!current_lun) { 309 /* No such drive */ 310 s->rregs[ESP_RSTAT] = 0; 311 s->rregs[ESP_RINTR] = INTR_DC; 312 s->rregs[ESP_RSEQ] = SEQ_0; 313 esp_raise_irq(s); 314 return; 315 } 316 317 s->current_req = scsi_req_new(current_lun, 0, s->lun, buf, cmdlen, s); 318 datalen = scsi_req_enqueue(s->current_req); 319 s->ti_size = datalen; 320 fifo8_reset(&s->cmdfifo); 321 if (datalen != 0) { 322 s->ti_cmd = 0; 323 if (datalen > 0) { 324 /* 325 * Switch to DATA IN phase but wait until initial data xfer is 326 * complete before raising the command completion interrupt 327 */ 328 s->data_in_ready = false; 329 esp_set_phase(s, STAT_DI); 330 } else { 331 esp_set_phase(s, STAT_DO); 332 s->rregs[ESP_RINTR] |= INTR_BS | INTR_FC; 333 esp_raise_irq(s); 334 esp_lower_drq(s); 335 } 336 scsi_req_continue(s->current_req); 337 return; 338 } 339 } 340 341 static void do_message_phase(ESPState *s) 342 { 343 if (s->cmdfifo_cdb_offset) { 344 uint8_t message = esp_fifo_pop(&s->cmdfifo); 345 346 trace_esp_do_identify(message); 347 s->lun = message & 7; 348 s->cmdfifo_cdb_offset--; 349 } 350 351 /* Ignore extended messages for now */ 352 if (s->cmdfifo_cdb_offset) { 353 int len = MIN(s->cmdfifo_cdb_offset, fifo8_num_used(&s->cmdfifo)); 354 esp_fifo_pop_buf(&s->cmdfifo, NULL, len); 355 s->cmdfifo_cdb_offset = 0; 356 } 357 } 358 359 static void do_cmd(ESPState *s) 360 { 361 do_message_phase(s); 362 assert(s->cmdfifo_cdb_offset == 0); 363 do_command_phase(s); 364 } 365 366 static void satn_pdma_cb(ESPState *s) 367 { 368 uint8_t buf[ESP_FIFO_SZ]; 369 int n; 370 371 /* Copy FIFO into cmdfifo */ 372 n = esp_fifo_pop_buf(&s->fifo, buf, fifo8_num_used(&s->fifo)); 373 n = MIN(fifo8_num_free(&s->cmdfifo), n); 374 fifo8_push_all(&s->cmdfifo, buf, n); 375 376 if (!esp_get_tc(s) && !fifo8_is_empty(&s->cmdfifo)) { 377 s->cmdfifo_cdb_offset = 1; 378 s->do_cmd = 0; 379 do_cmd(s); 380 } 381 } 382 383 static void handle_satn(ESPState *s) 384 { 385 int32_t cmdlen; 386 387 if (s->dma && !s->dma_enabled) { 388 s->dma_cb = handle_satn; 389 return; 390 } 391 esp_set_pdma_cb(s, SATN_PDMA_CB); 392 if (esp_select(s) < 0) { 393 return; 394 } 395 cmdlen = get_cmd(s, ESP_CMDFIFO_SZ); 396 if (cmdlen > 0) { 397 s->cmdfifo_cdb_offset = 1; 398 s->do_cmd = 0; 399 do_cmd(s); 400 } else if (cmdlen == 0) { 401 if (s->dma) { 402 esp_raise_drq(s); 403 } 404 s->do_cmd = 1; 405 /* Target present, but no cmd yet - switch to command phase */ 406 s->rregs[ESP_RSEQ] = SEQ_CD; 407 esp_set_phase(s, STAT_CD); 408 } 409 } 410 411 static void s_without_satn_pdma_cb(ESPState *s) 412 { 413 uint8_t buf[ESP_FIFO_SZ]; 414 int n; 415 416 /* Copy FIFO into cmdfifo */ 417 n = esp_fifo_pop_buf(&s->fifo, buf, fifo8_num_used(&s->fifo)); 418 n = MIN(fifo8_num_free(&s->cmdfifo), n); 419 fifo8_push_all(&s->cmdfifo, buf, n); 420 421 if (!esp_get_tc(s) && !fifo8_is_empty(&s->cmdfifo)) { 422 s->cmdfifo_cdb_offset = 0; 423 s->do_cmd = 0; 424 do_cmd(s); 425 } 426 } 427 428 static void handle_s_without_atn(ESPState *s) 429 { 430 int32_t cmdlen; 431 432 if (s->dma && !s->dma_enabled) { 433 s->dma_cb = handle_s_without_atn; 434 return; 435 } 436 esp_set_pdma_cb(s, S_WITHOUT_SATN_PDMA_CB); 437 if (esp_select(s) < 0) { 438 return; 439 } 440 cmdlen = get_cmd(s, ESP_CMDFIFO_SZ); 441 if (cmdlen > 0) { 442 s->cmdfifo_cdb_offset = 0; 443 s->do_cmd = 0; 444 do_cmd(s); 445 } else if (cmdlen == 0) { 446 if (s->dma) { 447 esp_raise_drq(s); 448 } 449 s->do_cmd = 1; 450 /* Target present, but no cmd yet - switch to command phase */ 451 s->rregs[ESP_RSEQ] = SEQ_CD; 452 esp_set_phase(s, STAT_CD); 453 } 454 } 455 456 static void satn_stop_pdma_cb(ESPState *s) 457 { 458 uint8_t buf[ESP_FIFO_SZ]; 459 int n; 460 461 /* Copy FIFO into cmdfifo */ 462 n = esp_fifo_pop_buf(&s->fifo, buf, fifo8_num_used(&s->fifo)); 463 n = MIN(fifo8_num_free(&s->cmdfifo), n); 464 fifo8_push_all(&s->cmdfifo, buf, n); 465 466 if (!esp_get_tc(s) && !fifo8_is_empty(&s->cmdfifo)) { 467 trace_esp_handle_satn_stop(fifo8_num_used(&s->cmdfifo)); 468 s->do_cmd = 1; 469 s->cmdfifo_cdb_offset = 1; 470 esp_set_phase(s, STAT_CD); 471 s->rregs[ESP_RSTAT] |= STAT_TC; 472 s->rregs[ESP_RINTR] |= INTR_BS | INTR_FC; 473 s->rregs[ESP_RSEQ] = SEQ_CD; 474 esp_raise_irq(s); 475 } 476 } 477 478 static void handle_satn_stop(ESPState *s) 479 { 480 int32_t cmdlen; 481 482 if (s->dma && !s->dma_enabled) { 483 s->dma_cb = handle_satn_stop; 484 return; 485 } 486 esp_set_pdma_cb(s, SATN_STOP_PDMA_CB); 487 if (esp_select(s) < 0) { 488 return; 489 } 490 cmdlen = get_cmd(s, 1); 491 if (cmdlen > 0) { 492 trace_esp_handle_satn_stop(fifo8_num_used(&s->cmdfifo)); 493 s->do_cmd = 1; 494 s->cmdfifo_cdb_offset = 1; 495 esp_set_phase(s, STAT_MO); 496 s->rregs[ESP_RINTR] |= INTR_BS | INTR_FC; 497 s->rregs[ESP_RSEQ] = SEQ_MO; 498 esp_raise_irq(s); 499 } else if (cmdlen == 0) { 500 if (s->dma) { 501 esp_raise_drq(s); 502 } 503 s->do_cmd = 1; 504 /* Target present, switch to message out phase */ 505 s->rregs[ESP_RSEQ] = SEQ_MO; 506 esp_set_phase(s, STAT_MO); 507 } 508 } 509 510 static void write_response_pdma_cb(ESPState *s) 511 { 512 esp_set_phase(s, STAT_ST); 513 s->rregs[ESP_RINTR] |= INTR_BS | INTR_FC; 514 s->rregs[ESP_RSEQ] = SEQ_CD; 515 esp_raise_irq(s); 516 } 517 518 static void write_response(ESPState *s) 519 { 520 uint8_t buf[2]; 521 522 trace_esp_write_response(s->status); 523 524 buf[0] = s->status; 525 buf[1] = 0; 526 527 if (s->dma) { 528 if (s->dma_memory_write) { 529 s->dma_memory_write(s->dma_opaque, buf, 2); 530 esp_set_phase(s, STAT_ST); 531 s->rregs[ESP_RINTR] |= INTR_BS | INTR_FC; 532 s->rregs[ESP_RSEQ] = SEQ_CD; 533 } else { 534 esp_set_pdma_cb(s, WRITE_RESPONSE_PDMA_CB); 535 esp_raise_drq(s); 536 return; 537 } 538 } else { 539 fifo8_reset(&s->fifo); 540 fifo8_push_all(&s->fifo, buf, 2); 541 s->rregs[ESP_RFLAGS] = 2; 542 } 543 esp_raise_irq(s); 544 } 545 546 static void esp_dma_done(ESPState *s) 547 { 548 if (esp_get_tc(s) == 0 && fifo8_num_used(&s->fifo) < 2) { 549 s->rregs[ESP_RINTR] |= INTR_BS; 550 esp_raise_irq(s); 551 esp_lower_drq(s); 552 } 553 } 554 555 static void do_dma_pdma_cb(ESPState *s) 556 { 557 int to_device = ((s->rregs[ESP_RSTAT] & 7) == STAT_DO); 558 uint8_t buf[ESP_CMDFIFO_SZ]; 559 int len; 560 uint32_t n; 561 562 if (s->do_cmd) { 563 /* Copy FIFO into cmdfifo */ 564 n = esp_fifo_pop_buf(&s->fifo, buf, fifo8_num_used(&s->fifo)); 565 n = MIN(fifo8_num_free(&s->cmdfifo), n); 566 fifo8_push_all(&s->cmdfifo, buf, n); 567 568 /* Ensure we have received complete command after SATN and stop */ 569 if (esp_get_tc(s) || fifo8_is_empty(&s->cmdfifo)) { 570 return; 571 } 572 573 s->ti_size = 0; 574 if ((s->rregs[ESP_RSTAT] & 7) == STAT_CD) { 575 /* No command received */ 576 if (s->cmdfifo_cdb_offset == fifo8_num_used(&s->cmdfifo)) { 577 return; 578 } 579 580 /* Command has been received */ 581 s->do_cmd = 0; 582 do_cmd(s); 583 } else { 584 /* 585 * Extra message out bytes received: update cmdfifo_cdb_offset 586 * and then switch to command phase 587 */ 588 s->cmdfifo_cdb_offset = fifo8_num_used(&s->cmdfifo); 589 esp_set_phase(s, STAT_CD); 590 s->rregs[ESP_RSEQ] = SEQ_CD; 591 s->rregs[ESP_RINTR] |= INTR_BS; 592 esp_raise_irq(s); 593 } 594 return; 595 } 596 597 if (!s->current_req) { 598 return; 599 } 600 601 if (to_device) { 602 /* Copy FIFO data to device */ 603 len = MIN(s->async_len, ESP_FIFO_SZ); 604 len = MIN(len, fifo8_num_used(&s->fifo)); 605 n = esp_fifo_pop_buf(&s->fifo, s->async_buf, len); 606 s->async_buf += n; 607 s->async_len -= n; 608 s->ti_size += n; 609 610 if (s->async_len == 0 && fifo8_num_used(&s->fifo) < 2) { 611 /* Defer until the scsi layer has completed */ 612 scsi_req_continue(s->current_req); 613 return; 614 } 615 616 esp_dma_done(s); 617 } else { 618 if (s->async_len == 0 && fifo8_num_used(&s->fifo) < 2) { 619 /* Defer until the scsi layer has completed */ 620 scsi_req_continue(s->current_req); 621 s->data_in_ready = false; 622 return; 623 } 624 625 esp_dma_done(s); 626 627 /* Copy device data to FIFO */ 628 len = MIN(s->async_len, esp_get_tc(s)); 629 len = MIN(len, fifo8_num_free(&s->fifo)); 630 fifo8_push_all(&s->fifo, s->async_buf, len); 631 s->async_buf += len; 632 s->async_len -= len; 633 s->ti_size -= len; 634 esp_set_tc(s, esp_get_tc(s) - len); 635 } 636 } 637 638 static void esp_do_dma(ESPState *s) 639 { 640 uint32_t len, cmdlen; 641 int to_device = ((s->rregs[ESP_RSTAT] & 7) == STAT_DO); 642 uint8_t buf[ESP_CMDFIFO_SZ]; 643 644 len = esp_get_tc(s); 645 if (s->do_cmd) { 646 /* 647 * handle_ti_cmd() case: esp_do_dma() is called only from 648 * handle_ti_cmd() with do_cmd != NULL (see the assert()) 649 */ 650 cmdlen = fifo8_num_used(&s->cmdfifo); 651 trace_esp_do_dma(cmdlen, len); 652 if (s->dma_memory_read) { 653 len = MIN(len, fifo8_num_free(&s->cmdfifo)); 654 s->dma_memory_read(s->dma_opaque, buf, len); 655 fifo8_push_all(&s->cmdfifo, buf, len); 656 esp_set_tc(s, esp_get_tc(s) - len); 657 } else { 658 esp_set_pdma_cb(s, DO_DMA_PDMA_CB); 659 esp_raise_drq(s); 660 return; 661 } 662 trace_esp_handle_ti_cmd(cmdlen); 663 s->ti_size = 0; 664 if ((s->rregs[ESP_RSTAT] & 7) == STAT_CD) { 665 /* No command received */ 666 if (s->cmdfifo_cdb_offset == fifo8_num_used(&s->cmdfifo)) { 667 return; 668 } 669 670 /* Command has been received */ 671 s->do_cmd = 0; 672 do_cmd(s); 673 } else { 674 /* 675 * Extra message out bytes received: update cmdfifo_cdb_offset 676 * and then switch to command phase 677 */ 678 s->cmdfifo_cdb_offset = fifo8_num_used(&s->cmdfifo); 679 esp_set_phase(s, STAT_CD); 680 s->rregs[ESP_RSEQ] = SEQ_CD; 681 s->rregs[ESP_RINTR] |= INTR_BS; 682 esp_raise_irq(s); 683 } 684 return; 685 } 686 if (!s->current_req) { 687 return; 688 } 689 if (s->async_len == 0) { 690 /* Defer until data is available. */ 691 return; 692 } 693 if (len > s->async_len) { 694 len = s->async_len; 695 } 696 if (to_device) { 697 if (s->dma_memory_read) { 698 s->dma_memory_read(s->dma_opaque, s->async_buf, len); 699 700 esp_set_tc(s, esp_get_tc(s) - len); 701 s->async_buf += len; 702 s->async_len -= len; 703 s->ti_size += len; 704 705 if (s->async_len == 0 && fifo8_num_used(&s->fifo) < 2) { 706 /* Defer until the scsi layer has completed */ 707 scsi_req_continue(s->current_req); 708 return; 709 } 710 711 esp_dma_done(s); 712 } else { 713 esp_set_pdma_cb(s, DO_DMA_PDMA_CB); 714 esp_raise_drq(s); 715 716 if (s->async_len == 0 && fifo8_num_used(&s->fifo) < 2) { 717 /* Defer until the scsi layer has completed */ 718 scsi_req_continue(s->current_req); 719 return; 720 } 721 722 esp_dma_done(s); 723 } 724 } else { 725 if (s->dma_memory_write) { 726 s->dma_memory_write(s->dma_opaque, s->async_buf, len); 727 728 esp_set_tc(s, esp_get_tc(s) - len); 729 s->async_buf += len; 730 s->async_len -= len; 731 s->ti_size -= len; 732 733 if (s->async_len == 0 && fifo8_num_used(&s->fifo) < 2) { 734 /* Defer until the scsi layer has completed */ 735 scsi_req_continue(s->current_req); 736 return; 737 } 738 739 esp_dma_done(s); 740 } else { 741 /* Copy device data to FIFO */ 742 len = MIN(len, fifo8_num_free(&s->fifo)); 743 fifo8_push_all(&s->fifo, s->async_buf, len); 744 s->async_buf += len; 745 s->async_len -= len; 746 s->ti_size -= len; 747 esp_set_tc(s, esp_get_tc(s) - len); 748 esp_set_pdma_cb(s, DO_DMA_PDMA_CB); 749 esp_raise_drq(s); 750 751 if (s->async_len == 0 && fifo8_num_used(&s->fifo) < 2) { 752 /* Defer until the scsi layer has completed */ 753 scsi_req_continue(s->current_req); 754 return; 755 } 756 757 esp_dma_done(s); 758 } 759 } 760 } 761 762 static void esp_do_nodma(ESPState *s) 763 { 764 int to_device = ((s->rregs[ESP_RSTAT] & 7) == STAT_DO); 765 uint8_t buf[ESP_FIFO_SZ]; 766 uint32_t cmdlen; 767 int len, n; 768 769 if (s->do_cmd) { 770 /* Copy FIFO into cmdfifo */ 771 n = esp_fifo_pop_buf(&s->fifo, buf, fifo8_num_used(&s->fifo)); 772 n = MIN(fifo8_num_free(&s->cmdfifo), n); 773 fifo8_push_all(&s->cmdfifo, buf, n); 774 775 cmdlen = fifo8_num_used(&s->cmdfifo); 776 trace_esp_handle_ti_cmd(cmdlen); 777 s->ti_size = 0; 778 if ((s->rregs[ESP_RSTAT] & 7) == STAT_CD) { 779 /* No command received */ 780 if (s->cmdfifo_cdb_offset == fifo8_num_used(&s->cmdfifo)) { 781 return; 782 } 783 784 /* Command has been received */ 785 s->do_cmd = 0; 786 do_cmd(s); 787 } else { 788 /* 789 * Extra message out bytes received: update cmdfifo_cdb_offset 790 * and then switch to command phase 791 */ 792 s->cmdfifo_cdb_offset = fifo8_num_used(&s->cmdfifo); 793 esp_set_phase(s, STAT_CD); 794 s->rregs[ESP_RSEQ] = SEQ_CD; 795 s->rregs[ESP_RINTR] |= INTR_BS; 796 esp_raise_irq(s); 797 } 798 return; 799 } 800 801 if (!s->current_req) { 802 return; 803 } 804 805 if (s->async_len == 0) { 806 /* Defer until data is available. */ 807 return; 808 } 809 810 if (to_device) { 811 len = MIN(s->async_len, ESP_FIFO_SZ); 812 len = MIN(len, fifo8_num_used(&s->fifo)); 813 esp_fifo_pop_buf(&s->fifo, s->async_buf, len); 814 s->async_buf += len; 815 s->async_len -= len; 816 s->ti_size += len; 817 } else { 818 if (fifo8_is_empty(&s->fifo)) { 819 fifo8_push(&s->fifo, s->async_buf[0]); 820 s->async_buf++; 821 s->async_len--; 822 s->ti_size--; 823 } 824 } 825 826 if (s->async_len == 0) { 827 scsi_req_continue(s->current_req); 828 return; 829 } 830 831 s->rregs[ESP_RINTR] |= INTR_BS; 832 esp_raise_irq(s); 833 } 834 835 static void esp_pdma_cb(ESPState *s) 836 { 837 switch (s->pdma_cb) { 838 case SATN_PDMA_CB: 839 satn_pdma_cb(s); 840 break; 841 case S_WITHOUT_SATN_PDMA_CB: 842 s_without_satn_pdma_cb(s); 843 break; 844 case SATN_STOP_PDMA_CB: 845 satn_stop_pdma_cb(s); 846 break; 847 case WRITE_RESPONSE_PDMA_CB: 848 write_response_pdma_cb(s); 849 break; 850 case DO_DMA_PDMA_CB: 851 do_dma_pdma_cb(s); 852 break; 853 default: 854 g_assert_not_reached(); 855 } 856 } 857 858 void esp_command_complete(SCSIRequest *req, size_t resid) 859 { 860 ESPState *s = req->hba_private; 861 int to_device = ((s->rregs[ESP_RSTAT] & 7) == STAT_DO); 862 863 trace_esp_command_complete(); 864 865 /* 866 * Non-DMA transfers from the target will leave the last byte in 867 * the FIFO so don't reset ti_size in this case 868 */ 869 if (s->dma || to_device) { 870 if (s->ti_size != 0) { 871 trace_esp_command_complete_unexpected(); 872 } 873 } 874 875 s->async_len = 0; 876 if (req->status) { 877 trace_esp_command_complete_fail(); 878 } 879 s->status = req->status; 880 881 /* 882 * Switch to status phase. For non-DMA transfers from the target the last 883 * byte is still in the FIFO 884 */ 885 esp_set_phase(s, STAT_ST); 886 if (s->ti_size == 0) { 887 /* 888 * Transfer complete: force TC to zero just in case a TI command was 889 * requested for more data than the command returns (Solaris 8 does 890 * this) 891 */ 892 esp_set_tc(s, 0); 893 esp_dma_done(s); 894 } else { 895 /* 896 * Transfer truncated: raise INTR_BS to indicate early change of 897 * phase 898 */ 899 s->rregs[ESP_RINTR] |= INTR_BS; 900 esp_raise_irq(s); 901 s->ti_size = 0; 902 } 903 904 if (s->current_req) { 905 scsi_req_unref(s->current_req); 906 s->current_req = NULL; 907 s->current_dev = NULL; 908 } 909 } 910 911 void esp_transfer_data(SCSIRequest *req, uint32_t len) 912 { 913 ESPState *s = req->hba_private; 914 int to_device = ((s->rregs[ESP_RSTAT] & 7) == STAT_DO); 915 uint32_t dmalen = esp_get_tc(s); 916 917 assert(!s->do_cmd); 918 trace_esp_transfer_data(dmalen, s->ti_size); 919 s->async_len = len; 920 s->async_buf = scsi_req_get_buf(req); 921 922 if (!to_device && !s->data_in_ready) { 923 /* 924 * Initial incoming data xfer is complete so raise command 925 * completion interrupt 926 */ 927 s->data_in_ready = true; 928 s->rregs[ESP_RINTR] |= INTR_BS; 929 esp_raise_irq(s); 930 } 931 932 /* 933 * Always perform the initial transfer upon reception of the next TI 934 * command to ensure the DMA/non-DMA status of the command is correct. 935 * It is not possible to use s->dma directly in the section below as 936 * some OSs send non-DMA NOP commands after a DMA transfer. Hence if the 937 * async data transfer is delayed then s->dma is set incorrectly. 938 */ 939 940 if (s->ti_cmd == (CMD_TI | CMD_DMA)) { 941 /* When the SCSI layer returns more data, raise deferred INTR_BS */ 942 esp_dma_done(s); 943 944 esp_do_dma(s); 945 } else if (s->ti_cmd == CMD_TI) { 946 esp_do_nodma(s); 947 } 948 } 949 950 static void handle_ti(ESPState *s) 951 { 952 uint32_t dmalen; 953 954 if (s->dma && !s->dma_enabled) { 955 s->dma_cb = handle_ti; 956 return; 957 } 958 959 s->ti_cmd = s->rregs[ESP_CMD]; 960 if (s->dma) { 961 dmalen = esp_get_tc(s); 962 trace_esp_handle_ti(dmalen); 963 esp_do_dma(s); 964 } else { 965 trace_esp_handle_ti(s->ti_size); 966 esp_do_nodma(s); 967 } 968 } 969 970 void esp_hard_reset(ESPState *s) 971 { 972 memset(s->rregs, 0, ESP_REGS); 973 memset(s->wregs, 0, ESP_REGS); 974 s->tchi_written = 0; 975 s->ti_size = 0; 976 s->async_len = 0; 977 fifo8_reset(&s->fifo); 978 fifo8_reset(&s->cmdfifo); 979 s->dma = 0; 980 s->do_cmd = 0; 981 s->dma_cb = NULL; 982 983 s->rregs[ESP_CFG1] = 7; 984 } 985 986 static void esp_soft_reset(ESPState *s) 987 { 988 qemu_irq_lower(s->irq); 989 qemu_irq_lower(s->irq_data); 990 esp_hard_reset(s); 991 } 992 993 static void esp_bus_reset(ESPState *s) 994 { 995 bus_cold_reset(BUS(&s->bus)); 996 } 997 998 static void parent_esp_reset(ESPState *s, int irq, int level) 999 { 1000 if (level) { 1001 esp_soft_reset(s); 1002 } 1003 } 1004 1005 static void esp_run_cmd(ESPState *s) 1006 { 1007 uint8_t cmd = s->rregs[ESP_CMD]; 1008 1009 if (cmd & CMD_DMA) { 1010 s->dma = 1; 1011 /* Reload DMA counter. */ 1012 if (esp_get_stc(s) == 0) { 1013 esp_set_tc(s, 0x10000); 1014 } else { 1015 esp_set_tc(s, esp_get_stc(s)); 1016 } 1017 } else { 1018 s->dma = 0; 1019 } 1020 switch (cmd & CMD_CMD) { 1021 case CMD_NOP: 1022 trace_esp_mem_writeb_cmd_nop(cmd); 1023 break; 1024 case CMD_FLUSH: 1025 trace_esp_mem_writeb_cmd_flush(cmd); 1026 fifo8_reset(&s->fifo); 1027 break; 1028 case CMD_RESET: 1029 trace_esp_mem_writeb_cmd_reset(cmd); 1030 esp_soft_reset(s); 1031 break; 1032 case CMD_BUSRESET: 1033 trace_esp_mem_writeb_cmd_bus_reset(cmd); 1034 esp_bus_reset(s); 1035 if (!(s->wregs[ESP_CFG1] & CFG1_RESREPT)) { 1036 s->rregs[ESP_RINTR] |= INTR_RST; 1037 esp_raise_irq(s); 1038 } 1039 break; 1040 case CMD_TI: 1041 trace_esp_mem_writeb_cmd_ti(cmd); 1042 handle_ti(s); 1043 break; 1044 case CMD_ICCS: 1045 trace_esp_mem_writeb_cmd_iccs(cmd); 1046 write_response(s); 1047 s->rregs[ESP_RINTR] |= INTR_FC; 1048 esp_set_phase(s, STAT_MI); 1049 break; 1050 case CMD_MSGACC: 1051 trace_esp_mem_writeb_cmd_msgacc(cmd); 1052 s->rregs[ESP_RINTR] |= INTR_DC; 1053 s->rregs[ESP_RSEQ] = 0; 1054 s->rregs[ESP_RFLAGS] = 0; 1055 esp_raise_irq(s); 1056 break; 1057 case CMD_PAD: 1058 trace_esp_mem_writeb_cmd_pad(cmd); 1059 s->rregs[ESP_RSTAT] = STAT_TC; 1060 s->rregs[ESP_RINTR] |= INTR_FC; 1061 s->rregs[ESP_RSEQ] = 0; 1062 break; 1063 case CMD_SATN: 1064 trace_esp_mem_writeb_cmd_satn(cmd); 1065 break; 1066 case CMD_RSTATN: 1067 trace_esp_mem_writeb_cmd_rstatn(cmd); 1068 break; 1069 case CMD_SEL: 1070 trace_esp_mem_writeb_cmd_sel(cmd); 1071 handle_s_without_atn(s); 1072 break; 1073 case CMD_SELATN: 1074 trace_esp_mem_writeb_cmd_selatn(cmd); 1075 handle_satn(s); 1076 break; 1077 case CMD_SELATNS: 1078 trace_esp_mem_writeb_cmd_selatns(cmd); 1079 handle_satn_stop(s); 1080 break; 1081 case CMD_ENSEL: 1082 trace_esp_mem_writeb_cmd_ensel(cmd); 1083 s->rregs[ESP_RINTR] = 0; 1084 break; 1085 case CMD_DISSEL: 1086 trace_esp_mem_writeb_cmd_dissel(cmd); 1087 s->rregs[ESP_RINTR] = 0; 1088 esp_raise_irq(s); 1089 break; 1090 default: 1091 trace_esp_error_unhandled_command(cmd); 1092 break; 1093 } 1094 } 1095 1096 uint64_t esp_reg_read(ESPState *s, uint32_t saddr) 1097 { 1098 uint32_t val; 1099 1100 switch (saddr) { 1101 case ESP_FIFO: 1102 if (s->dma_memory_read && s->dma_memory_write && 1103 (s->rregs[ESP_RSTAT] & STAT_PIO_MASK) == 0) { 1104 /* Data out. */ 1105 qemu_log_mask(LOG_UNIMP, "esp: PIO data read not implemented\n"); 1106 s->rregs[ESP_FIFO] = 0; 1107 } else { 1108 if ((s->rregs[ESP_RSTAT] & 0x7) == STAT_DI) { 1109 if (s->ti_size) { 1110 esp_do_nodma(s); 1111 } else { 1112 /* 1113 * The last byte of a non-DMA transfer has been read out 1114 * of the FIFO so switch to status phase 1115 */ 1116 esp_set_phase(s, STAT_ST); 1117 } 1118 } 1119 s->rregs[ESP_FIFO] = esp_fifo_pop(&s->fifo); 1120 } 1121 val = s->rregs[ESP_FIFO]; 1122 break; 1123 case ESP_RINTR: 1124 /* 1125 * Clear sequence step, interrupt register and all status bits 1126 * except TC 1127 */ 1128 val = s->rregs[ESP_RINTR]; 1129 s->rregs[ESP_RINTR] = 0; 1130 s->rregs[ESP_RSTAT] &= ~STAT_TC; 1131 /* 1132 * According to the datasheet ESP_RSEQ should be cleared, but as the 1133 * emulation currently defers information transfers to the next TI 1134 * command leave it for now so that pedantic guests such as the old 1135 * Linux 2.6 driver see the correct flags before the next SCSI phase 1136 * transition. 1137 * 1138 * s->rregs[ESP_RSEQ] = SEQ_0; 1139 */ 1140 esp_lower_irq(s); 1141 break; 1142 case ESP_TCHI: 1143 /* Return the unique id if the value has never been written */ 1144 if (!s->tchi_written) { 1145 val = s->chip_id; 1146 } else { 1147 val = s->rregs[saddr]; 1148 } 1149 break; 1150 case ESP_RFLAGS: 1151 /* Bottom 5 bits indicate number of bytes in FIFO */ 1152 val = fifo8_num_used(&s->fifo); 1153 break; 1154 default: 1155 val = s->rregs[saddr]; 1156 break; 1157 } 1158 1159 trace_esp_mem_readb(saddr, val); 1160 return val; 1161 } 1162 1163 void esp_reg_write(ESPState *s, uint32_t saddr, uint64_t val) 1164 { 1165 trace_esp_mem_writeb(saddr, s->wregs[saddr], val); 1166 switch (saddr) { 1167 case ESP_TCHI: 1168 s->tchi_written = true; 1169 /* fall through */ 1170 case ESP_TCLO: 1171 case ESP_TCMID: 1172 s->rregs[ESP_RSTAT] &= ~STAT_TC; 1173 break; 1174 case ESP_FIFO: 1175 if (s->do_cmd) { 1176 if (!fifo8_is_full(&s->fifo)) { 1177 esp_fifo_push(&s->fifo, val); 1178 esp_fifo_push(&s->cmdfifo, fifo8_pop(&s->fifo)); 1179 } 1180 1181 /* 1182 * If any unexpected message out/command phase data is 1183 * transferred using non-DMA, raise the interrupt 1184 */ 1185 if (s->rregs[ESP_CMD] == CMD_TI) { 1186 s->rregs[ESP_RINTR] |= INTR_BS; 1187 esp_raise_irq(s); 1188 } 1189 } else { 1190 esp_fifo_push(&s->fifo, val); 1191 } 1192 break; 1193 case ESP_CMD: 1194 s->rregs[saddr] = val; 1195 esp_run_cmd(s); 1196 break; 1197 case ESP_WBUSID ... ESP_WSYNO: 1198 break; 1199 case ESP_CFG1: 1200 case ESP_CFG2: case ESP_CFG3: 1201 case ESP_RES3: case ESP_RES4: 1202 s->rregs[saddr] = val; 1203 break; 1204 case ESP_WCCF ... ESP_WTEST: 1205 break; 1206 default: 1207 trace_esp_error_invalid_write(val, saddr); 1208 return; 1209 } 1210 s->wregs[saddr] = val; 1211 } 1212 1213 static bool esp_mem_accepts(void *opaque, hwaddr addr, 1214 unsigned size, bool is_write, 1215 MemTxAttrs attrs) 1216 { 1217 return (size == 1) || (is_write && size == 4); 1218 } 1219 1220 static bool esp_is_before_version_5(void *opaque, int version_id) 1221 { 1222 ESPState *s = ESP(opaque); 1223 1224 version_id = MIN(version_id, s->mig_version_id); 1225 return version_id < 5; 1226 } 1227 1228 static bool esp_is_version_5(void *opaque, int version_id) 1229 { 1230 ESPState *s = ESP(opaque); 1231 1232 version_id = MIN(version_id, s->mig_version_id); 1233 return version_id >= 5; 1234 } 1235 1236 static bool esp_is_version_6(void *opaque, int version_id) 1237 { 1238 ESPState *s = ESP(opaque); 1239 1240 version_id = MIN(version_id, s->mig_version_id); 1241 return version_id >= 6; 1242 } 1243 1244 int esp_pre_save(void *opaque) 1245 { 1246 ESPState *s = ESP(object_resolve_path_component( 1247 OBJECT(opaque), "esp")); 1248 1249 s->mig_version_id = vmstate_esp.version_id; 1250 return 0; 1251 } 1252 1253 static int esp_post_load(void *opaque, int version_id) 1254 { 1255 ESPState *s = ESP(opaque); 1256 int len, i; 1257 1258 version_id = MIN(version_id, s->mig_version_id); 1259 1260 if (version_id < 5) { 1261 esp_set_tc(s, s->mig_dma_left); 1262 1263 /* Migrate ti_buf to fifo */ 1264 len = s->mig_ti_wptr - s->mig_ti_rptr; 1265 for (i = 0; i < len; i++) { 1266 fifo8_push(&s->fifo, s->mig_ti_buf[i]); 1267 } 1268 1269 /* Migrate cmdbuf to cmdfifo */ 1270 for (i = 0; i < s->mig_cmdlen; i++) { 1271 fifo8_push(&s->cmdfifo, s->mig_cmdbuf[i]); 1272 } 1273 } 1274 1275 s->mig_version_id = vmstate_esp.version_id; 1276 return 0; 1277 } 1278 1279 /* 1280 * PDMA (or pseudo-DMA) is only used on the Macintosh and requires the 1281 * guest CPU to perform the transfers between the SCSI bus and memory 1282 * itself. This is indicated by the dma_memory_read and dma_memory_write 1283 * functions being NULL (in contrast to the ESP PCI device) whilst 1284 * dma_enabled is still set. 1285 */ 1286 1287 static bool esp_pdma_needed(void *opaque) 1288 { 1289 ESPState *s = ESP(opaque); 1290 1291 return s->dma_memory_read == NULL && s->dma_memory_write == NULL && 1292 s->dma_enabled; 1293 } 1294 1295 static const VMStateDescription vmstate_esp_pdma = { 1296 .name = "esp/pdma", 1297 .version_id = 0, 1298 .minimum_version_id = 0, 1299 .needed = esp_pdma_needed, 1300 .fields = (const VMStateField[]) { 1301 VMSTATE_UINT8(pdma_cb, ESPState), 1302 VMSTATE_END_OF_LIST() 1303 } 1304 }; 1305 1306 const VMStateDescription vmstate_esp = { 1307 .name = "esp", 1308 .version_id = 6, 1309 .minimum_version_id = 3, 1310 .post_load = esp_post_load, 1311 .fields = (const VMStateField[]) { 1312 VMSTATE_BUFFER(rregs, ESPState), 1313 VMSTATE_BUFFER(wregs, ESPState), 1314 VMSTATE_INT32(ti_size, ESPState), 1315 VMSTATE_UINT32_TEST(mig_ti_rptr, ESPState, esp_is_before_version_5), 1316 VMSTATE_UINT32_TEST(mig_ti_wptr, ESPState, esp_is_before_version_5), 1317 VMSTATE_BUFFER_TEST(mig_ti_buf, ESPState, esp_is_before_version_5), 1318 VMSTATE_UINT32(status, ESPState), 1319 VMSTATE_UINT32_TEST(mig_deferred_status, ESPState, 1320 esp_is_before_version_5), 1321 VMSTATE_BOOL_TEST(mig_deferred_complete, ESPState, 1322 esp_is_before_version_5), 1323 VMSTATE_UINT32(dma, ESPState), 1324 VMSTATE_STATIC_BUFFER(mig_cmdbuf, ESPState, 0, 1325 esp_is_before_version_5, 0, 16), 1326 VMSTATE_STATIC_BUFFER(mig_cmdbuf, ESPState, 4, 1327 esp_is_before_version_5, 16, 1328 sizeof(typeof_field(ESPState, mig_cmdbuf))), 1329 VMSTATE_UINT32_TEST(mig_cmdlen, ESPState, esp_is_before_version_5), 1330 VMSTATE_UINT32(do_cmd, ESPState), 1331 VMSTATE_UINT32_TEST(mig_dma_left, ESPState, esp_is_before_version_5), 1332 VMSTATE_BOOL_TEST(data_in_ready, ESPState, esp_is_version_5), 1333 VMSTATE_UINT8_TEST(cmdfifo_cdb_offset, ESPState, esp_is_version_5), 1334 VMSTATE_FIFO8_TEST(fifo, ESPState, esp_is_version_5), 1335 VMSTATE_FIFO8_TEST(cmdfifo, ESPState, esp_is_version_5), 1336 VMSTATE_UINT8_TEST(ti_cmd, ESPState, esp_is_version_5), 1337 VMSTATE_UINT8_TEST(lun, ESPState, esp_is_version_6), 1338 VMSTATE_END_OF_LIST() 1339 }, 1340 .subsections = (const VMStateDescription * const []) { 1341 &vmstate_esp_pdma, 1342 NULL 1343 } 1344 }; 1345 1346 static void sysbus_esp_mem_write(void *opaque, hwaddr addr, 1347 uint64_t val, unsigned int size) 1348 { 1349 SysBusESPState *sysbus = opaque; 1350 ESPState *s = ESP(&sysbus->esp); 1351 uint32_t saddr; 1352 1353 saddr = addr >> sysbus->it_shift; 1354 esp_reg_write(s, saddr, val); 1355 } 1356 1357 static uint64_t sysbus_esp_mem_read(void *opaque, hwaddr addr, 1358 unsigned int size) 1359 { 1360 SysBusESPState *sysbus = opaque; 1361 ESPState *s = ESP(&sysbus->esp); 1362 uint32_t saddr; 1363 1364 saddr = addr >> sysbus->it_shift; 1365 return esp_reg_read(s, saddr); 1366 } 1367 1368 static const MemoryRegionOps sysbus_esp_mem_ops = { 1369 .read = sysbus_esp_mem_read, 1370 .write = sysbus_esp_mem_write, 1371 .endianness = DEVICE_NATIVE_ENDIAN, 1372 .valid.accepts = esp_mem_accepts, 1373 }; 1374 1375 static void sysbus_esp_pdma_write(void *opaque, hwaddr addr, 1376 uint64_t val, unsigned int size) 1377 { 1378 SysBusESPState *sysbus = opaque; 1379 ESPState *s = ESP(&sysbus->esp); 1380 1381 trace_esp_pdma_write(size); 1382 1383 switch (size) { 1384 case 1: 1385 esp_pdma_write(s, val); 1386 break; 1387 case 2: 1388 esp_pdma_write(s, val >> 8); 1389 esp_pdma_write(s, val); 1390 break; 1391 } 1392 esp_pdma_cb(s); 1393 } 1394 1395 static uint64_t sysbus_esp_pdma_read(void *opaque, hwaddr addr, 1396 unsigned int size) 1397 { 1398 SysBusESPState *sysbus = opaque; 1399 ESPState *s = ESP(&sysbus->esp); 1400 uint64_t val = 0; 1401 1402 trace_esp_pdma_read(size); 1403 1404 switch (size) { 1405 case 1: 1406 val = esp_pdma_read(s); 1407 break; 1408 case 2: 1409 val = esp_pdma_read(s); 1410 val = (val << 8) | esp_pdma_read(s); 1411 break; 1412 } 1413 esp_pdma_cb(s); 1414 return val; 1415 } 1416 1417 static void *esp_load_request(QEMUFile *f, SCSIRequest *req) 1418 { 1419 ESPState *s = container_of(req->bus, ESPState, bus); 1420 1421 scsi_req_ref(req); 1422 s->current_req = req; 1423 return s; 1424 } 1425 1426 static const MemoryRegionOps sysbus_esp_pdma_ops = { 1427 .read = sysbus_esp_pdma_read, 1428 .write = sysbus_esp_pdma_write, 1429 .endianness = DEVICE_NATIVE_ENDIAN, 1430 .valid.min_access_size = 1, 1431 .valid.max_access_size = 4, 1432 .impl.min_access_size = 1, 1433 .impl.max_access_size = 2, 1434 }; 1435 1436 static const struct SCSIBusInfo esp_scsi_info = { 1437 .tcq = false, 1438 .max_target = ESP_MAX_DEVS, 1439 .max_lun = 7, 1440 1441 .load_request = esp_load_request, 1442 .transfer_data = esp_transfer_data, 1443 .complete = esp_command_complete, 1444 .cancel = esp_request_cancelled 1445 }; 1446 1447 static void sysbus_esp_gpio_demux(void *opaque, int irq, int level) 1448 { 1449 SysBusESPState *sysbus = SYSBUS_ESP(opaque); 1450 ESPState *s = ESP(&sysbus->esp); 1451 1452 switch (irq) { 1453 case 0: 1454 parent_esp_reset(s, irq, level); 1455 break; 1456 case 1: 1457 esp_dma_enable(s, irq, level); 1458 break; 1459 } 1460 } 1461 1462 static void sysbus_esp_realize(DeviceState *dev, Error **errp) 1463 { 1464 SysBusDevice *sbd = SYS_BUS_DEVICE(dev); 1465 SysBusESPState *sysbus = SYSBUS_ESP(dev); 1466 ESPState *s = ESP(&sysbus->esp); 1467 1468 if (!qdev_realize(DEVICE(s), NULL, errp)) { 1469 return; 1470 } 1471 1472 sysbus_init_irq(sbd, &s->irq); 1473 sysbus_init_irq(sbd, &s->irq_data); 1474 assert(sysbus->it_shift != -1); 1475 1476 s->chip_id = TCHI_FAS100A; 1477 memory_region_init_io(&sysbus->iomem, OBJECT(sysbus), &sysbus_esp_mem_ops, 1478 sysbus, "esp-regs", ESP_REGS << sysbus->it_shift); 1479 sysbus_init_mmio(sbd, &sysbus->iomem); 1480 memory_region_init_io(&sysbus->pdma, OBJECT(sysbus), &sysbus_esp_pdma_ops, 1481 sysbus, "esp-pdma", 4); 1482 sysbus_init_mmio(sbd, &sysbus->pdma); 1483 1484 qdev_init_gpio_in(dev, sysbus_esp_gpio_demux, 2); 1485 1486 scsi_bus_init(&s->bus, sizeof(s->bus), dev, &esp_scsi_info); 1487 } 1488 1489 static void sysbus_esp_hard_reset(DeviceState *dev) 1490 { 1491 SysBusESPState *sysbus = SYSBUS_ESP(dev); 1492 ESPState *s = ESP(&sysbus->esp); 1493 1494 esp_hard_reset(s); 1495 } 1496 1497 static void sysbus_esp_init(Object *obj) 1498 { 1499 SysBusESPState *sysbus = SYSBUS_ESP(obj); 1500 1501 object_initialize_child(obj, "esp", &sysbus->esp, TYPE_ESP); 1502 } 1503 1504 static const VMStateDescription vmstate_sysbus_esp_scsi = { 1505 .name = "sysbusespscsi", 1506 .version_id = 2, 1507 .minimum_version_id = 1, 1508 .pre_save = esp_pre_save, 1509 .fields = (const VMStateField[]) { 1510 VMSTATE_UINT8_V(esp.mig_version_id, SysBusESPState, 2), 1511 VMSTATE_STRUCT(esp, SysBusESPState, 0, vmstate_esp, ESPState), 1512 VMSTATE_END_OF_LIST() 1513 } 1514 }; 1515 1516 static void sysbus_esp_class_init(ObjectClass *klass, void *data) 1517 { 1518 DeviceClass *dc = DEVICE_CLASS(klass); 1519 1520 dc->realize = sysbus_esp_realize; 1521 dc->reset = sysbus_esp_hard_reset; 1522 dc->vmsd = &vmstate_sysbus_esp_scsi; 1523 set_bit(DEVICE_CATEGORY_STORAGE, dc->categories); 1524 } 1525 1526 static const TypeInfo sysbus_esp_info = { 1527 .name = TYPE_SYSBUS_ESP, 1528 .parent = TYPE_SYS_BUS_DEVICE, 1529 .instance_init = sysbus_esp_init, 1530 .instance_size = sizeof(SysBusESPState), 1531 .class_init = sysbus_esp_class_init, 1532 }; 1533 1534 static void esp_finalize(Object *obj) 1535 { 1536 ESPState *s = ESP(obj); 1537 1538 fifo8_destroy(&s->fifo); 1539 fifo8_destroy(&s->cmdfifo); 1540 } 1541 1542 static void esp_init(Object *obj) 1543 { 1544 ESPState *s = ESP(obj); 1545 1546 fifo8_create(&s->fifo, ESP_FIFO_SZ); 1547 fifo8_create(&s->cmdfifo, ESP_CMDFIFO_SZ); 1548 } 1549 1550 static void esp_class_init(ObjectClass *klass, void *data) 1551 { 1552 DeviceClass *dc = DEVICE_CLASS(klass); 1553 1554 /* internal device for sysbusesp/pciespscsi, not user-creatable */ 1555 dc->user_creatable = false; 1556 set_bit(DEVICE_CATEGORY_STORAGE, dc->categories); 1557 } 1558 1559 static const TypeInfo esp_info = { 1560 .name = TYPE_ESP, 1561 .parent = TYPE_DEVICE, 1562 .instance_init = esp_init, 1563 .instance_finalize = esp_finalize, 1564 .instance_size = sizeof(ESPState), 1565 .class_init = esp_class_init, 1566 }; 1567 1568 static void esp_register_types(void) 1569 { 1570 type_register_static(&sysbus_esp_info); 1571 type_register_static(&esp_info); 1572 } 1573 1574 type_init(esp_register_types) 1575