1 /* 2 * QEMU ESP/NCR53C9x emulation 3 * 4 * Copyright (c) 2005-2006 Fabrice Bellard 5 * Copyright (c) 2012 Herve Poussineau 6 * 7 * Permission is hereby granted, free of charge, to any person obtaining a copy 8 * of this software and associated documentation files (the "Software"), to deal 9 * in the Software without restriction, including without limitation the rights 10 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 11 * copies of the Software, and to permit persons to whom the Software is 12 * furnished to do so, subject to the following conditions: 13 * 14 * The above copyright notice and this permission notice shall be included in 15 * all copies or substantial portions of the Software. 16 * 17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 22 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 23 * THE SOFTWARE. 24 */ 25 26 #include "qemu/osdep.h" 27 #include "hw/sysbus.h" 28 #include "migration/vmstate.h" 29 #include "hw/irq.h" 30 #include "hw/scsi/esp.h" 31 #include "trace.h" 32 #include "qemu/log.h" 33 #include "qemu/module.h" 34 35 /* 36 * On Sparc32, this is the ESP (NCR53C90) part of chip STP2000 (Master I/O), 37 * also produced as NCR89C100. See 38 * http://www.ibiblio.org/pub/historic-linux/early-ports/Sparc/NCR/NCR89C100.txt 39 * and 40 * http://www.ibiblio.org/pub/historic-linux/early-ports/Sparc/NCR/NCR53C9X.txt 41 * 42 * On Macintosh Quadra it is a NCR53C96. 43 */ 44 45 static void esp_raise_irq(ESPState *s) 46 { 47 if (!(s->rregs[ESP_RSTAT] & STAT_INT)) { 48 s->rregs[ESP_RSTAT] |= STAT_INT; 49 qemu_irq_raise(s->irq); 50 trace_esp_raise_irq(); 51 } 52 } 53 54 static void esp_lower_irq(ESPState *s) 55 { 56 if (s->rregs[ESP_RSTAT] & STAT_INT) { 57 s->rregs[ESP_RSTAT] &= ~STAT_INT; 58 qemu_irq_lower(s->irq); 59 trace_esp_lower_irq(); 60 } 61 } 62 63 static void esp_raise_drq(ESPState *s) 64 { 65 qemu_irq_raise(s->irq_data); 66 trace_esp_raise_drq(); 67 } 68 69 static void esp_lower_drq(ESPState *s) 70 { 71 qemu_irq_lower(s->irq_data); 72 trace_esp_lower_drq(); 73 } 74 75 void esp_dma_enable(ESPState *s, int irq, int level) 76 { 77 if (level) { 78 s->dma_enabled = 1; 79 trace_esp_dma_enable(); 80 if (s->dma_cb) { 81 s->dma_cb(s); 82 s->dma_cb = NULL; 83 } 84 } else { 85 trace_esp_dma_disable(); 86 s->dma_enabled = 0; 87 } 88 } 89 90 void esp_request_cancelled(SCSIRequest *req) 91 { 92 ESPState *s = req->hba_private; 93 94 if (req == s->current_req) { 95 scsi_req_unref(s->current_req); 96 s->current_req = NULL; 97 s->current_dev = NULL; 98 s->async_len = 0; 99 } 100 } 101 102 static void esp_fifo_push(Fifo8 *fifo, uint8_t val) 103 { 104 if (fifo8_num_used(fifo) == fifo->capacity) { 105 trace_esp_error_fifo_overrun(); 106 return; 107 } 108 109 fifo8_push(fifo, val); 110 } 111 112 static uint8_t esp_fifo_pop(Fifo8 *fifo) 113 { 114 if (fifo8_is_empty(fifo)) { 115 return 0; 116 } 117 118 return fifo8_pop(fifo); 119 } 120 121 static uint32_t esp_fifo_pop_buf(Fifo8 *fifo, uint8_t *dest, int maxlen) 122 { 123 const uint8_t *buf; 124 uint32_t n, n2; 125 int len; 126 127 if (maxlen == 0) { 128 return 0; 129 } 130 131 len = maxlen; 132 buf = fifo8_pop_buf(fifo, len, &n); 133 if (dest) { 134 memcpy(dest, buf, n); 135 } 136 137 /* Add FIFO wraparound if needed */ 138 len -= n; 139 len = MIN(len, fifo8_num_used(fifo)); 140 if (len) { 141 buf = fifo8_pop_buf(fifo, len, &n2); 142 if (dest) { 143 memcpy(&dest[n], buf, n2); 144 } 145 n += n2; 146 } 147 148 return n; 149 } 150 151 static uint32_t esp_get_tc(ESPState *s) 152 { 153 uint32_t dmalen; 154 155 dmalen = s->rregs[ESP_TCLO]; 156 dmalen |= s->rregs[ESP_TCMID] << 8; 157 dmalen |= s->rregs[ESP_TCHI] << 16; 158 159 return dmalen; 160 } 161 162 static void esp_set_tc(ESPState *s, uint32_t dmalen) 163 { 164 uint32_t old_tc = esp_get_tc(s); 165 166 s->rregs[ESP_TCLO] = dmalen; 167 s->rregs[ESP_TCMID] = dmalen >> 8; 168 s->rregs[ESP_TCHI] = dmalen >> 16; 169 170 if (old_tc && dmalen == 0) { 171 s->rregs[ESP_RSTAT] |= STAT_TC; 172 } 173 } 174 175 static uint32_t esp_get_stc(ESPState *s) 176 { 177 uint32_t dmalen; 178 179 dmalen = s->wregs[ESP_TCLO]; 180 dmalen |= s->wregs[ESP_TCMID] << 8; 181 dmalen |= s->wregs[ESP_TCHI] << 16; 182 183 return dmalen; 184 } 185 186 static const char *esp_phase_names[8] = { 187 "DATA OUT", "DATA IN", "COMMAND", "STATUS", 188 "(reserved)", "(reserved)", "MESSAGE OUT", "MESSAGE IN" 189 }; 190 191 static void esp_set_phase(ESPState *s, uint8_t phase) 192 { 193 s->rregs[ESP_RSTAT] &= ~7; 194 s->rregs[ESP_RSTAT] |= phase; 195 196 trace_esp_set_phase(esp_phase_names[phase]); 197 } 198 199 static uint8_t esp_get_phase(ESPState *s) 200 { 201 return s->rregs[ESP_RSTAT] & 7; 202 } 203 204 static uint8_t esp_pdma_read(ESPState *s) 205 { 206 uint8_t val; 207 208 val = esp_fifo_pop(&s->fifo); 209 return val; 210 } 211 212 static void esp_pdma_write(ESPState *s, uint8_t val) 213 { 214 uint32_t dmalen = esp_get_tc(s); 215 216 if (dmalen == 0) { 217 return; 218 } 219 220 esp_fifo_push(&s->fifo, val); 221 222 dmalen--; 223 esp_set_tc(s, dmalen); 224 } 225 226 static void esp_set_pdma_cb(ESPState *s, enum pdma_cb cb) 227 { 228 s->pdma_cb = cb; 229 } 230 231 static int esp_select(ESPState *s) 232 { 233 int target; 234 235 target = s->wregs[ESP_WBUSID] & BUSID_DID; 236 237 s->ti_size = 0; 238 239 if (s->current_req) { 240 /* Started a new command before the old one finished. Cancel it. */ 241 scsi_req_cancel(s->current_req); 242 } 243 244 s->current_dev = scsi_device_find(&s->bus, 0, target, 0); 245 if (!s->current_dev) { 246 /* No such drive */ 247 s->rregs[ESP_RSTAT] = 0; 248 s->rregs[ESP_RINTR] = INTR_DC; 249 s->rregs[ESP_RSEQ] = SEQ_0; 250 esp_raise_irq(s); 251 return -1; 252 } 253 254 /* 255 * Note that we deliberately don't raise the IRQ here: this will be done 256 * either in do_command_phase() for DATA OUT transfers or by the deferred 257 * IRQ mechanism in esp_transfer_data() for DATA IN transfers 258 */ 259 s->rregs[ESP_RINTR] |= INTR_FC; 260 s->rregs[ESP_RSEQ] = SEQ_CD; 261 return 0; 262 } 263 264 static uint32_t get_cmd(ESPState *s, uint32_t maxlen) 265 { 266 uint8_t buf[ESP_CMDFIFO_SZ]; 267 uint32_t dmalen, n; 268 int target; 269 270 target = s->wregs[ESP_WBUSID] & BUSID_DID; 271 if (s->dma) { 272 dmalen = MIN(esp_get_tc(s), maxlen); 273 if (dmalen == 0) { 274 return 0; 275 } 276 if (s->dma_memory_read) { 277 s->dma_memory_read(s->dma_opaque, buf, dmalen); 278 dmalen = MIN(fifo8_num_free(&s->cmdfifo), dmalen); 279 fifo8_push_all(&s->cmdfifo, buf, dmalen); 280 esp_set_tc(s, esp_get_tc(s) - dmalen); 281 } else { 282 return 0; 283 } 284 } else { 285 dmalen = MIN(fifo8_num_used(&s->fifo), maxlen); 286 if (dmalen == 0) { 287 return 0; 288 } 289 n = esp_fifo_pop_buf(&s->fifo, buf, dmalen); 290 n = MIN(fifo8_num_free(&s->cmdfifo), n); 291 fifo8_push_all(&s->cmdfifo, buf, n); 292 } 293 trace_esp_get_cmd(dmalen, target); 294 295 return dmalen; 296 } 297 298 static void do_command_phase(ESPState *s) 299 { 300 uint32_t cmdlen; 301 int32_t datalen; 302 SCSIDevice *current_lun; 303 uint8_t buf[ESP_CMDFIFO_SZ]; 304 305 trace_esp_do_command_phase(s->lun); 306 cmdlen = fifo8_num_used(&s->cmdfifo); 307 if (!cmdlen || !s->current_dev) { 308 return; 309 } 310 esp_fifo_pop_buf(&s->cmdfifo, buf, cmdlen); 311 312 current_lun = scsi_device_find(&s->bus, 0, s->current_dev->id, s->lun); 313 if (!current_lun) { 314 /* No such drive */ 315 s->rregs[ESP_RSTAT] = 0; 316 s->rregs[ESP_RINTR] = INTR_DC; 317 s->rregs[ESP_RSEQ] = SEQ_0; 318 esp_raise_irq(s); 319 return; 320 } 321 322 s->current_req = scsi_req_new(current_lun, 0, s->lun, buf, cmdlen, s); 323 datalen = scsi_req_enqueue(s->current_req); 324 s->ti_size = datalen; 325 fifo8_reset(&s->cmdfifo); 326 if (datalen != 0) { 327 s->ti_cmd = 0; 328 if (datalen > 0) { 329 /* 330 * Switch to DATA IN phase but wait until initial data xfer is 331 * complete before raising the command completion interrupt 332 */ 333 s->data_in_ready = false; 334 esp_set_phase(s, STAT_DI); 335 } else { 336 esp_set_phase(s, STAT_DO); 337 s->rregs[ESP_RINTR] |= INTR_BS | INTR_FC; 338 esp_raise_irq(s); 339 esp_lower_drq(s); 340 } 341 scsi_req_continue(s->current_req); 342 return; 343 } 344 } 345 346 static void do_message_phase(ESPState *s) 347 { 348 if (s->cmdfifo_cdb_offset) { 349 uint8_t message = esp_fifo_pop(&s->cmdfifo); 350 351 trace_esp_do_identify(message); 352 s->lun = message & 7; 353 s->cmdfifo_cdb_offset--; 354 } 355 356 /* Ignore extended messages for now */ 357 if (s->cmdfifo_cdb_offset) { 358 int len = MIN(s->cmdfifo_cdb_offset, fifo8_num_used(&s->cmdfifo)); 359 esp_fifo_pop_buf(&s->cmdfifo, NULL, len); 360 s->cmdfifo_cdb_offset = 0; 361 } 362 } 363 364 static void do_cmd(ESPState *s) 365 { 366 do_message_phase(s); 367 assert(s->cmdfifo_cdb_offset == 0); 368 do_command_phase(s); 369 } 370 371 static void satn_pdma_cb(ESPState *s) 372 { 373 uint8_t buf[ESP_FIFO_SZ]; 374 int n; 375 376 /* Copy FIFO into cmdfifo */ 377 n = esp_fifo_pop_buf(&s->fifo, buf, fifo8_num_used(&s->fifo)); 378 n = MIN(fifo8_num_free(&s->cmdfifo), n); 379 fifo8_push_all(&s->cmdfifo, buf, n); 380 381 if (!esp_get_tc(s) && !fifo8_is_empty(&s->cmdfifo)) { 382 s->cmdfifo_cdb_offset = 1; 383 s->do_cmd = 0; 384 do_cmd(s); 385 } 386 } 387 388 static void handle_satn(ESPState *s) 389 { 390 int32_t cmdlen; 391 392 if (s->dma && !s->dma_enabled) { 393 s->dma_cb = handle_satn; 394 return; 395 } 396 esp_set_pdma_cb(s, SATN_PDMA_CB); 397 if (esp_select(s) < 0) { 398 return; 399 } 400 cmdlen = get_cmd(s, ESP_CMDFIFO_SZ); 401 if (cmdlen > 0) { 402 s->cmdfifo_cdb_offset = 1; 403 s->do_cmd = 0; 404 do_cmd(s); 405 } else if (cmdlen == 0) { 406 if (s->dma) { 407 esp_raise_drq(s); 408 } 409 s->do_cmd = 1; 410 /* Target present, but no cmd yet - switch to command phase */ 411 s->rregs[ESP_RSEQ] = SEQ_CD; 412 esp_set_phase(s, STAT_CD); 413 } 414 } 415 416 static void handle_s_without_atn(ESPState *s) 417 { 418 int32_t cmdlen; 419 420 if (s->dma && !s->dma_enabled) { 421 s->dma_cb = handle_s_without_atn; 422 return; 423 } 424 esp_set_pdma_cb(s, DO_DMA_PDMA_CB); 425 if (esp_select(s) < 0) { 426 return; 427 } 428 cmdlen = get_cmd(s, ESP_CMDFIFO_SZ); 429 if (cmdlen > 0) { 430 s->cmdfifo_cdb_offset = 0; 431 s->do_cmd = 0; 432 do_cmd(s); 433 } else if (cmdlen == 0) { 434 if (s->dma) { 435 esp_raise_drq(s); 436 } 437 s->do_cmd = 1; 438 /* Target present, but no cmd yet - switch to command phase */ 439 s->rregs[ESP_RSEQ] = SEQ_CD; 440 esp_set_phase(s, STAT_CD); 441 } 442 } 443 444 static void satn_stop_pdma_cb(ESPState *s) 445 { 446 uint8_t buf[ESP_FIFO_SZ]; 447 int n; 448 449 /* Copy FIFO into cmdfifo */ 450 n = esp_fifo_pop_buf(&s->fifo, buf, fifo8_num_used(&s->fifo)); 451 n = MIN(fifo8_num_free(&s->cmdfifo), n); 452 fifo8_push_all(&s->cmdfifo, buf, n); 453 454 if (!esp_get_tc(s) && !fifo8_is_empty(&s->cmdfifo)) { 455 trace_esp_handle_satn_stop(fifo8_num_used(&s->cmdfifo)); 456 s->do_cmd = 1; 457 s->cmdfifo_cdb_offset = 1; 458 esp_set_phase(s, STAT_CD); 459 s->rregs[ESP_RSTAT] |= STAT_TC; 460 s->rregs[ESP_RINTR] |= INTR_BS | INTR_FC; 461 s->rregs[ESP_RSEQ] = SEQ_CD; 462 esp_raise_irq(s); 463 } 464 } 465 466 static void handle_satn_stop(ESPState *s) 467 { 468 int32_t cmdlen; 469 470 if (s->dma && !s->dma_enabled) { 471 s->dma_cb = handle_satn_stop; 472 return; 473 } 474 esp_set_pdma_cb(s, SATN_STOP_PDMA_CB); 475 if (esp_select(s) < 0) { 476 return; 477 } 478 cmdlen = get_cmd(s, 1); 479 if (cmdlen > 0) { 480 trace_esp_handle_satn_stop(fifo8_num_used(&s->cmdfifo)); 481 s->do_cmd = 1; 482 s->cmdfifo_cdb_offset = 1; 483 esp_set_phase(s, STAT_MO); 484 s->rregs[ESP_RINTR] |= INTR_BS | INTR_FC; 485 s->rregs[ESP_RSEQ] = SEQ_MO; 486 esp_raise_irq(s); 487 } else if (cmdlen == 0) { 488 if (s->dma) { 489 esp_raise_drq(s); 490 } 491 s->do_cmd = 1; 492 /* Target present, switch to message out phase */ 493 s->rregs[ESP_RSEQ] = SEQ_MO; 494 esp_set_phase(s, STAT_MO); 495 } 496 } 497 498 static void write_response_pdma_cb(ESPState *s) 499 { 500 esp_set_phase(s, STAT_ST); 501 s->rregs[ESP_RINTR] |= INTR_BS | INTR_FC; 502 s->rregs[ESP_RSEQ] = SEQ_CD; 503 esp_raise_irq(s); 504 } 505 506 static void write_response(ESPState *s) 507 { 508 uint8_t buf[2]; 509 510 trace_esp_write_response(s->status); 511 512 buf[0] = s->status; 513 buf[1] = 0; 514 515 if (s->dma) { 516 if (s->dma_memory_write) { 517 s->dma_memory_write(s->dma_opaque, buf, 2); 518 esp_set_phase(s, STAT_ST); 519 s->rregs[ESP_RINTR] |= INTR_BS | INTR_FC; 520 s->rregs[ESP_RSEQ] = SEQ_CD; 521 } else { 522 esp_set_pdma_cb(s, WRITE_RESPONSE_PDMA_CB); 523 esp_raise_drq(s); 524 return; 525 } 526 } else { 527 fifo8_reset(&s->fifo); 528 fifo8_push_all(&s->fifo, buf, 2); 529 s->rregs[ESP_RFLAGS] = 2; 530 } 531 esp_raise_irq(s); 532 } 533 534 static void esp_dma_ti_check(ESPState *s) 535 { 536 if (esp_get_tc(s) == 0 && fifo8_num_used(&s->fifo) < 2) { 537 s->rregs[ESP_RINTR] |= INTR_BS; 538 esp_raise_irq(s); 539 esp_lower_drq(s); 540 } 541 } 542 543 static void do_dma_pdma_cb(ESPState *s) 544 { 545 uint8_t buf[ESP_CMDFIFO_SZ]; 546 int len; 547 uint32_t n; 548 549 if (s->do_cmd) { 550 /* Copy FIFO into cmdfifo */ 551 n = esp_fifo_pop_buf(&s->fifo, buf, fifo8_num_used(&s->fifo)); 552 n = MIN(fifo8_num_free(&s->cmdfifo), n); 553 fifo8_push_all(&s->cmdfifo, buf, n); 554 555 /* Ensure we have received complete command after SATN and stop */ 556 if (esp_get_tc(s) || fifo8_is_empty(&s->cmdfifo)) { 557 return; 558 } 559 560 s->ti_size = 0; 561 if (esp_get_phase(s) == STAT_CD) { 562 /* No command received */ 563 if (s->cmdfifo_cdb_offset == fifo8_num_used(&s->cmdfifo)) { 564 return; 565 } 566 567 /* Command has been received */ 568 s->do_cmd = 0; 569 do_cmd(s); 570 } else { 571 /* 572 * Extra message out bytes received: update cmdfifo_cdb_offset 573 * and then switch to command phase 574 */ 575 s->cmdfifo_cdb_offset = fifo8_num_used(&s->cmdfifo); 576 esp_set_phase(s, STAT_CD); 577 s->rregs[ESP_RSEQ] = SEQ_CD; 578 s->rregs[ESP_RINTR] |= INTR_BS; 579 esp_raise_irq(s); 580 } 581 return; 582 } 583 584 switch (esp_get_phase(s)) { 585 case STAT_DO: 586 if (!s->current_req) { 587 return; 588 } 589 /* Copy FIFO data to device */ 590 len = MIN(s->async_len, ESP_FIFO_SZ); 591 len = MIN(len, fifo8_num_used(&s->fifo)); 592 n = esp_fifo_pop_buf(&s->fifo, s->async_buf, len); 593 s->async_buf += n; 594 s->async_len -= n; 595 s->ti_size += n; 596 597 if (s->async_len == 0 && fifo8_num_used(&s->fifo) < 2) { 598 /* Defer until the scsi layer has completed */ 599 scsi_req_continue(s->current_req); 600 return; 601 } 602 603 esp_dma_ti_check(s); 604 break; 605 606 case STAT_DI: 607 if (!s->current_req) { 608 return; 609 } 610 /* Copy device data to FIFO */ 611 len = MIN(s->async_len, esp_get_tc(s)); 612 len = MIN(len, fifo8_num_free(&s->fifo)); 613 fifo8_push_all(&s->fifo, s->async_buf, len); 614 s->async_buf += len; 615 s->async_len -= len; 616 s->ti_size -= len; 617 esp_set_tc(s, esp_get_tc(s) - len); 618 619 if (s->async_len == 0 && fifo8_num_used(&s->fifo) < 2) { 620 /* Defer until the scsi layer has completed */ 621 scsi_req_continue(s->current_req); 622 s->data_in_ready = false; 623 return; 624 } 625 626 esp_dma_ti_check(s); 627 break; 628 } 629 } 630 631 static void esp_do_dma(ESPState *s) 632 { 633 uint32_t len, cmdlen; 634 uint8_t buf[ESP_CMDFIFO_SZ]; 635 int n; 636 637 len = esp_get_tc(s); 638 if (s->do_cmd) { 639 /* 640 * handle_ti_cmd() case: esp_do_dma() is called only from 641 * handle_ti_cmd() with do_cmd != NULL (see the assert()) 642 */ 643 cmdlen = fifo8_num_used(&s->cmdfifo); 644 trace_esp_do_dma(cmdlen, len); 645 if (s->dma_memory_read) { 646 len = MIN(len, fifo8_num_free(&s->cmdfifo)); 647 s->dma_memory_read(s->dma_opaque, buf, len); 648 fifo8_push_all(&s->cmdfifo, buf, len); 649 esp_set_tc(s, esp_get_tc(s) - len); 650 } else { 651 n = esp_fifo_pop_buf(&s->fifo, buf, fifo8_num_used(&s->fifo)); 652 n = MIN(fifo8_num_free(&s->cmdfifo), n); 653 fifo8_push_all(&s->cmdfifo, buf, n); 654 esp_set_tc(s, esp_get_tc(s) - n); 655 656 esp_set_pdma_cb(s, DO_DMA_PDMA_CB); 657 esp_raise_drq(s); 658 659 /* Ensure we have received complete command after SATN and stop */ 660 if (esp_get_tc(s) || fifo8_is_empty(&s->cmdfifo)) { 661 return; 662 } 663 } 664 trace_esp_handle_ti_cmd(cmdlen); 665 s->ti_size = 0; 666 if (esp_get_phase(s) == STAT_CD) { 667 /* No command received */ 668 if (s->cmdfifo_cdb_offset == fifo8_num_used(&s->cmdfifo)) { 669 return; 670 } 671 672 /* Command has been received */ 673 s->do_cmd = 0; 674 do_cmd(s); 675 } else { 676 /* 677 * Extra message out bytes received: update cmdfifo_cdb_offset 678 * and then switch to command phase 679 */ 680 s->cmdfifo_cdb_offset = fifo8_num_used(&s->cmdfifo); 681 esp_set_phase(s, STAT_CD); 682 s->rregs[ESP_RSEQ] = SEQ_CD; 683 s->rregs[ESP_RINTR] |= INTR_BS; 684 esp_raise_irq(s); 685 } 686 return; 687 } 688 689 switch (esp_get_phase(s)) { 690 case STAT_DO: 691 if (!s->current_req) { 692 return; 693 } 694 if (s->async_len == 0 && esp_get_tc(s) && s->ti_size) { 695 /* Defer until data is available. */ 696 return; 697 } 698 if (len > s->async_len) { 699 len = s->async_len; 700 } 701 if (s->dma_memory_read) { 702 s->dma_memory_read(s->dma_opaque, s->async_buf, len); 703 704 esp_set_tc(s, esp_get_tc(s) - len); 705 s->async_buf += len; 706 s->async_len -= len; 707 s->ti_size += len; 708 709 if (s->async_len == 0 && fifo8_num_used(&s->fifo) < 2) { 710 /* Defer until the scsi layer has completed */ 711 scsi_req_continue(s->current_req); 712 return; 713 } 714 715 esp_dma_ti_check(s); 716 } else { 717 /* Copy FIFO data to device */ 718 len = MIN(s->async_len, ESP_FIFO_SZ); 719 len = MIN(len, fifo8_num_used(&s->fifo)); 720 n = esp_fifo_pop_buf(&s->fifo, s->async_buf, len); 721 s->async_buf += n; 722 s->async_len -= n; 723 s->ti_size += n; 724 725 esp_set_pdma_cb(s, DO_DMA_PDMA_CB); 726 esp_raise_drq(s); 727 728 if (s->async_len == 0 && fifo8_num_used(&s->fifo) < 2) { 729 /* Defer until the scsi layer has completed */ 730 scsi_req_continue(s->current_req); 731 return; 732 } 733 734 esp_dma_ti_check(s); 735 } 736 break; 737 738 case STAT_DI: 739 if (!s->current_req) { 740 return; 741 } 742 if (s->async_len == 0 && esp_get_tc(s) && s->ti_size) { 743 /* Defer until data is available. */ 744 return; 745 } 746 if (len > s->async_len) { 747 len = s->async_len; 748 } 749 if (s->dma_memory_write) { 750 s->dma_memory_write(s->dma_opaque, s->async_buf, len); 751 752 esp_set_tc(s, esp_get_tc(s) - len); 753 s->async_buf += len; 754 s->async_len -= len; 755 s->ti_size -= len; 756 757 if (s->async_len == 0 && fifo8_num_used(&s->fifo) < 2) { 758 /* Defer until the scsi layer has completed */ 759 scsi_req_continue(s->current_req); 760 return; 761 } 762 763 esp_dma_ti_check(s); 764 } else { 765 /* Copy device data to FIFO */ 766 len = MIN(len, fifo8_num_free(&s->fifo)); 767 fifo8_push_all(&s->fifo, s->async_buf, len); 768 s->async_buf += len; 769 s->async_len -= len; 770 s->ti_size -= len; 771 esp_set_tc(s, esp_get_tc(s) - len); 772 esp_set_pdma_cb(s, DO_DMA_PDMA_CB); 773 esp_raise_drq(s); 774 775 if (s->async_len == 0 && fifo8_num_used(&s->fifo) < 2) { 776 /* Defer until the scsi layer has completed */ 777 scsi_req_continue(s->current_req); 778 return; 779 } 780 781 esp_dma_ti_check(s); 782 } 783 break; 784 } 785 } 786 787 static void esp_do_nodma(ESPState *s) 788 { 789 uint8_t buf[ESP_FIFO_SZ]; 790 uint32_t cmdlen; 791 int len, n; 792 793 if (s->do_cmd) { 794 /* Copy FIFO into cmdfifo */ 795 n = esp_fifo_pop_buf(&s->fifo, buf, fifo8_num_used(&s->fifo)); 796 n = MIN(fifo8_num_free(&s->cmdfifo), n); 797 fifo8_push_all(&s->cmdfifo, buf, n); 798 799 cmdlen = fifo8_num_used(&s->cmdfifo); 800 trace_esp_handle_ti_cmd(cmdlen); 801 s->ti_size = 0; 802 if (esp_get_phase(s) == STAT_CD) { 803 /* No command received */ 804 if (s->cmdfifo_cdb_offset == fifo8_num_used(&s->cmdfifo)) { 805 return; 806 } 807 808 /* Command has been received */ 809 s->do_cmd = 0; 810 do_cmd(s); 811 } else { 812 /* 813 * Extra message out bytes received: update cmdfifo_cdb_offset 814 * and then switch to command phase 815 */ 816 s->cmdfifo_cdb_offset = fifo8_num_used(&s->cmdfifo); 817 esp_set_phase(s, STAT_CD); 818 s->rregs[ESP_RSEQ] = SEQ_CD; 819 s->rregs[ESP_RINTR] |= INTR_BS; 820 esp_raise_irq(s); 821 } 822 return; 823 } 824 825 switch (esp_get_phase(s)) { 826 case STAT_DO: 827 if (!s->current_req) { 828 return; 829 } 830 if (s->async_len == 0) { 831 /* Defer until data is available. */ 832 return; 833 } 834 len = MIN(s->async_len, ESP_FIFO_SZ); 835 len = MIN(len, fifo8_num_used(&s->fifo)); 836 esp_fifo_pop_buf(&s->fifo, s->async_buf, len); 837 s->async_buf += len; 838 s->async_len -= len; 839 s->ti_size += len; 840 841 if (s->async_len == 0) { 842 scsi_req_continue(s->current_req); 843 return; 844 } 845 846 s->rregs[ESP_RINTR] |= INTR_BS; 847 esp_raise_irq(s); 848 break; 849 850 case STAT_DI: 851 if (!s->current_req) { 852 return; 853 } 854 if (s->async_len == 0) { 855 /* Defer until data is available. */ 856 return; 857 } 858 if (fifo8_is_empty(&s->fifo)) { 859 fifo8_push(&s->fifo, s->async_buf[0]); 860 s->async_buf++; 861 s->async_len--; 862 s->ti_size--; 863 } 864 865 if (s->async_len == 0) { 866 scsi_req_continue(s->current_req); 867 return; 868 } 869 870 s->rregs[ESP_RINTR] |= INTR_BS; 871 esp_raise_irq(s); 872 break; 873 } 874 } 875 876 static void esp_pdma_cb(ESPState *s) 877 { 878 switch (s->pdma_cb) { 879 case SATN_PDMA_CB: 880 satn_pdma_cb(s); 881 break; 882 case SATN_STOP_PDMA_CB: 883 satn_stop_pdma_cb(s); 884 break; 885 case WRITE_RESPONSE_PDMA_CB: 886 write_response_pdma_cb(s); 887 break; 888 case DO_DMA_PDMA_CB: 889 do_dma_pdma_cb(s); 890 break; 891 default: 892 g_assert_not_reached(); 893 } 894 } 895 896 void esp_command_complete(SCSIRequest *req, size_t resid) 897 { 898 ESPState *s = req->hba_private; 899 int to_device = (esp_get_phase(s) == STAT_DO); 900 901 trace_esp_command_complete(); 902 903 /* 904 * Non-DMA transfers from the target will leave the last byte in 905 * the FIFO so don't reset ti_size in this case 906 */ 907 if (s->dma || to_device) { 908 if (s->ti_size != 0) { 909 trace_esp_command_complete_unexpected(); 910 } 911 } 912 913 s->async_len = 0; 914 if (req->status) { 915 trace_esp_command_complete_fail(); 916 } 917 s->status = req->status; 918 919 /* 920 * Switch to status phase. For non-DMA transfers from the target the last 921 * byte is still in the FIFO 922 */ 923 esp_set_phase(s, STAT_ST); 924 if (s->ti_size == 0) { 925 /* 926 * Transfer complete: force TC to zero just in case a TI command was 927 * requested for more data than the command returns (Solaris 8 does 928 * this) 929 */ 930 esp_set_tc(s, 0); 931 esp_dma_ti_check(s); 932 } else { 933 /* 934 * Transfer truncated: raise INTR_BS to indicate early change of 935 * phase 936 */ 937 s->rregs[ESP_RINTR] |= INTR_BS; 938 esp_raise_irq(s); 939 s->ti_size = 0; 940 } 941 942 if (s->current_req) { 943 scsi_req_unref(s->current_req); 944 s->current_req = NULL; 945 s->current_dev = NULL; 946 } 947 } 948 949 void esp_transfer_data(SCSIRequest *req, uint32_t len) 950 { 951 ESPState *s = req->hba_private; 952 int to_device = (esp_get_phase(s) == STAT_DO); 953 uint32_t dmalen = esp_get_tc(s); 954 955 assert(!s->do_cmd); 956 trace_esp_transfer_data(dmalen, s->ti_size); 957 s->async_len = len; 958 s->async_buf = scsi_req_get_buf(req); 959 960 if (!to_device && !s->data_in_ready) { 961 /* 962 * Initial incoming data xfer is complete so raise command 963 * completion interrupt 964 */ 965 s->data_in_ready = true; 966 s->rregs[ESP_RINTR] |= INTR_BS; 967 esp_raise_irq(s); 968 } 969 970 /* 971 * Always perform the initial transfer upon reception of the next TI 972 * command to ensure the DMA/non-DMA status of the command is correct. 973 * It is not possible to use s->dma directly in the section below as 974 * some OSs send non-DMA NOP commands after a DMA transfer. Hence if the 975 * async data transfer is delayed then s->dma is set incorrectly. 976 */ 977 978 if (s->ti_cmd == (CMD_TI | CMD_DMA)) { 979 /* When the SCSI layer returns more data, raise deferred INTR_BS */ 980 esp_dma_ti_check(s); 981 982 esp_do_dma(s); 983 } else if (s->ti_cmd == CMD_TI) { 984 esp_do_nodma(s); 985 } 986 } 987 988 static void handle_ti(ESPState *s) 989 { 990 uint32_t dmalen; 991 992 if (s->dma && !s->dma_enabled) { 993 s->dma_cb = handle_ti; 994 return; 995 } 996 997 s->ti_cmd = s->rregs[ESP_CMD]; 998 if (s->dma) { 999 dmalen = esp_get_tc(s); 1000 trace_esp_handle_ti(dmalen); 1001 esp_do_dma(s); 1002 } else { 1003 trace_esp_handle_ti(s->ti_size); 1004 esp_do_nodma(s); 1005 } 1006 } 1007 1008 void esp_hard_reset(ESPState *s) 1009 { 1010 memset(s->rregs, 0, ESP_REGS); 1011 memset(s->wregs, 0, ESP_REGS); 1012 s->tchi_written = 0; 1013 s->ti_size = 0; 1014 s->async_len = 0; 1015 fifo8_reset(&s->fifo); 1016 fifo8_reset(&s->cmdfifo); 1017 s->dma = 0; 1018 s->do_cmd = 0; 1019 s->dma_cb = NULL; 1020 1021 s->rregs[ESP_CFG1] = 7; 1022 } 1023 1024 static void esp_soft_reset(ESPState *s) 1025 { 1026 qemu_irq_lower(s->irq); 1027 qemu_irq_lower(s->irq_data); 1028 esp_hard_reset(s); 1029 } 1030 1031 static void esp_bus_reset(ESPState *s) 1032 { 1033 bus_cold_reset(BUS(&s->bus)); 1034 } 1035 1036 static void parent_esp_reset(ESPState *s, int irq, int level) 1037 { 1038 if (level) { 1039 esp_soft_reset(s); 1040 } 1041 } 1042 1043 static void esp_run_cmd(ESPState *s) 1044 { 1045 uint8_t cmd = s->rregs[ESP_CMD]; 1046 1047 if (cmd & CMD_DMA) { 1048 s->dma = 1; 1049 /* Reload DMA counter. */ 1050 if (esp_get_stc(s) == 0) { 1051 esp_set_tc(s, 0x10000); 1052 } else { 1053 esp_set_tc(s, esp_get_stc(s)); 1054 } 1055 } else { 1056 s->dma = 0; 1057 } 1058 switch (cmd & CMD_CMD) { 1059 case CMD_NOP: 1060 trace_esp_mem_writeb_cmd_nop(cmd); 1061 break; 1062 case CMD_FLUSH: 1063 trace_esp_mem_writeb_cmd_flush(cmd); 1064 fifo8_reset(&s->fifo); 1065 break; 1066 case CMD_RESET: 1067 trace_esp_mem_writeb_cmd_reset(cmd); 1068 esp_soft_reset(s); 1069 break; 1070 case CMD_BUSRESET: 1071 trace_esp_mem_writeb_cmd_bus_reset(cmd); 1072 esp_bus_reset(s); 1073 if (!(s->wregs[ESP_CFG1] & CFG1_RESREPT)) { 1074 s->rregs[ESP_RINTR] |= INTR_RST; 1075 esp_raise_irq(s); 1076 } 1077 break; 1078 case CMD_TI: 1079 trace_esp_mem_writeb_cmd_ti(cmd); 1080 handle_ti(s); 1081 break; 1082 case CMD_ICCS: 1083 trace_esp_mem_writeb_cmd_iccs(cmd); 1084 write_response(s); 1085 s->rregs[ESP_RINTR] |= INTR_FC; 1086 esp_set_phase(s, STAT_MI); 1087 break; 1088 case CMD_MSGACC: 1089 trace_esp_mem_writeb_cmd_msgacc(cmd); 1090 s->rregs[ESP_RINTR] |= INTR_DC; 1091 s->rregs[ESP_RSEQ] = 0; 1092 s->rregs[ESP_RFLAGS] = 0; 1093 esp_raise_irq(s); 1094 break; 1095 case CMD_PAD: 1096 trace_esp_mem_writeb_cmd_pad(cmd); 1097 s->rregs[ESP_RSTAT] = STAT_TC; 1098 s->rregs[ESP_RINTR] |= INTR_FC; 1099 s->rregs[ESP_RSEQ] = 0; 1100 break; 1101 case CMD_SATN: 1102 trace_esp_mem_writeb_cmd_satn(cmd); 1103 break; 1104 case CMD_RSTATN: 1105 trace_esp_mem_writeb_cmd_rstatn(cmd); 1106 break; 1107 case CMD_SEL: 1108 trace_esp_mem_writeb_cmd_sel(cmd); 1109 handle_s_without_atn(s); 1110 break; 1111 case CMD_SELATN: 1112 trace_esp_mem_writeb_cmd_selatn(cmd); 1113 handle_satn(s); 1114 break; 1115 case CMD_SELATNS: 1116 trace_esp_mem_writeb_cmd_selatns(cmd); 1117 handle_satn_stop(s); 1118 break; 1119 case CMD_ENSEL: 1120 trace_esp_mem_writeb_cmd_ensel(cmd); 1121 s->rregs[ESP_RINTR] = 0; 1122 break; 1123 case CMD_DISSEL: 1124 trace_esp_mem_writeb_cmd_dissel(cmd); 1125 s->rregs[ESP_RINTR] = 0; 1126 esp_raise_irq(s); 1127 break; 1128 default: 1129 trace_esp_error_unhandled_command(cmd); 1130 break; 1131 } 1132 } 1133 1134 uint64_t esp_reg_read(ESPState *s, uint32_t saddr) 1135 { 1136 uint32_t val; 1137 1138 switch (saddr) { 1139 case ESP_FIFO: 1140 if (s->dma_memory_read && s->dma_memory_write && 1141 (s->rregs[ESP_RSTAT] & STAT_PIO_MASK) == 0) { 1142 /* Data out. */ 1143 qemu_log_mask(LOG_UNIMP, "esp: PIO data read not implemented\n"); 1144 s->rregs[ESP_FIFO] = 0; 1145 } else { 1146 if (esp_get_phase(s) == STAT_DI) { 1147 if (s->ti_size) { 1148 esp_do_nodma(s); 1149 } else { 1150 /* 1151 * The last byte of a non-DMA transfer has been read out 1152 * of the FIFO so switch to status phase 1153 */ 1154 esp_set_phase(s, STAT_ST); 1155 } 1156 } 1157 s->rregs[ESP_FIFO] = esp_fifo_pop(&s->fifo); 1158 } 1159 val = s->rregs[ESP_FIFO]; 1160 break; 1161 case ESP_RINTR: 1162 /* 1163 * Clear sequence step, interrupt register and all status bits 1164 * except TC 1165 */ 1166 val = s->rregs[ESP_RINTR]; 1167 s->rregs[ESP_RINTR] = 0; 1168 s->rregs[ESP_RSTAT] &= ~STAT_TC; 1169 /* 1170 * According to the datasheet ESP_RSEQ should be cleared, but as the 1171 * emulation currently defers information transfers to the next TI 1172 * command leave it for now so that pedantic guests such as the old 1173 * Linux 2.6 driver see the correct flags before the next SCSI phase 1174 * transition. 1175 * 1176 * s->rregs[ESP_RSEQ] = SEQ_0; 1177 */ 1178 esp_lower_irq(s); 1179 break; 1180 case ESP_TCHI: 1181 /* Return the unique id if the value has never been written */ 1182 if (!s->tchi_written) { 1183 val = s->chip_id; 1184 } else { 1185 val = s->rregs[saddr]; 1186 } 1187 break; 1188 case ESP_RFLAGS: 1189 /* Bottom 5 bits indicate number of bytes in FIFO */ 1190 val = fifo8_num_used(&s->fifo); 1191 break; 1192 default: 1193 val = s->rregs[saddr]; 1194 break; 1195 } 1196 1197 trace_esp_mem_readb(saddr, val); 1198 return val; 1199 } 1200 1201 void esp_reg_write(ESPState *s, uint32_t saddr, uint64_t val) 1202 { 1203 trace_esp_mem_writeb(saddr, s->wregs[saddr], val); 1204 switch (saddr) { 1205 case ESP_TCHI: 1206 s->tchi_written = true; 1207 /* fall through */ 1208 case ESP_TCLO: 1209 case ESP_TCMID: 1210 s->rregs[ESP_RSTAT] &= ~STAT_TC; 1211 break; 1212 case ESP_FIFO: 1213 if (s->do_cmd) { 1214 if (!fifo8_is_full(&s->fifo)) { 1215 esp_fifo_push(&s->fifo, val); 1216 esp_fifo_push(&s->cmdfifo, fifo8_pop(&s->fifo)); 1217 } 1218 1219 /* 1220 * If any unexpected message out/command phase data is 1221 * transferred using non-DMA, raise the interrupt 1222 */ 1223 if (s->rregs[ESP_CMD] == CMD_TI) { 1224 s->rregs[ESP_RINTR] |= INTR_BS; 1225 esp_raise_irq(s); 1226 } 1227 } else { 1228 esp_fifo_push(&s->fifo, val); 1229 } 1230 break; 1231 case ESP_CMD: 1232 s->rregs[saddr] = val; 1233 esp_run_cmd(s); 1234 break; 1235 case ESP_WBUSID ... ESP_WSYNO: 1236 break; 1237 case ESP_CFG1: 1238 case ESP_CFG2: case ESP_CFG3: 1239 case ESP_RES3: case ESP_RES4: 1240 s->rregs[saddr] = val; 1241 break; 1242 case ESP_WCCF ... ESP_WTEST: 1243 break; 1244 default: 1245 trace_esp_error_invalid_write(val, saddr); 1246 return; 1247 } 1248 s->wregs[saddr] = val; 1249 } 1250 1251 static bool esp_mem_accepts(void *opaque, hwaddr addr, 1252 unsigned size, bool is_write, 1253 MemTxAttrs attrs) 1254 { 1255 return (size == 1) || (is_write && size == 4); 1256 } 1257 1258 static bool esp_is_before_version_5(void *opaque, int version_id) 1259 { 1260 ESPState *s = ESP(opaque); 1261 1262 version_id = MIN(version_id, s->mig_version_id); 1263 return version_id < 5; 1264 } 1265 1266 static bool esp_is_version_5(void *opaque, int version_id) 1267 { 1268 ESPState *s = ESP(opaque); 1269 1270 version_id = MIN(version_id, s->mig_version_id); 1271 return version_id >= 5; 1272 } 1273 1274 static bool esp_is_version_6(void *opaque, int version_id) 1275 { 1276 ESPState *s = ESP(opaque); 1277 1278 version_id = MIN(version_id, s->mig_version_id); 1279 return version_id >= 6; 1280 } 1281 1282 int esp_pre_save(void *opaque) 1283 { 1284 ESPState *s = ESP(object_resolve_path_component( 1285 OBJECT(opaque), "esp")); 1286 1287 s->mig_version_id = vmstate_esp.version_id; 1288 return 0; 1289 } 1290 1291 static int esp_post_load(void *opaque, int version_id) 1292 { 1293 ESPState *s = ESP(opaque); 1294 int len, i; 1295 1296 version_id = MIN(version_id, s->mig_version_id); 1297 1298 if (version_id < 5) { 1299 esp_set_tc(s, s->mig_dma_left); 1300 1301 /* Migrate ti_buf to fifo */ 1302 len = s->mig_ti_wptr - s->mig_ti_rptr; 1303 for (i = 0; i < len; i++) { 1304 fifo8_push(&s->fifo, s->mig_ti_buf[i]); 1305 } 1306 1307 /* Migrate cmdbuf to cmdfifo */ 1308 for (i = 0; i < s->mig_cmdlen; i++) { 1309 fifo8_push(&s->cmdfifo, s->mig_cmdbuf[i]); 1310 } 1311 } 1312 1313 s->mig_version_id = vmstate_esp.version_id; 1314 return 0; 1315 } 1316 1317 /* 1318 * PDMA (or pseudo-DMA) is only used on the Macintosh and requires the 1319 * guest CPU to perform the transfers between the SCSI bus and memory 1320 * itself. This is indicated by the dma_memory_read and dma_memory_write 1321 * functions being NULL (in contrast to the ESP PCI device) whilst 1322 * dma_enabled is still set. 1323 */ 1324 1325 static bool esp_pdma_needed(void *opaque) 1326 { 1327 ESPState *s = ESP(opaque); 1328 1329 return s->dma_memory_read == NULL && s->dma_memory_write == NULL && 1330 s->dma_enabled; 1331 } 1332 1333 static const VMStateDescription vmstate_esp_pdma = { 1334 .name = "esp/pdma", 1335 .version_id = 0, 1336 .minimum_version_id = 0, 1337 .needed = esp_pdma_needed, 1338 .fields = (const VMStateField[]) { 1339 VMSTATE_UINT8(pdma_cb, ESPState), 1340 VMSTATE_END_OF_LIST() 1341 } 1342 }; 1343 1344 const VMStateDescription vmstate_esp = { 1345 .name = "esp", 1346 .version_id = 6, 1347 .minimum_version_id = 3, 1348 .post_load = esp_post_load, 1349 .fields = (const VMStateField[]) { 1350 VMSTATE_BUFFER(rregs, ESPState), 1351 VMSTATE_BUFFER(wregs, ESPState), 1352 VMSTATE_INT32(ti_size, ESPState), 1353 VMSTATE_UINT32_TEST(mig_ti_rptr, ESPState, esp_is_before_version_5), 1354 VMSTATE_UINT32_TEST(mig_ti_wptr, ESPState, esp_is_before_version_5), 1355 VMSTATE_BUFFER_TEST(mig_ti_buf, ESPState, esp_is_before_version_5), 1356 VMSTATE_UINT32(status, ESPState), 1357 VMSTATE_UINT32_TEST(mig_deferred_status, ESPState, 1358 esp_is_before_version_5), 1359 VMSTATE_BOOL_TEST(mig_deferred_complete, ESPState, 1360 esp_is_before_version_5), 1361 VMSTATE_UINT32(dma, ESPState), 1362 VMSTATE_STATIC_BUFFER(mig_cmdbuf, ESPState, 0, 1363 esp_is_before_version_5, 0, 16), 1364 VMSTATE_STATIC_BUFFER(mig_cmdbuf, ESPState, 4, 1365 esp_is_before_version_5, 16, 1366 sizeof(typeof_field(ESPState, mig_cmdbuf))), 1367 VMSTATE_UINT32_TEST(mig_cmdlen, ESPState, esp_is_before_version_5), 1368 VMSTATE_UINT32(do_cmd, ESPState), 1369 VMSTATE_UINT32_TEST(mig_dma_left, ESPState, esp_is_before_version_5), 1370 VMSTATE_BOOL_TEST(data_in_ready, ESPState, esp_is_version_5), 1371 VMSTATE_UINT8_TEST(cmdfifo_cdb_offset, ESPState, esp_is_version_5), 1372 VMSTATE_FIFO8_TEST(fifo, ESPState, esp_is_version_5), 1373 VMSTATE_FIFO8_TEST(cmdfifo, ESPState, esp_is_version_5), 1374 VMSTATE_UINT8_TEST(ti_cmd, ESPState, esp_is_version_5), 1375 VMSTATE_UINT8_TEST(lun, ESPState, esp_is_version_6), 1376 VMSTATE_END_OF_LIST() 1377 }, 1378 .subsections = (const VMStateDescription * const []) { 1379 &vmstate_esp_pdma, 1380 NULL 1381 } 1382 }; 1383 1384 static void sysbus_esp_mem_write(void *opaque, hwaddr addr, 1385 uint64_t val, unsigned int size) 1386 { 1387 SysBusESPState *sysbus = opaque; 1388 ESPState *s = ESP(&sysbus->esp); 1389 uint32_t saddr; 1390 1391 saddr = addr >> sysbus->it_shift; 1392 esp_reg_write(s, saddr, val); 1393 } 1394 1395 static uint64_t sysbus_esp_mem_read(void *opaque, hwaddr addr, 1396 unsigned int size) 1397 { 1398 SysBusESPState *sysbus = opaque; 1399 ESPState *s = ESP(&sysbus->esp); 1400 uint32_t saddr; 1401 1402 saddr = addr >> sysbus->it_shift; 1403 return esp_reg_read(s, saddr); 1404 } 1405 1406 static const MemoryRegionOps sysbus_esp_mem_ops = { 1407 .read = sysbus_esp_mem_read, 1408 .write = sysbus_esp_mem_write, 1409 .endianness = DEVICE_NATIVE_ENDIAN, 1410 .valid.accepts = esp_mem_accepts, 1411 }; 1412 1413 static void sysbus_esp_pdma_write(void *opaque, hwaddr addr, 1414 uint64_t val, unsigned int size) 1415 { 1416 SysBusESPState *sysbus = opaque; 1417 ESPState *s = ESP(&sysbus->esp); 1418 1419 trace_esp_pdma_write(size); 1420 1421 switch (size) { 1422 case 1: 1423 esp_pdma_write(s, val); 1424 break; 1425 case 2: 1426 esp_pdma_write(s, val >> 8); 1427 esp_pdma_write(s, val); 1428 break; 1429 } 1430 esp_pdma_cb(s); 1431 } 1432 1433 static uint64_t sysbus_esp_pdma_read(void *opaque, hwaddr addr, 1434 unsigned int size) 1435 { 1436 SysBusESPState *sysbus = opaque; 1437 ESPState *s = ESP(&sysbus->esp); 1438 uint64_t val = 0; 1439 1440 trace_esp_pdma_read(size); 1441 1442 switch (size) { 1443 case 1: 1444 val = esp_pdma_read(s); 1445 break; 1446 case 2: 1447 val = esp_pdma_read(s); 1448 val = (val << 8) | esp_pdma_read(s); 1449 break; 1450 } 1451 esp_pdma_cb(s); 1452 return val; 1453 } 1454 1455 static void *esp_load_request(QEMUFile *f, SCSIRequest *req) 1456 { 1457 ESPState *s = container_of(req->bus, ESPState, bus); 1458 1459 scsi_req_ref(req); 1460 s->current_req = req; 1461 return s; 1462 } 1463 1464 static const MemoryRegionOps sysbus_esp_pdma_ops = { 1465 .read = sysbus_esp_pdma_read, 1466 .write = sysbus_esp_pdma_write, 1467 .endianness = DEVICE_NATIVE_ENDIAN, 1468 .valid.min_access_size = 1, 1469 .valid.max_access_size = 4, 1470 .impl.min_access_size = 1, 1471 .impl.max_access_size = 2, 1472 }; 1473 1474 static const struct SCSIBusInfo esp_scsi_info = { 1475 .tcq = false, 1476 .max_target = ESP_MAX_DEVS, 1477 .max_lun = 7, 1478 1479 .load_request = esp_load_request, 1480 .transfer_data = esp_transfer_data, 1481 .complete = esp_command_complete, 1482 .cancel = esp_request_cancelled 1483 }; 1484 1485 static void sysbus_esp_gpio_demux(void *opaque, int irq, int level) 1486 { 1487 SysBusESPState *sysbus = SYSBUS_ESP(opaque); 1488 ESPState *s = ESP(&sysbus->esp); 1489 1490 switch (irq) { 1491 case 0: 1492 parent_esp_reset(s, irq, level); 1493 break; 1494 case 1: 1495 esp_dma_enable(s, irq, level); 1496 break; 1497 } 1498 } 1499 1500 static void sysbus_esp_realize(DeviceState *dev, Error **errp) 1501 { 1502 SysBusDevice *sbd = SYS_BUS_DEVICE(dev); 1503 SysBusESPState *sysbus = SYSBUS_ESP(dev); 1504 ESPState *s = ESP(&sysbus->esp); 1505 1506 if (!qdev_realize(DEVICE(s), NULL, errp)) { 1507 return; 1508 } 1509 1510 sysbus_init_irq(sbd, &s->irq); 1511 sysbus_init_irq(sbd, &s->irq_data); 1512 assert(sysbus->it_shift != -1); 1513 1514 s->chip_id = TCHI_FAS100A; 1515 memory_region_init_io(&sysbus->iomem, OBJECT(sysbus), &sysbus_esp_mem_ops, 1516 sysbus, "esp-regs", ESP_REGS << sysbus->it_shift); 1517 sysbus_init_mmio(sbd, &sysbus->iomem); 1518 memory_region_init_io(&sysbus->pdma, OBJECT(sysbus), &sysbus_esp_pdma_ops, 1519 sysbus, "esp-pdma", 4); 1520 sysbus_init_mmio(sbd, &sysbus->pdma); 1521 1522 qdev_init_gpio_in(dev, sysbus_esp_gpio_demux, 2); 1523 1524 scsi_bus_init(&s->bus, sizeof(s->bus), dev, &esp_scsi_info); 1525 } 1526 1527 static void sysbus_esp_hard_reset(DeviceState *dev) 1528 { 1529 SysBusESPState *sysbus = SYSBUS_ESP(dev); 1530 ESPState *s = ESP(&sysbus->esp); 1531 1532 esp_hard_reset(s); 1533 } 1534 1535 static void sysbus_esp_init(Object *obj) 1536 { 1537 SysBusESPState *sysbus = SYSBUS_ESP(obj); 1538 1539 object_initialize_child(obj, "esp", &sysbus->esp, TYPE_ESP); 1540 } 1541 1542 static const VMStateDescription vmstate_sysbus_esp_scsi = { 1543 .name = "sysbusespscsi", 1544 .version_id = 2, 1545 .minimum_version_id = 1, 1546 .pre_save = esp_pre_save, 1547 .fields = (const VMStateField[]) { 1548 VMSTATE_UINT8_V(esp.mig_version_id, SysBusESPState, 2), 1549 VMSTATE_STRUCT(esp, SysBusESPState, 0, vmstate_esp, ESPState), 1550 VMSTATE_END_OF_LIST() 1551 } 1552 }; 1553 1554 static void sysbus_esp_class_init(ObjectClass *klass, void *data) 1555 { 1556 DeviceClass *dc = DEVICE_CLASS(klass); 1557 1558 dc->realize = sysbus_esp_realize; 1559 dc->reset = sysbus_esp_hard_reset; 1560 dc->vmsd = &vmstate_sysbus_esp_scsi; 1561 set_bit(DEVICE_CATEGORY_STORAGE, dc->categories); 1562 } 1563 1564 static const TypeInfo sysbus_esp_info = { 1565 .name = TYPE_SYSBUS_ESP, 1566 .parent = TYPE_SYS_BUS_DEVICE, 1567 .instance_init = sysbus_esp_init, 1568 .instance_size = sizeof(SysBusESPState), 1569 .class_init = sysbus_esp_class_init, 1570 }; 1571 1572 static void esp_finalize(Object *obj) 1573 { 1574 ESPState *s = ESP(obj); 1575 1576 fifo8_destroy(&s->fifo); 1577 fifo8_destroy(&s->cmdfifo); 1578 } 1579 1580 static void esp_init(Object *obj) 1581 { 1582 ESPState *s = ESP(obj); 1583 1584 fifo8_create(&s->fifo, ESP_FIFO_SZ); 1585 fifo8_create(&s->cmdfifo, ESP_CMDFIFO_SZ); 1586 } 1587 1588 static void esp_class_init(ObjectClass *klass, void *data) 1589 { 1590 DeviceClass *dc = DEVICE_CLASS(klass); 1591 1592 /* internal device for sysbusesp/pciespscsi, not user-creatable */ 1593 dc->user_creatable = false; 1594 set_bit(DEVICE_CATEGORY_STORAGE, dc->categories); 1595 } 1596 1597 static const TypeInfo esp_info = { 1598 .name = TYPE_ESP, 1599 .parent = TYPE_DEVICE, 1600 .instance_init = esp_init, 1601 .instance_finalize = esp_finalize, 1602 .instance_size = sizeof(ESPState), 1603 .class_init = esp_class_init, 1604 }; 1605 1606 static void esp_register_types(void) 1607 { 1608 type_register_static(&sysbus_esp_info); 1609 type_register_static(&esp_info); 1610 } 1611 1612 type_init(esp_register_types) 1613