1 /* 2 * QEMU ESP/NCR53C9x emulation 3 * 4 * Copyright (c) 2005-2006 Fabrice Bellard 5 * Copyright (c) 2012 Herve Poussineau 6 * 7 * Permission is hereby granted, free of charge, to any person obtaining a copy 8 * of this software and associated documentation files (the "Software"), to deal 9 * in the Software without restriction, including without limitation the rights 10 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 11 * copies of the Software, and to permit persons to whom the Software is 12 * furnished to do so, subject to the following conditions: 13 * 14 * The above copyright notice and this permission notice shall be included in 15 * all copies or substantial portions of the Software. 16 * 17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 22 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 23 * THE SOFTWARE. 24 */ 25 26 #include "qemu/osdep.h" 27 #include "hw/sysbus.h" 28 #include "migration/vmstate.h" 29 #include "hw/irq.h" 30 #include "hw/scsi/esp.h" 31 #include "trace.h" 32 #include "qemu/log.h" 33 #include "qemu/module.h" 34 35 /* 36 * On Sparc32, this is the ESP (NCR53C90) part of chip STP2000 (Master I/O), 37 * also produced as NCR89C100. See 38 * http://www.ibiblio.org/pub/historic-linux/early-ports/Sparc/NCR/NCR89C100.txt 39 * and 40 * http://www.ibiblio.org/pub/historic-linux/early-ports/Sparc/NCR/NCR53C9X.txt 41 * 42 * On Macintosh Quadra it is a NCR53C96. 43 */ 44 45 static void esp_raise_irq(ESPState *s) 46 { 47 if (!(s->rregs[ESP_RSTAT] & STAT_INT)) { 48 s->rregs[ESP_RSTAT] |= STAT_INT; 49 qemu_irq_raise(s->irq); 50 trace_esp_raise_irq(); 51 } 52 } 53 54 static void esp_lower_irq(ESPState *s) 55 { 56 if (s->rregs[ESP_RSTAT] & STAT_INT) { 57 s->rregs[ESP_RSTAT] &= ~STAT_INT; 58 qemu_irq_lower(s->irq); 59 trace_esp_lower_irq(); 60 } 61 } 62 63 static void esp_raise_drq(ESPState *s) 64 { 65 qemu_irq_raise(s->irq_data); 66 trace_esp_raise_drq(); 67 } 68 69 static void esp_lower_drq(ESPState *s) 70 { 71 qemu_irq_lower(s->irq_data); 72 trace_esp_lower_drq(); 73 } 74 75 void esp_dma_enable(ESPState *s, int irq, int level) 76 { 77 if (level) { 78 s->dma_enabled = 1; 79 trace_esp_dma_enable(); 80 if (s->dma_cb) { 81 s->dma_cb(s); 82 s->dma_cb = NULL; 83 } 84 } else { 85 trace_esp_dma_disable(); 86 s->dma_enabled = 0; 87 } 88 } 89 90 void esp_request_cancelled(SCSIRequest *req) 91 { 92 ESPState *s = req->hba_private; 93 94 if (req == s->current_req) { 95 scsi_req_unref(s->current_req); 96 s->current_req = NULL; 97 s->current_dev = NULL; 98 } 99 } 100 101 static uint32_t esp_get_tc(ESPState *s) 102 { 103 uint32_t dmalen; 104 105 dmalen = s->rregs[ESP_TCLO]; 106 dmalen |= s->rregs[ESP_TCMID] << 8; 107 dmalen |= s->rregs[ESP_TCHI] << 16; 108 109 return dmalen; 110 } 111 112 static void esp_set_tc(ESPState *s, uint32_t dmalen) 113 { 114 s->rregs[ESP_TCLO] = dmalen; 115 s->rregs[ESP_TCMID] = dmalen >> 8; 116 s->rregs[ESP_TCHI] = dmalen >> 16; 117 } 118 119 static uint32_t esp_get_stc(ESPState *s) 120 { 121 uint32_t dmalen; 122 123 dmalen = s->wregs[ESP_TCLO]; 124 dmalen |= s->wregs[ESP_TCMID] << 8; 125 dmalen |= s->wregs[ESP_TCHI] << 16; 126 127 return dmalen; 128 } 129 130 static void set_pdma(ESPState *s, enum pdma_origin_id origin, 131 uint32_t index, uint32_t len) 132 { 133 s->pdma_origin = origin; 134 s->pdma_start = index; 135 s->pdma_cur = index; 136 s->pdma_len = len; 137 } 138 139 static uint8_t *get_pdma_buf(ESPState *s) 140 { 141 switch (s->pdma_origin) { 142 case PDMA: 143 return s->pdma_buf; 144 case TI: 145 return s->ti_buf; 146 case CMD: 147 return s->cmdbuf; 148 case ASYNC: 149 return s->async_buf; 150 } 151 return NULL; 152 } 153 154 static int get_cmd_cb(ESPState *s) 155 { 156 int target; 157 158 target = s->wregs[ESP_WBUSID] & BUSID_DID; 159 160 s->ti_size = 0; 161 s->ti_rptr = 0; 162 s->ti_wptr = 0; 163 164 if (s->current_req) { 165 /* Started a new command before the old one finished. Cancel it. */ 166 scsi_req_cancel(s->current_req); 167 s->async_len = 0; 168 } 169 170 s->current_dev = scsi_device_find(&s->bus, 0, target, 0); 171 if (!s->current_dev) { 172 /* No such drive */ 173 s->rregs[ESP_RSTAT] = 0; 174 s->rregs[ESP_RINTR] = INTR_DC; 175 s->rregs[ESP_RSEQ] = SEQ_0; 176 esp_raise_irq(s); 177 return -1; 178 } 179 return 0; 180 } 181 182 static uint32_t get_cmd(ESPState *s, uint8_t *buf, uint8_t buflen) 183 { 184 uint32_t dmalen; 185 int target; 186 187 target = s->wregs[ESP_WBUSID] & BUSID_DID; 188 if (s->dma) { 189 dmalen = esp_get_tc(s); 190 if (dmalen > buflen) { 191 return 0; 192 } 193 if (s->dma_memory_read) { 194 s->dma_memory_read(s->dma_opaque, buf, dmalen); 195 } else { 196 memcpy(s->pdma_buf, buf, dmalen); 197 set_pdma(s, PDMA, 0, dmalen); 198 esp_raise_drq(s); 199 return 0; 200 } 201 } else { 202 dmalen = s->ti_size; 203 if (dmalen > TI_BUFSZ) { 204 return 0; 205 } 206 memcpy(buf, s->ti_buf, dmalen); 207 buf[0] = buf[2] >> 5; 208 } 209 trace_esp_get_cmd(dmalen, target); 210 211 if (get_cmd_cb(s) < 0) { 212 return 0; 213 } 214 return dmalen; 215 } 216 217 static void do_busid_cmd(ESPState *s, uint8_t *buf, uint8_t busid) 218 { 219 int32_t datalen; 220 int lun; 221 SCSIDevice *current_lun; 222 223 trace_esp_do_busid_cmd(busid); 224 lun = busid & 7; 225 current_lun = scsi_device_find(&s->bus, 0, s->current_dev->id, lun); 226 s->current_req = scsi_req_new(current_lun, 0, lun, buf, s); 227 datalen = scsi_req_enqueue(s->current_req); 228 s->ti_size = datalen; 229 if (datalen != 0) { 230 s->rregs[ESP_RSTAT] = STAT_TC; 231 s->dma_left = 0; 232 s->dma_counter = 0; 233 if (datalen > 0) { 234 s->rregs[ESP_RSTAT] |= STAT_DI; 235 } else { 236 s->rregs[ESP_RSTAT] |= STAT_DO; 237 } 238 scsi_req_continue(s->current_req); 239 } 240 s->rregs[ESP_RINTR] = INTR_BS | INTR_FC; 241 s->rregs[ESP_RSEQ] = SEQ_CD; 242 esp_raise_irq(s); 243 } 244 245 static void do_cmd(ESPState *s, uint8_t *buf) 246 { 247 uint8_t busid = buf[0]; 248 249 do_busid_cmd(s, &buf[1], busid); 250 } 251 252 static void satn_pdma_cb(ESPState *s) 253 { 254 if (get_cmd_cb(s) < 0) { 255 return; 256 } 257 if (s->pdma_cur != s->pdma_start) { 258 do_cmd(s, get_pdma_buf(s) + s->pdma_start); 259 } 260 } 261 262 static void handle_satn(ESPState *s) 263 { 264 uint8_t buf[32]; 265 int len; 266 267 if (s->dma && !s->dma_enabled) { 268 s->dma_cb = handle_satn; 269 return; 270 } 271 s->pdma_cb = satn_pdma_cb; 272 len = get_cmd(s, buf, sizeof(buf)); 273 if (len) { 274 do_cmd(s, buf); 275 } 276 } 277 278 static void s_without_satn_pdma_cb(ESPState *s) 279 { 280 if (get_cmd_cb(s) < 0) { 281 return; 282 } 283 if (s->pdma_cur != s->pdma_start) { 284 do_busid_cmd(s, get_pdma_buf(s) + s->pdma_start, 0); 285 } 286 } 287 288 static void handle_s_without_atn(ESPState *s) 289 { 290 uint8_t buf[32]; 291 int len; 292 293 if (s->dma && !s->dma_enabled) { 294 s->dma_cb = handle_s_without_atn; 295 return; 296 } 297 s->pdma_cb = s_without_satn_pdma_cb; 298 len = get_cmd(s, buf, sizeof(buf)); 299 if (len) { 300 do_busid_cmd(s, buf, 0); 301 } 302 } 303 304 static void satn_stop_pdma_cb(ESPState *s) 305 { 306 if (get_cmd_cb(s) < 0) { 307 return; 308 } 309 s->cmdlen = s->pdma_cur - s->pdma_start; 310 if (s->cmdlen) { 311 trace_esp_handle_satn_stop(s->cmdlen); 312 s->do_cmd = 1; 313 s->rregs[ESP_RSTAT] = STAT_TC | STAT_CD; 314 s->rregs[ESP_RINTR] = INTR_BS | INTR_FC; 315 s->rregs[ESP_RSEQ] = SEQ_CD; 316 esp_raise_irq(s); 317 } 318 } 319 320 static void handle_satn_stop(ESPState *s) 321 { 322 if (s->dma && !s->dma_enabled) { 323 s->dma_cb = handle_satn_stop; 324 return; 325 } 326 s->pdma_cb = satn_stop_pdma_cb; 327 s->cmdlen = get_cmd(s, s->cmdbuf, sizeof(s->cmdbuf)); 328 if (s->cmdlen) { 329 trace_esp_handle_satn_stop(s->cmdlen); 330 s->do_cmd = 1; 331 s->rregs[ESP_RSTAT] = STAT_TC | STAT_CD; 332 s->rregs[ESP_RINTR] = INTR_BS | INTR_FC; 333 s->rregs[ESP_RSEQ] = SEQ_CD; 334 esp_raise_irq(s); 335 } 336 } 337 338 static void write_response_pdma_cb(ESPState *s) 339 { 340 s->rregs[ESP_RSTAT] = STAT_TC | STAT_ST; 341 s->rregs[ESP_RINTR] = INTR_BS | INTR_FC; 342 s->rregs[ESP_RSEQ] = SEQ_CD; 343 esp_raise_irq(s); 344 } 345 346 static void write_response(ESPState *s) 347 { 348 trace_esp_write_response(s->status); 349 s->ti_buf[0] = s->status; 350 s->ti_buf[1] = 0; 351 if (s->dma) { 352 if (s->dma_memory_write) { 353 s->dma_memory_write(s->dma_opaque, s->ti_buf, 2); 354 s->rregs[ESP_RSTAT] = STAT_TC | STAT_ST; 355 s->rregs[ESP_RINTR] = INTR_BS | INTR_FC; 356 s->rregs[ESP_RSEQ] = SEQ_CD; 357 } else { 358 set_pdma(s, TI, 0, 2); 359 s->pdma_cb = write_response_pdma_cb; 360 esp_raise_drq(s); 361 return; 362 } 363 } else { 364 s->ti_size = 2; 365 s->ti_rptr = 0; 366 s->ti_wptr = 2; 367 s->rregs[ESP_RFLAGS] = 2; 368 } 369 esp_raise_irq(s); 370 } 371 372 static void esp_dma_done(ESPState *s) 373 { 374 s->rregs[ESP_RSTAT] |= STAT_TC; 375 s->rregs[ESP_RINTR] = INTR_BS; 376 s->rregs[ESP_RSEQ] = 0; 377 s->rregs[ESP_RFLAGS] = 0; 378 esp_set_tc(s, 0); 379 esp_raise_irq(s); 380 } 381 382 static void do_dma_pdma_cb(ESPState *s) 383 { 384 int to_device = ((s->rregs[ESP_RSTAT] & 7) == STAT_DO); 385 int len = s->pdma_cur - s->pdma_start; 386 if (s->do_cmd) { 387 s->ti_size = 0; 388 s->cmdlen = 0; 389 s->do_cmd = 0; 390 do_cmd(s, s->cmdbuf); 391 return; 392 } 393 s->dma_left -= len; 394 s->async_buf += len; 395 s->async_len -= len; 396 if (to_device) { 397 s->ti_size += len; 398 } else { 399 s->ti_size -= len; 400 } 401 if (s->async_len == 0) { 402 scsi_req_continue(s->current_req); 403 /* 404 * If there is still data to be read from the device then 405 * complete the DMA operation immediately. Otherwise defer 406 * until the scsi layer has completed. 407 */ 408 if (to_device || s->dma_left != 0 || s->ti_size == 0) { 409 return; 410 } 411 } 412 413 /* Partially filled a scsi buffer. Complete immediately. */ 414 esp_dma_done(s); 415 } 416 417 static void esp_do_dma(ESPState *s) 418 { 419 uint32_t len; 420 int to_device = ((s->rregs[ESP_RSTAT] & 7) == STAT_DO); 421 422 len = s->dma_left; 423 if (s->do_cmd) { 424 /* 425 * handle_ti_cmd() case: esp_do_dma() is called only from 426 * handle_ti_cmd() with do_cmd != NULL (see the assert()) 427 */ 428 trace_esp_do_dma(s->cmdlen, len); 429 assert(s->cmdlen <= sizeof(s->cmdbuf) && 430 len <= sizeof(s->cmdbuf) - s->cmdlen); 431 if (s->dma_memory_read) { 432 s->dma_memory_read(s->dma_opaque, &s->cmdbuf[s->cmdlen], len); 433 } else { 434 set_pdma(s, CMD, s->cmdlen, len); 435 s->pdma_cb = do_dma_pdma_cb; 436 esp_raise_drq(s); 437 return; 438 } 439 trace_esp_handle_ti_cmd(s->cmdlen); 440 s->ti_size = 0; 441 s->cmdlen = 0; 442 s->do_cmd = 0; 443 do_cmd(s, s->cmdbuf); 444 return; 445 } 446 if (s->async_len == 0) { 447 /* Defer until data is available. */ 448 return; 449 } 450 if (len > s->async_len) { 451 len = s->async_len; 452 } 453 if (to_device) { 454 if (s->dma_memory_read) { 455 s->dma_memory_read(s->dma_opaque, s->async_buf, len); 456 } else { 457 set_pdma(s, ASYNC, 0, len); 458 s->pdma_cb = do_dma_pdma_cb; 459 esp_raise_drq(s); 460 return; 461 } 462 } else { 463 if (s->dma_memory_write) { 464 s->dma_memory_write(s->dma_opaque, s->async_buf, len); 465 } else { 466 set_pdma(s, ASYNC, 0, len); 467 s->pdma_cb = do_dma_pdma_cb; 468 esp_raise_drq(s); 469 return; 470 } 471 } 472 s->dma_left -= len; 473 s->async_buf += len; 474 s->async_len -= len; 475 if (to_device) { 476 s->ti_size += len; 477 } else { 478 s->ti_size -= len; 479 } 480 if (s->async_len == 0) { 481 scsi_req_continue(s->current_req); 482 /* 483 * If there is still data to be read from the device then 484 * complete the DMA operation immediately. Otherwise defer 485 * until the scsi layer has completed. 486 */ 487 if (to_device || s->dma_left != 0 || s->ti_size == 0) { 488 return; 489 } 490 } 491 492 /* Partially filled a scsi buffer. Complete immediately. */ 493 esp_dma_done(s); 494 } 495 496 static void esp_report_command_complete(ESPState *s, uint32_t status) 497 { 498 trace_esp_command_complete(); 499 if (s->ti_size != 0) { 500 trace_esp_command_complete_unexpected(); 501 } 502 s->ti_size = 0; 503 s->dma_left = 0; 504 s->async_len = 0; 505 if (status) { 506 trace_esp_command_complete_fail(); 507 } 508 s->status = status; 509 s->rregs[ESP_RSTAT] = STAT_ST; 510 esp_dma_done(s); 511 if (s->current_req) { 512 scsi_req_unref(s->current_req); 513 s->current_req = NULL; 514 s->current_dev = NULL; 515 } 516 } 517 518 void esp_command_complete(SCSIRequest *req, size_t resid) 519 { 520 ESPState *s = req->hba_private; 521 522 if (s->rregs[ESP_RSTAT] & STAT_INT) { 523 /* 524 * Defer handling command complete until the previous 525 * interrupt has been handled. 526 */ 527 trace_esp_command_complete_deferred(); 528 s->deferred_status = req->status; 529 s->deferred_complete = true; 530 return; 531 } 532 esp_report_command_complete(s, req->status); 533 } 534 535 void esp_transfer_data(SCSIRequest *req, uint32_t len) 536 { 537 ESPState *s = req->hba_private; 538 539 assert(!s->do_cmd); 540 trace_esp_transfer_data(s->dma_left, s->ti_size); 541 s->async_len = len; 542 s->async_buf = scsi_req_get_buf(req); 543 if (s->dma_left) { 544 esp_do_dma(s); 545 } else if (s->dma_counter != 0 && s->ti_size <= 0) { 546 /* 547 * If this was the last part of a DMA transfer then the 548 * completion interrupt is deferred to here. 549 */ 550 esp_dma_done(s); 551 } 552 } 553 554 static void handle_ti(ESPState *s) 555 { 556 uint32_t dmalen, minlen; 557 558 if (s->dma && !s->dma_enabled) { 559 s->dma_cb = handle_ti; 560 return; 561 } 562 563 dmalen = esp_get_tc(s); 564 s->dma_counter = dmalen; 565 566 if (s->do_cmd) { 567 minlen = (dmalen < ESP_CMDBUF_SZ) ? dmalen : ESP_CMDBUF_SZ; 568 } else if (s->ti_size < 0) { 569 minlen = (dmalen < -s->ti_size) ? dmalen : -s->ti_size; 570 } else { 571 minlen = (dmalen < s->ti_size) ? dmalen : s->ti_size; 572 } 573 trace_esp_handle_ti(minlen); 574 if (s->dma) { 575 s->dma_left = minlen; 576 s->rregs[ESP_RSTAT] &= ~STAT_TC; 577 esp_do_dma(s); 578 } else if (s->do_cmd) { 579 trace_esp_handle_ti_cmd(s->cmdlen); 580 s->ti_size = 0; 581 s->cmdlen = 0; 582 s->do_cmd = 0; 583 do_cmd(s, s->cmdbuf); 584 } 585 } 586 587 void esp_hard_reset(ESPState *s) 588 { 589 memset(s->rregs, 0, ESP_REGS); 590 memset(s->wregs, 0, ESP_REGS); 591 s->tchi_written = 0; 592 s->ti_size = 0; 593 s->ti_rptr = 0; 594 s->ti_wptr = 0; 595 s->dma = 0; 596 s->do_cmd = 0; 597 s->dma_cb = NULL; 598 599 s->rregs[ESP_CFG1] = 7; 600 } 601 602 static void esp_soft_reset(ESPState *s) 603 { 604 qemu_irq_lower(s->irq); 605 qemu_irq_lower(s->irq_data); 606 esp_hard_reset(s); 607 } 608 609 static void parent_esp_reset(ESPState *s, int irq, int level) 610 { 611 if (level) { 612 esp_soft_reset(s); 613 } 614 } 615 616 uint64_t esp_reg_read(ESPState *s, uint32_t saddr) 617 { 618 uint32_t val; 619 620 switch (saddr) { 621 case ESP_FIFO: 622 if ((s->rregs[ESP_RSTAT] & STAT_PIO_MASK) == 0) { 623 /* Data out. */ 624 qemu_log_mask(LOG_UNIMP, "esp: PIO data read not implemented\n"); 625 s->rregs[ESP_FIFO] = 0; 626 } else if (s->ti_rptr < s->ti_wptr) { 627 s->ti_size--; 628 s->rregs[ESP_FIFO] = s->ti_buf[s->ti_rptr++]; 629 } 630 if (s->ti_rptr == s->ti_wptr) { 631 s->ti_rptr = 0; 632 s->ti_wptr = 0; 633 } 634 val = s->rregs[ESP_FIFO]; 635 break; 636 case ESP_RINTR: 637 /* 638 * Clear sequence step, interrupt register and all status bits 639 * except TC 640 */ 641 val = s->rregs[ESP_RINTR]; 642 s->rregs[ESP_RINTR] = 0; 643 s->rregs[ESP_RSTAT] &= ~STAT_TC; 644 s->rregs[ESP_RSEQ] = SEQ_CD; 645 esp_lower_irq(s); 646 if (s->deferred_complete) { 647 esp_report_command_complete(s, s->deferred_status); 648 s->deferred_complete = false; 649 } 650 break; 651 case ESP_TCHI: 652 /* Return the unique id if the value has never been written */ 653 if (!s->tchi_written) { 654 val = s->chip_id; 655 } else { 656 val = s->rregs[saddr]; 657 } 658 break; 659 default: 660 val = s->rregs[saddr]; 661 break; 662 } 663 664 trace_esp_mem_readb(saddr, val); 665 return val; 666 } 667 668 void esp_reg_write(ESPState *s, uint32_t saddr, uint64_t val) 669 { 670 trace_esp_mem_writeb(saddr, s->wregs[saddr], val); 671 switch (saddr) { 672 case ESP_TCHI: 673 s->tchi_written = true; 674 /* fall through */ 675 case ESP_TCLO: 676 case ESP_TCMID: 677 s->rregs[ESP_RSTAT] &= ~STAT_TC; 678 break; 679 case ESP_FIFO: 680 if (s->do_cmd) { 681 if (s->cmdlen < ESP_CMDBUF_SZ) { 682 s->cmdbuf[s->cmdlen++] = val & 0xff; 683 } else { 684 trace_esp_error_fifo_overrun(); 685 } 686 } else if (s->ti_wptr == TI_BUFSZ - 1) { 687 trace_esp_error_fifo_overrun(); 688 } else { 689 s->ti_size++; 690 s->ti_buf[s->ti_wptr++] = val & 0xff; 691 } 692 break; 693 case ESP_CMD: 694 s->rregs[saddr] = val; 695 if (val & CMD_DMA) { 696 s->dma = 1; 697 /* Reload DMA counter. */ 698 if (esp_get_stc(s) == 0) { 699 esp_set_tc(s, 0x10000); 700 } else { 701 esp_set_tc(s, esp_get_stc(s)); 702 } 703 } else { 704 s->dma = 0; 705 } 706 switch (val & CMD_CMD) { 707 case CMD_NOP: 708 trace_esp_mem_writeb_cmd_nop(val); 709 break; 710 case CMD_FLUSH: 711 trace_esp_mem_writeb_cmd_flush(val); 712 /*s->ti_size = 0;*/ 713 s->rregs[ESP_RINTR] = INTR_FC; 714 s->rregs[ESP_RSEQ] = 0; 715 s->rregs[ESP_RFLAGS] = 0; 716 break; 717 case CMD_RESET: 718 trace_esp_mem_writeb_cmd_reset(val); 719 esp_soft_reset(s); 720 break; 721 case CMD_BUSRESET: 722 trace_esp_mem_writeb_cmd_bus_reset(val); 723 s->rregs[ESP_RINTR] = INTR_RST; 724 if (!(s->wregs[ESP_CFG1] & CFG1_RESREPT)) { 725 esp_raise_irq(s); 726 } 727 break; 728 case CMD_TI: 729 trace_esp_mem_writeb_cmd_ti(val); 730 handle_ti(s); 731 break; 732 case CMD_ICCS: 733 trace_esp_mem_writeb_cmd_iccs(val); 734 write_response(s); 735 s->rregs[ESP_RINTR] = INTR_FC; 736 s->rregs[ESP_RSTAT] |= STAT_MI; 737 break; 738 case CMD_MSGACC: 739 trace_esp_mem_writeb_cmd_msgacc(val); 740 s->rregs[ESP_RINTR] = INTR_DC; 741 s->rregs[ESP_RSEQ] = 0; 742 s->rregs[ESP_RFLAGS] = 0; 743 esp_raise_irq(s); 744 break; 745 case CMD_PAD: 746 trace_esp_mem_writeb_cmd_pad(val); 747 s->rregs[ESP_RSTAT] = STAT_TC; 748 s->rregs[ESP_RINTR] = INTR_FC; 749 s->rregs[ESP_RSEQ] = 0; 750 break; 751 case CMD_SATN: 752 trace_esp_mem_writeb_cmd_satn(val); 753 break; 754 case CMD_RSTATN: 755 trace_esp_mem_writeb_cmd_rstatn(val); 756 break; 757 case CMD_SEL: 758 trace_esp_mem_writeb_cmd_sel(val); 759 handle_s_without_atn(s); 760 break; 761 case CMD_SELATN: 762 trace_esp_mem_writeb_cmd_selatn(val); 763 handle_satn(s); 764 break; 765 case CMD_SELATNS: 766 trace_esp_mem_writeb_cmd_selatns(val); 767 handle_satn_stop(s); 768 break; 769 case CMD_ENSEL: 770 trace_esp_mem_writeb_cmd_ensel(val); 771 s->rregs[ESP_RINTR] = 0; 772 break; 773 case CMD_DISSEL: 774 trace_esp_mem_writeb_cmd_dissel(val); 775 s->rregs[ESP_RINTR] = 0; 776 esp_raise_irq(s); 777 break; 778 default: 779 trace_esp_error_unhandled_command(val); 780 break; 781 } 782 break; 783 case ESP_WBUSID ... ESP_WSYNO: 784 break; 785 case ESP_CFG1: 786 case ESP_CFG2: case ESP_CFG3: 787 case ESP_RES3: case ESP_RES4: 788 s->rregs[saddr] = val; 789 break; 790 case ESP_WCCF ... ESP_WTEST: 791 break; 792 default: 793 trace_esp_error_invalid_write(val, saddr); 794 return; 795 } 796 s->wregs[saddr] = val; 797 } 798 799 static bool esp_mem_accepts(void *opaque, hwaddr addr, 800 unsigned size, bool is_write, 801 MemTxAttrs attrs) 802 { 803 return (size == 1) || (is_write && size == 4); 804 } 805 806 static bool esp_pdma_needed(void *opaque) 807 { 808 ESPState *s = opaque; 809 return s->dma_memory_read == NULL && s->dma_memory_write == NULL && 810 s->dma_enabled; 811 } 812 813 static const VMStateDescription vmstate_esp_pdma = { 814 .name = "esp/pdma", 815 .version_id = 1, 816 .minimum_version_id = 1, 817 .needed = esp_pdma_needed, 818 .fields = (VMStateField[]) { 819 VMSTATE_BUFFER(pdma_buf, ESPState), 820 VMSTATE_INT32(pdma_origin, ESPState), 821 VMSTATE_UINT32(pdma_len, ESPState), 822 VMSTATE_UINT32(pdma_start, ESPState), 823 VMSTATE_UINT32(pdma_cur, ESPState), 824 VMSTATE_END_OF_LIST() 825 } 826 }; 827 828 static int esp_pre_save(void *opaque) 829 { 830 ESPState *s = ESP(opaque); 831 832 s->mig_version_id = vmstate_esp.version_id; 833 return 0; 834 } 835 836 static int esp_post_load(void *opaque, int version_id) 837 { 838 ESPState *s = ESP(opaque); 839 840 s->mig_version_id = vmstate_esp.version_id; 841 return 0; 842 } 843 844 const VMStateDescription vmstate_esp = { 845 .name = "esp", 846 .version_id = 5, 847 .minimum_version_id = 3, 848 .pre_save = esp_pre_save, 849 .post_load = esp_post_load, 850 .fields = (VMStateField[]) { 851 VMSTATE_BUFFER(rregs, ESPState), 852 VMSTATE_BUFFER(wregs, ESPState), 853 VMSTATE_INT32(ti_size, ESPState), 854 VMSTATE_UINT32(ti_rptr, ESPState), 855 VMSTATE_UINT32(ti_wptr, ESPState), 856 VMSTATE_BUFFER(ti_buf, ESPState), 857 VMSTATE_UINT32(status, ESPState), 858 VMSTATE_UINT32(deferred_status, ESPState), 859 VMSTATE_BOOL(deferred_complete, ESPState), 860 VMSTATE_UINT32(dma, ESPState), 861 VMSTATE_PARTIAL_BUFFER(cmdbuf, ESPState, 16), 862 VMSTATE_BUFFER_START_MIDDLE_V(cmdbuf, ESPState, 16, 4), 863 VMSTATE_UINT32(cmdlen, ESPState), 864 VMSTATE_UINT32(do_cmd, ESPState), 865 VMSTATE_UINT32(dma_left, ESPState), 866 VMSTATE_END_OF_LIST() 867 }, 868 .subsections = (const VMStateDescription * []) { 869 &vmstate_esp_pdma, 870 NULL 871 } 872 }; 873 874 static void sysbus_esp_mem_write(void *opaque, hwaddr addr, 875 uint64_t val, unsigned int size) 876 { 877 SysBusESPState *sysbus = opaque; 878 ESPState *s = ESP(&sysbus->esp); 879 uint32_t saddr; 880 881 saddr = addr >> sysbus->it_shift; 882 esp_reg_write(s, saddr, val); 883 } 884 885 static uint64_t sysbus_esp_mem_read(void *opaque, hwaddr addr, 886 unsigned int size) 887 { 888 SysBusESPState *sysbus = opaque; 889 ESPState *s = ESP(&sysbus->esp); 890 uint32_t saddr; 891 892 saddr = addr >> sysbus->it_shift; 893 return esp_reg_read(s, saddr); 894 } 895 896 static const MemoryRegionOps sysbus_esp_mem_ops = { 897 .read = sysbus_esp_mem_read, 898 .write = sysbus_esp_mem_write, 899 .endianness = DEVICE_NATIVE_ENDIAN, 900 .valid.accepts = esp_mem_accepts, 901 }; 902 903 static void sysbus_esp_pdma_write(void *opaque, hwaddr addr, 904 uint64_t val, unsigned int size) 905 { 906 SysBusESPState *sysbus = opaque; 907 ESPState *s = ESP(&sysbus->esp); 908 uint32_t dmalen; 909 uint8_t *buf = get_pdma_buf(s); 910 911 trace_esp_pdma_write(size); 912 913 dmalen = esp_get_tc(s); 914 if (dmalen == 0 || s->pdma_len == 0) { 915 return; 916 } 917 switch (size) { 918 case 1: 919 buf[s->pdma_cur++] = val; 920 s->pdma_len--; 921 dmalen--; 922 break; 923 case 2: 924 buf[s->pdma_cur++] = val >> 8; 925 buf[s->pdma_cur++] = val; 926 s->pdma_len -= 2; 927 dmalen -= 2; 928 break; 929 } 930 esp_set_tc(s, dmalen); 931 if (s->pdma_len == 0 && s->pdma_cb) { 932 esp_lower_drq(s); 933 s->pdma_cb(s); 934 s->pdma_cb = NULL; 935 } 936 } 937 938 static uint64_t sysbus_esp_pdma_read(void *opaque, hwaddr addr, 939 unsigned int size) 940 { 941 SysBusESPState *sysbus = opaque; 942 ESPState *s = ESP(&sysbus->esp); 943 uint8_t *buf = get_pdma_buf(s); 944 uint64_t val = 0; 945 946 trace_esp_pdma_read(size); 947 948 if (s->pdma_len == 0) { 949 return 0; 950 } 951 switch (size) { 952 case 1: 953 val = buf[s->pdma_cur++]; 954 s->pdma_len--; 955 break; 956 case 2: 957 val = buf[s->pdma_cur++]; 958 val = (val << 8) | buf[s->pdma_cur++]; 959 s->pdma_len -= 2; 960 break; 961 } 962 963 if (s->pdma_len == 0 && s->pdma_cb) { 964 esp_lower_drq(s); 965 s->pdma_cb(s); 966 s->pdma_cb = NULL; 967 } 968 return val; 969 } 970 971 static const MemoryRegionOps sysbus_esp_pdma_ops = { 972 .read = sysbus_esp_pdma_read, 973 .write = sysbus_esp_pdma_write, 974 .endianness = DEVICE_NATIVE_ENDIAN, 975 .valid.min_access_size = 1, 976 .valid.max_access_size = 2, 977 }; 978 979 static const struct SCSIBusInfo esp_scsi_info = { 980 .tcq = false, 981 .max_target = ESP_MAX_DEVS, 982 .max_lun = 7, 983 984 .transfer_data = esp_transfer_data, 985 .complete = esp_command_complete, 986 .cancel = esp_request_cancelled 987 }; 988 989 static void sysbus_esp_gpio_demux(void *opaque, int irq, int level) 990 { 991 SysBusESPState *sysbus = SYSBUS_ESP(opaque); 992 ESPState *s = ESP(&sysbus->esp); 993 994 switch (irq) { 995 case 0: 996 parent_esp_reset(s, irq, level); 997 break; 998 case 1: 999 esp_dma_enable(opaque, irq, level); 1000 break; 1001 } 1002 } 1003 1004 static void sysbus_esp_realize(DeviceState *dev, Error **errp) 1005 { 1006 SysBusDevice *sbd = SYS_BUS_DEVICE(dev); 1007 SysBusESPState *sysbus = SYSBUS_ESP(dev); 1008 ESPState *s = ESP(&sysbus->esp); 1009 1010 if (!qdev_realize(DEVICE(s), NULL, errp)) { 1011 return; 1012 } 1013 1014 sysbus_init_irq(sbd, &s->irq); 1015 sysbus_init_irq(sbd, &s->irq_data); 1016 assert(sysbus->it_shift != -1); 1017 1018 s->chip_id = TCHI_FAS100A; 1019 memory_region_init_io(&sysbus->iomem, OBJECT(sysbus), &sysbus_esp_mem_ops, 1020 sysbus, "esp-regs", ESP_REGS << sysbus->it_shift); 1021 sysbus_init_mmio(sbd, &sysbus->iomem); 1022 memory_region_init_io(&sysbus->pdma, OBJECT(sysbus), &sysbus_esp_pdma_ops, 1023 sysbus, "esp-pdma", 2); 1024 sysbus_init_mmio(sbd, &sysbus->pdma); 1025 1026 qdev_init_gpio_in(dev, sysbus_esp_gpio_demux, 2); 1027 1028 scsi_bus_new(&s->bus, sizeof(s->bus), dev, &esp_scsi_info, NULL); 1029 } 1030 1031 static void sysbus_esp_hard_reset(DeviceState *dev) 1032 { 1033 SysBusESPState *sysbus = SYSBUS_ESP(dev); 1034 ESPState *s = ESP(&sysbus->esp); 1035 1036 esp_hard_reset(s); 1037 } 1038 1039 static void sysbus_esp_init(Object *obj) 1040 { 1041 SysBusESPState *sysbus = SYSBUS_ESP(obj); 1042 1043 object_initialize_child(obj, "esp", &sysbus->esp, TYPE_ESP); 1044 } 1045 1046 static const VMStateDescription vmstate_sysbus_esp_scsi = { 1047 .name = "sysbusespscsi", 1048 .version_id = 2, 1049 .minimum_version_id = 1, 1050 .fields = (VMStateField[]) { 1051 VMSTATE_UINT8_V(esp.mig_version_id, SysBusESPState, 2), 1052 VMSTATE_STRUCT(esp, SysBusESPState, 0, vmstate_esp, ESPState), 1053 VMSTATE_END_OF_LIST() 1054 } 1055 }; 1056 1057 static void sysbus_esp_class_init(ObjectClass *klass, void *data) 1058 { 1059 DeviceClass *dc = DEVICE_CLASS(klass); 1060 1061 dc->realize = sysbus_esp_realize; 1062 dc->reset = sysbus_esp_hard_reset; 1063 dc->vmsd = &vmstate_sysbus_esp_scsi; 1064 set_bit(DEVICE_CATEGORY_STORAGE, dc->categories); 1065 } 1066 1067 static const TypeInfo sysbus_esp_info = { 1068 .name = TYPE_SYSBUS_ESP, 1069 .parent = TYPE_SYS_BUS_DEVICE, 1070 .instance_init = sysbus_esp_init, 1071 .instance_size = sizeof(SysBusESPState), 1072 .class_init = sysbus_esp_class_init, 1073 }; 1074 1075 static void esp_class_init(ObjectClass *klass, void *data) 1076 { 1077 DeviceClass *dc = DEVICE_CLASS(klass); 1078 1079 /* internal device for sysbusesp/pciespscsi, not user-creatable */ 1080 dc->user_creatable = false; 1081 set_bit(DEVICE_CATEGORY_STORAGE, dc->categories); 1082 } 1083 1084 static const TypeInfo esp_info = { 1085 .name = TYPE_ESP, 1086 .parent = TYPE_DEVICE, 1087 .instance_size = sizeof(ESPState), 1088 .class_init = esp_class_init, 1089 }; 1090 1091 static void esp_register_types(void) 1092 { 1093 type_register_static(&sysbus_esp_info); 1094 type_register_static(&esp_info); 1095 } 1096 1097 type_init(esp_register_types) 1098