1 /* 2 * QEMU ESP/NCR53C9x emulation 3 * 4 * Copyright (c) 2005-2006 Fabrice Bellard 5 * Copyright (c) 2012 Herve Poussineau 6 * 7 * Permission is hereby granted, free of charge, to any person obtaining a copy 8 * of this software and associated documentation files (the "Software"), to deal 9 * in the Software without restriction, including without limitation the rights 10 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 11 * copies of the Software, and to permit persons to whom the Software is 12 * furnished to do so, subject to the following conditions: 13 * 14 * The above copyright notice and this permission notice shall be included in 15 * all copies or substantial portions of the Software. 16 * 17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 22 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 23 * THE SOFTWARE. 24 */ 25 26 #include "qemu/osdep.h" 27 #include "hw/sysbus.h" 28 #include "migration/vmstate.h" 29 #include "hw/irq.h" 30 #include "hw/scsi/esp.h" 31 #include "trace.h" 32 #include "qemu/log.h" 33 #include "qemu/module.h" 34 35 /* 36 * On Sparc32, this is the ESP (NCR53C90) part of chip STP2000 (Master I/O), 37 * also produced as NCR89C100. See 38 * http://www.ibiblio.org/pub/historic-linux/early-ports/Sparc/NCR/NCR89C100.txt 39 * and 40 * http://www.ibiblio.org/pub/historic-linux/early-ports/Sparc/NCR/NCR53C9X.txt 41 * 42 * On Macintosh Quadra it is a NCR53C96. 43 */ 44 45 static void esp_raise_irq(ESPState *s) 46 { 47 if (!(s->rregs[ESP_RSTAT] & STAT_INT)) { 48 s->rregs[ESP_RSTAT] |= STAT_INT; 49 qemu_irq_raise(s->irq); 50 trace_esp_raise_irq(); 51 } 52 } 53 54 static void esp_lower_irq(ESPState *s) 55 { 56 if (s->rregs[ESP_RSTAT] & STAT_INT) { 57 s->rregs[ESP_RSTAT] &= ~STAT_INT; 58 qemu_irq_lower(s->irq); 59 trace_esp_lower_irq(); 60 } 61 } 62 63 static void esp_raise_drq(ESPState *s) 64 { 65 qemu_irq_raise(s->irq_data); 66 trace_esp_raise_drq(); 67 } 68 69 static void esp_lower_drq(ESPState *s) 70 { 71 qemu_irq_lower(s->irq_data); 72 trace_esp_lower_drq(); 73 } 74 75 void esp_dma_enable(ESPState *s, int irq, int level) 76 { 77 if (level) { 78 s->dma_enabled = 1; 79 trace_esp_dma_enable(); 80 if (s->dma_cb) { 81 s->dma_cb(s); 82 s->dma_cb = NULL; 83 } 84 } else { 85 trace_esp_dma_disable(); 86 s->dma_enabled = 0; 87 } 88 } 89 90 void esp_request_cancelled(SCSIRequest *req) 91 { 92 ESPState *s = req->hba_private; 93 94 if (req == s->current_req) { 95 scsi_req_unref(s->current_req); 96 s->current_req = NULL; 97 s->current_dev = NULL; 98 s->async_len = 0; 99 } 100 } 101 102 static void esp_fifo_push(Fifo8 *fifo, uint8_t val) 103 { 104 if (fifo8_num_used(fifo) == fifo->capacity) { 105 trace_esp_error_fifo_overrun(); 106 return; 107 } 108 109 fifo8_push(fifo, val); 110 } 111 112 static uint8_t esp_fifo_pop(Fifo8 *fifo) 113 { 114 if (fifo8_is_empty(fifo)) { 115 return 0; 116 } 117 118 return fifo8_pop(fifo); 119 } 120 121 static uint32_t esp_fifo_pop_buf(Fifo8 *fifo, uint8_t *dest, int maxlen) 122 { 123 const uint8_t *buf; 124 uint32_t n, n2; 125 int len; 126 127 if (maxlen == 0) { 128 return 0; 129 } 130 131 len = maxlen; 132 buf = fifo8_pop_buf(fifo, len, &n); 133 if (dest) { 134 memcpy(dest, buf, n); 135 } 136 137 /* Add FIFO wraparound if needed */ 138 len -= n; 139 len = MIN(len, fifo8_num_used(fifo)); 140 if (len) { 141 buf = fifo8_pop_buf(fifo, len, &n2); 142 if (dest) { 143 memcpy(&dest[n], buf, n2); 144 } 145 n += n2; 146 } 147 148 return n; 149 } 150 151 static uint32_t esp_get_tc(ESPState *s) 152 { 153 uint32_t dmalen; 154 155 dmalen = s->rregs[ESP_TCLO]; 156 dmalen |= s->rregs[ESP_TCMID] << 8; 157 dmalen |= s->rregs[ESP_TCHI] << 16; 158 159 return dmalen; 160 } 161 162 static void esp_set_tc(ESPState *s, uint32_t dmalen) 163 { 164 uint32_t old_tc = esp_get_tc(s); 165 166 s->rregs[ESP_TCLO] = dmalen; 167 s->rregs[ESP_TCMID] = dmalen >> 8; 168 s->rregs[ESP_TCHI] = dmalen >> 16; 169 170 if (old_tc && dmalen == 0) { 171 s->rregs[ESP_RSTAT] |= STAT_TC; 172 } 173 } 174 175 static uint32_t esp_get_stc(ESPState *s) 176 { 177 uint32_t dmalen; 178 179 dmalen = s->wregs[ESP_TCLO]; 180 dmalen |= s->wregs[ESP_TCMID] << 8; 181 dmalen |= s->wregs[ESP_TCHI] << 16; 182 183 return dmalen; 184 } 185 186 static const char *esp_phase_names[8] = { 187 "DATA OUT", "DATA IN", "COMMAND", "STATUS", 188 "(reserved)", "(reserved)", "MESSAGE OUT", "MESSAGE IN" 189 }; 190 191 static void esp_set_phase(ESPState *s, uint8_t phase) 192 { 193 s->rregs[ESP_RSTAT] &= ~7; 194 s->rregs[ESP_RSTAT] |= phase; 195 196 trace_esp_set_phase(esp_phase_names[phase]); 197 } 198 199 static uint8_t esp_pdma_read(ESPState *s) 200 { 201 uint8_t val; 202 203 val = esp_fifo_pop(&s->fifo); 204 return val; 205 } 206 207 static void esp_pdma_write(ESPState *s, uint8_t val) 208 { 209 uint32_t dmalen = esp_get_tc(s); 210 211 if (dmalen == 0) { 212 return; 213 } 214 215 esp_fifo_push(&s->fifo, val); 216 217 dmalen--; 218 esp_set_tc(s, dmalen); 219 } 220 221 static void esp_set_pdma_cb(ESPState *s, enum pdma_cb cb) 222 { 223 s->pdma_cb = cb; 224 } 225 226 static int esp_select(ESPState *s) 227 { 228 int target; 229 230 target = s->wregs[ESP_WBUSID] & BUSID_DID; 231 232 s->ti_size = 0; 233 234 if (s->current_req) { 235 /* Started a new command before the old one finished. Cancel it. */ 236 scsi_req_cancel(s->current_req); 237 } 238 239 s->current_dev = scsi_device_find(&s->bus, 0, target, 0); 240 if (!s->current_dev) { 241 /* No such drive */ 242 s->rregs[ESP_RSTAT] = 0; 243 s->rregs[ESP_RINTR] = INTR_DC; 244 s->rregs[ESP_RSEQ] = SEQ_0; 245 esp_raise_irq(s); 246 return -1; 247 } 248 249 /* 250 * Note that we deliberately don't raise the IRQ here: this will be done 251 * either in do_command_phase() for DATA OUT transfers or by the deferred 252 * IRQ mechanism in esp_transfer_data() for DATA IN transfers 253 */ 254 s->rregs[ESP_RINTR] |= INTR_FC; 255 s->rregs[ESP_RSEQ] = SEQ_CD; 256 return 0; 257 } 258 259 static uint32_t get_cmd(ESPState *s, uint32_t maxlen) 260 { 261 uint8_t buf[ESP_CMDFIFO_SZ]; 262 uint32_t dmalen, n; 263 int target; 264 265 target = s->wregs[ESP_WBUSID] & BUSID_DID; 266 if (s->dma) { 267 dmalen = MIN(esp_get_tc(s), maxlen); 268 if (dmalen == 0) { 269 return 0; 270 } 271 if (s->dma_memory_read) { 272 s->dma_memory_read(s->dma_opaque, buf, dmalen); 273 dmalen = MIN(fifo8_num_free(&s->cmdfifo), dmalen); 274 fifo8_push_all(&s->cmdfifo, buf, dmalen); 275 esp_set_tc(s, esp_get_tc(s) - dmalen); 276 } else { 277 return 0; 278 } 279 } else { 280 dmalen = MIN(fifo8_num_used(&s->fifo), maxlen); 281 if (dmalen == 0) { 282 return 0; 283 } 284 n = esp_fifo_pop_buf(&s->fifo, buf, dmalen); 285 n = MIN(fifo8_num_free(&s->cmdfifo), n); 286 fifo8_push_all(&s->cmdfifo, buf, n); 287 } 288 trace_esp_get_cmd(dmalen, target); 289 290 return dmalen; 291 } 292 293 static void do_command_phase(ESPState *s) 294 { 295 uint32_t cmdlen; 296 int32_t datalen; 297 SCSIDevice *current_lun; 298 uint8_t buf[ESP_CMDFIFO_SZ]; 299 300 trace_esp_do_command_phase(s->lun); 301 cmdlen = fifo8_num_used(&s->cmdfifo); 302 if (!cmdlen || !s->current_dev) { 303 return; 304 } 305 esp_fifo_pop_buf(&s->cmdfifo, buf, cmdlen); 306 307 current_lun = scsi_device_find(&s->bus, 0, s->current_dev->id, s->lun); 308 if (!current_lun) { 309 /* No such drive */ 310 s->rregs[ESP_RSTAT] = 0; 311 s->rregs[ESP_RINTR] = INTR_DC; 312 s->rregs[ESP_RSEQ] = SEQ_0; 313 esp_raise_irq(s); 314 return; 315 } 316 317 s->current_req = scsi_req_new(current_lun, 0, s->lun, buf, cmdlen, s); 318 datalen = scsi_req_enqueue(s->current_req); 319 s->ti_size = datalen; 320 fifo8_reset(&s->cmdfifo); 321 if (datalen != 0) { 322 s->ti_cmd = 0; 323 if (datalen > 0) { 324 /* 325 * Switch to DATA IN phase but wait until initial data xfer is 326 * complete before raising the command completion interrupt 327 */ 328 s->data_in_ready = false; 329 esp_set_phase(s, STAT_DI); 330 } else { 331 esp_set_phase(s, STAT_DO); 332 s->rregs[ESP_RINTR] |= INTR_BS | INTR_FC; 333 esp_raise_irq(s); 334 esp_lower_drq(s); 335 } 336 scsi_req_continue(s->current_req); 337 return; 338 } 339 } 340 341 static void do_message_phase(ESPState *s) 342 { 343 if (s->cmdfifo_cdb_offset) { 344 uint8_t message = esp_fifo_pop(&s->cmdfifo); 345 346 trace_esp_do_identify(message); 347 s->lun = message & 7; 348 s->cmdfifo_cdb_offset--; 349 } 350 351 /* Ignore extended messages for now */ 352 if (s->cmdfifo_cdb_offset) { 353 int len = MIN(s->cmdfifo_cdb_offset, fifo8_num_used(&s->cmdfifo)); 354 esp_fifo_pop_buf(&s->cmdfifo, NULL, len); 355 s->cmdfifo_cdb_offset = 0; 356 } 357 } 358 359 static void do_cmd(ESPState *s) 360 { 361 do_message_phase(s); 362 assert(s->cmdfifo_cdb_offset == 0); 363 do_command_phase(s); 364 } 365 366 static void satn_pdma_cb(ESPState *s) 367 { 368 uint8_t buf[ESP_FIFO_SZ]; 369 int n; 370 371 /* Copy FIFO into cmdfifo */ 372 n = esp_fifo_pop_buf(&s->fifo, buf, fifo8_num_used(&s->fifo)); 373 n = MIN(fifo8_num_free(&s->cmdfifo), n); 374 fifo8_push_all(&s->cmdfifo, buf, n); 375 376 if (!esp_get_tc(s) && !fifo8_is_empty(&s->cmdfifo)) { 377 s->cmdfifo_cdb_offset = 1; 378 s->do_cmd = 0; 379 do_cmd(s); 380 } 381 } 382 383 static void handle_satn(ESPState *s) 384 { 385 int32_t cmdlen; 386 387 if (s->dma && !s->dma_enabled) { 388 s->dma_cb = handle_satn; 389 return; 390 } 391 esp_set_pdma_cb(s, SATN_PDMA_CB); 392 if (esp_select(s) < 0) { 393 return; 394 } 395 cmdlen = get_cmd(s, ESP_CMDFIFO_SZ); 396 if (cmdlen > 0) { 397 s->cmdfifo_cdb_offset = 1; 398 s->do_cmd = 0; 399 do_cmd(s); 400 } else if (cmdlen == 0) { 401 if (s->dma) { 402 esp_raise_drq(s); 403 } 404 s->do_cmd = 1; 405 /* Target present, but no cmd yet - switch to command phase */ 406 s->rregs[ESP_RSEQ] = SEQ_CD; 407 esp_set_phase(s, STAT_CD); 408 } 409 } 410 411 static void s_without_satn_pdma_cb(ESPState *s) 412 { 413 uint8_t buf[ESP_FIFO_SZ]; 414 int n; 415 416 /* Copy FIFO into cmdfifo */ 417 n = esp_fifo_pop_buf(&s->fifo, buf, fifo8_num_used(&s->fifo)); 418 n = MIN(fifo8_num_free(&s->cmdfifo), n); 419 fifo8_push_all(&s->cmdfifo, buf, n); 420 421 if (!esp_get_tc(s) && !fifo8_is_empty(&s->cmdfifo)) { 422 s->cmdfifo_cdb_offset = 0; 423 s->do_cmd = 0; 424 do_cmd(s); 425 } 426 } 427 428 static void handle_s_without_atn(ESPState *s) 429 { 430 int32_t cmdlen; 431 432 if (s->dma && !s->dma_enabled) { 433 s->dma_cb = handle_s_without_atn; 434 return; 435 } 436 esp_set_pdma_cb(s, S_WITHOUT_SATN_PDMA_CB); 437 if (esp_select(s) < 0) { 438 return; 439 } 440 cmdlen = get_cmd(s, ESP_CMDFIFO_SZ); 441 if (cmdlen > 0) { 442 s->cmdfifo_cdb_offset = 0; 443 s->do_cmd = 0; 444 do_cmd(s); 445 } else if (cmdlen == 0) { 446 if (s->dma) { 447 esp_raise_drq(s); 448 } 449 s->do_cmd = 1; 450 /* Target present, but no cmd yet - switch to command phase */ 451 s->rregs[ESP_RSEQ] = SEQ_CD; 452 esp_set_phase(s, STAT_CD); 453 } 454 } 455 456 static void satn_stop_pdma_cb(ESPState *s) 457 { 458 uint8_t buf[ESP_FIFO_SZ]; 459 int n; 460 461 /* Copy FIFO into cmdfifo */ 462 n = esp_fifo_pop_buf(&s->fifo, buf, fifo8_num_used(&s->fifo)); 463 n = MIN(fifo8_num_free(&s->cmdfifo), n); 464 fifo8_push_all(&s->cmdfifo, buf, n); 465 466 if (!esp_get_tc(s) && !fifo8_is_empty(&s->cmdfifo)) { 467 trace_esp_handle_satn_stop(fifo8_num_used(&s->cmdfifo)); 468 s->do_cmd = 1; 469 s->cmdfifo_cdb_offset = 1; 470 esp_set_phase(s, STAT_CD); 471 s->rregs[ESP_RSTAT] |= STAT_TC; 472 s->rregs[ESP_RINTR] |= INTR_BS | INTR_FC; 473 s->rregs[ESP_RSEQ] = SEQ_CD; 474 esp_raise_irq(s); 475 } 476 } 477 478 static void handle_satn_stop(ESPState *s) 479 { 480 int32_t cmdlen; 481 482 if (s->dma && !s->dma_enabled) { 483 s->dma_cb = handle_satn_stop; 484 return; 485 } 486 esp_set_pdma_cb(s, SATN_STOP_PDMA_CB); 487 if (esp_select(s) < 0) { 488 return; 489 } 490 cmdlen = get_cmd(s, 1); 491 if (cmdlen > 0) { 492 trace_esp_handle_satn_stop(fifo8_num_used(&s->cmdfifo)); 493 s->do_cmd = 1; 494 s->cmdfifo_cdb_offset = 1; 495 esp_set_phase(s, STAT_MO); 496 s->rregs[ESP_RINTR] |= INTR_BS | INTR_FC; 497 s->rregs[ESP_RSEQ] = SEQ_MO; 498 esp_raise_irq(s); 499 } else if (cmdlen == 0) { 500 if (s->dma) { 501 esp_raise_drq(s); 502 } 503 s->do_cmd = 1; 504 /* Target present, switch to message out phase */ 505 s->rregs[ESP_RSEQ] = SEQ_MO; 506 esp_set_phase(s, STAT_MO); 507 } 508 } 509 510 static void write_response_pdma_cb(ESPState *s) 511 { 512 esp_set_phase(s, STAT_ST); 513 s->rregs[ESP_RINTR] |= INTR_BS | INTR_FC; 514 s->rregs[ESP_RSEQ] = SEQ_CD; 515 esp_raise_irq(s); 516 } 517 518 static void write_response(ESPState *s) 519 { 520 uint8_t buf[2]; 521 522 trace_esp_write_response(s->status); 523 524 buf[0] = s->status; 525 buf[1] = 0; 526 527 if (s->dma) { 528 if (s->dma_memory_write) { 529 s->dma_memory_write(s->dma_opaque, buf, 2); 530 esp_set_phase(s, STAT_ST); 531 s->rregs[ESP_RINTR] |= INTR_BS | INTR_FC; 532 s->rregs[ESP_RSEQ] = SEQ_CD; 533 } else { 534 esp_set_pdma_cb(s, WRITE_RESPONSE_PDMA_CB); 535 esp_raise_drq(s); 536 return; 537 } 538 } else { 539 fifo8_reset(&s->fifo); 540 fifo8_push_all(&s->fifo, buf, 2); 541 s->rregs[ESP_RFLAGS] = 2; 542 } 543 esp_raise_irq(s); 544 } 545 546 static void esp_dma_done(ESPState *s) 547 { 548 s->rregs[ESP_RINTR] |= INTR_BS; 549 esp_raise_irq(s); 550 } 551 552 static void do_dma_pdma_cb(ESPState *s) 553 { 554 int to_device = ((s->rregs[ESP_RSTAT] & 7) == STAT_DO); 555 uint8_t buf[ESP_CMDFIFO_SZ]; 556 int len; 557 uint32_t n; 558 559 if (s->do_cmd) { 560 /* Copy FIFO into cmdfifo */ 561 n = esp_fifo_pop_buf(&s->fifo, buf, fifo8_num_used(&s->fifo)); 562 n = MIN(fifo8_num_free(&s->cmdfifo), n); 563 fifo8_push_all(&s->cmdfifo, buf, n); 564 565 /* Ensure we have received complete command after SATN and stop */ 566 if (esp_get_tc(s) || fifo8_is_empty(&s->cmdfifo)) { 567 return; 568 } 569 570 s->ti_size = 0; 571 if ((s->rregs[ESP_RSTAT] & 7) == STAT_CD) { 572 /* No command received */ 573 if (s->cmdfifo_cdb_offset == fifo8_num_used(&s->cmdfifo)) { 574 return; 575 } 576 577 /* Command has been received */ 578 s->do_cmd = 0; 579 do_cmd(s); 580 } else { 581 /* 582 * Extra message out bytes received: update cmdfifo_cdb_offset 583 * and then switch to command phase 584 */ 585 s->cmdfifo_cdb_offset = fifo8_num_used(&s->cmdfifo); 586 esp_set_phase(s, STAT_CD); 587 s->rregs[ESP_RSEQ] = SEQ_CD; 588 s->rregs[ESP_RINTR] |= INTR_BS; 589 esp_raise_irq(s); 590 } 591 return; 592 } 593 594 if (!s->current_req) { 595 return; 596 } 597 598 if (to_device) { 599 /* Copy FIFO data to device */ 600 len = MIN(s->async_len, ESP_FIFO_SZ); 601 len = MIN(len, fifo8_num_used(&s->fifo)); 602 n = esp_fifo_pop_buf(&s->fifo, s->async_buf, len); 603 s->async_buf += n; 604 s->async_len -= n; 605 s->ti_size += n; 606 607 if (n < len) { 608 /* Unaligned accesses can cause FIFO wraparound */ 609 len = len - n; 610 n = esp_fifo_pop_buf(&s->fifo, s->async_buf, len); 611 s->async_buf += n; 612 s->async_len -= n; 613 s->ti_size += n; 614 } 615 616 if (s->async_len == 0) { 617 scsi_req_continue(s->current_req); 618 return; 619 } 620 621 if (esp_get_tc(s) == 0) { 622 esp_lower_drq(s); 623 esp_dma_done(s); 624 } 625 626 return; 627 } else { 628 if (s->async_len == 0) { 629 /* Defer until the scsi layer has completed */ 630 scsi_req_continue(s->current_req); 631 s->data_in_ready = false; 632 return; 633 } 634 635 if (esp_get_tc(s) == 0) { 636 esp_lower_drq(s); 637 esp_dma_done(s); 638 } 639 640 /* Copy device data to FIFO */ 641 len = MIN(s->async_len, esp_get_tc(s)); 642 len = MIN(len, fifo8_num_free(&s->fifo)); 643 fifo8_push_all(&s->fifo, s->async_buf, len); 644 s->async_buf += len; 645 s->async_len -= len; 646 s->ti_size -= len; 647 esp_set_tc(s, esp_get_tc(s) - len); 648 } 649 } 650 651 static void esp_do_dma(ESPState *s) 652 { 653 uint32_t len, cmdlen; 654 int to_device = ((s->rregs[ESP_RSTAT] & 7) == STAT_DO); 655 uint8_t buf[ESP_CMDFIFO_SZ]; 656 657 len = esp_get_tc(s); 658 if (s->do_cmd) { 659 /* 660 * handle_ti_cmd() case: esp_do_dma() is called only from 661 * handle_ti_cmd() with do_cmd != NULL (see the assert()) 662 */ 663 cmdlen = fifo8_num_used(&s->cmdfifo); 664 trace_esp_do_dma(cmdlen, len); 665 if (s->dma_memory_read) { 666 len = MIN(len, fifo8_num_free(&s->cmdfifo)); 667 s->dma_memory_read(s->dma_opaque, buf, len); 668 fifo8_push_all(&s->cmdfifo, buf, len); 669 esp_set_tc(s, esp_get_tc(s) - len); 670 } else { 671 esp_set_pdma_cb(s, DO_DMA_PDMA_CB); 672 esp_raise_drq(s); 673 return; 674 } 675 trace_esp_handle_ti_cmd(cmdlen); 676 s->ti_size = 0; 677 if ((s->rregs[ESP_RSTAT] & 7) == STAT_CD) { 678 /* No command received */ 679 if (s->cmdfifo_cdb_offset == fifo8_num_used(&s->cmdfifo)) { 680 return; 681 } 682 683 /* Command has been received */ 684 s->do_cmd = 0; 685 do_cmd(s); 686 } else { 687 /* 688 * Extra message out bytes received: update cmdfifo_cdb_offset 689 * and then switch to command phase 690 */ 691 s->cmdfifo_cdb_offset = fifo8_num_used(&s->cmdfifo); 692 esp_set_phase(s, STAT_CD); 693 s->rregs[ESP_RSEQ] = SEQ_CD; 694 s->rregs[ESP_RINTR] |= INTR_BS; 695 esp_raise_irq(s); 696 } 697 return; 698 } 699 if (!s->current_req) { 700 return; 701 } 702 if (s->async_len == 0) { 703 /* Defer until data is available. */ 704 return; 705 } 706 if (len > s->async_len) { 707 len = s->async_len; 708 } 709 if (to_device) { 710 if (s->dma_memory_read) { 711 s->dma_memory_read(s->dma_opaque, s->async_buf, len); 712 713 esp_set_tc(s, esp_get_tc(s) - len); 714 s->async_buf += len; 715 s->async_len -= len; 716 s->ti_size += len; 717 718 if (s->async_len == 0) { 719 scsi_req_continue(s->current_req); 720 /* 721 * If there is still data to be read from the device then 722 * complete the DMA operation immediately. Otherwise defer 723 * until the scsi layer has completed. 724 */ 725 return; 726 } 727 728 /* Partially filled a scsi buffer. Complete immediately. */ 729 esp_dma_done(s); 730 esp_lower_drq(s); 731 } else { 732 esp_set_pdma_cb(s, DO_DMA_PDMA_CB); 733 esp_raise_drq(s); 734 } 735 } else { 736 if (s->dma_memory_write) { 737 s->dma_memory_write(s->dma_opaque, s->async_buf, len); 738 739 esp_set_tc(s, esp_get_tc(s) - len); 740 s->async_buf += len; 741 s->async_len -= len; 742 s->ti_size -= len; 743 744 if (s->async_len == 0) { 745 scsi_req_continue(s->current_req); 746 /* 747 * If there is still data to be read from the device then 748 * complete the DMA operation immediately. Otherwise defer 749 * until the scsi layer has completed. 750 */ 751 if (esp_get_tc(s) != 0 || s->ti_size == 0) { 752 return; 753 } 754 } 755 756 /* Partially filled a scsi buffer. Complete immediately. */ 757 esp_dma_done(s); 758 esp_lower_drq(s); 759 } else { 760 /* Adjust TC for any leftover data in the FIFO */ 761 if (!fifo8_is_empty(&s->fifo)) { 762 esp_set_tc(s, esp_get_tc(s) - fifo8_num_used(&s->fifo)); 763 } 764 765 /* Copy device data to FIFO */ 766 len = MIN(len, fifo8_num_free(&s->fifo)); 767 fifo8_push_all(&s->fifo, s->async_buf, len); 768 s->async_buf += len; 769 s->async_len -= len; 770 s->ti_size -= len; 771 esp_set_tc(s, esp_get_tc(s) - len); 772 esp_set_pdma_cb(s, DO_DMA_PDMA_CB); 773 esp_raise_drq(s); 774 } 775 } 776 } 777 778 static void esp_do_nodma(ESPState *s) 779 { 780 int to_device = ((s->rregs[ESP_RSTAT] & 7) == STAT_DO); 781 uint8_t buf[ESP_FIFO_SZ]; 782 uint32_t cmdlen; 783 int len, n; 784 785 if (s->do_cmd) { 786 /* Copy FIFO into cmdfifo */ 787 n = esp_fifo_pop_buf(&s->fifo, buf, fifo8_num_used(&s->fifo)); 788 n = MIN(fifo8_num_free(&s->cmdfifo), n); 789 fifo8_push_all(&s->cmdfifo, buf, n); 790 791 cmdlen = fifo8_num_used(&s->cmdfifo); 792 trace_esp_handle_ti_cmd(cmdlen); 793 s->ti_size = 0; 794 if ((s->rregs[ESP_RSTAT] & 7) == STAT_CD) { 795 /* No command received */ 796 if (s->cmdfifo_cdb_offset == fifo8_num_used(&s->cmdfifo)) { 797 return; 798 } 799 800 /* Command has been received */ 801 s->do_cmd = 0; 802 do_cmd(s); 803 } else { 804 /* 805 * Extra message out bytes received: update cmdfifo_cdb_offset 806 * and then switch to command phase 807 */ 808 s->cmdfifo_cdb_offset = fifo8_num_used(&s->cmdfifo); 809 esp_set_phase(s, STAT_CD); 810 s->rregs[ESP_RSEQ] = SEQ_CD; 811 s->rregs[ESP_RINTR] |= INTR_BS; 812 esp_raise_irq(s); 813 } 814 return; 815 } 816 817 if (!s->current_req) { 818 return; 819 } 820 821 if (s->async_len == 0) { 822 /* Defer until data is available. */ 823 return; 824 } 825 826 if (to_device) { 827 len = MIN(s->async_len, ESP_FIFO_SZ); 828 len = MIN(len, fifo8_num_used(&s->fifo)); 829 esp_fifo_pop_buf(&s->fifo, s->async_buf, len); 830 s->async_buf += len; 831 s->async_len -= len; 832 s->ti_size += len; 833 } else { 834 if (fifo8_is_empty(&s->fifo)) { 835 fifo8_push(&s->fifo, s->async_buf[0]); 836 s->async_buf++; 837 s->async_len--; 838 s->ti_size--; 839 } 840 } 841 842 if (s->async_len == 0) { 843 scsi_req_continue(s->current_req); 844 return; 845 } 846 847 s->rregs[ESP_RINTR] |= INTR_BS; 848 esp_raise_irq(s); 849 } 850 851 static void esp_pdma_cb(ESPState *s) 852 { 853 switch (s->pdma_cb) { 854 case SATN_PDMA_CB: 855 satn_pdma_cb(s); 856 break; 857 case S_WITHOUT_SATN_PDMA_CB: 858 s_without_satn_pdma_cb(s); 859 break; 860 case SATN_STOP_PDMA_CB: 861 satn_stop_pdma_cb(s); 862 break; 863 case WRITE_RESPONSE_PDMA_CB: 864 write_response_pdma_cb(s); 865 break; 866 case DO_DMA_PDMA_CB: 867 do_dma_pdma_cb(s); 868 break; 869 default: 870 g_assert_not_reached(); 871 } 872 } 873 874 void esp_command_complete(SCSIRequest *req, size_t resid) 875 { 876 ESPState *s = req->hba_private; 877 int to_device = ((s->rregs[ESP_RSTAT] & 7) == STAT_DO); 878 879 trace_esp_command_complete(); 880 881 /* 882 * Non-DMA transfers from the target will leave the last byte in 883 * the FIFO so don't reset ti_size in this case 884 */ 885 if (s->dma || to_device) { 886 if (s->ti_size != 0) { 887 trace_esp_command_complete_unexpected(); 888 } 889 s->ti_size = 0; 890 } 891 892 s->async_len = 0; 893 if (req->status) { 894 trace_esp_command_complete_fail(); 895 } 896 s->status = req->status; 897 898 /* 899 * If the transfer is finished, switch to status phase. For non-DMA 900 * transfers from the target the last byte is still in the FIFO 901 */ 902 if (s->ti_size == 0) { 903 esp_set_phase(s, STAT_ST); 904 esp_dma_done(s); 905 esp_lower_drq(s); 906 } 907 908 if (s->current_req) { 909 scsi_req_unref(s->current_req); 910 s->current_req = NULL; 911 s->current_dev = NULL; 912 } 913 } 914 915 void esp_transfer_data(SCSIRequest *req, uint32_t len) 916 { 917 ESPState *s = req->hba_private; 918 int to_device = ((s->rregs[ESP_RSTAT] & 7) == STAT_DO); 919 uint32_t dmalen = esp_get_tc(s); 920 921 assert(!s->do_cmd); 922 trace_esp_transfer_data(dmalen, s->ti_size); 923 s->async_len = len; 924 s->async_buf = scsi_req_get_buf(req); 925 926 if (!to_device && !s->data_in_ready) { 927 /* 928 * Initial incoming data xfer is complete so raise command 929 * completion interrupt 930 */ 931 s->data_in_ready = true; 932 s->rregs[ESP_RINTR] |= INTR_BS; 933 esp_raise_irq(s); 934 } 935 936 if (s->ti_cmd == 0) { 937 /* 938 * Always perform the initial transfer upon reception of the next TI 939 * command to ensure the DMA/non-DMA status of the command is correct. 940 * It is not possible to use s->dma directly in the section below as 941 * some OSs send non-DMA NOP commands after a DMA transfer. Hence if the 942 * async data transfer is delayed then s->dma is set incorrectly. 943 */ 944 return; 945 } 946 947 if (s->ti_cmd == (CMD_TI | CMD_DMA)) { 948 if (dmalen) { 949 esp_do_dma(s); 950 } else if (s->ti_size <= 0) { 951 /* 952 * If this was the last part of a DMA transfer then the 953 * completion interrupt is deferred to here. 954 */ 955 esp_dma_done(s); 956 esp_lower_drq(s); 957 } 958 } else if (s->ti_cmd == CMD_TI) { 959 esp_do_nodma(s); 960 } 961 } 962 963 static void handle_ti(ESPState *s) 964 { 965 uint32_t dmalen; 966 967 if (s->dma && !s->dma_enabled) { 968 s->dma_cb = handle_ti; 969 return; 970 } 971 972 s->ti_cmd = s->rregs[ESP_CMD]; 973 if (s->dma) { 974 dmalen = esp_get_tc(s); 975 trace_esp_handle_ti(dmalen); 976 esp_do_dma(s); 977 } else { 978 trace_esp_handle_ti(s->ti_size); 979 esp_do_nodma(s); 980 } 981 } 982 983 void esp_hard_reset(ESPState *s) 984 { 985 memset(s->rregs, 0, ESP_REGS); 986 memset(s->wregs, 0, ESP_REGS); 987 s->tchi_written = 0; 988 s->ti_size = 0; 989 s->async_len = 0; 990 fifo8_reset(&s->fifo); 991 fifo8_reset(&s->cmdfifo); 992 s->dma = 0; 993 s->do_cmd = 0; 994 s->dma_cb = NULL; 995 996 s->rregs[ESP_CFG1] = 7; 997 } 998 999 static void esp_soft_reset(ESPState *s) 1000 { 1001 qemu_irq_lower(s->irq); 1002 qemu_irq_lower(s->irq_data); 1003 esp_hard_reset(s); 1004 } 1005 1006 static void esp_bus_reset(ESPState *s) 1007 { 1008 bus_cold_reset(BUS(&s->bus)); 1009 } 1010 1011 static void parent_esp_reset(ESPState *s, int irq, int level) 1012 { 1013 if (level) { 1014 esp_soft_reset(s); 1015 } 1016 } 1017 1018 static void esp_run_cmd(ESPState *s) 1019 { 1020 uint8_t cmd = s->rregs[ESP_CMD]; 1021 1022 if (cmd & CMD_DMA) { 1023 s->dma = 1; 1024 /* Reload DMA counter. */ 1025 if (esp_get_stc(s) == 0) { 1026 esp_set_tc(s, 0x10000); 1027 } else { 1028 esp_set_tc(s, esp_get_stc(s)); 1029 } 1030 } else { 1031 s->dma = 0; 1032 } 1033 switch (cmd & CMD_CMD) { 1034 case CMD_NOP: 1035 trace_esp_mem_writeb_cmd_nop(cmd); 1036 break; 1037 case CMD_FLUSH: 1038 trace_esp_mem_writeb_cmd_flush(cmd); 1039 fifo8_reset(&s->fifo); 1040 break; 1041 case CMD_RESET: 1042 trace_esp_mem_writeb_cmd_reset(cmd); 1043 esp_soft_reset(s); 1044 break; 1045 case CMD_BUSRESET: 1046 trace_esp_mem_writeb_cmd_bus_reset(cmd); 1047 esp_bus_reset(s); 1048 if (!(s->wregs[ESP_CFG1] & CFG1_RESREPT)) { 1049 s->rregs[ESP_RINTR] |= INTR_RST; 1050 esp_raise_irq(s); 1051 } 1052 break; 1053 case CMD_TI: 1054 trace_esp_mem_writeb_cmd_ti(cmd); 1055 handle_ti(s); 1056 break; 1057 case CMD_ICCS: 1058 trace_esp_mem_writeb_cmd_iccs(cmd); 1059 write_response(s); 1060 s->rregs[ESP_RINTR] |= INTR_FC; 1061 esp_set_phase(s, STAT_MI); 1062 break; 1063 case CMD_MSGACC: 1064 trace_esp_mem_writeb_cmd_msgacc(cmd); 1065 s->rregs[ESP_RINTR] |= INTR_DC; 1066 s->rregs[ESP_RSEQ] = 0; 1067 s->rregs[ESP_RFLAGS] = 0; 1068 esp_raise_irq(s); 1069 break; 1070 case CMD_PAD: 1071 trace_esp_mem_writeb_cmd_pad(cmd); 1072 s->rregs[ESP_RSTAT] = STAT_TC; 1073 s->rregs[ESP_RINTR] |= INTR_FC; 1074 s->rregs[ESP_RSEQ] = 0; 1075 break; 1076 case CMD_SATN: 1077 trace_esp_mem_writeb_cmd_satn(cmd); 1078 break; 1079 case CMD_RSTATN: 1080 trace_esp_mem_writeb_cmd_rstatn(cmd); 1081 break; 1082 case CMD_SEL: 1083 trace_esp_mem_writeb_cmd_sel(cmd); 1084 handle_s_without_atn(s); 1085 break; 1086 case CMD_SELATN: 1087 trace_esp_mem_writeb_cmd_selatn(cmd); 1088 handle_satn(s); 1089 break; 1090 case CMD_SELATNS: 1091 trace_esp_mem_writeb_cmd_selatns(cmd); 1092 handle_satn_stop(s); 1093 break; 1094 case CMD_ENSEL: 1095 trace_esp_mem_writeb_cmd_ensel(cmd); 1096 s->rregs[ESP_RINTR] = 0; 1097 break; 1098 case CMD_DISSEL: 1099 trace_esp_mem_writeb_cmd_dissel(cmd); 1100 s->rregs[ESP_RINTR] = 0; 1101 esp_raise_irq(s); 1102 break; 1103 default: 1104 trace_esp_error_unhandled_command(cmd); 1105 break; 1106 } 1107 } 1108 1109 uint64_t esp_reg_read(ESPState *s, uint32_t saddr) 1110 { 1111 uint32_t val; 1112 1113 switch (saddr) { 1114 case ESP_FIFO: 1115 if (s->dma_memory_read && s->dma_memory_write && 1116 (s->rregs[ESP_RSTAT] & STAT_PIO_MASK) == 0) { 1117 /* Data out. */ 1118 qemu_log_mask(LOG_UNIMP, "esp: PIO data read not implemented\n"); 1119 s->rregs[ESP_FIFO] = 0; 1120 } else { 1121 if ((s->rregs[ESP_RSTAT] & 0x7) == STAT_DI) { 1122 if (s->ti_size) { 1123 esp_do_nodma(s); 1124 } else { 1125 /* 1126 * The last byte of a non-DMA transfer has been read out 1127 * of the FIFO so switch to status phase 1128 */ 1129 esp_set_phase(s, STAT_ST); 1130 } 1131 } 1132 s->rregs[ESP_FIFO] = esp_fifo_pop(&s->fifo); 1133 } 1134 val = s->rregs[ESP_FIFO]; 1135 break; 1136 case ESP_RINTR: 1137 /* 1138 * Clear sequence step, interrupt register and all status bits 1139 * except TC 1140 */ 1141 val = s->rregs[ESP_RINTR]; 1142 s->rregs[ESP_RINTR] = 0; 1143 s->rregs[ESP_RSTAT] &= ~STAT_TC; 1144 /* 1145 * According to the datasheet ESP_RSEQ should be cleared, but as the 1146 * emulation currently defers information transfers to the next TI 1147 * command leave it for now so that pedantic guests such as the old 1148 * Linux 2.6 driver see the correct flags before the next SCSI phase 1149 * transition. 1150 * 1151 * s->rregs[ESP_RSEQ] = SEQ_0; 1152 */ 1153 esp_lower_irq(s); 1154 break; 1155 case ESP_TCHI: 1156 /* Return the unique id if the value has never been written */ 1157 if (!s->tchi_written) { 1158 val = s->chip_id; 1159 } else { 1160 val = s->rregs[saddr]; 1161 } 1162 break; 1163 case ESP_RFLAGS: 1164 /* Bottom 5 bits indicate number of bytes in FIFO */ 1165 val = fifo8_num_used(&s->fifo); 1166 break; 1167 default: 1168 val = s->rregs[saddr]; 1169 break; 1170 } 1171 1172 trace_esp_mem_readb(saddr, val); 1173 return val; 1174 } 1175 1176 void esp_reg_write(ESPState *s, uint32_t saddr, uint64_t val) 1177 { 1178 trace_esp_mem_writeb(saddr, s->wregs[saddr], val); 1179 switch (saddr) { 1180 case ESP_TCHI: 1181 s->tchi_written = true; 1182 /* fall through */ 1183 case ESP_TCLO: 1184 case ESP_TCMID: 1185 s->rregs[ESP_RSTAT] &= ~STAT_TC; 1186 break; 1187 case ESP_FIFO: 1188 if (s->do_cmd) { 1189 if (!fifo8_is_full(&s->fifo)) { 1190 esp_fifo_push(&s->fifo, val); 1191 esp_fifo_push(&s->cmdfifo, fifo8_pop(&s->fifo)); 1192 } 1193 1194 /* 1195 * If any unexpected message out/command phase data is 1196 * transferred using non-DMA, raise the interrupt 1197 */ 1198 if (s->rregs[ESP_CMD] == CMD_TI) { 1199 s->rregs[ESP_RINTR] |= INTR_BS; 1200 esp_raise_irq(s); 1201 } 1202 } else { 1203 esp_fifo_push(&s->fifo, val); 1204 } 1205 break; 1206 case ESP_CMD: 1207 s->rregs[saddr] = val; 1208 esp_run_cmd(s); 1209 break; 1210 case ESP_WBUSID ... ESP_WSYNO: 1211 break; 1212 case ESP_CFG1: 1213 case ESP_CFG2: case ESP_CFG3: 1214 case ESP_RES3: case ESP_RES4: 1215 s->rregs[saddr] = val; 1216 break; 1217 case ESP_WCCF ... ESP_WTEST: 1218 break; 1219 default: 1220 trace_esp_error_invalid_write(val, saddr); 1221 return; 1222 } 1223 s->wregs[saddr] = val; 1224 } 1225 1226 static bool esp_mem_accepts(void *opaque, hwaddr addr, 1227 unsigned size, bool is_write, 1228 MemTxAttrs attrs) 1229 { 1230 return (size == 1) || (is_write && size == 4); 1231 } 1232 1233 static bool esp_is_before_version_5(void *opaque, int version_id) 1234 { 1235 ESPState *s = ESP(opaque); 1236 1237 version_id = MIN(version_id, s->mig_version_id); 1238 return version_id < 5; 1239 } 1240 1241 static bool esp_is_version_5(void *opaque, int version_id) 1242 { 1243 ESPState *s = ESP(opaque); 1244 1245 version_id = MIN(version_id, s->mig_version_id); 1246 return version_id >= 5; 1247 } 1248 1249 static bool esp_is_version_6(void *opaque, int version_id) 1250 { 1251 ESPState *s = ESP(opaque); 1252 1253 version_id = MIN(version_id, s->mig_version_id); 1254 return version_id >= 6; 1255 } 1256 1257 int esp_pre_save(void *opaque) 1258 { 1259 ESPState *s = ESP(object_resolve_path_component( 1260 OBJECT(opaque), "esp")); 1261 1262 s->mig_version_id = vmstate_esp.version_id; 1263 return 0; 1264 } 1265 1266 static int esp_post_load(void *opaque, int version_id) 1267 { 1268 ESPState *s = ESP(opaque); 1269 int len, i; 1270 1271 version_id = MIN(version_id, s->mig_version_id); 1272 1273 if (version_id < 5) { 1274 esp_set_tc(s, s->mig_dma_left); 1275 1276 /* Migrate ti_buf to fifo */ 1277 len = s->mig_ti_wptr - s->mig_ti_rptr; 1278 for (i = 0; i < len; i++) { 1279 fifo8_push(&s->fifo, s->mig_ti_buf[i]); 1280 } 1281 1282 /* Migrate cmdbuf to cmdfifo */ 1283 for (i = 0; i < s->mig_cmdlen; i++) { 1284 fifo8_push(&s->cmdfifo, s->mig_cmdbuf[i]); 1285 } 1286 } 1287 1288 s->mig_version_id = vmstate_esp.version_id; 1289 return 0; 1290 } 1291 1292 /* 1293 * PDMA (or pseudo-DMA) is only used on the Macintosh and requires the 1294 * guest CPU to perform the transfers between the SCSI bus and memory 1295 * itself. This is indicated by the dma_memory_read and dma_memory_write 1296 * functions being NULL (in contrast to the ESP PCI device) whilst 1297 * dma_enabled is still set. 1298 */ 1299 1300 static bool esp_pdma_needed(void *opaque) 1301 { 1302 ESPState *s = ESP(opaque); 1303 1304 return s->dma_memory_read == NULL && s->dma_memory_write == NULL && 1305 s->dma_enabled; 1306 } 1307 1308 static const VMStateDescription vmstate_esp_pdma = { 1309 .name = "esp/pdma", 1310 .version_id = 0, 1311 .minimum_version_id = 0, 1312 .needed = esp_pdma_needed, 1313 .fields = (const VMStateField[]) { 1314 VMSTATE_UINT8(pdma_cb, ESPState), 1315 VMSTATE_END_OF_LIST() 1316 } 1317 }; 1318 1319 const VMStateDescription vmstate_esp = { 1320 .name = "esp", 1321 .version_id = 6, 1322 .minimum_version_id = 3, 1323 .post_load = esp_post_load, 1324 .fields = (const VMStateField[]) { 1325 VMSTATE_BUFFER(rregs, ESPState), 1326 VMSTATE_BUFFER(wregs, ESPState), 1327 VMSTATE_INT32(ti_size, ESPState), 1328 VMSTATE_UINT32_TEST(mig_ti_rptr, ESPState, esp_is_before_version_5), 1329 VMSTATE_UINT32_TEST(mig_ti_wptr, ESPState, esp_is_before_version_5), 1330 VMSTATE_BUFFER_TEST(mig_ti_buf, ESPState, esp_is_before_version_5), 1331 VMSTATE_UINT32(status, ESPState), 1332 VMSTATE_UINT32_TEST(mig_deferred_status, ESPState, 1333 esp_is_before_version_5), 1334 VMSTATE_BOOL_TEST(mig_deferred_complete, ESPState, 1335 esp_is_before_version_5), 1336 VMSTATE_UINT32(dma, ESPState), 1337 VMSTATE_STATIC_BUFFER(mig_cmdbuf, ESPState, 0, 1338 esp_is_before_version_5, 0, 16), 1339 VMSTATE_STATIC_BUFFER(mig_cmdbuf, ESPState, 4, 1340 esp_is_before_version_5, 16, 1341 sizeof(typeof_field(ESPState, mig_cmdbuf))), 1342 VMSTATE_UINT32_TEST(mig_cmdlen, ESPState, esp_is_before_version_5), 1343 VMSTATE_UINT32(do_cmd, ESPState), 1344 VMSTATE_UINT32_TEST(mig_dma_left, ESPState, esp_is_before_version_5), 1345 VMSTATE_BOOL_TEST(data_in_ready, ESPState, esp_is_version_5), 1346 VMSTATE_UINT8_TEST(cmdfifo_cdb_offset, ESPState, esp_is_version_5), 1347 VMSTATE_FIFO8_TEST(fifo, ESPState, esp_is_version_5), 1348 VMSTATE_FIFO8_TEST(cmdfifo, ESPState, esp_is_version_5), 1349 VMSTATE_UINT8_TEST(ti_cmd, ESPState, esp_is_version_5), 1350 VMSTATE_UINT8_TEST(lun, ESPState, esp_is_version_6), 1351 VMSTATE_END_OF_LIST() 1352 }, 1353 .subsections = (const VMStateDescription * const []) { 1354 &vmstate_esp_pdma, 1355 NULL 1356 } 1357 }; 1358 1359 static void sysbus_esp_mem_write(void *opaque, hwaddr addr, 1360 uint64_t val, unsigned int size) 1361 { 1362 SysBusESPState *sysbus = opaque; 1363 ESPState *s = ESP(&sysbus->esp); 1364 uint32_t saddr; 1365 1366 saddr = addr >> sysbus->it_shift; 1367 esp_reg_write(s, saddr, val); 1368 } 1369 1370 static uint64_t sysbus_esp_mem_read(void *opaque, hwaddr addr, 1371 unsigned int size) 1372 { 1373 SysBusESPState *sysbus = opaque; 1374 ESPState *s = ESP(&sysbus->esp); 1375 uint32_t saddr; 1376 1377 saddr = addr >> sysbus->it_shift; 1378 return esp_reg_read(s, saddr); 1379 } 1380 1381 static const MemoryRegionOps sysbus_esp_mem_ops = { 1382 .read = sysbus_esp_mem_read, 1383 .write = sysbus_esp_mem_write, 1384 .endianness = DEVICE_NATIVE_ENDIAN, 1385 .valid.accepts = esp_mem_accepts, 1386 }; 1387 1388 static void sysbus_esp_pdma_write(void *opaque, hwaddr addr, 1389 uint64_t val, unsigned int size) 1390 { 1391 SysBusESPState *sysbus = opaque; 1392 ESPState *s = ESP(&sysbus->esp); 1393 1394 trace_esp_pdma_write(size); 1395 1396 switch (size) { 1397 case 1: 1398 esp_pdma_write(s, val); 1399 break; 1400 case 2: 1401 esp_pdma_write(s, val >> 8); 1402 esp_pdma_write(s, val); 1403 break; 1404 } 1405 esp_pdma_cb(s); 1406 } 1407 1408 static uint64_t sysbus_esp_pdma_read(void *opaque, hwaddr addr, 1409 unsigned int size) 1410 { 1411 SysBusESPState *sysbus = opaque; 1412 ESPState *s = ESP(&sysbus->esp); 1413 uint64_t val = 0; 1414 1415 trace_esp_pdma_read(size); 1416 1417 switch (size) { 1418 case 1: 1419 val = esp_pdma_read(s); 1420 break; 1421 case 2: 1422 val = esp_pdma_read(s); 1423 val = (val << 8) | esp_pdma_read(s); 1424 break; 1425 } 1426 if (fifo8_num_used(&s->fifo) < 2) { 1427 esp_pdma_cb(s); 1428 } 1429 return val; 1430 } 1431 1432 static void *esp_load_request(QEMUFile *f, SCSIRequest *req) 1433 { 1434 ESPState *s = container_of(req->bus, ESPState, bus); 1435 1436 scsi_req_ref(req); 1437 s->current_req = req; 1438 return s; 1439 } 1440 1441 static const MemoryRegionOps sysbus_esp_pdma_ops = { 1442 .read = sysbus_esp_pdma_read, 1443 .write = sysbus_esp_pdma_write, 1444 .endianness = DEVICE_NATIVE_ENDIAN, 1445 .valid.min_access_size = 1, 1446 .valid.max_access_size = 4, 1447 .impl.min_access_size = 1, 1448 .impl.max_access_size = 2, 1449 }; 1450 1451 static const struct SCSIBusInfo esp_scsi_info = { 1452 .tcq = false, 1453 .max_target = ESP_MAX_DEVS, 1454 .max_lun = 7, 1455 1456 .load_request = esp_load_request, 1457 .transfer_data = esp_transfer_data, 1458 .complete = esp_command_complete, 1459 .cancel = esp_request_cancelled 1460 }; 1461 1462 static void sysbus_esp_gpio_demux(void *opaque, int irq, int level) 1463 { 1464 SysBusESPState *sysbus = SYSBUS_ESP(opaque); 1465 ESPState *s = ESP(&sysbus->esp); 1466 1467 switch (irq) { 1468 case 0: 1469 parent_esp_reset(s, irq, level); 1470 break; 1471 case 1: 1472 esp_dma_enable(s, irq, level); 1473 break; 1474 } 1475 } 1476 1477 static void sysbus_esp_realize(DeviceState *dev, Error **errp) 1478 { 1479 SysBusDevice *sbd = SYS_BUS_DEVICE(dev); 1480 SysBusESPState *sysbus = SYSBUS_ESP(dev); 1481 ESPState *s = ESP(&sysbus->esp); 1482 1483 if (!qdev_realize(DEVICE(s), NULL, errp)) { 1484 return; 1485 } 1486 1487 sysbus_init_irq(sbd, &s->irq); 1488 sysbus_init_irq(sbd, &s->irq_data); 1489 assert(sysbus->it_shift != -1); 1490 1491 s->chip_id = TCHI_FAS100A; 1492 memory_region_init_io(&sysbus->iomem, OBJECT(sysbus), &sysbus_esp_mem_ops, 1493 sysbus, "esp-regs", ESP_REGS << sysbus->it_shift); 1494 sysbus_init_mmio(sbd, &sysbus->iomem); 1495 memory_region_init_io(&sysbus->pdma, OBJECT(sysbus), &sysbus_esp_pdma_ops, 1496 sysbus, "esp-pdma", 4); 1497 sysbus_init_mmio(sbd, &sysbus->pdma); 1498 1499 qdev_init_gpio_in(dev, sysbus_esp_gpio_demux, 2); 1500 1501 scsi_bus_init(&s->bus, sizeof(s->bus), dev, &esp_scsi_info); 1502 } 1503 1504 static void sysbus_esp_hard_reset(DeviceState *dev) 1505 { 1506 SysBusESPState *sysbus = SYSBUS_ESP(dev); 1507 ESPState *s = ESP(&sysbus->esp); 1508 1509 esp_hard_reset(s); 1510 } 1511 1512 static void sysbus_esp_init(Object *obj) 1513 { 1514 SysBusESPState *sysbus = SYSBUS_ESP(obj); 1515 1516 object_initialize_child(obj, "esp", &sysbus->esp, TYPE_ESP); 1517 } 1518 1519 static const VMStateDescription vmstate_sysbus_esp_scsi = { 1520 .name = "sysbusespscsi", 1521 .version_id = 2, 1522 .minimum_version_id = 1, 1523 .pre_save = esp_pre_save, 1524 .fields = (const VMStateField[]) { 1525 VMSTATE_UINT8_V(esp.mig_version_id, SysBusESPState, 2), 1526 VMSTATE_STRUCT(esp, SysBusESPState, 0, vmstate_esp, ESPState), 1527 VMSTATE_END_OF_LIST() 1528 } 1529 }; 1530 1531 static void sysbus_esp_class_init(ObjectClass *klass, void *data) 1532 { 1533 DeviceClass *dc = DEVICE_CLASS(klass); 1534 1535 dc->realize = sysbus_esp_realize; 1536 dc->reset = sysbus_esp_hard_reset; 1537 dc->vmsd = &vmstate_sysbus_esp_scsi; 1538 set_bit(DEVICE_CATEGORY_STORAGE, dc->categories); 1539 } 1540 1541 static const TypeInfo sysbus_esp_info = { 1542 .name = TYPE_SYSBUS_ESP, 1543 .parent = TYPE_SYS_BUS_DEVICE, 1544 .instance_init = sysbus_esp_init, 1545 .instance_size = sizeof(SysBusESPState), 1546 .class_init = sysbus_esp_class_init, 1547 }; 1548 1549 static void esp_finalize(Object *obj) 1550 { 1551 ESPState *s = ESP(obj); 1552 1553 fifo8_destroy(&s->fifo); 1554 fifo8_destroy(&s->cmdfifo); 1555 } 1556 1557 static void esp_init(Object *obj) 1558 { 1559 ESPState *s = ESP(obj); 1560 1561 fifo8_create(&s->fifo, ESP_FIFO_SZ); 1562 fifo8_create(&s->cmdfifo, ESP_CMDFIFO_SZ); 1563 } 1564 1565 static void esp_class_init(ObjectClass *klass, void *data) 1566 { 1567 DeviceClass *dc = DEVICE_CLASS(klass); 1568 1569 /* internal device for sysbusesp/pciespscsi, not user-creatable */ 1570 dc->user_creatable = false; 1571 set_bit(DEVICE_CATEGORY_STORAGE, dc->categories); 1572 } 1573 1574 static const TypeInfo esp_info = { 1575 .name = TYPE_ESP, 1576 .parent = TYPE_DEVICE, 1577 .instance_init = esp_init, 1578 .instance_finalize = esp_finalize, 1579 .instance_size = sizeof(ESPState), 1580 .class_init = esp_class_init, 1581 }; 1582 1583 static void esp_register_types(void) 1584 { 1585 type_register_static(&sysbus_esp_info); 1586 type_register_static(&esp_info); 1587 } 1588 1589 type_init(esp_register_types) 1590