1 /* 2 * QEMU ESP/NCR53C9x emulation 3 * 4 * Copyright (c) 2005-2006 Fabrice Bellard 5 * Copyright (c) 2012 Herve Poussineau 6 * 7 * Permission is hereby granted, free of charge, to any person obtaining a copy 8 * of this software and associated documentation files (the "Software"), to deal 9 * in the Software without restriction, including without limitation the rights 10 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 11 * copies of the Software, and to permit persons to whom the Software is 12 * furnished to do so, subject to the following conditions: 13 * 14 * The above copyright notice and this permission notice shall be included in 15 * all copies or substantial portions of the Software. 16 * 17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 22 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 23 * THE SOFTWARE. 24 */ 25 26 #include "qemu/osdep.h" 27 #include "hw/sysbus.h" 28 #include "migration/vmstate.h" 29 #include "hw/irq.h" 30 #include "hw/scsi/esp.h" 31 #include "trace.h" 32 #include "qemu/log.h" 33 #include "qemu/module.h" 34 35 /* 36 * On Sparc32, this is the ESP (NCR53C90) part of chip STP2000 (Master I/O), 37 * also produced as NCR89C100. See 38 * http://www.ibiblio.org/pub/historic-linux/early-ports/Sparc/NCR/NCR89C100.txt 39 * and 40 * http://www.ibiblio.org/pub/historic-linux/early-ports/Sparc/NCR/NCR53C9X.txt 41 * 42 * On Macintosh Quadra it is a NCR53C96. 43 */ 44 45 static void esp_raise_irq(ESPState *s) 46 { 47 if (!(s->rregs[ESP_RSTAT] & STAT_INT)) { 48 s->rregs[ESP_RSTAT] |= STAT_INT; 49 qemu_irq_raise(s->irq); 50 trace_esp_raise_irq(); 51 } 52 } 53 54 static void esp_lower_irq(ESPState *s) 55 { 56 if (s->rregs[ESP_RSTAT] & STAT_INT) { 57 s->rregs[ESP_RSTAT] &= ~STAT_INT; 58 qemu_irq_lower(s->irq); 59 trace_esp_lower_irq(); 60 } 61 } 62 63 static void esp_raise_drq(ESPState *s) 64 { 65 qemu_irq_raise(s->irq_data); 66 trace_esp_raise_drq(); 67 } 68 69 static void esp_lower_drq(ESPState *s) 70 { 71 qemu_irq_lower(s->irq_data); 72 trace_esp_lower_drq(); 73 } 74 75 void esp_dma_enable(ESPState *s, int irq, int level) 76 { 77 if (level) { 78 s->dma_enabled = 1; 79 trace_esp_dma_enable(); 80 if (s->dma_cb) { 81 s->dma_cb(s); 82 s->dma_cb = NULL; 83 } 84 } else { 85 trace_esp_dma_disable(); 86 s->dma_enabled = 0; 87 } 88 } 89 90 void esp_request_cancelled(SCSIRequest *req) 91 { 92 ESPState *s = req->hba_private; 93 94 if (req == s->current_req) { 95 scsi_req_unref(s->current_req); 96 s->current_req = NULL; 97 s->current_dev = NULL; 98 s->async_len = 0; 99 } 100 } 101 102 static void esp_fifo_push(Fifo8 *fifo, uint8_t val) 103 { 104 if (fifo8_num_used(fifo) == fifo->capacity) { 105 trace_esp_error_fifo_overrun(); 106 return; 107 } 108 109 fifo8_push(fifo, val); 110 } 111 112 static uint8_t esp_fifo_pop(Fifo8 *fifo) 113 { 114 if (fifo8_is_empty(fifo)) { 115 return 0; 116 } 117 118 return fifo8_pop(fifo); 119 } 120 121 static uint32_t esp_fifo_pop_buf(Fifo8 *fifo, uint8_t *dest, int maxlen) 122 { 123 const uint8_t *buf; 124 uint32_t n, n2; 125 int len; 126 127 if (maxlen == 0) { 128 return 0; 129 } 130 131 len = maxlen; 132 buf = fifo8_pop_buf(fifo, len, &n); 133 if (dest) { 134 memcpy(dest, buf, n); 135 } 136 137 /* Add FIFO wraparound if needed */ 138 len -= n; 139 len = MIN(len, fifo8_num_used(fifo)); 140 if (len) { 141 buf = fifo8_pop_buf(fifo, len, &n2); 142 if (dest) { 143 memcpy(&dest[n], buf, n2); 144 } 145 n += n2; 146 } 147 148 return n; 149 } 150 151 static uint32_t esp_get_tc(ESPState *s) 152 { 153 uint32_t dmalen; 154 155 dmalen = s->rregs[ESP_TCLO]; 156 dmalen |= s->rregs[ESP_TCMID] << 8; 157 dmalen |= s->rregs[ESP_TCHI] << 16; 158 159 return dmalen; 160 } 161 162 static void esp_set_tc(ESPState *s, uint32_t dmalen) 163 { 164 uint32_t old_tc = esp_get_tc(s); 165 166 s->rregs[ESP_TCLO] = dmalen; 167 s->rregs[ESP_TCMID] = dmalen >> 8; 168 s->rregs[ESP_TCHI] = dmalen >> 16; 169 170 if (old_tc && dmalen == 0) { 171 s->rregs[ESP_RSTAT] |= STAT_TC; 172 } 173 } 174 175 static uint32_t esp_get_stc(ESPState *s) 176 { 177 uint32_t dmalen; 178 179 dmalen = s->wregs[ESP_TCLO]; 180 dmalen |= s->wregs[ESP_TCMID] << 8; 181 dmalen |= s->wregs[ESP_TCHI] << 16; 182 183 return dmalen; 184 } 185 186 static const char *esp_phase_names[8] = { 187 "DATA OUT", "DATA IN", "COMMAND", "STATUS", 188 "(reserved)", "(reserved)", "MESSAGE OUT", "MESSAGE IN" 189 }; 190 191 static void esp_set_phase(ESPState *s, uint8_t phase) 192 { 193 s->rregs[ESP_RSTAT] &= ~7; 194 s->rregs[ESP_RSTAT] |= phase; 195 196 trace_esp_set_phase(esp_phase_names[phase]); 197 } 198 199 static uint8_t esp_pdma_read(ESPState *s) 200 { 201 uint8_t val; 202 203 val = esp_fifo_pop(&s->fifo); 204 return val; 205 } 206 207 static void esp_pdma_write(ESPState *s, uint8_t val) 208 { 209 uint32_t dmalen = esp_get_tc(s); 210 211 if (dmalen == 0) { 212 return; 213 } 214 215 esp_fifo_push(&s->fifo, val); 216 217 dmalen--; 218 esp_set_tc(s, dmalen); 219 } 220 221 static void esp_set_pdma_cb(ESPState *s, enum pdma_cb cb) 222 { 223 s->pdma_cb = cb; 224 } 225 226 static int esp_select(ESPState *s) 227 { 228 int target; 229 230 target = s->wregs[ESP_WBUSID] & BUSID_DID; 231 232 s->ti_size = 0; 233 234 if (s->current_req) { 235 /* Started a new command before the old one finished. Cancel it. */ 236 scsi_req_cancel(s->current_req); 237 } 238 239 s->current_dev = scsi_device_find(&s->bus, 0, target, 0); 240 if (!s->current_dev) { 241 /* No such drive */ 242 s->rregs[ESP_RSTAT] = 0; 243 s->rregs[ESP_RINTR] = INTR_DC; 244 s->rregs[ESP_RSEQ] = SEQ_0; 245 esp_raise_irq(s); 246 return -1; 247 } 248 249 /* 250 * Note that we deliberately don't raise the IRQ here: this will be done 251 * either in do_command_phase() for DATA OUT transfers or by the deferred 252 * IRQ mechanism in esp_transfer_data() for DATA IN transfers 253 */ 254 s->rregs[ESP_RINTR] |= INTR_FC; 255 s->rregs[ESP_RSEQ] = SEQ_CD; 256 return 0; 257 } 258 259 static uint32_t get_cmd(ESPState *s, uint32_t maxlen) 260 { 261 uint8_t buf[ESP_CMDFIFO_SZ]; 262 uint32_t dmalen, n; 263 int target; 264 265 target = s->wregs[ESP_WBUSID] & BUSID_DID; 266 if (s->dma) { 267 dmalen = MIN(esp_get_tc(s), maxlen); 268 if (dmalen == 0) { 269 return 0; 270 } 271 if (s->dma_memory_read) { 272 s->dma_memory_read(s->dma_opaque, buf, dmalen); 273 dmalen = MIN(fifo8_num_free(&s->cmdfifo), dmalen); 274 fifo8_push_all(&s->cmdfifo, buf, dmalen); 275 esp_set_tc(s, esp_get_tc(s) - dmalen); 276 } else { 277 return 0; 278 } 279 } else { 280 dmalen = MIN(fifo8_num_used(&s->fifo), maxlen); 281 if (dmalen == 0) { 282 return 0; 283 } 284 n = esp_fifo_pop_buf(&s->fifo, buf, dmalen); 285 n = MIN(fifo8_num_free(&s->cmdfifo), n); 286 fifo8_push_all(&s->cmdfifo, buf, n); 287 } 288 trace_esp_get_cmd(dmalen, target); 289 290 return dmalen; 291 } 292 293 static void do_command_phase(ESPState *s) 294 { 295 uint32_t cmdlen; 296 int32_t datalen; 297 SCSIDevice *current_lun; 298 uint8_t buf[ESP_CMDFIFO_SZ]; 299 300 trace_esp_do_command_phase(s->lun); 301 cmdlen = fifo8_num_used(&s->cmdfifo); 302 if (!cmdlen || !s->current_dev) { 303 return; 304 } 305 esp_fifo_pop_buf(&s->cmdfifo, buf, cmdlen); 306 307 current_lun = scsi_device_find(&s->bus, 0, s->current_dev->id, s->lun); 308 if (!current_lun) { 309 /* No such drive */ 310 s->rregs[ESP_RSTAT] = 0; 311 s->rregs[ESP_RINTR] = INTR_DC; 312 s->rregs[ESP_RSEQ] = SEQ_0; 313 esp_raise_irq(s); 314 return; 315 } 316 317 s->current_req = scsi_req_new(current_lun, 0, s->lun, buf, cmdlen, s); 318 datalen = scsi_req_enqueue(s->current_req); 319 s->ti_size = datalen; 320 fifo8_reset(&s->cmdfifo); 321 if (datalen != 0) { 322 s->ti_cmd = 0; 323 if (datalen > 0) { 324 /* 325 * Switch to DATA IN phase but wait until initial data xfer is 326 * complete before raising the command completion interrupt 327 */ 328 s->data_in_ready = false; 329 esp_set_phase(s, STAT_DI); 330 } else { 331 esp_set_phase(s, STAT_DO); 332 s->rregs[ESP_RINTR] |= INTR_BS | INTR_FC; 333 esp_raise_irq(s); 334 esp_lower_drq(s); 335 } 336 scsi_req_continue(s->current_req); 337 return; 338 } 339 } 340 341 static void do_message_phase(ESPState *s) 342 { 343 if (s->cmdfifo_cdb_offset) { 344 uint8_t message = esp_fifo_pop(&s->cmdfifo); 345 346 trace_esp_do_identify(message); 347 s->lun = message & 7; 348 s->cmdfifo_cdb_offset--; 349 } 350 351 /* Ignore extended messages for now */ 352 if (s->cmdfifo_cdb_offset) { 353 int len = MIN(s->cmdfifo_cdb_offset, fifo8_num_used(&s->cmdfifo)); 354 esp_fifo_pop_buf(&s->cmdfifo, NULL, len); 355 s->cmdfifo_cdb_offset = 0; 356 } 357 } 358 359 static void do_cmd(ESPState *s) 360 { 361 do_message_phase(s); 362 assert(s->cmdfifo_cdb_offset == 0); 363 do_command_phase(s); 364 } 365 366 static void satn_pdma_cb(ESPState *s) 367 { 368 uint8_t buf[ESP_FIFO_SZ]; 369 int n; 370 371 /* Copy FIFO into cmdfifo */ 372 n = esp_fifo_pop_buf(&s->fifo, buf, fifo8_num_used(&s->fifo)); 373 n = MIN(fifo8_num_free(&s->cmdfifo), n); 374 fifo8_push_all(&s->cmdfifo, buf, n); 375 376 if (!esp_get_tc(s) && !fifo8_is_empty(&s->cmdfifo)) { 377 s->cmdfifo_cdb_offset = 1; 378 s->do_cmd = 0; 379 do_cmd(s); 380 } 381 } 382 383 static void handle_satn(ESPState *s) 384 { 385 int32_t cmdlen; 386 387 if (s->dma && !s->dma_enabled) { 388 s->dma_cb = handle_satn; 389 return; 390 } 391 esp_set_pdma_cb(s, SATN_PDMA_CB); 392 if (esp_select(s) < 0) { 393 return; 394 } 395 cmdlen = get_cmd(s, ESP_CMDFIFO_SZ); 396 if (cmdlen > 0) { 397 s->cmdfifo_cdb_offset = 1; 398 s->do_cmd = 0; 399 do_cmd(s); 400 } else if (cmdlen == 0) { 401 if (s->dma) { 402 esp_raise_drq(s); 403 } 404 s->do_cmd = 1; 405 /* Target present, but no cmd yet - switch to command phase */ 406 s->rregs[ESP_RSEQ] = SEQ_CD; 407 esp_set_phase(s, STAT_CD); 408 } 409 } 410 411 static void s_without_satn_pdma_cb(ESPState *s) 412 { 413 uint8_t buf[ESP_FIFO_SZ]; 414 int n; 415 416 /* Copy FIFO into cmdfifo */ 417 n = esp_fifo_pop_buf(&s->fifo, buf, fifo8_num_used(&s->fifo)); 418 n = MIN(fifo8_num_free(&s->cmdfifo), n); 419 fifo8_push_all(&s->cmdfifo, buf, n); 420 421 if (!esp_get_tc(s) && !fifo8_is_empty(&s->cmdfifo)) { 422 s->cmdfifo_cdb_offset = 0; 423 s->do_cmd = 0; 424 do_cmd(s); 425 } 426 } 427 428 static void handle_s_without_atn(ESPState *s) 429 { 430 int32_t cmdlen; 431 432 if (s->dma && !s->dma_enabled) { 433 s->dma_cb = handle_s_without_atn; 434 return; 435 } 436 esp_set_pdma_cb(s, S_WITHOUT_SATN_PDMA_CB); 437 if (esp_select(s) < 0) { 438 return; 439 } 440 cmdlen = get_cmd(s, ESP_CMDFIFO_SZ); 441 if (cmdlen > 0) { 442 s->cmdfifo_cdb_offset = 0; 443 s->do_cmd = 0; 444 do_cmd(s); 445 } else if (cmdlen == 0) { 446 if (s->dma) { 447 esp_raise_drq(s); 448 } 449 s->do_cmd = 1; 450 /* Target present, but no cmd yet - switch to command phase */ 451 s->rregs[ESP_RSEQ] = SEQ_CD; 452 esp_set_phase(s, STAT_CD); 453 } 454 } 455 456 static void satn_stop_pdma_cb(ESPState *s) 457 { 458 uint8_t buf[ESP_FIFO_SZ]; 459 int n; 460 461 /* Copy FIFO into cmdfifo */ 462 n = esp_fifo_pop_buf(&s->fifo, buf, fifo8_num_used(&s->fifo)); 463 n = MIN(fifo8_num_free(&s->cmdfifo), n); 464 fifo8_push_all(&s->cmdfifo, buf, n); 465 466 if (!esp_get_tc(s) && !fifo8_is_empty(&s->cmdfifo)) { 467 trace_esp_handle_satn_stop(fifo8_num_used(&s->cmdfifo)); 468 s->do_cmd = 1; 469 s->cmdfifo_cdb_offset = 1; 470 esp_set_phase(s, STAT_CD); 471 s->rregs[ESP_RSTAT] |= STAT_TC; 472 s->rregs[ESP_RINTR] |= INTR_BS | INTR_FC; 473 s->rregs[ESP_RSEQ] = SEQ_CD; 474 esp_raise_irq(s); 475 } 476 } 477 478 static void handle_satn_stop(ESPState *s) 479 { 480 int32_t cmdlen; 481 482 if (s->dma && !s->dma_enabled) { 483 s->dma_cb = handle_satn_stop; 484 return; 485 } 486 esp_set_pdma_cb(s, SATN_STOP_PDMA_CB); 487 if (esp_select(s) < 0) { 488 return; 489 } 490 cmdlen = get_cmd(s, 1); 491 if (cmdlen > 0) { 492 trace_esp_handle_satn_stop(fifo8_num_used(&s->cmdfifo)); 493 s->do_cmd = 1; 494 s->cmdfifo_cdb_offset = 1; 495 esp_set_phase(s, STAT_MO); 496 s->rregs[ESP_RINTR] |= INTR_BS | INTR_FC; 497 s->rregs[ESP_RSEQ] = SEQ_MO; 498 esp_raise_irq(s); 499 } else if (cmdlen == 0) { 500 if (s->dma) { 501 esp_raise_drq(s); 502 } 503 s->do_cmd = 1; 504 /* Target present, switch to message out phase */ 505 s->rregs[ESP_RSEQ] = SEQ_MO; 506 esp_set_phase(s, STAT_MO); 507 } 508 } 509 510 static void write_response_pdma_cb(ESPState *s) 511 { 512 esp_set_phase(s, STAT_ST); 513 s->rregs[ESP_RINTR] |= INTR_BS | INTR_FC; 514 s->rregs[ESP_RSEQ] = SEQ_CD; 515 esp_raise_irq(s); 516 } 517 518 static void write_response(ESPState *s) 519 { 520 uint8_t buf[2]; 521 522 trace_esp_write_response(s->status); 523 524 buf[0] = s->status; 525 buf[1] = 0; 526 527 if (s->dma) { 528 if (s->dma_memory_write) { 529 s->dma_memory_write(s->dma_opaque, buf, 2); 530 esp_set_phase(s, STAT_ST); 531 s->rregs[ESP_RINTR] |= INTR_BS | INTR_FC; 532 s->rregs[ESP_RSEQ] = SEQ_CD; 533 } else { 534 esp_set_pdma_cb(s, WRITE_RESPONSE_PDMA_CB); 535 esp_raise_drq(s); 536 return; 537 } 538 } else { 539 fifo8_reset(&s->fifo); 540 fifo8_push_all(&s->fifo, buf, 2); 541 s->rregs[ESP_RFLAGS] = 2; 542 } 543 esp_raise_irq(s); 544 } 545 546 static void esp_dma_done(ESPState *s) 547 { 548 s->rregs[ESP_RINTR] |= INTR_BS; 549 esp_raise_irq(s); 550 } 551 552 static void do_dma_pdma_cb(ESPState *s) 553 { 554 int to_device = ((s->rregs[ESP_RSTAT] & 7) == STAT_DO); 555 uint8_t buf[ESP_CMDFIFO_SZ]; 556 int len; 557 uint32_t n; 558 559 if (s->do_cmd) { 560 /* Copy FIFO into cmdfifo */ 561 n = esp_fifo_pop_buf(&s->fifo, buf, fifo8_num_used(&s->fifo)); 562 n = MIN(fifo8_num_free(&s->cmdfifo), n); 563 fifo8_push_all(&s->cmdfifo, buf, n); 564 565 /* Ensure we have received complete command after SATN and stop */ 566 if (esp_get_tc(s) || fifo8_is_empty(&s->cmdfifo)) { 567 return; 568 } 569 570 s->ti_size = 0; 571 if ((s->rregs[ESP_RSTAT] & 7) == STAT_CD) { 572 /* No command received */ 573 if (s->cmdfifo_cdb_offset == fifo8_num_used(&s->cmdfifo)) { 574 return; 575 } 576 577 /* Command has been received */ 578 s->do_cmd = 0; 579 do_cmd(s); 580 } else { 581 /* 582 * Extra message out bytes received: update cmdfifo_cdb_offset 583 * and then switch to command phase 584 */ 585 s->cmdfifo_cdb_offset = fifo8_num_used(&s->cmdfifo); 586 esp_set_phase(s, STAT_CD); 587 s->rregs[ESP_RSEQ] = SEQ_CD; 588 s->rregs[ESP_RINTR] |= INTR_BS; 589 esp_raise_irq(s); 590 } 591 return; 592 } 593 594 if (!s->current_req) { 595 return; 596 } 597 598 if (to_device) { 599 /* Copy FIFO data to device */ 600 len = MIN(s->async_len, ESP_FIFO_SZ); 601 len = MIN(len, fifo8_num_used(&s->fifo)); 602 n = esp_fifo_pop_buf(&s->fifo, s->async_buf, len); 603 s->async_buf += n; 604 s->async_len -= n; 605 s->ti_size += n; 606 607 if (s->async_len == 0) { 608 scsi_req_continue(s->current_req); 609 return; 610 } 611 612 if (esp_get_tc(s) == 0) { 613 esp_lower_drq(s); 614 esp_dma_done(s); 615 } 616 617 return; 618 } else { 619 if (s->async_len == 0 && fifo8_num_used(&s->fifo) < 2) { 620 /* Defer until the scsi layer has completed */ 621 scsi_req_continue(s->current_req); 622 s->data_in_ready = false; 623 return; 624 } 625 626 if (esp_get_tc(s) == 0 && fifo8_num_used(&s->fifo) < 2) { 627 esp_lower_drq(s); 628 esp_dma_done(s); 629 } 630 631 /* Copy device data to FIFO */ 632 len = MIN(s->async_len, esp_get_tc(s)); 633 len = MIN(len, fifo8_num_free(&s->fifo)); 634 fifo8_push_all(&s->fifo, s->async_buf, len); 635 s->async_buf += len; 636 s->async_len -= len; 637 s->ti_size -= len; 638 esp_set_tc(s, esp_get_tc(s) - len); 639 } 640 } 641 642 static void esp_do_dma(ESPState *s) 643 { 644 uint32_t len, cmdlen; 645 int to_device = ((s->rregs[ESP_RSTAT] & 7) == STAT_DO); 646 uint8_t buf[ESP_CMDFIFO_SZ]; 647 648 len = esp_get_tc(s); 649 if (s->do_cmd) { 650 /* 651 * handle_ti_cmd() case: esp_do_dma() is called only from 652 * handle_ti_cmd() with do_cmd != NULL (see the assert()) 653 */ 654 cmdlen = fifo8_num_used(&s->cmdfifo); 655 trace_esp_do_dma(cmdlen, len); 656 if (s->dma_memory_read) { 657 len = MIN(len, fifo8_num_free(&s->cmdfifo)); 658 s->dma_memory_read(s->dma_opaque, buf, len); 659 fifo8_push_all(&s->cmdfifo, buf, len); 660 esp_set_tc(s, esp_get_tc(s) - len); 661 } else { 662 esp_set_pdma_cb(s, DO_DMA_PDMA_CB); 663 esp_raise_drq(s); 664 return; 665 } 666 trace_esp_handle_ti_cmd(cmdlen); 667 s->ti_size = 0; 668 if ((s->rregs[ESP_RSTAT] & 7) == STAT_CD) { 669 /* No command received */ 670 if (s->cmdfifo_cdb_offset == fifo8_num_used(&s->cmdfifo)) { 671 return; 672 } 673 674 /* Command has been received */ 675 s->do_cmd = 0; 676 do_cmd(s); 677 } else { 678 /* 679 * Extra message out bytes received: update cmdfifo_cdb_offset 680 * and then switch to command phase 681 */ 682 s->cmdfifo_cdb_offset = fifo8_num_used(&s->cmdfifo); 683 esp_set_phase(s, STAT_CD); 684 s->rregs[ESP_RSEQ] = SEQ_CD; 685 s->rregs[ESP_RINTR] |= INTR_BS; 686 esp_raise_irq(s); 687 } 688 return; 689 } 690 if (!s->current_req) { 691 return; 692 } 693 if (s->async_len == 0) { 694 /* Defer until data is available. */ 695 return; 696 } 697 if (len > s->async_len) { 698 len = s->async_len; 699 } 700 if (to_device) { 701 if (s->dma_memory_read) { 702 s->dma_memory_read(s->dma_opaque, s->async_buf, len); 703 704 esp_set_tc(s, esp_get_tc(s) - len); 705 s->async_buf += len; 706 s->async_len -= len; 707 s->ti_size += len; 708 709 if (s->async_len == 0) { 710 scsi_req_continue(s->current_req); 711 /* 712 * If there is still data to be read from the device then 713 * complete the DMA operation immediately. Otherwise defer 714 * until the scsi layer has completed. 715 */ 716 return; 717 } 718 719 if (esp_get_tc(s) == 0) { 720 /* Partially filled a scsi buffer. Complete immediately. */ 721 esp_dma_done(s); 722 esp_lower_drq(s); 723 } 724 } else { 725 esp_set_pdma_cb(s, DO_DMA_PDMA_CB); 726 esp_raise_drq(s); 727 } 728 } else { 729 if (s->dma_memory_write) { 730 s->dma_memory_write(s->dma_opaque, s->async_buf, len); 731 732 esp_set_tc(s, esp_get_tc(s) - len); 733 s->async_buf += len; 734 s->async_len -= len; 735 s->ti_size -= len; 736 737 if (s->async_len == 0) { 738 scsi_req_continue(s->current_req); 739 return; 740 } 741 742 if (esp_get_tc(s) == 0) { 743 /* Partially filled a scsi buffer. Complete immediately. */ 744 esp_dma_done(s); 745 esp_lower_drq(s); 746 } 747 } else { 748 /* Copy device data to FIFO */ 749 len = MIN(len, fifo8_num_free(&s->fifo)); 750 fifo8_push_all(&s->fifo, s->async_buf, len); 751 s->async_buf += len; 752 s->async_len -= len; 753 s->ti_size -= len; 754 esp_set_tc(s, esp_get_tc(s) - len); 755 esp_set_pdma_cb(s, DO_DMA_PDMA_CB); 756 esp_raise_drq(s); 757 } 758 } 759 } 760 761 static void esp_do_nodma(ESPState *s) 762 { 763 int to_device = ((s->rregs[ESP_RSTAT] & 7) == STAT_DO); 764 uint8_t buf[ESP_FIFO_SZ]; 765 uint32_t cmdlen; 766 int len, n; 767 768 if (s->do_cmd) { 769 /* Copy FIFO into cmdfifo */ 770 n = esp_fifo_pop_buf(&s->fifo, buf, fifo8_num_used(&s->fifo)); 771 n = MIN(fifo8_num_free(&s->cmdfifo), n); 772 fifo8_push_all(&s->cmdfifo, buf, n); 773 774 cmdlen = fifo8_num_used(&s->cmdfifo); 775 trace_esp_handle_ti_cmd(cmdlen); 776 s->ti_size = 0; 777 if ((s->rregs[ESP_RSTAT] & 7) == STAT_CD) { 778 /* No command received */ 779 if (s->cmdfifo_cdb_offset == fifo8_num_used(&s->cmdfifo)) { 780 return; 781 } 782 783 /* Command has been received */ 784 s->do_cmd = 0; 785 do_cmd(s); 786 } else { 787 /* 788 * Extra message out bytes received: update cmdfifo_cdb_offset 789 * and then switch to command phase 790 */ 791 s->cmdfifo_cdb_offset = fifo8_num_used(&s->cmdfifo); 792 esp_set_phase(s, STAT_CD); 793 s->rregs[ESP_RSEQ] = SEQ_CD; 794 s->rregs[ESP_RINTR] |= INTR_BS; 795 esp_raise_irq(s); 796 } 797 return; 798 } 799 800 if (!s->current_req) { 801 return; 802 } 803 804 if (s->async_len == 0) { 805 /* Defer until data is available. */ 806 return; 807 } 808 809 if (to_device) { 810 len = MIN(s->async_len, ESP_FIFO_SZ); 811 len = MIN(len, fifo8_num_used(&s->fifo)); 812 esp_fifo_pop_buf(&s->fifo, s->async_buf, len); 813 s->async_buf += len; 814 s->async_len -= len; 815 s->ti_size += len; 816 } else { 817 if (fifo8_is_empty(&s->fifo)) { 818 fifo8_push(&s->fifo, s->async_buf[0]); 819 s->async_buf++; 820 s->async_len--; 821 s->ti_size--; 822 } 823 } 824 825 if (s->async_len == 0) { 826 scsi_req_continue(s->current_req); 827 return; 828 } 829 830 s->rregs[ESP_RINTR] |= INTR_BS; 831 esp_raise_irq(s); 832 } 833 834 static void esp_pdma_cb(ESPState *s) 835 { 836 switch (s->pdma_cb) { 837 case SATN_PDMA_CB: 838 satn_pdma_cb(s); 839 break; 840 case S_WITHOUT_SATN_PDMA_CB: 841 s_without_satn_pdma_cb(s); 842 break; 843 case SATN_STOP_PDMA_CB: 844 satn_stop_pdma_cb(s); 845 break; 846 case WRITE_RESPONSE_PDMA_CB: 847 write_response_pdma_cb(s); 848 break; 849 case DO_DMA_PDMA_CB: 850 do_dma_pdma_cb(s); 851 break; 852 default: 853 g_assert_not_reached(); 854 } 855 } 856 857 void esp_command_complete(SCSIRequest *req, size_t resid) 858 { 859 ESPState *s = req->hba_private; 860 int to_device = ((s->rregs[ESP_RSTAT] & 7) == STAT_DO); 861 862 trace_esp_command_complete(); 863 864 /* 865 * Non-DMA transfers from the target will leave the last byte in 866 * the FIFO so don't reset ti_size in this case 867 */ 868 if (s->dma || to_device) { 869 if (s->ti_size != 0) { 870 trace_esp_command_complete_unexpected(); 871 } 872 s->ti_size = 0; 873 } 874 875 s->async_len = 0; 876 if (req->status) { 877 trace_esp_command_complete_fail(); 878 } 879 s->status = req->status; 880 881 /* 882 * If the transfer is finished, switch to status phase. For non-DMA 883 * transfers from the target the last byte is still in the FIFO 884 */ 885 if (s->ti_size == 0) { 886 esp_set_phase(s, STAT_ST); 887 esp_dma_done(s); 888 esp_lower_drq(s); 889 } 890 891 if (s->current_req) { 892 scsi_req_unref(s->current_req); 893 s->current_req = NULL; 894 s->current_dev = NULL; 895 } 896 } 897 898 void esp_transfer_data(SCSIRequest *req, uint32_t len) 899 { 900 ESPState *s = req->hba_private; 901 int to_device = ((s->rregs[ESP_RSTAT] & 7) == STAT_DO); 902 uint32_t dmalen = esp_get_tc(s); 903 904 assert(!s->do_cmd); 905 trace_esp_transfer_data(dmalen, s->ti_size); 906 s->async_len = len; 907 s->async_buf = scsi_req_get_buf(req); 908 909 if (!to_device && !s->data_in_ready) { 910 /* 911 * Initial incoming data xfer is complete so raise command 912 * completion interrupt 913 */ 914 s->data_in_ready = true; 915 s->rregs[ESP_RINTR] |= INTR_BS; 916 esp_raise_irq(s); 917 } 918 919 if (s->ti_cmd == 0) { 920 /* 921 * Always perform the initial transfer upon reception of the next TI 922 * command to ensure the DMA/non-DMA status of the command is correct. 923 * It is not possible to use s->dma directly in the section below as 924 * some OSs send non-DMA NOP commands after a DMA transfer. Hence if the 925 * async data transfer is delayed then s->dma is set incorrectly. 926 */ 927 return; 928 } 929 930 if (s->ti_cmd == (CMD_TI | CMD_DMA)) { 931 if (dmalen) { 932 esp_do_dma(s); 933 } else if (s->ti_size <= 0) { 934 /* 935 * If this was the last part of a DMA transfer then the 936 * completion interrupt is deferred to here. 937 */ 938 esp_dma_done(s); 939 esp_lower_drq(s); 940 } 941 } else if (s->ti_cmd == CMD_TI) { 942 esp_do_nodma(s); 943 } 944 } 945 946 static void handle_ti(ESPState *s) 947 { 948 uint32_t dmalen; 949 950 if (s->dma && !s->dma_enabled) { 951 s->dma_cb = handle_ti; 952 return; 953 } 954 955 s->ti_cmd = s->rregs[ESP_CMD]; 956 if (s->dma) { 957 dmalen = esp_get_tc(s); 958 trace_esp_handle_ti(dmalen); 959 esp_do_dma(s); 960 } else { 961 trace_esp_handle_ti(s->ti_size); 962 esp_do_nodma(s); 963 } 964 } 965 966 void esp_hard_reset(ESPState *s) 967 { 968 memset(s->rregs, 0, ESP_REGS); 969 memset(s->wregs, 0, ESP_REGS); 970 s->tchi_written = 0; 971 s->ti_size = 0; 972 s->async_len = 0; 973 fifo8_reset(&s->fifo); 974 fifo8_reset(&s->cmdfifo); 975 s->dma = 0; 976 s->do_cmd = 0; 977 s->dma_cb = NULL; 978 979 s->rregs[ESP_CFG1] = 7; 980 } 981 982 static void esp_soft_reset(ESPState *s) 983 { 984 qemu_irq_lower(s->irq); 985 qemu_irq_lower(s->irq_data); 986 esp_hard_reset(s); 987 } 988 989 static void esp_bus_reset(ESPState *s) 990 { 991 bus_cold_reset(BUS(&s->bus)); 992 } 993 994 static void parent_esp_reset(ESPState *s, int irq, int level) 995 { 996 if (level) { 997 esp_soft_reset(s); 998 } 999 } 1000 1001 static void esp_run_cmd(ESPState *s) 1002 { 1003 uint8_t cmd = s->rregs[ESP_CMD]; 1004 1005 if (cmd & CMD_DMA) { 1006 s->dma = 1; 1007 /* Reload DMA counter. */ 1008 if (esp_get_stc(s) == 0) { 1009 esp_set_tc(s, 0x10000); 1010 } else { 1011 esp_set_tc(s, esp_get_stc(s)); 1012 } 1013 } else { 1014 s->dma = 0; 1015 } 1016 switch (cmd & CMD_CMD) { 1017 case CMD_NOP: 1018 trace_esp_mem_writeb_cmd_nop(cmd); 1019 break; 1020 case CMD_FLUSH: 1021 trace_esp_mem_writeb_cmd_flush(cmd); 1022 fifo8_reset(&s->fifo); 1023 break; 1024 case CMD_RESET: 1025 trace_esp_mem_writeb_cmd_reset(cmd); 1026 esp_soft_reset(s); 1027 break; 1028 case CMD_BUSRESET: 1029 trace_esp_mem_writeb_cmd_bus_reset(cmd); 1030 esp_bus_reset(s); 1031 if (!(s->wregs[ESP_CFG1] & CFG1_RESREPT)) { 1032 s->rregs[ESP_RINTR] |= INTR_RST; 1033 esp_raise_irq(s); 1034 } 1035 break; 1036 case CMD_TI: 1037 trace_esp_mem_writeb_cmd_ti(cmd); 1038 handle_ti(s); 1039 break; 1040 case CMD_ICCS: 1041 trace_esp_mem_writeb_cmd_iccs(cmd); 1042 write_response(s); 1043 s->rregs[ESP_RINTR] |= INTR_FC; 1044 esp_set_phase(s, STAT_MI); 1045 break; 1046 case CMD_MSGACC: 1047 trace_esp_mem_writeb_cmd_msgacc(cmd); 1048 s->rregs[ESP_RINTR] |= INTR_DC; 1049 s->rregs[ESP_RSEQ] = 0; 1050 s->rregs[ESP_RFLAGS] = 0; 1051 esp_raise_irq(s); 1052 break; 1053 case CMD_PAD: 1054 trace_esp_mem_writeb_cmd_pad(cmd); 1055 s->rregs[ESP_RSTAT] = STAT_TC; 1056 s->rregs[ESP_RINTR] |= INTR_FC; 1057 s->rregs[ESP_RSEQ] = 0; 1058 break; 1059 case CMD_SATN: 1060 trace_esp_mem_writeb_cmd_satn(cmd); 1061 break; 1062 case CMD_RSTATN: 1063 trace_esp_mem_writeb_cmd_rstatn(cmd); 1064 break; 1065 case CMD_SEL: 1066 trace_esp_mem_writeb_cmd_sel(cmd); 1067 handle_s_without_atn(s); 1068 break; 1069 case CMD_SELATN: 1070 trace_esp_mem_writeb_cmd_selatn(cmd); 1071 handle_satn(s); 1072 break; 1073 case CMD_SELATNS: 1074 trace_esp_mem_writeb_cmd_selatns(cmd); 1075 handle_satn_stop(s); 1076 break; 1077 case CMD_ENSEL: 1078 trace_esp_mem_writeb_cmd_ensel(cmd); 1079 s->rregs[ESP_RINTR] = 0; 1080 break; 1081 case CMD_DISSEL: 1082 trace_esp_mem_writeb_cmd_dissel(cmd); 1083 s->rregs[ESP_RINTR] = 0; 1084 esp_raise_irq(s); 1085 break; 1086 default: 1087 trace_esp_error_unhandled_command(cmd); 1088 break; 1089 } 1090 } 1091 1092 uint64_t esp_reg_read(ESPState *s, uint32_t saddr) 1093 { 1094 uint32_t val; 1095 1096 switch (saddr) { 1097 case ESP_FIFO: 1098 if (s->dma_memory_read && s->dma_memory_write && 1099 (s->rregs[ESP_RSTAT] & STAT_PIO_MASK) == 0) { 1100 /* Data out. */ 1101 qemu_log_mask(LOG_UNIMP, "esp: PIO data read not implemented\n"); 1102 s->rregs[ESP_FIFO] = 0; 1103 } else { 1104 if ((s->rregs[ESP_RSTAT] & 0x7) == STAT_DI) { 1105 if (s->ti_size) { 1106 esp_do_nodma(s); 1107 } else { 1108 /* 1109 * The last byte of a non-DMA transfer has been read out 1110 * of the FIFO so switch to status phase 1111 */ 1112 esp_set_phase(s, STAT_ST); 1113 } 1114 } 1115 s->rregs[ESP_FIFO] = esp_fifo_pop(&s->fifo); 1116 } 1117 val = s->rregs[ESP_FIFO]; 1118 break; 1119 case ESP_RINTR: 1120 /* 1121 * Clear sequence step, interrupt register and all status bits 1122 * except TC 1123 */ 1124 val = s->rregs[ESP_RINTR]; 1125 s->rregs[ESP_RINTR] = 0; 1126 s->rregs[ESP_RSTAT] &= ~STAT_TC; 1127 /* 1128 * According to the datasheet ESP_RSEQ should be cleared, but as the 1129 * emulation currently defers information transfers to the next TI 1130 * command leave it for now so that pedantic guests such as the old 1131 * Linux 2.6 driver see the correct flags before the next SCSI phase 1132 * transition. 1133 * 1134 * s->rregs[ESP_RSEQ] = SEQ_0; 1135 */ 1136 esp_lower_irq(s); 1137 break; 1138 case ESP_TCHI: 1139 /* Return the unique id if the value has never been written */ 1140 if (!s->tchi_written) { 1141 val = s->chip_id; 1142 } else { 1143 val = s->rregs[saddr]; 1144 } 1145 break; 1146 case ESP_RFLAGS: 1147 /* Bottom 5 bits indicate number of bytes in FIFO */ 1148 val = fifo8_num_used(&s->fifo); 1149 break; 1150 default: 1151 val = s->rregs[saddr]; 1152 break; 1153 } 1154 1155 trace_esp_mem_readb(saddr, val); 1156 return val; 1157 } 1158 1159 void esp_reg_write(ESPState *s, uint32_t saddr, uint64_t val) 1160 { 1161 trace_esp_mem_writeb(saddr, s->wregs[saddr], val); 1162 switch (saddr) { 1163 case ESP_TCHI: 1164 s->tchi_written = true; 1165 /* fall through */ 1166 case ESP_TCLO: 1167 case ESP_TCMID: 1168 s->rregs[ESP_RSTAT] &= ~STAT_TC; 1169 break; 1170 case ESP_FIFO: 1171 if (s->do_cmd) { 1172 if (!fifo8_is_full(&s->fifo)) { 1173 esp_fifo_push(&s->fifo, val); 1174 esp_fifo_push(&s->cmdfifo, fifo8_pop(&s->fifo)); 1175 } 1176 1177 /* 1178 * If any unexpected message out/command phase data is 1179 * transferred using non-DMA, raise the interrupt 1180 */ 1181 if (s->rregs[ESP_CMD] == CMD_TI) { 1182 s->rregs[ESP_RINTR] |= INTR_BS; 1183 esp_raise_irq(s); 1184 } 1185 } else { 1186 esp_fifo_push(&s->fifo, val); 1187 } 1188 break; 1189 case ESP_CMD: 1190 s->rregs[saddr] = val; 1191 esp_run_cmd(s); 1192 break; 1193 case ESP_WBUSID ... ESP_WSYNO: 1194 break; 1195 case ESP_CFG1: 1196 case ESP_CFG2: case ESP_CFG3: 1197 case ESP_RES3: case ESP_RES4: 1198 s->rregs[saddr] = val; 1199 break; 1200 case ESP_WCCF ... ESP_WTEST: 1201 break; 1202 default: 1203 trace_esp_error_invalid_write(val, saddr); 1204 return; 1205 } 1206 s->wregs[saddr] = val; 1207 } 1208 1209 static bool esp_mem_accepts(void *opaque, hwaddr addr, 1210 unsigned size, bool is_write, 1211 MemTxAttrs attrs) 1212 { 1213 return (size == 1) || (is_write && size == 4); 1214 } 1215 1216 static bool esp_is_before_version_5(void *opaque, int version_id) 1217 { 1218 ESPState *s = ESP(opaque); 1219 1220 version_id = MIN(version_id, s->mig_version_id); 1221 return version_id < 5; 1222 } 1223 1224 static bool esp_is_version_5(void *opaque, int version_id) 1225 { 1226 ESPState *s = ESP(opaque); 1227 1228 version_id = MIN(version_id, s->mig_version_id); 1229 return version_id >= 5; 1230 } 1231 1232 static bool esp_is_version_6(void *opaque, int version_id) 1233 { 1234 ESPState *s = ESP(opaque); 1235 1236 version_id = MIN(version_id, s->mig_version_id); 1237 return version_id >= 6; 1238 } 1239 1240 int esp_pre_save(void *opaque) 1241 { 1242 ESPState *s = ESP(object_resolve_path_component( 1243 OBJECT(opaque), "esp")); 1244 1245 s->mig_version_id = vmstate_esp.version_id; 1246 return 0; 1247 } 1248 1249 static int esp_post_load(void *opaque, int version_id) 1250 { 1251 ESPState *s = ESP(opaque); 1252 int len, i; 1253 1254 version_id = MIN(version_id, s->mig_version_id); 1255 1256 if (version_id < 5) { 1257 esp_set_tc(s, s->mig_dma_left); 1258 1259 /* Migrate ti_buf to fifo */ 1260 len = s->mig_ti_wptr - s->mig_ti_rptr; 1261 for (i = 0; i < len; i++) { 1262 fifo8_push(&s->fifo, s->mig_ti_buf[i]); 1263 } 1264 1265 /* Migrate cmdbuf to cmdfifo */ 1266 for (i = 0; i < s->mig_cmdlen; i++) { 1267 fifo8_push(&s->cmdfifo, s->mig_cmdbuf[i]); 1268 } 1269 } 1270 1271 s->mig_version_id = vmstate_esp.version_id; 1272 return 0; 1273 } 1274 1275 /* 1276 * PDMA (or pseudo-DMA) is only used on the Macintosh and requires the 1277 * guest CPU to perform the transfers between the SCSI bus and memory 1278 * itself. This is indicated by the dma_memory_read and dma_memory_write 1279 * functions being NULL (in contrast to the ESP PCI device) whilst 1280 * dma_enabled is still set. 1281 */ 1282 1283 static bool esp_pdma_needed(void *opaque) 1284 { 1285 ESPState *s = ESP(opaque); 1286 1287 return s->dma_memory_read == NULL && s->dma_memory_write == NULL && 1288 s->dma_enabled; 1289 } 1290 1291 static const VMStateDescription vmstate_esp_pdma = { 1292 .name = "esp/pdma", 1293 .version_id = 0, 1294 .minimum_version_id = 0, 1295 .needed = esp_pdma_needed, 1296 .fields = (const VMStateField[]) { 1297 VMSTATE_UINT8(pdma_cb, ESPState), 1298 VMSTATE_END_OF_LIST() 1299 } 1300 }; 1301 1302 const VMStateDescription vmstate_esp = { 1303 .name = "esp", 1304 .version_id = 6, 1305 .minimum_version_id = 3, 1306 .post_load = esp_post_load, 1307 .fields = (const VMStateField[]) { 1308 VMSTATE_BUFFER(rregs, ESPState), 1309 VMSTATE_BUFFER(wregs, ESPState), 1310 VMSTATE_INT32(ti_size, ESPState), 1311 VMSTATE_UINT32_TEST(mig_ti_rptr, ESPState, esp_is_before_version_5), 1312 VMSTATE_UINT32_TEST(mig_ti_wptr, ESPState, esp_is_before_version_5), 1313 VMSTATE_BUFFER_TEST(mig_ti_buf, ESPState, esp_is_before_version_5), 1314 VMSTATE_UINT32(status, ESPState), 1315 VMSTATE_UINT32_TEST(mig_deferred_status, ESPState, 1316 esp_is_before_version_5), 1317 VMSTATE_BOOL_TEST(mig_deferred_complete, ESPState, 1318 esp_is_before_version_5), 1319 VMSTATE_UINT32(dma, ESPState), 1320 VMSTATE_STATIC_BUFFER(mig_cmdbuf, ESPState, 0, 1321 esp_is_before_version_5, 0, 16), 1322 VMSTATE_STATIC_BUFFER(mig_cmdbuf, ESPState, 4, 1323 esp_is_before_version_5, 16, 1324 sizeof(typeof_field(ESPState, mig_cmdbuf))), 1325 VMSTATE_UINT32_TEST(mig_cmdlen, ESPState, esp_is_before_version_5), 1326 VMSTATE_UINT32(do_cmd, ESPState), 1327 VMSTATE_UINT32_TEST(mig_dma_left, ESPState, esp_is_before_version_5), 1328 VMSTATE_BOOL_TEST(data_in_ready, ESPState, esp_is_version_5), 1329 VMSTATE_UINT8_TEST(cmdfifo_cdb_offset, ESPState, esp_is_version_5), 1330 VMSTATE_FIFO8_TEST(fifo, ESPState, esp_is_version_5), 1331 VMSTATE_FIFO8_TEST(cmdfifo, ESPState, esp_is_version_5), 1332 VMSTATE_UINT8_TEST(ti_cmd, ESPState, esp_is_version_5), 1333 VMSTATE_UINT8_TEST(lun, ESPState, esp_is_version_6), 1334 VMSTATE_END_OF_LIST() 1335 }, 1336 .subsections = (const VMStateDescription * const []) { 1337 &vmstate_esp_pdma, 1338 NULL 1339 } 1340 }; 1341 1342 static void sysbus_esp_mem_write(void *opaque, hwaddr addr, 1343 uint64_t val, unsigned int size) 1344 { 1345 SysBusESPState *sysbus = opaque; 1346 ESPState *s = ESP(&sysbus->esp); 1347 uint32_t saddr; 1348 1349 saddr = addr >> sysbus->it_shift; 1350 esp_reg_write(s, saddr, val); 1351 } 1352 1353 static uint64_t sysbus_esp_mem_read(void *opaque, hwaddr addr, 1354 unsigned int size) 1355 { 1356 SysBusESPState *sysbus = opaque; 1357 ESPState *s = ESP(&sysbus->esp); 1358 uint32_t saddr; 1359 1360 saddr = addr >> sysbus->it_shift; 1361 return esp_reg_read(s, saddr); 1362 } 1363 1364 static const MemoryRegionOps sysbus_esp_mem_ops = { 1365 .read = sysbus_esp_mem_read, 1366 .write = sysbus_esp_mem_write, 1367 .endianness = DEVICE_NATIVE_ENDIAN, 1368 .valid.accepts = esp_mem_accepts, 1369 }; 1370 1371 static void sysbus_esp_pdma_write(void *opaque, hwaddr addr, 1372 uint64_t val, unsigned int size) 1373 { 1374 SysBusESPState *sysbus = opaque; 1375 ESPState *s = ESP(&sysbus->esp); 1376 1377 trace_esp_pdma_write(size); 1378 1379 switch (size) { 1380 case 1: 1381 esp_pdma_write(s, val); 1382 break; 1383 case 2: 1384 esp_pdma_write(s, val >> 8); 1385 esp_pdma_write(s, val); 1386 break; 1387 } 1388 esp_pdma_cb(s); 1389 } 1390 1391 static uint64_t sysbus_esp_pdma_read(void *opaque, hwaddr addr, 1392 unsigned int size) 1393 { 1394 SysBusESPState *sysbus = opaque; 1395 ESPState *s = ESP(&sysbus->esp); 1396 uint64_t val = 0; 1397 1398 trace_esp_pdma_read(size); 1399 1400 switch (size) { 1401 case 1: 1402 val = esp_pdma_read(s); 1403 break; 1404 case 2: 1405 val = esp_pdma_read(s); 1406 val = (val << 8) | esp_pdma_read(s); 1407 break; 1408 } 1409 esp_pdma_cb(s); 1410 return val; 1411 } 1412 1413 static void *esp_load_request(QEMUFile *f, SCSIRequest *req) 1414 { 1415 ESPState *s = container_of(req->bus, ESPState, bus); 1416 1417 scsi_req_ref(req); 1418 s->current_req = req; 1419 return s; 1420 } 1421 1422 static const MemoryRegionOps sysbus_esp_pdma_ops = { 1423 .read = sysbus_esp_pdma_read, 1424 .write = sysbus_esp_pdma_write, 1425 .endianness = DEVICE_NATIVE_ENDIAN, 1426 .valid.min_access_size = 1, 1427 .valid.max_access_size = 4, 1428 .impl.min_access_size = 1, 1429 .impl.max_access_size = 2, 1430 }; 1431 1432 static const struct SCSIBusInfo esp_scsi_info = { 1433 .tcq = false, 1434 .max_target = ESP_MAX_DEVS, 1435 .max_lun = 7, 1436 1437 .load_request = esp_load_request, 1438 .transfer_data = esp_transfer_data, 1439 .complete = esp_command_complete, 1440 .cancel = esp_request_cancelled 1441 }; 1442 1443 static void sysbus_esp_gpio_demux(void *opaque, int irq, int level) 1444 { 1445 SysBusESPState *sysbus = SYSBUS_ESP(opaque); 1446 ESPState *s = ESP(&sysbus->esp); 1447 1448 switch (irq) { 1449 case 0: 1450 parent_esp_reset(s, irq, level); 1451 break; 1452 case 1: 1453 esp_dma_enable(s, irq, level); 1454 break; 1455 } 1456 } 1457 1458 static void sysbus_esp_realize(DeviceState *dev, Error **errp) 1459 { 1460 SysBusDevice *sbd = SYS_BUS_DEVICE(dev); 1461 SysBusESPState *sysbus = SYSBUS_ESP(dev); 1462 ESPState *s = ESP(&sysbus->esp); 1463 1464 if (!qdev_realize(DEVICE(s), NULL, errp)) { 1465 return; 1466 } 1467 1468 sysbus_init_irq(sbd, &s->irq); 1469 sysbus_init_irq(sbd, &s->irq_data); 1470 assert(sysbus->it_shift != -1); 1471 1472 s->chip_id = TCHI_FAS100A; 1473 memory_region_init_io(&sysbus->iomem, OBJECT(sysbus), &sysbus_esp_mem_ops, 1474 sysbus, "esp-regs", ESP_REGS << sysbus->it_shift); 1475 sysbus_init_mmio(sbd, &sysbus->iomem); 1476 memory_region_init_io(&sysbus->pdma, OBJECT(sysbus), &sysbus_esp_pdma_ops, 1477 sysbus, "esp-pdma", 4); 1478 sysbus_init_mmio(sbd, &sysbus->pdma); 1479 1480 qdev_init_gpio_in(dev, sysbus_esp_gpio_demux, 2); 1481 1482 scsi_bus_init(&s->bus, sizeof(s->bus), dev, &esp_scsi_info); 1483 } 1484 1485 static void sysbus_esp_hard_reset(DeviceState *dev) 1486 { 1487 SysBusESPState *sysbus = SYSBUS_ESP(dev); 1488 ESPState *s = ESP(&sysbus->esp); 1489 1490 esp_hard_reset(s); 1491 } 1492 1493 static void sysbus_esp_init(Object *obj) 1494 { 1495 SysBusESPState *sysbus = SYSBUS_ESP(obj); 1496 1497 object_initialize_child(obj, "esp", &sysbus->esp, TYPE_ESP); 1498 } 1499 1500 static const VMStateDescription vmstate_sysbus_esp_scsi = { 1501 .name = "sysbusespscsi", 1502 .version_id = 2, 1503 .minimum_version_id = 1, 1504 .pre_save = esp_pre_save, 1505 .fields = (const VMStateField[]) { 1506 VMSTATE_UINT8_V(esp.mig_version_id, SysBusESPState, 2), 1507 VMSTATE_STRUCT(esp, SysBusESPState, 0, vmstate_esp, ESPState), 1508 VMSTATE_END_OF_LIST() 1509 } 1510 }; 1511 1512 static void sysbus_esp_class_init(ObjectClass *klass, void *data) 1513 { 1514 DeviceClass *dc = DEVICE_CLASS(klass); 1515 1516 dc->realize = sysbus_esp_realize; 1517 dc->reset = sysbus_esp_hard_reset; 1518 dc->vmsd = &vmstate_sysbus_esp_scsi; 1519 set_bit(DEVICE_CATEGORY_STORAGE, dc->categories); 1520 } 1521 1522 static const TypeInfo sysbus_esp_info = { 1523 .name = TYPE_SYSBUS_ESP, 1524 .parent = TYPE_SYS_BUS_DEVICE, 1525 .instance_init = sysbus_esp_init, 1526 .instance_size = sizeof(SysBusESPState), 1527 .class_init = sysbus_esp_class_init, 1528 }; 1529 1530 static void esp_finalize(Object *obj) 1531 { 1532 ESPState *s = ESP(obj); 1533 1534 fifo8_destroy(&s->fifo); 1535 fifo8_destroy(&s->cmdfifo); 1536 } 1537 1538 static void esp_init(Object *obj) 1539 { 1540 ESPState *s = ESP(obj); 1541 1542 fifo8_create(&s->fifo, ESP_FIFO_SZ); 1543 fifo8_create(&s->cmdfifo, ESP_CMDFIFO_SZ); 1544 } 1545 1546 static void esp_class_init(ObjectClass *klass, void *data) 1547 { 1548 DeviceClass *dc = DEVICE_CLASS(klass); 1549 1550 /* internal device for sysbusesp/pciespscsi, not user-creatable */ 1551 dc->user_creatable = false; 1552 set_bit(DEVICE_CATEGORY_STORAGE, dc->categories); 1553 } 1554 1555 static const TypeInfo esp_info = { 1556 .name = TYPE_ESP, 1557 .parent = TYPE_DEVICE, 1558 .instance_init = esp_init, 1559 .instance_finalize = esp_finalize, 1560 .instance_size = sizeof(ESPState), 1561 .class_init = esp_class_init, 1562 }; 1563 1564 static void esp_register_types(void) 1565 { 1566 type_register_static(&sysbus_esp_info); 1567 type_register_static(&esp_info); 1568 } 1569 1570 type_init(esp_register_types) 1571