1 /* 2 * QEMU ESP/NCR53C9x emulation 3 * 4 * Copyright (c) 2005-2006 Fabrice Bellard 5 * Copyright (c) 2012 Herve Poussineau 6 * 7 * Permission is hereby granted, free of charge, to any person obtaining a copy 8 * of this software and associated documentation files (the "Software"), to deal 9 * in the Software without restriction, including without limitation the rights 10 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 11 * copies of the Software, and to permit persons to whom the Software is 12 * furnished to do so, subject to the following conditions: 13 * 14 * The above copyright notice and this permission notice shall be included in 15 * all copies or substantial portions of the Software. 16 * 17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 22 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 23 * THE SOFTWARE. 24 */ 25 26 #include "qemu/osdep.h" 27 #include "hw/sysbus.h" 28 #include "migration/vmstate.h" 29 #include "hw/irq.h" 30 #include "hw/scsi/esp.h" 31 #include "trace.h" 32 #include "qemu/log.h" 33 #include "qemu/module.h" 34 35 /* 36 * On Sparc32, this is the ESP (NCR53C90) part of chip STP2000 (Master I/O), 37 * also produced as NCR89C100. See 38 * http://www.ibiblio.org/pub/historic-linux/early-ports/Sparc/NCR/NCR89C100.txt 39 * and 40 * http://www.ibiblio.org/pub/historic-linux/early-ports/Sparc/NCR/NCR53C9X.txt 41 * 42 * On Macintosh Quadra it is a NCR53C96. 43 */ 44 45 static void esp_raise_irq(ESPState *s) 46 { 47 if (!(s->rregs[ESP_RSTAT] & STAT_INT)) { 48 s->rregs[ESP_RSTAT] |= STAT_INT; 49 qemu_irq_raise(s->irq); 50 trace_esp_raise_irq(); 51 } 52 } 53 54 static void esp_lower_irq(ESPState *s) 55 { 56 if (s->rregs[ESP_RSTAT] & STAT_INT) { 57 s->rregs[ESP_RSTAT] &= ~STAT_INT; 58 qemu_irq_lower(s->irq); 59 trace_esp_lower_irq(); 60 } 61 } 62 63 static void esp_raise_drq(ESPState *s) 64 { 65 qemu_irq_raise(s->irq_data); 66 trace_esp_raise_drq(); 67 } 68 69 static void esp_lower_drq(ESPState *s) 70 { 71 qemu_irq_lower(s->irq_data); 72 trace_esp_lower_drq(); 73 } 74 75 void esp_dma_enable(ESPState *s, int irq, int level) 76 { 77 if (level) { 78 s->dma_enabled = 1; 79 trace_esp_dma_enable(); 80 if (s->dma_cb) { 81 s->dma_cb(s); 82 s->dma_cb = NULL; 83 } 84 } else { 85 trace_esp_dma_disable(); 86 s->dma_enabled = 0; 87 } 88 } 89 90 void esp_request_cancelled(SCSIRequest *req) 91 { 92 ESPState *s = req->hba_private; 93 94 if (req == s->current_req) { 95 scsi_req_unref(s->current_req); 96 s->current_req = NULL; 97 s->current_dev = NULL; 98 s->async_len = 0; 99 } 100 } 101 102 static void esp_fifo_push(Fifo8 *fifo, uint8_t val) 103 { 104 if (fifo8_num_used(fifo) == fifo->capacity) { 105 trace_esp_error_fifo_overrun(); 106 return; 107 } 108 109 fifo8_push(fifo, val); 110 } 111 112 static uint8_t esp_fifo_pop(Fifo8 *fifo) 113 { 114 if (fifo8_is_empty(fifo)) { 115 return 0; 116 } 117 118 return fifo8_pop(fifo); 119 } 120 121 static uint32_t esp_fifo_pop_buf(Fifo8 *fifo, uint8_t *dest, int maxlen) 122 { 123 const uint8_t *buf; 124 uint32_t n, n2; 125 int len; 126 127 if (maxlen == 0) { 128 return 0; 129 } 130 131 len = maxlen; 132 buf = fifo8_pop_buf(fifo, len, &n); 133 if (dest) { 134 memcpy(dest, buf, n); 135 } 136 137 /* Add FIFO wraparound if needed */ 138 len -= n; 139 len = MIN(len, fifo8_num_used(fifo)); 140 if (len) { 141 buf = fifo8_pop_buf(fifo, len, &n2); 142 if (dest) { 143 memcpy(&dest[n], buf, n2); 144 } 145 n += n2; 146 } 147 148 return n; 149 } 150 151 static uint32_t esp_get_tc(ESPState *s) 152 { 153 uint32_t dmalen; 154 155 dmalen = s->rregs[ESP_TCLO]; 156 dmalen |= s->rregs[ESP_TCMID] << 8; 157 dmalen |= s->rregs[ESP_TCHI] << 16; 158 159 return dmalen; 160 } 161 162 static void esp_set_tc(ESPState *s, uint32_t dmalen) 163 { 164 uint32_t old_tc = esp_get_tc(s); 165 166 s->rregs[ESP_TCLO] = dmalen; 167 s->rregs[ESP_TCMID] = dmalen >> 8; 168 s->rregs[ESP_TCHI] = dmalen >> 16; 169 170 if (old_tc && dmalen == 0) { 171 s->rregs[ESP_RSTAT] |= STAT_TC; 172 } 173 } 174 175 static uint32_t esp_get_stc(ESPState *s) 176 { 177 uint32_t dmalen; 178 179 dmalen = s->wregs[ESP_TCLO]; 180 dmalen |= s->wregs[ESP_TCMID] << 8; 181 dmalen |= s->wregs[ESP_TCHI] << 16; 182 183 return dmalen; 184 } 185 186 static const char *esp_phase_names[8] = { 187 "DATA OUT", "DATA IN", "COMMAND", "STATUS", 188 "(reserved)", "(reserved)", "MESSAGE OUT", "MESSAGE IN" 189 }; 190 191 static void esp_set_phase(ESPState *s, uint8_t phase) 192 { 193 s->rregs[ESP_RSTAT] &= ~7; 194 s->rregs[ESP_RSTAT] |= phase; 195 196 trace_esp_set_phase(esp_phase_names[phase]); 197 } 198 199 static uint8_t esp_get_phase(ESPState *s) 200 { 201 return s->rregs[ESP_RSTAT] & 7; 202 } 203 204 static uint8_t esp_pdma_read(ESPState *s) 205 { 206 uint8_t val; 207 208 val = esp_fifo_pop(&s->fifo); 209 return val; 210 } 211 212 static void esp_pdma_write(ESPState *s, uint8_t val) 213 { 214 uint32_t dmalen = esp_get_tc(s); 215 216 if (dmalen == 0) { 217 return; 218 } 219 220 esp_fifo_push(&s->fifo, val); 221 222 dmalen--; 223 esp_set_tc(s, dmalen); 224 } 225 226 static void esp_set_pdma_cb(ESPState *s, enum pdma_cb cb) 227 { 228 s->pdma_cb = cb; 229 } 230 231 static int esp_select(ESPState *s) 232 { 233 int target; 234 235 target = s->wregs[ESP_WBUSID] & BUSID_DID; 236 237 s->ti_size = 0; 238 239 if (s->current_req) { 240 /* Started a new command before the old one finished. Cancel it. */ 241 scsi_req_cancel(s->current_req); 242 } 243 244 s->current_dev = scsi_device_find(&s->bus, 0, target, 0); 245 if (!s->current_dev) { 246 /* No such drive */ 247 s->rregs[ESP_RSTAT] = 0; 248 s->rregs[ESP_RINTR] = INTR_DC; 249 s->rregs[ESP_RSEQ] = SEQ_0; 250 esp_raise_irq(s); 251 return -1; 252 } 253 254 /* 255 * Note that we deliberately don't raise the IRQ here: this will be done 256 * either in do_command_phase() for DATA OUT transfers or by the deferred 257 * IRQ mechanism in esp_transfer_data() for DATA IN transfers 258 */ 259 s->rregs[ESP_RINTR] |= INTR_FC; 260 s->rregs[ESP_RSEQ] = SEQ_CD; 261 return 0; 262 } 263 264 static uint32_t get_cmd(ESPState *s, uint32_t maxlen) 265 { 266 uint8_t buf[ESP_CMDFIFO_SZ]; 267 uint32_t dmalen, n; 268 int target; 269 270 target = s->wregs[ESP_WBUSID] & BUSID_DID; 271 if (s->dma) { 272 dmalen = MIN(esp_get_tc(s), maxlen); 273 if (dmalen == 0) { 274 return 0; 275 } 276 if (s->dma_memory_read) { 277 s->dma_memory_read(s->dma_opaque, buf, dmalen); 278 dmalen = MIN(fifo8_num_free(&s->cmdfifo), dmalen); 279 fifo8_push_all(&s->cmdfifo, buf, dmalen); 280 esp_set_tc(s, esp_get_tc(s) - dmalen); 281 } else { 282 return 0; 283 } 284 } else { 285 dmalen = MIN(fifo8_num_used(&s->fifo), maxlen); 286 if (dmalen == 0) { 287 return 0; 288 } 289 n = esp_fifo_pop_buf(&s->fifo, buf, dmalen); 290 n = MIN(fifo8_num_free(&s->cmdfifo), n); 291 fifo8_push_all(&s->cmdfifo, buf, n); 292 } 293 trace_esp_get_cmd(dmalen, target); 294 295 return dmalen; 296 } 297 298 static void do_command_phase(ESPState *s) 299 { 300 uint32_t cmdlen; 301 int32_t datalen; 302 SCSIDevice *current_lun; 303 uint8_t buf[ESP_CMDFIFO_SZ]; 304 305 trace_esp_do_command_phase(s->lun); 306 cmdlen = fifo8_num_used(&s->cmdfifo); 307 if (!cmdlen || !s->current_dev) { 308 return; 309 } 310 esp_fifo_pop_buf(&s->cmdfifo, buf, cmdlen); 311 312 current_lun = scsi_device_find(&s->bus, 0, s->current_dev->id, s->lun); 313 if (!current_lun) { 314 /* No such drive */ 315 s->rregs[ESP_RSTAT] = 0; 316 s->rregs[ESP_RINTR] = INTR_DC; 317 s->rregs[ESP_RSEQ] = SEQ_0; 318 esp_raise_irq(s); 319 return; 320 } 321 322 s->current_req = scsi_req_new(current_lun, 0, s->lun, buf, cmdlen, s); 323 datalen = scsi_req_enqueue(s->current_req); 324 s->ti_size = datalen; 325 fifo8_reset(&s->cmdfifo); 326 if (datalen != 0) { 327 s->ti_cmd = 0; 328 if (datalen > 0) { 329 /* 330 * Switch to DATA IN phase but wait until initial data xfer is 331 * complete before raising the command completion interrupt 332 */ 333 s->data_in_ready = false; 334 esp_set_phase(s, STAT_DI); 335 } else { 336 esp_set_phase(s, STAT_DO); 337 s->rregs[ESP_RINTR] |= INTR_BS | INTR_FC; 338 esp_raise_irq(s); 339 esp_lower_drq(s); 340 } 341 scsi_req_continue(s->current_req); 342 return; 343 } 344 } 345 346 static void do_message_phase(ESPState *s) 347 { 348 if (s->cmdfifo_cdb_offset) { 349 uint8_t message = esp_fifo_pop(&s->cmdfifo); 350 351 trace_esp_do_identify(message); 352 s->lun = message & 7; 353 s->cmdfifo_cdb_offset--; 354 } 355 356 /* Ignore extended messages for now */ 357 if (s->cmdfifo_cdb_offset) { 358 int len = MIN(s->cmdfifo_cdb_offset, fifo8_num_used(&s->cmdfifo)); 359 esp_fifo_pop_buf(&s->cmdfifo, NULL, len); 360 s->cmdfifo_cdb_offset = 0; 361 } 362 } 363 364 static void do_cmd(ESPState *s) 365 { 366 do_message_phase(s); 367 assert(s->cmdfifo_cdb_offset == 0); 368 do_command_phase(s); 369 } 370 371 static void satn_pdma_cb(ESPState *s) 372 { 373 uint8_t buf[ESP_FIFO_SZ]; 374 int n; 375 376 /* Copy FIFO into cmdfifo */ 377 n = esp_fifo_pop_buf(&s->fifo, buf, fifo8_num_used(&s->fifo)); 378 n = MIN(fifo8_num_free(&s->cmdfifo), n); 379 fifo8_push_all(&s->cmdfifo, buf, n); 380 381 if (!esp_get_tc(s) && !fifo8_is_empty(&s->cmdfifo)) { 382 s->cmdfifo_cdb_offset = 1; 383 do_cmd(s); 384 } 385 } 386 387 static void handle_satn(ESPState *s) 388 { 389 int32_t cmdlen; 390 391 if (s->dma && !s->dma_enabled) { 392 s->dma_cb = handle_satn; 393 return; 394 } 395 esp_set_pdma_cb(s, SATN_PDMA_CB); 396 if (esp_select(s) < 0) { 397 return; 398 } 399 cmdlen = get_cmd(s, ESP_CMDFIFO_SZ); 400 if (cmdlen > 0) { 401 s->cmdfifo_cdb_offset = 1; 402 do_cmd(s); 403 } else if (cmdlen == 0) { 404 if (s->dma) { 405 esp_raise_drq(s); 406 } 407 /* Target present, but no cmd yet - switch to command phase */ 408 s->rregs[ESP_RSEQ] = SEQ_CD; 409 esp_set_phase(s, STAT_CD); 410 } 411 } 412 413 static void handle_s_without_atn(ESPState *s) 414 { 415 int32_t cmdlen; 416 417 if (s->dma && !s->dma_enabled) { 418 s->dma_cb = handle_s_without_atn; 419 return; 420 } 421 esp_set_pdma_cb(s, DO_DMA_PDMA_CB); 422 if (esp_select(s) < 0) { 423 return; 424 } 425 cmdlen = get_cmd(s, ESP_CMDFIFO_SZ); 426 if (cmdlen > 0) { 427 s->cmdfifo_cdb_offset = 0; 428 do_cmd(s); 429 } else if (cmdlen == 0) { 430 if (s->dma) { 431 esp_raise_drq(s); 432 } 433 /* Target present, but no cmd yet - switch to command phase */ 434 s->rregs[ESP_RSEQ] = SEQ_CD; 435 esp_set_phase(s, STAT_CD); 436 } 437 } 438 439 static void satn_stop_pdma_cb(ESPState *s) 440 { 441 uint8_t buf[ESP_FIFO_SZ]; 442 int n; 443 444 /* Copy FIFO into cmdfifo */ 445 n = esp_fifo_pop_buf(&s->fifo, buf, fifo8_num_used(&s->fifo)); 446 n = MIN(fifo8_num_free(&s->cmdfifo), n); 447 fifo8_push_all(&s->cmdfifo, buf, n); 448 449 if (!esp_get_tc(s) && !fifo8_is_empty(&s->cmdfifo)) { 450 trace_esp_handle_satn_stop(fifo8_num_used(&s->cmdfifo)); 451 s->cmdfifo_cdb_offset = 1; 452 esp_set_phase(s, STAT_CD); 453 s->rregs[ESP_RSTAT] |= STAT_TC; 454 s->rregs[ESP_RINTR] |= INTR_BS | INTR_FC; 455 s->rregs[ESP_RSEQ] = SEQ_CD; 456 esp_raise_irq(s); 457 } 458 } 459 460 static void handle_satn_stop(ESPState *s) 461 { 462 int32_t cmdlen; 463 464 if (s->dma && !s->dma_enabled) { 465 s->dma_cb = handle_satn_stop; 466 return; 467 } 468 esp_set_pdma_cb(s, SATN_STOP_PDMA_CB); 469 if (esp_select(s) < 0) { 470 return; 471 } 472 cmdlen = get_cmd(s, 1); 473 if (cmdlen > 0) { 474 trace_esp_handle_satn_stop(fifo8_num_used(&s->cmdfifo)); 475 s->cmdfifo_cdb_offset = 1; 476 esp_set_phase(s, STAT_MO); 477 s->rregs[ESP_RINTR] |= INTR_BS | INTR_FC; 478 s->rregs[ESP_RSEQ] = SEQ_MO; 479 esp_raise_irq(s); 480 } else if (cmdlen == 0) { 481 if (s->dma) { 482 esp_raise_drq(s); 483 } 484 /* Target present, switch to message out phase */ 485 s->rregs[ESP_RSEQ] = SEQ_MO; 486 esp_set_phase(s, STAT_MO); 487 } 488 } 489 490 static void write_response_pdma_cb(ESPState *s) 491 { 492 esp_set_phase(s, STAT_ST); 493 s->rregs[ESP_RINTR] |= INTR_BS | INTR_FC; 494 s->rregs[ESP_RSEQ] = SEQ_CD; 495 esp_raise_irq(s); 496 } 497 498 static void write_response(ESPState *s) 499 { 500 uint8_t buf[2]; 501 502 trace_esp_write_response(s->status); 503 504 buf[0] = s->status; 505 buf[1] = 0; 506 507 if (s->dma) { 508 if (s->dma_memory_write) { 509 s->dma_memory_write(s->dma_opaque, buf, 2); 510 esp_set_phase(s, STAT_ST); 511 s->rregs[ESP_RINTR] |= INTR_BS | INTR_FC; 512 s->rregs[ESP_RSEQ] = SEQ_CD; 513 } else { 514 esp_set_pdma_cb(s, WRITE_RESPONSE_PDMA_CB); 515 esp_raise_drq(s); 516 return; 517 } 518 } else { 519 fifo8_reset(&s->fifo); 520 fifo8_push_all(&s->fifo, buf, 2); 521 s->rregs[ESP_RFLAGS] = 2; 522 } 523 esp_raise_irq(s); 524 } 525 526 static void esp_dma_ti_check(ESPState *s) 527 { 528 if (esp_get_tc(s) == 0 && fifo8_num_used(&s->fifo) < 2) { 529 s->rregs[ESP_RINTR] |= INTR_BS; 530 esp_raise_irq(s); 531 esp_lower_drq(s); 532 } 533 } 534 535 static void do_dma_pdma_cb(ESPState *s) 536 { 537 uint8_t buf[ESP_CMDFIFO_SZ]; 538 int len; 539 uint32_t n; 540 541 switch (esp_get_phase(s)) { 542 case STAT_MO: 543 case STAT_CD: 544 /* Copy FIFO into cmdfifo */ 545 n = esp_fifo_pop_buf(&s->fifo, buf, fifo8_num_used(&s->fifo)); 546 n = MIN(fifo8_num_free(&s->cmdfifo), n); 547 fifo8_push_all(&s->cmdfifo, buf, n); 548 549 /* Ensure we have received complete command after SATN and stop */ 550 if (esp_get_tc(s) || fifo8_is_empty(&s->cmdfifo)) { 551 return; 552 } 553 554 s->ti_size = 0; 555 if (esp_get_phase(s) == STAT_CD) { 556 /* No command received */ 557 if (s->cmdfifo_cdb_offset == fifo8_num_used(&s->cmdfifo)) { 558 return; 559 } 560 561 /* Command has been received */ 562 do_cmd(s); 563 } else { 564 /* 565 * Extra message out bytes received: update cmdfifo_cdb_offset 566 * and then switch to command phase 567 */ 568 s->cmdfifo_cdb_offset = fifo8_num_used(&s->cmdfifo); 569 esp_set_phase(s, STAT_CD); 570 s->rregs[ESP_RSEQ] = SEQ_CD; 571 s->rregs[ESP_RINTR] |= INTR_BS; 572 esp_raise_irq(s); 573 } 574 break; 575 576 case STAT_DO: 577 if (!s->current_req) { 578 return; 579 } 580 /* Copy FIFO data to device */ 581 len = MIN(s->async_len, ESP_FIFO_SZ); 582 len = MIN(len, fifo8_num_used(&s->fifo)); 583 n = esp_fifo_pop_buf(&s->fifo, s->async_buf, len); 584 s->async_buf += n; 585 s->async_len -= n; 586 s->ti_size += n; 587 588 if (s->async_len == 0 && fifo8_num_used(&s->fifo) < 2) { 589 /* Defer until the scsi layer has completed */ 590 scsi_req_continue(s->current_req); 591 return; 592 } 593 594 esp_dma_ti_check(s); 595 break; 596 597 case STAT_DI: 598 if (!s->current_req) { 599 return; 600 } 601 /* Copy device data to FIFO */ 602 len = MIN(s->async_len, esp_get_tc(s)); 603 len = MIN(len, fifo8_num_free(&s->fifo)); 604 fifo8_push_all(&s->fifo, s->async_buf, len); 605 s->async_buf += len; 606 s->async_len -= len; 607 s->ti_size -= len; 608 esp_set_tc(s, esp_get_tc(s) - len); 609 610 if (s->async_len == 0 && fifo8_num_used(&s->fifo) < 2) { 611 /* Defer until the scsi layer has completed */ 612 scsi_req_continue(s->current_req); 613 s->data_in_ready = false; 614 return; 615 } 616 617 esp_dma_ti_check(s); 618 break; 619 } 620 } 621 622 static void esp_do_dma(ESPState *s) 623 { 624 uint32_t len, cmdlen; 625 uint8_t buf[ESP_CMDFIFO_SZ]; 626 int n; 627 628 len = esp_get_tc(s); 629 630 switch (esp_get_phase(s)) { 631 case STAT_MO: 632 case STAT_CD: 633 cmdlen = fifo8_num_used(&s->cmdfifo); 634 trace_esp_do_dma(cmdlen, len); 635 if (s->dma_memory_read) { 636 len = MIN(len, fifo8_num_free(&s->cmdfifo)); 637 s->dma_memory_read(s->dma_opaque, buf, len); 638 fifo8_push_all(&s->cmdfifo, buf, len); 639 esp_set_tc(s, esp_get_tc(s) - len); 640 } else { 641 n = esp_fifo_pop_buf(&s->fifo, buf, fifo8_num_used(&s->fifo)); 642 n = MIN(fifo8_num_free(&s->cmdfifo), n); 643 fifo8_push_all(&s->cmdfifo, buf, n); 644 esp_set_tc(s, esp_get_tc(s) - n); 645 646 esp_set_pdma_cb(s, DO_DMA_PDMA_CB); 647 esp_raise_drq(s); 648 649 /* Ensure we have received complete command after SATN and stop */ 650 if (esp_get_tc(s) || fifo8_is_empty(&s->cmdfifo)) { 651 return; 652 } 653 } 654 trace_esp_handle_ti_cmd(cmdlen); 655 s->ti_size = 0; 656 if (esp_get_phase(s) == STAT_CD) { 657 /* No command received */ 658 if (s->cmdfifo_cdb_offset == fifo8_num_used(&s->cmdfifo)) { 659 return; 660 } 661 662 /* Command has been received */ 663 do_cmd(s); 664 } else { 665 /* 666 * Extra message out bytes received: update cmdfifo_cdb_offset 667 * and then switch to command phase 668 */ 669 s->cmdfifo_cdb_offset = fifo8_num_used(&s->cmdfifo); 670 esp_set_phase(s, STAT_CD); 671 s->rregs[ESP_RSEQ] = SEQ_CD; 672 s->rregs[ESP_RINTR] |= INTR_BS; 673 esp_raise_irq(s); 674 } 675 break; 676 677 case STAT_DO: 678 if (!s->current_req) { 679 return; 680 } 681 if (s->async_len == 0 && esp_get_tc(s) && s->ti_size) { 682 /* Defer until data is available. */ 683 return; 684 } 685 if (len > s->async_len) { 686 len = s->async_len; 687 } 688 if (s->dma_memory_read) { 689 s->dma_memory_read(s->dma_opaque, s->async_buf, len); 690 691 esp_set_tc(s, esp_get_tc(s) - len); 692 s->async_buf += len; 693 s->async_len -= len; 694 s->ti_size += len; 695 696 if (s->async_len == 0 && fifo8_num_used(&s->fifo) < 2) { 697 /* Defer until the scsi layer has completed */ 698 scsi_req_continue(s->current_req); 699 return; 700 } 701 702 esp_dma_ti_check(s); 703 } else { 704 /* Copy FIFO data to device */ 705 len = MIN(s->async_len, ESP_FIFO_SZ); 706 len = MIN(len, fifo8_num_used(&s->fifo)); 707 n = esp_fifo_pop_buf(&s->fifo, s->async_buf, len); 708 s->async_buf += n; 709 s->async_len -= n; 710 s->ti_size += n; 711 712 esp_set_pdma_cb(s, DO_DMA_PDMA_CB); 713 esp_raise_drq(s); 714 715 if (s->async_len == 0 && fifo8_num_used(&s->fifo) < 2) { 716 /* Defer until the scsi layer has completed */ 717 scsi_req_continue(s->current_req); 718 return; 719 } 720 721 esp_dma_ti_check(s); 722 } 723 break; 724 725 case STAT_DI: 726 if (!s->current_req) { 727 return; 728 } 729 if (s->async_len == 0 && esp_get_tc(s) && s->ti_size) { 730 /* Defer until data is available. */ 731 return; 732 } 733 if (len > s->async_len) { 734 len = s->async_len; 735 } 736 if (s->dma_memory_write) { 737 s->dma_memory_write(s->dma_opaque, s->async_buf, len); 738 739 esp_set_tc(s, esp_get_tc(s) - len); 740 s->async_buf += len; 741 s->async_len -= len; 742 s->ti_size -= len; 743 744 if (s->async_len == 0 && fifo8_num_used(&s->fifo) < 2) { 745 /* Defer until the scsi layer has completed */ 746 scsi_req_continue(s->current_req); 747 return; 748 } 749 750 esp_dma_ti_check(s); 751 } else { 752 /* Copy device data to FIFO */ 753 len = MIN(len, fifo8_num_free(&s->fifo)); 754 fifo8_push_all(&s->fifo, s->async_buf, len); 755 s->async_buf += len; 756 s->async_len -= len; 757 s->ti_size -= len; 758 esp_set_tc(s, esp_get_tc(s) - len); 759 esp_set_pdma_cb(s, DO_DMA_PDMA_CB); 760 esp_raise_drq(s); 761 762 if (s->async_len == 0 && fifo8_num_used(&s->fifo) < 2) { 763 /* Defer until the scsi layer has completed */ 764 scsi_req_continue(s->current_req); 765 return; 766 } 767 768 esp_dma_ti_check(s); 769 } 770 break; 771 } 772 } 773 774 static void esp_do_nodma(ESPState *s) 775 { 776 uint8_t buf[ESP_FIFO_SZ]; 777 uint32_t cmdlen; 778 int len, n; 779 780 switch (esp_get_phase(s)) { 781 case STAT_MO: 782 case STAT_CD: 783 /* Copy FIFO into cmdfifo */ 784 n = esp_fifo_pop_buf(&s->fifo, buf, fifo8_num_used(&s->fifo)); 785 n = MIN(fifo8_num_free(&s->cmdfifo), n); 786 fifo8_push_all(&s->cmdfifo, buf, n); 787 788 cmdlen = fifo8_num_used(&s->cmdfifo); 789 trace_esp_handle_ti_cmd(cmdlen); 790 s->ti_size = 0; 791 if (esp_get_phase(s) == STAT_CD) { 792 /* No command received */ 793 if (s->cmdfifo_cdb_offset == fifo8_num_used(&s->cmdfifo)) { 794 return; 795 } 796 797 /* Command has been received */ 798 do_cmd(s); 799 } else { 800 /* 801 * Extra message out bytes received: update cmdfifo_cdb_offset 802 * and then switch to command phase 803 */ 804 s->cmdfifo_cdb_offset = fifo8_num_used(&s->cmdfifo); 805 esp_set_phase(s, STAT_CD); 806 s->rregs[ESP_RSEQ] = SEQ_CD; 807 s->rregs[ESP_RINTR] |= INTR_BS; 808 esp_raise_irq(s); 809 } 810 break; 811 812 case STAT_DO: 813 if (!s->current_req) { 814 return; 815 } 816 if (s->async_len == 0) { 817 /* Defer until data is available. */ 818 return; 819 } 820 len = MIN(s->async_len, ESP_FIFO_SZ); 821 len = MIN(len, fifo8_num_used(&s->fifo)); 822 esp_fifo_pop_buf(&s->fifo, s->async_buf, len); 823 s->async_buf += len; 824 s->async_len -= len; 825 s->ti_size += len; 826 827 if (s->async_len == 0) { 828 scsi_req_continue(s->current_req); 829 return; 830 } 831 832 s->rregs[ESP_RINTR] |= INTR_BS; 833 esp_raise_irq(s); 834 break; 835 836 case STAT_DI: 837 if (!s->current_req) { 838 return; 839 } 840 if (s->async_len == 0) { 841 /* Defer until data is available. */ 842 return; 843 } 844 if (fifo8_is_empty(&s->fifo)) { 845 fifo8_push(&s->fifo, s->async_buf[0]); 846 s->async_buf++; 847 s->async_len--; 848 s->ti_size--; 849 } 850 851 if (s->async_len == 0) { 852 scsi_req_continue(s->current_req); 853 return; 854 } 855 856 s->rregs[ESP_RINTR] |= INTR_BS; 857 esp_raise_irq(s); 858 break; 859 } 860 } 861 862 static void esp_pdma_cb(ESPState *s) 863 { 864 switch (s->pdma_cb) { 865 case SATN_PDMA_CB: 866 satn_pdma_cb(s); 867 break; 868 case SATN_STOP_PDMA_CB: 869 satn_stop_pdma_cb(s); 870 break; 871 case WRITE_RESPONSE_PDMA_CB: 872 write_response_pdma_cb(s); 873 break; 874 case DO_DMA_PDMA_CB: 875 do_dma_pdma_cb(s); 876 break; 877 default: 878 g_assert_not_reached(); 879 } 880 } 881 882 void esp_command_complete(SCSIRequest *req, size_t resid) 883 { 884 ESPState *s = req->hba_private; 885 int to_device = (esp_get_phase(s) == STAT_DO); 886 887 trace_esp_command_complete(); 888 889 /* 890 * Non-DMA transfers from the target will leave the last byte in 891 * the FIFO so don't reset ti_size in this case 892 */ 893 if (s->dma || to_device) { 894 if (s->ti_size != 0) { 895 trace_esp_command_complete_unexpected(); 896 } 897 } 898 899 s->async_len = 0; 900 if (req->status) { 901 trace_esp_command_complete_fail(); 902 } 903 s->status = req->status; 904 905 /* 906 * Switch to status phase. For non-DMA transfers from the target the last 907 * byte is still in the FIFO 908 */ 909 esp_set_phase(s, STAT_ST); 910 if (s->ti_size == 0) { 911 /* 912 * Transfer complete: force TC to zero just in case a TI command was 913 * requested for more data than the command returns (Solaris 8 does 914 * this) 915 */ 916 esp_set_tc(s, 0); 917 esp_dma_ti_check(s); 918 } else { 919 /* 920 * Transfer truncated: raise INTR_BS to indicate early change of 921 * phase 922 */ 923 s->rregs[ESP_RINTR] |= INTR_BS; 924 esp_raise_irq(s); 925 s->ti_size = 0; 926 } 927 928 if (s->current_req) { 929 scsi_req_unref(s->current_req); 930 s->current_req = NULL; 931 s->current_dev = NULL; 932 } 933 } 934 935 void esp_transfer_data(SCSIRequest *req, uint32_t len) 936 { 937 ESPState *s = req->hba_private; 938 int to_device = (esp_get_phase(s) == STAT_DO); 939 uint32_t dmalen = esp_get_tc(s); 940 941 trace_esp_transfer_data(dmalen, s->ti_size); 942 s->async_len = len; 943 s->async_buf = scsi_req_get_buf(req); 944 945 if (!to_device && !s->data_in_ready) { 946 /* 947 * Initial incoming data xfer is complete so raise command 948 * completion interrupt 949 */ 950 s->data_in_ready = true; 951 s->rregs[ESP_RINTR] |= INTR_BS; 952 esp_raise_irq(s); 953 } 954 955 /* 956 * Always perform the initial transfer upon reception of the next TI 957 * command to ensure the DMA/non-DMA status of the command is correct. 958 * It is not possible to use s->dma directly in the section below as 959 * some OSs send non-DMA NOP commands after a DMA transfer. Hence if the 960 * async data transfer is delayed then s->dma is set incorrectly. 961 */ 962 963 if (s->ti_cmd == (CMD_TI | CMD_DMA)) { 964 /* When the SCSI layer returns more data, raise deferred INTR_BS */ 965 esp_dma_ti_check(s); 966 967 esp_do_dma(s); 968 } else if (s->ti_cmd == CMD_TI) { 969 esp_do_nodma(s); 970 } 971 } 972 973 static void handle_ti(ESPState *s) 974 { 975 uint32_t dmalen; 976 977 if (s->dma && !s->dma_enabled) { 978 s->dma_cb = handle_ti; 979 return; 980 } 981 982 s->ti_cmd = s->rregs[ESP_CMD]; 983 if (s->dma) { 984 dmalen = esp_get_tc(s); 985 trace_esp_handle_ti(dmalen); 986 esp_do_dma(s); 987 } else { 988 trace_esp_handle_ti(s->ti_size); 989 esp_do_nodma(s); 990 } 991 } 992 993 void esp_hard_reset(ESPState *s) 994 { 995 memset(s->rregs, 0, ESP_REGS); 996 memset(s->wregs, 0, ESP_REGS); 997 s->tchi_written = 0; 998 s->ti_size = 0; 999 s->async_len = 0; 1000 fifo8_reset(&s->fifo); 1001 fifo8_reset(&s->cmdfifo); 1002 s->dma = 0; 1003 s->dma_cb = NULL; 1004 1005 s->rregs[ESP_CFG1] = 7; 1006 } 1007 1008 static void esp_soft_reset(ESPState *s) 1009 { 1010 qemu_irq_lower(s->irq); 1011 qemu_irq_lower(s->irq_data); 1012 esp_hard_reset(s); 1013 } 1014 1015 static void esp_bus_reset(ESPState *s) 1016 { 1017 bus_cold_reset(BUS(&s->bus)); 1018 } 1019 1020 static void parent_esp_reset(ESPState *s, int irq, int level) 1021 { 1022 if (level) { 1023 esp_soft_reset(s); 1024 } 1025 } 1026 1027 static void esp_run_cmd(ESPState *s) 1028 { 1029 uint8_t cmd = s->rregs[ESP_CMD]; 1030 1031 if (cmd & CMD_DMA) { 1032 s->dma = 1; 1033 /* Reload DMA counter. */ 1034 if (esp_get_stc(s) == 0) { 1035 esp_set_tc(s, 0x10000); 1036 } else { 1037 esp_set_tc(s, esp_get_stc(s)); 1038 } 1039 } else { 1040 s->dma = 0; 1041 } 1042 switch (cmd & CMD_CMD) { 1043 case CMD_NOP: 1044 trace_esp_mem_writeb_cmd_nop(cmd); 1045 break; 1046 case CMD_FLUSH: 1047 trace_esp_mem_writeb_cmd_flush(cmd); 1048 fifo8_reset(&s->fifo); 1049 break; 1050 case CMD_RESET: 1051 trace_esp_mem_writeb_cmd_reset(cmd); 1052 esp_soft_reset(s); 1053 break; 1054 case CMD_BUSRESET: 1055 trace_esp_mem_writeb_cmd_bus_reset(cmd); 1056 esp_bus_reset(s); 1057 if (!(s->wregs[ESP_CFG1] & CFG1_RESREPT)) { 1058 s->rregs[ESP_RINTR] |= INTR_RST; 1059 esp_raise_irq(s); 1060 } 1061 break; 1062 case CMD_TI: 1063 trace_esp_mem_writeb_cmd_ti(cmd); 1064 handle_ti(s); 1065 break; 1066 case CMD_ICCS: 1067 trace_esp_mem_writeb_cmd_iccs(cmd); 1068 write_response(s); 1069 s->rregs[ESP_RINTR] |= INTR_FC; 1070 esp_set_phase(s, STAT_MI); 1071 break; 1072 case CMD_MSGACC: 1073 trace_esp_mem_writeb_cmd_msgacc(cmd); 1074 s->rregs[ESP_RINTR] |= INTR_DC; 1075 s->rregs[ESP_RSEQ] = 0; 1076 s->rregs[ESP_RFLAGS] = 0; 1077 esp_raise_irq(s); 1078 break; 1079 case CMD_PAD: 1080 trace_esp_mem_writeb_cmd_pad(cmd); 1081 s->rregs[ESP_RSTAT] = STAT_TC; 1082 s->rregs[ESP_RINTR] |= INTR_FC; 1083 s->rregs[ESP_RSEQ] = 0; 1084 break; 1085 case CMD_SATN: 1086 trace_esp_mem_writeb_cmd_satn(cmd); 1087 break; 1088 case CMD_RSTATN: 1089 trace_esp_mem_writeb_cmd_rstatn(cmd); 1090 break; 1091 case CMD_SEL: 1092 trace_esp_mem_writeb_cmd_sel(cmd); 1093 handle_s_without_atn(s); 1094 break; 1095 case CMD_SELATN: 1096 trace_esp_mem_writeb_cmd_selatn(cmd); 1097 handle_satn(s); 1098 break; 1099 case CMD_SELATNS: 1100 trace_esp_mem_writeb_cmd_selatns(cmd); 1101 handle_satn_stop(s); 1102 break; 1103 case CMD_ENSEL: 1104 trace_esp_mem_writeb_cmd_ensel(cmd); 1105 s->rregs[ESP_RINTR] = 0; 1106 break; 1107 case CMD_DISSEL: 1108 trace_esp_mem_writeb_cmd_dissel(cmd); 1109 s->rregs[ESP_RINTR] = 0; 1110 esp_raise_irq(s); 1111 break; 1112 default: 1113 trace_esp_error_unhandled_command(cmd); 1114 break; 1115 } 1116 } 1117 1118 uint64_t esp_reg_read(ESPState *s, uint32_t saddr) 1119 { 1120 uint32_t val; 1121 1122 switch (saddr) { 1123 case ESP_FIFO: 1124 if (s->dma_memory_read && s->dma_memory_write && 1125 (s->rregs[ESP_RSTAT] & STAT_PIO_MASK) == 0) { 1126 /* Data out. */ 1127 qemu_log_mask(LOG_UNIMP, "esp: PIO data read not implemented\n"); 1128 s->rregs[ESP_FIFO] = 0; 1129 } else { 1130 if (esp_get_phase(s) == STAT_DI) { 1131 if (s->ti_size) { 1132 esp_do_nodma(s); 1133 } else { 1134 /* 1135 * The last byte of a non-DMA transfer has been read out 1136 * of the FIFO so switch to status phase 1137 */ 1138 esp_set_phase(s, STAT_ST); 1139 } 1140 } 1141 s->rregs[ESP_FIFO] = esp_fifo_pop(&s->fifo); 1142 } 1143 val = s->rregs[ESP_FIFO]; 1144 break; 1145 case ESP_RINTR: 1146 /* 1147 * Clear sequence step, interrupt register and all status bits 1148 * except TC 1149 */ 1150 val = s->rregs[ESP_RINTR]; 1151 s->rregs[ESP_RINTR] = 0; 1152 s->rregs[ESP_RSTAT] &= ~STAT_TC; 1153 /* 1154 * According to the datasheet ESP_RSEQ should be cleared, but as the 1155 * emulation currently defers information transfers to the next TI 1156 * command leave it for now so that pedantic guests such as the old 1157 * Linux 2.6 driver see the correct flags before the next SCSI phase 1158 * transition. 1159 * 1160 * s->rregs[ESP_RSEQ] = SEQ_0; 1161 */ 1162 esp_lower_irq(s); 1163 break; 1164 case ESP_TCHI: 1165 /* Return the unique id if the value has never been written */ 1166 if (!s->tchi_written) { 1167 val = s->chip_id; 1168 } else { 1169 val = s->rregs[saddr]; 1170 } 1171 break; 1172 case ESP_RFLAGS: 1173 /* Bottom 5 bits indicate number of bytes in FIFO */ 1174 val = fifo8_num_used(&s->fifo); 1175 break; 1176 default: 1177 val = s->rregs[saddr]; 1178 break; 1179 } 1180 1181 trace_esp_mem_readb(saddr, val); 1182 return val; 1183 } 1184 1185 void esp_reg_write(ESPState *s, uint32_t saddr, uint64_t val) 1186 { 1187 trace_esp_mem_writeb(saddr, s->wregs[saddr], val); 1188 switch (saddr) { 1189 case ESP_TCHI: 1190 s->tchi_written = true; 1191 /* fall through */ 1192 case ESP_TCLO: 1193 case ESP_TCMID: 1194 s->rregs[ESP_RSTAT] &= ~STAT_TC; 1195 break; 1196 case ESP_FIFO: 1197 if (esp_get_phase(s) == STAT_MO || esp_get_phase(s) == STAT_CD) { 1198 if (!fifo8_is_full(&s->fifo)) { 1199 esp_fifo_push(&s->fifo, val); 1200 esp_fifo_push(&s->cmdfifo, fifo8_pop(&s->fifo)); 1201 } 1202 1203 /* 1204 * If any unexpected message out/command phase data is 1205 * transferred using non-DMA, raise the interrupt 1206 */ 1207 if (s->rregs[ESP_CMD] == CMD_TI) { 1208 s->rregs[ESP_RINTR] |= INTR_BS; 1209 esp_raise_irq(s); 1210 } 1211 } else { 1212 esp_fifo_push(&s->fifo, val); 1213 } 1214 break; 1215 case ESP_CMD: 1216 s->rregs[saddr] = val; 1217 esp_run_cmd(s); 1218 break; 1219 case ESP_WBUSID ... ESP_WSYNO: 1220 break; 1221 case ESP_CFG1: 1222 case ESP_CFG2: case ESP_CFG3: 1223 case ESP_RES3: case ESP_RES4: 1224 s->rregs[saddr] = val; 1225 break; 1226 case ESP_WCCF ... ESP_WTEST: 1227 break; 1228 default: 1229 trace_esp_error_invalid_write(val, saddr); 1230 return; 1231 } 1232 s->wregs[saddr] = val; 1233 } 1234 1235 static bool esp_mem_accepts(void *opaque, hwaddr addr, 1236 unsigned size, bool is_write, 1237 MemTxAttrs attrs) 1238 { 1239 return (size == 1) || (is_write && size == 4); 1240 } 1241 1242 static bool esp_is_before_version_5(void *opaque, int version_id) 1243 { 1244 ESPState *s = ESP(opaque); 1245 1246 version_id = MIN(version_id, s->mig_version_id); 1247 return version_id < 5; 1248 } 1249 1250 static bool esp_is_version_5(void *opaque, int version_id) 1251 { 1252 ESPState *s = ESP(opaque); 1253 1254 version_id = MIN(version_id, s->mig_version_id); 1255 return version_id >= 5; 1256 } 1257 1258 static bool esp_is_version_6(void *opaque, int version_id) 1259 { 1260 ESPState *s = ESP(opaque); 1261 1262 version_id = MIN(version_id, s->mig_version_id); 1263 return version_id >= 6; 1264 } 1265 1266 int esp_pre_save(void *opaque) 1267 { 1268 ESPState *s = ESP(object_resolve_path_component( 1269 OBJECT(opaque), "esp")); 1270 1271 s->mig_version_id = vmstate_esp.version_id; 1272 return 0; 1273 } 1274 1275 static int esp_post_load(void *opaque, int version_id) 1276 { 1277 ESPState *s = ESP(opaque); 1278 int len, i; 1279 1280 version_id = MIN(version_id, s->mig_version_id); 1281 1282 if (version_id < 5) { 1283 esp_set_tc(s, s->mig_dma_left); 1284 1285 /* Migrate ti_buf to fifo */ 1286 len = s->mig_ti_wptr - s->mig_ti_rptr; 1287 for (i = 0; i < len; i++) { 1288 fifo8_push(&s->fifo, s->mig_ti_buf[i]); 1289 } 1290 1291 /* Migrate cmdbuf to cmdfifo */ 1292 for (i = 0; i < s->mig_cmdlen; i++) { 1293 fifo8_push(&s->cmdfifo, s->mig_cmdbuf[i]); 1294 } 1295 } 1296 1297 s->mig_version_id = vmstate_esp.version_id; 1298 return 0; 1299 } 1300 1301 /* 1302 * PDMA (or pseudo-DMA) is only used on the Macintosh and requires the 1303 * guest CPU to perform the transfers between the SCSI bus and memory 1304 * itself. This is indicated by the dma_memory_read and dma_memory_write 1305 * functions being NULL (in contrast to the ESP PCI device) whilst 1306 * dma_enabled is still set. 1307 */ 1308 1309 static bool esp_pdma_needed(void *opaque) 1310 { 1311 ESPState *s = ESP(opaque); 1312 1313 return s->dma_memory_read == NULL && s->dma_memory_write == NULL && 1314 s->dma_enabled; 1315 } 1316 1317 static const VMStateDescription vmstate_esp_pdma = { 1318 .name = "esp/pdma", 1319 .version_id = 0, 1320 .minimum_version_id = 0, 1321 .needed = esp_pdma_needed, 1322 .fields = (const VMStateField[]) { 1323 VMSTATE_UINT8(pdma_cb, ESPState), 1324 VMSTATE_END_OF_LIST() 1325 } 1326 }; 1327 1328 const VMStateDescription vmstate_esp = { 1329 .name = "esp", 1330 .version_id = 6, 1331 .minimum_version_id = 3, 1332 .post_load = esp_post_load, 1333 .fields = (const VMStateField[]) { 1334 VMSTATE_BUFFER(rregs, ESPState), 1335 VMSTATE_BUFFER(wregs, ESPState), 1336 VMSTATE_INT32(ti_size, ESPState), 1337 VMSTATE_UINT32_TEST(mig_ti_rptr, ESPState, esp_is_before_version_5), 1338 VMSTATE_UINT32_TEST(mig_ti_wptr, ESPState, esp_is_before_version_5), 1339 VMSTATE_BUFFER_TEST(mig_ti_buf, ESPState, esp_is_before_version_5), 1340 VMSTATE_UINT32(status, ESPState), 1341 VMSTATE_UINT32_TEST(mig_deferred_status, ESPState, 1342 esp_is_before_version_5), 1343 VMSTATE_BOOL_TEST(mig_deferred_complete, ESPState, 1344 esp_is_before_version_5), 1345 VMSTATE_UINT32(dma, ESPState), 1346 VMSTATE_STATIC_BUFFER(mig_cmdbuf, ESPState, 0, 1347 esp_is_before_version_5, 0, 16), 1348 VMSTATE_STATIC_BUFFER(mig_cmdbuf, ESPState, 4, 1349 esp_is_before_version_5, 16, 1350 sizeof(typeof_field(ESPState, mig_cmdbuf))), 1351 VMSTATE_UINT32_TEST(mig_cmdlen, ESPState, esp_is_before_version_5), 1352 VMSTATE_UINT32(do_cmd, ESPState), 1353 VMSTATE_UINT32_TEST(mig_dma_left, ESPState, esp_is_before_version_5), 1354 VMSTATE_BOOL_TEST(data_in_ready, ESPState, esp_is_version_5), 1355 VMSTATE_UINT8_TEST(cmdfifo_cdb_offset, ESPState, esp_is_version_5), 1356 VMSTATE_FIFO8_TEST(fifo, ESPState, esp_is_version_5), 1357 VMSTATE_FIFO8_TEST(cmdfifo, ESPState, esp_is_version_5), 1358 VMSTATE_UINT8_TEST(ti_cmd, ESPState, esp_is_version_5), 1359 VMSTATE_UINT8_TEST(lun, ESPState, esp_is_version_6), 1360 VMSTATE_END_OF_LIST() 1361 }, 1362 .subsections = (const VMStateDescription * const []) { 1363 &vmstate_esp_pdma, 1364 NULL 1365 } 1366 }; 1367 1368 static void sysbus_esp_mem_write(void *opaque, hwaddr addr, 1369 uint64_t val, unsigned int size) 1370 { 1371 SysBusESPState *sysbus = opaque; 1372 ESPState *s = ESP(&sysbus->esp); 1373 uint32_t saddr; 1374 1375 saddr = addr >> sysbus->it_shift; 1376 esp_reg_write(s, saddr, val); 1377 } 1378 1379 static uint64_t sysbus_esp_mem_read(void *opaque, hwaddr addr, 1380 unsigned int size) 1381 { 1382 SysBusESPState *sysbus = opaque; 1383 ESPState *s = ESP(&sysbus->esp); 1384 uint32_t saddr; 1385 1386 saddr = addr >> sysbus->it_shift; 1387 return esp_reg_read(s, saddr); 1388 } 1389 1390 static const MemoryRegionOps sysbus_esp_mem_ops = { 1391 .read = sysbus_esp_mem_read, 1392 .write = sysbus_esp_mem_write, 1393 .endianness = DEVICE_NATIVE_ENDIAN, 1394 .valid.accepts = esp_mem_accepts, 1395 }; 1396 1397 static void sysbus_esp_pdma_write(void *opaque, hwaddr addr, 1398 uint64_t val, unsigned int size) 1399 { 1400 SysBusESPState *sysbus = opaque; 1401 ESPState *s = ESP(&sysbus->esp); 1402 1403 trace_esp_pdma_write(size); 1404 1405 switch (size) { 1406 case 1: 1407 esp_pdma_write(s, val); 1408 break; 1409 case 2: 1410 esp_pdma_write(s, val >> 8); 1411 esp_pdma_write(s, val); 1412 break; 1413 } 1414 esp_pdma_cb(s); 1415 } 1416 1417 static uint64_t sysbus_esp_pdma_read(void *opaque, hwaddr addr, 1418 unsigned int size) 1419 { 1420 SysBusESPState *sysbus = opaque; 1421 ESPState *s = ESP(&sysbus->esp); 1422 uint64_t val = 0; 1423 1424 trace_esp_pdma_read(size); 1425 1426 switch (size) { 1427 case 1: 1428 val = esp_pdma_read(s); 1429 break; 1430 case 2: 1431 val = esp_pdma_read(s); 1432 val = (val << 8) | esp_pdma_read(s); 1433 break; 1434 } 1435 esp_pdma_cb(s); 1436 return val; 1437 } 1438 1439 static void *esp_load_request(QEMUFile *f, SCSIRequest *req) 1440 { 1441 ESPState *s = container_of(req->bus, ESPState, bus); 1442 1443 scsi_req_ref(req); 1444 s->current_req = req; 1445 return s; 1446 } 1447 1448 static const MemoryRegionOps sysbus_esp_pdma_ops = { 1449 .read = sysbus_esp_pdma_read, 1450 .write = sysbus_esp_pdma_write, 1451 .endianness = DEVICE_NATIVE_ENDIAN, 1452 .valid.min_access_size = 1, 1453 .valid.max_access_size = 4, 1454 .impl.min_access_size = 1, 1455 .impl.max_access_size = 2, 1456 }; 1457 1458 static const struct SCSIBusInfo esp_scsi_info = { 1459 .tcq = false, 1460 .max_target = ESP_MAX_DEVS, 1461 .max_lun = 7, 1462 1463 .load_request = esp_load_request, 1464 .transfer_data = esp_transfer_data, 1465 .complete = esp_command_complete, 1466 .cancel = esp_request_cancelled 1467 }; 1468 1469 static void sysbus_esp_gpio_demux(void *opaque, int irq, int level) 1470 { 1471 SysBusESPState *sysbus = SYSBUS_ESP(opaque); 1472 ESPState *s = ESP(&sysbus->esp); 1473 1474 switch (irq) { 1475 case 0: 1476 parent_esp_reset(s, irq, level); 1477 break; 1478 case 1: 1479 esp_dma_enable(s, irq, level); 1480 break; 1481 } 1482 } 1483 1484 static void sysbus_esp_realize(DeviceState *dev, Error **errp) 1485 { 1486 SysBusDevice *sbd = SYS_BUS_DEVICE(dev); 1487 SysBusESPState *sysbus = SYSBUS_ESP(dev); 1488 ESPState *s = ESP(&sysbus->esp); 1489 1490 if (!qdev_realize(DEVICE(s), NULL, errp)) { 1491 return; 1492 } 1493 1494 sysbus_init_irq(sbd, &s->irq); 1495 sysbus_init_irq(sbd, &s->irq_data); 1496 assert(sysbus->it_shift != -1); 1497 1498 s->chip_id = TCHI_FAS100A; 1499 memory_region_init_io(&sysbus->iomem, OBJECT(sysbus), &sysbus_esp_mem_ops, 1500 sysbus, "esp-regs", ESP_REGS << sysbus->it_shift); 1501 sysbus_init_mmio(sbd, &sysbus->iomem); 1502 memory_region_init_io(&sysbus->pdma, OBJECT(sysbus), &sysbus_esp_pdma_ops, 1503 sysbus, "esp-pdma", 4); 1504 sysbus_init_mmio(sbd, &sysbus->pdma); 1505 1506 qdev_init_gpio_in(dev, sysbus_esp_gpio_demux, 2); 1507 1508 scsi_bus_init(&s->bus, sizeof(s->bus), dev, &esp_scsi_info); 1509 } 1510 1511 static void sysbus_esp_hard_reset(DeviceState *dev) 1512 { 1513 SysBusESPState *sysbus = SYSBUS_ESP(dev); 1514 ESPState *s = ESP(&sysbus->esp); 1515 1516 esp_hard_reset(s); 1517 } 1518 1519 static void sysbus_esp_init(Object *obj) 1520 { 1521 SysBusESPState *sysbus = SYSBUS_ESP(obj); 1522 1523 object_initialize_child(obj, "esp", &sysbus->esp, TYPE_ESP); 1524 } 1525 1526 static const VMStateDescription vmstate_sysbus_esp_scsi = { 1527 .name = "sysbusespscsi", 1528 .version_id = 2, 1529 .minimum_version_id = 1, 1530 .pre_save = esp_pre_save, 1531 .fields = (const VMStateField[]) { 1532 VMSTATE_UINT8_V(esp.mig_version_id, SysBusESPState, 2), 1533 VMSTATE_STRUCT(esp, SysBusESPState, 0, vmstate_esp, ESPState), 1534 VMSTATE_END_OF_LIST() 1535 } 1536 }; 1537 1538 static void sysbus_esp_class_init(ObjectClass *klass, void *data) 1539 { 1540 DeviceClass *dc = DEVICE_CLASS(klass); 1541 1542 dc->realize = sysbus_esp_realize; 1543 dc->reset = sysbus_esp_hard_reset; 1544 dc->vmsd = &vmstate_sysbus_esp_scsi; 1545 set_bit(DEVICE_CATEGORY_STORAGE, dc->categories); 1546 } 1547 1548 static const TypeInfo sysbus_esp_info = { 1549 .name = TYPE_SYSBUS_ESP, 1550 .parent = TYPE_SYS_BUS_DEVICE, 1551 .instance_init = sysbus_esp_init, 1552 .instance_size = sizeof(SysBusESPState), 1553 .class_init = sysbus_esp_class_init, 1554 }; 1555 1556 static void esp_finalize(Object *obj) 1557 { 1558 ESPState *s = ESP(obj); 1559 1560 fifo8_destroy(&s->fifo); 1561 fifo8_destroy(&s->cmdfifo); 1562 } 1563 1564 static void esp_init(Object *obj) 1565 { 1566 ESPState *s = ESP(obj); 1567 1568 fifo8_create(&s->fifo, ESP_FIFO_SZ); 1569 fifo8_create(&s->cmdfifo, ESP_CMDFIFO_SZ); 1570 } 1571 1572 static void esp_class_init(ObjectClass *klass, void *data) 1573 { 1574 DeviceClass *dc = DEVICE_CLASS(klass); 1575 1576 /* internal device for sysbusesp/pciespscsi, not user-creatable */ 1577 dc->user_creatable = false; 1578 set_bit(DEVICE_CATEGORY_STORAGE, dc->categories); 1579 } 1580 1581 static const TypeInfo esp_info = { 1582 .name = TYPE_ESP, 1583 .parent = TYPE_DEVICE, 1584 .instance_init = esp_init, 1585 .instance_finalize = esp_finalize, 1586 .instance_size = sizeof(ESPState), 1587 .class_init = esp_class_init, 1588 }; 1589 1590 static void esp_register_types(void) 1591 { 1592 type_register_static(&sysbus_esp_info); 1593 type_register_static(&esp_info); 1594 } 1595 1596 type_init(esp_register_types) 1597