1 /* 2 * QEMU ESP/NCR53C9x emulation 3 * 4 * Copyright (c) 2005-2006 Fabrice Bellard 5 * Copyright (c) 2012 Herve Poussineau 6 * 7 * Permission is hereby granted, free of charge, to any person obtaining a copy 8 * of this software and associated documentation files (the "Software"), to deal 9 * in the Software without restriction, including without limitation the rights 10 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 11 * copies of the Software, and to permit persons to whom the Software is 12 * furnished to do so, subject to the following conditions: 13 * 14 * The above copyright notice and this permission notice shall be included in 15 * all copies or substantial portions of the Software. 16 * 17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 22 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 23 * THE SOFTWARE. 24 */ 25 26 #include "qemu/osdep.h" 27 #include "hw/sysbus.h" 28 #include "migration/vmstate.h" 29 #include "hw/irq.h" 30 #include "hw/scsi/esp.h" 31 #include "trace.h" 32 #include "qemu/log.h" 33 #include "qemu/module.h" 34 35 /* 36 * On Sparc32, this is the ESP (NCR53C90) part of chip STP2000 (Master I/O), 37 * also produced as NCR89C100. See 38 * http://www.ibiblio.org/pub/historic-linux/early-ports/Sparc/NCR/NCR89C100.txt 39 * and 40 * http://www.ibiblio.org/pub/historic-linux/early-ports/Sparc/NCR/NCR53C9X.txt 41 * 42 * On Macintosh Quadra it is a NCR53C96. 43 */ 44 45 static void esp_raise_irq(ESPState *s) 46 { 47 if (!(s->rregs[ESP_RSTAT] & STAT_INT)) { 48 s->rregs[ESP_RSTAT] |= STAT_INT; 49 qemu_irq_raise(s->irq); 50 trace_esp_raise_irq(); 51 } 52 } 53 54 static void esp_lower_irq(ESPState *s) 55 { 56 if (s->rregs[ESP_RSTAT] & STAT_INT) { 57 s->rregs[ESP_RSTAT] &= ~STAT_INT; 58 qemu_irq_lower(s->irq); 59 trace_esp_lower_irq(); 60 } 61 } 62 63 static void esp_raise_drq(ESPState *s) 64 { 65 qemu_irq_raise(s->irq_data); 66 trace_esp_raise_drq(); 67 } 68 69 static void esp_lower_drq(ESPState *s) 70 { 71 qemu_irq_lower(s->irq_data); 72 trace_esp_lower_drq(); 73 } 74 75 void esp_dma_enable(ESPState *s, int irq, int level) 76 { 77 if (level) { 78 s->dma_enabled = 1; 79 trace_esp_dma_enable(); 80 if (s->dma_cb) { 81 s->dma_cb(s); 82 s->dma_cb = NULL; 83 } 84 } else { 85 trace_esp_dma_disable(); 86 s->dma_enabled = 0; 87 } 88 } 89 90 void esp_request_cancelled(SCSIRequest *req) 91 { 92 ESPState *s = req->hba_private; 93 94 if (req == s->current_req) { 95 scsi_req_unref(s->current_req); 96 s->current_req = NULL; 97 s->current_dev = NULL; 98 s->async_len = 0; 99 } 100 } 101 102 static void esp_fifo_push(Fifo8 *fifo, uint8_t val) 103 { 104 if (fifo8_num_used(fifo) == fifo->capacity) { 105 trace_esp_error_fifo_overrun(); 106 return; 107 } 108 109 fifo8_push(fifo, val); 110 } 111 112 static uint8_t esp_fifo_pop(Fifo8 *fifo) 113 { 114 if (fifo8_is_empty(fifo)) { 115 return 0; 116 } 117 118 return fifo8_pop(fifo); 119 } 120 121 static uint32_t esp_fifo_pop_buf(Fifo8 *fifo, uint8_t *dest, int maxlen) 122 { 123 const uint8_t *buf; 124 uint32_t n, n2; 125 int len; 126 127 if (maxlen == 0) { 128 return 0; 129 } 130 131 len = maxlen; 132 buf = fifo8_pop_buf(fifo, len, &n); 133 if (dest) { 134 memcpy(dest, buf, n); 135 } 136 137 /* Add FIFO wraparound if needed */ 138 len -= n; 139 len = MIN(len, fifo8_num_used(fifo)); 140 if (len) { 141 buf = fifo8_pop_buf(fifo, len, &n2); 142 if (dest) { 143 memcpy(&dest[n], buf, n2); 144 } 145 n += n2; 146 } 147 148 return n; 149 } 150 151 static uint32_t esp_get_tc(ESPState *s) 152 { 153 uint32_t dmalen; 154 155 dmalen = s->rregs[ESP_TCLO]; 156 dmalen |= s->rregs[ESP_TCMID] << 8; 157 dmalen |= s->rregs[ESP_TCHI] << 16; 158 159 return dmalen; 160 } 161 162 static void esp_set_tc(ESPState *s, uint32_t dmalen) 163 { 164 uint32_t old_tc = esp_get_tc(s); 165 166 s->rregs[ESP_TCLO] = dmalen; 167 s->rregs[ESP_TCMID] = dmalen >> 8; 168 s->rregs[ESP_TCHI] = dmalen >> 16; 169 170 if (old_tc && dmalen == 0) { 171 s->rregs[ESP_RSTAT] |= STAT_TC; 172 } 173 } 174 175 static uint32_t esp_get_stc(ESPState *s) 176 { 177 uint32_t dmalen; 178 179 dmalen = s->wregs[ESP_TCLO]; 180 dmalen |= s->wregs[ESP_TCMID] << 8; 181 dmalen |= s->wregs[ESP_TCHI] << 16; 182 183 return dmalen; 184 } 185 186 static const char *esp_phase_names[8] = { 187 "DATA OUT", "DATA IN", "COMMAND", "STATUS", 188 "(reserved)", "(reserved)", "MESSAGE OUT", "MESSAGE IN" 189 }; 190 191 static void esp_set_phase(ESPState *s, uint8_t phase) 192 { 193 s->rregs[ESP_RSTAT] &= ~7; 194 s->rregs[ESP_RSTAT] |= phase; 195 196 trace_esp_set_phase(esp_phase_names[phase]); 197 } 198 199 static uint8_t esp_pdma_read(ESPState *s) 200 { 201 uint8_t val; 202 203 val = esp_fifo_pop(&s->fifo); 204 return val; 205 } 206 207 static void esp_pdma_write(ESPState *s, uint8_t val) 208 { 209 uint32_t dmalen = esp_get_tc(s); 210 211 if (dmalen == 0) { 212 return; 213 } 214 215 esp_fifo_push(&s->fifo, val); 216 217 dmalen--; 218 esp_set_tc(s, dmalen); 219 } 220 221 static void esp_set_pdma_cb(ESPState *s, enum pdma_cb cb) 222 { 223 s->pdma_cb = cb; 224 } 225 226 static int esp_select(ESPState *s) 227 { 228 int target; 229 230 target = s->wregs[ESP_WBUSID] & BUSID_DID; 231 232 s->ti_size = 0; 233 234 if (s->current_req) { 235 /* Started a new command before the old one finished. Cancel it. */ 236 scsi_req_cancel(s->current_req); 237 } 238 239 s->current_dev = scsi_device_find(&s->bus, 0, target, 0); 240 if (!s->current_dev) { 241 /* No such drive */ 242 s->rregs[ESP_RSTAT] = 0; 243 s->rregs[ESP_RINTR] = INTR_DC; 244 s->rregs[ESP_RSEQ] = SEQ_0; 245 esp_raise_irq(s); 246 return -1; 247 } 248 249 /* 250 * Note that we deliberately don't raise the IRQ here: this will be done 251 * either in do_command_phase() for DATA OUT transfers or by the deferred 252 * IRQ mechanism in esp_transfer_data() for DATA IN transfers 253 */ 254 s->rregs[ESP_RINTR] |= INTR_FC; 255 s->rregs[ESP_RSEQ] = SEQ_CD; 256 return 0; 257 } 258 259 static uint32_t get_cmd(ESPState *s, uint32_t maxlen) 260 { 261 uint8_t buf[ESP_CMDFIFO_SZ]; 262 uint32_t dmalen, n; 263 int target; 264 265 target = s->wregs[ESP_WBUSID] & BUSID_DID; 266 if (s->dma) { 267 dmalen = MIN(esp_get_tc(s), maxlen); 268 if (dmalen == 0) { 269 return 0; 270 } 271 if (s->dma_memory_read) { 272 s->dma_memory_read(s->dma_opaque, buf, dmalen); 273 dmalen = MIN(fifo8_num_free(&s->cmdfifo), dmalen); 274 fifo8_push_all(&s->cmdfifo, buf, dmalen); 275 esp_set_tc(s, esp_get_tc(s) - dmalen); 276 } else { 277 return 0; 278 } 279 } else { 280 dmalen = MIN(fifo8_num_used(&s->fifo), maxlen); 281 if (dmalen == 0) { 282 return 0; 283 } 284 n = esp_fifo_pop_buf(&s->fifo, buf, dmalen); 285 n = MIN(fifo8_num_free(&s->cmdfifo), n); 286 fifo8_push_all(&s->cmdfifo, buf, n); 287 } 288 trace_esp_get_cmd(dmalen, target); 289 290 return dmalen; 291 } 292 293 static void do_command_phase(ESPState *s) 294 { 295 uint32_t cmdlen; 296 int32_t datalen; 297 SCSIDevice *current_lun; 298 uint8_t buf[ESP_CMDFIFO_SZ]; 299 300 trace_esp_do_command_phase(s->lun); 301 cmdlen = fifo8_num_used(&s->cmdfifo); 302 if (!cmdlen || !s->current_dev) { 303 return; 304 } 305 esp_fifo_pop_buf(&s->cmdfifo, buf, cmdlen); 306 307 current_lun = scsi_device_find(&s->bus, 0, s->current_dev->id, s->lun); 308 if (!current_lun) { 309 /* No such drive */ 310 s->rregs[ESP_RSTAT] = 0; 311 s->rregs[ESP_RINTR] = INTR_DC; 312 s->rregs[ESP_RSEQ] = SEQ_0; 313 esp_raise_irq(s); 314 return; 315 } 316 317 s->current_req = scsi_req_new(current_lun, 0, s->lun, buf, cmdlen, s); 318 datalen = scsi_req_enqueue(s->current_req); 319 s->ti_size = datalen; 320 fifo8_reset(&s->cmdfifo); 321 if (datalen != 0) { 322 s->ti_cmd = 0; 323 if (datalen > 0) { 324 /* 325 * Switch to DATA IN phase but wait until initial data xfer is 326 * complete before raising the command completion interrupt 327 */ 328 s->data_in_ready = false; 329 esp_set_phase(s, STAT_DI); 330 } else { 331 esp_set_phase(s, STAT_DO); 332 s->rregs[ESP_RINTR] |= INTR_BS | INTR_FC; 333 esp_raise_irq(s); 334 esp_lower_drq(s); 335 } 336 scsi_req_continue(s->current_req); 337 return; 338 } 339 } 340 341 static void do_message_phase(ESPState *s) 342 { 343 if (s->cmdfifo_cdb_offset) { 344 uint8_t message = esp_fifo_pop(&s->cmdfifo); 345 346 trace_esp_do_identify(message); 347 s->lun = message & 7; 348 s->cmdfifo_cdb_offset--; 349 } 350 351 /* Ignore extended messages for now */ 352 if (s->cmdfifo_cdb_offset) { 353 int len = MIN(s->cmdfifo_cdb_offset, fifo8_num_used(&s->cmdfifo)); 354 esp_fifo_pop_buf(&s->cmdfifo, NULL, len); 355 s->cmdfifo_cdb_offset = 0; 356 } 357 } 358 359 static void do_cmd(ESPState *s) 360 { 361 do_message_phase(s); 362 assert(s->cmdfifo_cdb_offset == 0); 363 do_command_phase(s); 364 } 365 366 static void satn_pdma_cb(ESPState *s) 367 { 368 uint8_t buf[ESP_FIFO_SZ]; 369 int n; 370 371 /* Copy FIFO into cmdfifo */ 372 n = esp_fifo_pop_buf(&s->fifo, buf, fifo8_num_used(&s->fifo)); 373 n = MIN(fifo8_num_free(&s->cmdfifo), n); 374 fifo8_push_all(&s->cmdfifo, buf, n); 375 376 if (!esp_get_tc(s) && !fifo8_is_empty(&s->cmdfifo)) { 377 s->cmdfifo_cdb_offset = 1; 378 s->do_cmd = 0; 379 do_cmd(s); 380 } 381 } 382 383 static void handle_satn(ESPState *s) 384 { 385 int32_t cmdlen; 386 387 if (s->dma && !s->dma_enabled) { 388 s->dma_cb = handle_satn; 389 return; 390 } 391 esp_set_pdma_cb(s, SATN_PDMA_CB); 392 if (esp_select(s) < 0) { 393 return; 394 } 395 cmdlen = get_cmd(s, ESP_CMDFIFO_SZ); 396 if (cmdlen > 0) { 397 s->cmdfifo_cdb_offset = 1; 398 s->do_cmd = 0; 399 do_cmd(s); 400 } else if (cmdlen == 0) { 401 if (s->dma) { 402 esp_raise_drq(s); 403 } 404 s->do_cmd = 1; 405 /* Target present, but no cmd yet - switch to command phase */ 406 s->rregs[ESP_RSEQ] = SEQ_CD; 407 esp_set_phase(s, STAT_CD); 408 } 409 } 410 411 static void handle_s_without_atn(ESPState *s) 412 { 413 int32_t cmdlen; 414 415 if (s->dma && !s->dma_enabled) { 416 s->dma_cb = handle_s_without_atn; 417 return; 418 } 419 esp_set_pdma_cb(s, DO_DMA_PDMA_CB); 420 if (esp_select(s) < 0) { 421 return; 422 } 423 cmdlen = get_cmd(s, ESP_CMDFIFO_SZ); 424 if (cmdlen > 0) { 425 s->cmdfifo_cdb_offset = 0; 426 s->do_cmd = 0; 427 do_cmd(s); 428 } else if (cmdlen == 0) { 429 if (s->dma) { 430 esp_raise_drq(s); 431 } 432 s->do_cmd = 1; 433 /* Target present, but no cmd yet - switch to command phase */ 434 s->rregs[ESP_RSEQ] = SEQ_CD; 435 esp_set_phase(s, STAT_CD); 436 } 437 } 438 439 static void satn_stop_pdma_cb(ESPState *s) 440 { 441 uint8_t buf[ESP_FIFO_SZ]; 442 int n; 443 444 /* Copy FIFO into cmdfifo */ 445 n = esp_fifo_pop_buf(&s->fifo, buf, fifo8_num_used(&s->fifo)); 446 n = MIN(fifo8_num_free(&s->cmdfifo), n); 447 fifo8_push_all(&s->cmdfifo, buf, n); 448 449 if (!esp_get_tc(s) && !fifo8_is_empty(&s->cmdfifo)) { 450 trace_esp_handle_satn_stop(fifo8_num_used(&s->cmdfifo)); 451 s->do_cmd = 1; 452 s->cmdfifo_cdb_offset = 1; 453 esp_set_phase(s, STAT_CD); 454 s->rregs[ESP_RSTAT] |= STAT_TC; 455 s->rregs[ESP_RINTR] |= INTR_BS | INTR_FC; 456 s->rregs[ESP_RSEQ] = SEQ_CD; 457 esp_raise_irq(s); 458 } 459 } 460 461 static void handle_satn_stop(ESPState *s) 462 { 463 int32_t cmdlen; 464 465 if (s->dma && !s->dma_enabled) { 466 s->dma_cb = handle_satn_stop; 467 return; 468 } 469 esp_set_pdma_cb(s, SATN_STOP_PDMA_CB); 470 if (esp_select(s) < 0) { 471 return; 472 } 473 cmdlen = get_cmd(s, 1); 474 if (cmdlen > 0) { 475 trace_esp_handle_satn_stop(fifo8_num_used(&s->cmdfifo)); 476 s->do_cmd = 1; 477 s->cmdfifo_cdb_offset = 1; 478 esp_set_phase(s, STAT_MO); 479 s->rregs[ESP_RINTR] |= INTR_BS | INTR_FC; 480 s->rregs[ESP_RSEQ] = SEQ_MO; 481 esp_raise_irq(s); 482 } else if (cmdlen == 0) { 483 if (s->dma) { 484 esp_raise_drq(s); 485 } 486 s->do_cmd = 1; 487 /* Target present, switch to message out phase */ 488 s->rregs[ESP_RSEQ] = SEQ_MO; 489 esp_set_phase(s, STAT_MO); 490 } 491 } 492 493 static void write_response_pdma_cb(ESPState *s) 494 { 495 esp_set_phase(s, STAT_ST); 496 s->rregs[ESP_RINTR] |= INTR_BS | INTR_FC; 497 s->rregs[ESP_RSEQ] = SEQ_CD; 498 esp_raise_irq(s); 499 } 500 501 static void write_response(ESPState *s) 502 { 503 uint8_t buf[2]; 504 505 trace_esp_write_response(s->status); 506 507 buf[0] = s->status; 508 buf[1] = 0; 509 510 if (s->dma) { 511 if (s->dma_memory_write) { 512 s->dma_memory_write(s->dma_opaque, buf, 2); 513 esp_set_phase(s, STAT_ST); 514 s->rregs[ESP_RINTR] |= INTR_BS | INTR_FC; 515 s->rregs[ESP_RSEQ] = SEQ_CD; 516 } else { 517 esp_set_pdma_cb(s, WRITE_RESPONSE_PDMA_CB); 518 esp_raise_drq(s); 519 return; 520 } 521 } else { 522 fifo8_reset(&s->fifo); 523 fifo8_push_all(&s->fifo, buf, 2); 524 s->rregs[ESP_RFLAGS] = 2; 525 } 526 esp_raise_irq(s); 527 } 528 529 static void esp_dma_ti_check(ESPState *s) 530 { 531 if (esp_get_tc(s) == 0 && fifo8_num_used(&s->fifo) < 2) { 532 s->rregs[ESP_RINTR] |= INTR_BS; 533 esp_raise_irq(s); 534 esp_lower_drq(s); 535 } 536 } 537 538 static void do_dma_pdma_cb(ESPState *s) 539 { 540 int to_device = ((s->rregs[ESP_RSTAT] & 7) == STAT_DO); 541 uint8_t buf[ESP_CMDFIFO_SZ]; 542 int len; 543 uint32_t n; 544 545 if (s->do_cmd) { 546 /* Copy FIFO into cmdfifo */ 547 n = esp_fifo_pop_buf(&s->fifo, buf, fifo8_num_used(&s->fifo)); 548 n = MIN(fifo8_num_free(&s->cmdfifo), n); 549 fifo8_push_all(&s->cmdfifo, buf, n); 550 551 /* Ensure we have received complete command after SATN and stop */ 552 if (esp_get_tc(s) || fifo8_is_empty(&s->cmdfifo)) { 553 return; 554 } 555 556 s->ti_size = 0; 557 if ((s->rregs[ESP_RSTAT] & 7) == STAT_CD) { 558 /* No command received */ 559 if (s->cmdfifo_cdb_offset == fifo8_num_used(&s->cmdfifo)) { 560 return; 561 } 562 563 /* Command has been received */ 564 s->do_cmd = 0; 565 do_cmd(s); 566 } else { 567 /* 568 * Extra message out bytes received: update cmdfifo_cdb_offset 569 * and then switch to command phase 570 */ 571 s->cmdfifo_cdb_offset = fifo8_num_used(&s->cmdfifo); 572 esp_set_phase(s, STAT_CD); 573 s->rregs[ESP_RSEQ] = SEQ_CD; 574 s->rregs[ESP_RINTR] |= INTR_BS; 575 esp_raise_irq(s); 576 } 577 return; 578 } 579 580 if (!s->current_req) { 581 return; 582 } 583 584 if (to_device) { 585 /* Copy FIFO data to device */ 586 len = MIN(s->async_len, ESP_FIFO_SZ); 587 len = MIN(len, fifo8_num_used(&s->fifo)); 588 n = esp_fifo_pop_buf(&s->fifo, s->async_buf, len); 589 s->async_buf += n; 590 s->async_len -= n; 591 s->ti_size += n; 592 593 if (s->async_len == 0 && fifo8_num_used(&s->fifo) < 2) { 594 /* Defer until the scsi layer has completed */ 595 scsi_req_continue(s->current_req); 596 return; 597 } 598 599 esp_dma_ti_check(s); 600 } else { 601 /* Copy device data to FIFO */ 602 len = MIN(s->async_len, esp_get_tc(s)); 603 len = MIN(len, fifo8_num_free(&s->fifo)); 604 fifo8_push_all(&s->fifo, s->async_buf, len); 605 s->async_buf += len; 606 s->async_len -= len; 607 s->ti_size -= len; 608 esp_set_tc(s, esp_get_tc(s) - len); 609 610 if (s->async_len == 0 && fifo8_num_used(&s->fifo) < 2) { 611 /* Defer until the scsi layer has completed */ 612 scsi_req_continue(s->current_req); 613 s->data_in_ready = false; 614 return; 615 } 616 617 esp_dma_ti_check(s); 618 } 619 } 620 621 static void esp_do_dma(ESPState *s) 622 { 623 uint32_t len, cmdlen; 624 int to_device = ((s->rregs[ESP_RSTAT] & 7) == STAT_DO); 625 uint8_t buf[ESP_CMDFIFO_SZ]; 626 int n; 627 628 len = esp_get_tc(s); 629 if (s->do_cmd) { 630 /* 631 * handle_ti_cmd() case: esp_do_dma() is called only from 632 * handle_ti_cmd() with do_cmd != NULL (see the assert()) 633 */ 634 cmdlen = fifo8_num_used(&s->cmdfifo); 635 trace_esp_do_dma(cmdlen, len); 636 if (s->dma_memory_read) { 637 len = MIN(len, fifo8_num_free(&s->cmdfifo)); 638 s->dma_memory_read(s->dma_opaque, buf, len); 639 fifo8_push_all(&s->cmdfifo, buf, len); 640 esp_set_tc(s, esp_get_tc(s) - len); 641 } else { 642 n = esp_fifo_pop_buf(&s->fifo, buf, fifo8_num_used(&s->fifo)); 643 n = MIN(fifo8_num_free(&s->cmdfifo), n); 644 fifo8_push_all(&s->cmdfifo, buf, n); 645 esp_set_tc(s, esp_get_tc(s) - n); 646 647 esp_set_pdma_cb(s, DO_DMA_PDMA_CB); 648 esp_raise_drq(s); 649 650 /* Ensure we have received complete command after SATN and stop */ 651 if (esp_get_tc(s) || fifo8_is_empty(&s->cmdfifo)) { 652 return; 653 } 654 } 655 trace_esp_handle_ti_cmd(cmdlen); 656 s->ti_size = 0; 657 if ((s->rregs[ESP_RSTAT] & 7) == STAT_CD) { 658 /* No command received */ 659 if (s->cmdfifo_cdb_offset == fifo8_num_used(&s->cmdfifo)) { 660 return; 661 } 662 663 /* Command has been received */ 664 s->do_cmd = 0; 665 do_cmd(s); 666 } else { 667 /* 668 * Extra message out bytes received: update cmdfifo_cdb_offset 669 * and then switch to command phase 670 */ 671 s->cmdfifo_cdb_offset = fifo8_num_used(&s->cmdfifo); 672 esp_set_phase(s, STAT_CD); 673 s->rregs[ESP_RSEQ] = SEQ_CD; 674 s->rregs[ESP_RINTR] |= INTR_BS; 675 esp_raise_irq(s); 676 } 677 return; 678 } 679 if (!s->current_req) { 680 return; 681 } 682 if (s->async_len == 0 && esp_get_tc(s) && s->ti_size) { 683 /* Defer until data is available. */ 684 return; 685 } 686 if (len > s->async_len) { 687 len = s->async_len; 688 } 689 if (to_device) { 690 if (s->dma_memory_read) { 691 s->dma_memory_read(s->dma_opaque, s->async_buf, len); 692 693 esp_set_tc(s, esp_get_tc(s) - len); 694 s->async_buf += len; 695 s->async_len -= len; 696 s->ti_size += len; 697 698 if (s->async_len == 0 && fifo8_num_used(&s->fifo) < 2) { 699 /* Defer until the scsi layer has completed */ 700 scsi_req_continue(s->current_req); 701 return; 702 } 703 704 esp_dma_ti_check(s); 705 } else { 706 /* Copy FIFO data to device */ 707 len = MIN(s->async_len, ESP_FIFO_SZ); 708 len = MIN(len, fifo8_num_used(&s->fifo)); 709 n = esp_fifo_pop_buf(&s->fifo, s->async_buf, len); 710 s->async_buf += n; 711 s->async_len -= n; 712 s->ti_size += n; 713 714 esp_set_pdma_cb(s, DO_DMA_PDMA_CB); 715 esp_raise_drq(s); 716 717 if (s->async_len == 0 && fifo8_num_used(&s->fifo) < 2) { 718 /* Defer until the scsi layer has completed */ 719 scsi_req_continue(s->current_req); 720 return; 721 } 722 723 esp_dma_ti_check(s); 724 } 725 } else { 726 if (s->dma_memory_write) { 727 s->dma_memory_write(s->dma_opaque, s->async_buf, len); 728 729 esp_set_tc(s, esp_get_tc(s) - len); 730 s->async_buf += len; 731 s->async_len -= len; 732 s->ti_size -= len; 733 734 if (s->async_len == 0 && fifo8_num_used(&s->fifo) < 2) { 735 /* Defer until the scsi layer has completed */ 736 scsi_req_continue(s->current_req); 737 return; 738 } 739 740 esp_dma_ti_check(s); 741 } else { 742 /* Copy device data to FIFO */ 743 len = MIN(len, fifo8_num_free(&s->fifo)); 744 fifo8_push_all(&s->fifo, s->async_buf, len); 745 s->async_buf += len; 746 s->async_len -= len; 747 s->ti_size -= len; 748 esp_set_tc(s, esp_get_tc(s) - len); 749 esp_set_pdma_cb(s, DO_DMA_PDMA_CB); 750 esp_raise_drq(s); 751 752 if (s->async_len == 0 && fifo8_num_used(&s->fifo) < 2) { 753 /* Defer until the scsi layer has completed */ 754 scsi_req_continue(s->current_req); 755 return; 756 } 757 758 esp_dma_ti_check(s); 759 } 760 } 761 } 762 763 static void esp_do_nodma(ESPState *s) 764 { 765 int to_device = ((s->rregs[ESP_RSTAT] & 7) == STAT_DO); 766 uint8_t buf[ESP_FIFO_SZ]; 767 uint32_t cmdlen; 768 int len, n; 769 770 if (s->do_cmd) { 771 /* Copy FIFO into cmdfifo */ 772 n = esp_fifo_pop_buf(&s->fifo, buf, fifo8_num_used(&s->fifo)); 773 n = MIN(fifo8_num_free(&s->cmdfifo), n); 774 fifo8_push_all(&s->cmdfifo, buf, n); 775 776 cmdlen = fifo8_num_used(&s->cmdfifo); 777 trace_esp_handle_ti_cmd(cmdlen); 778 s->ti_size = 0; 779 if ((s->rregs[ESP_RSTAT] & 7) == STAT_CD) { 780 /* No command received */ 781 if (s->cmdfifo_cdb_offset == fifo8_num_used(&s->cmdfifo)) { 782 return; 783 } 784 785 /* Command has been received */ 786 s->do_cmd = 0; 787 do_cmd(s); 788 } else { 789 /* 790 * Extra message out bytes received: update cmdfifo_cdb_offset 791 * and then switch to command phase 792 */ 793 s->cmdfifo_cdb_offset = fifo8_num_used(&s->cmdfifo); 794 esp_set_phase(s, STAT_CD); 795 s->rregs[ESP_RSEQ] = SEQ_CD; 796 s->rregs[ESP_RINTR] |= INTR_BS; 797 esp_raise_irq(s); 798 } 799 return; 800 } 801 802 if (!s->current_req) { 803 return; 804 } 805 806 if (s->async_len == 0) { 807 /* Defer until data is available. */ 808 return; 809 } 810 811 if (to_device) { 812 len = MIN(s->async_len, ESP_FIFO_SZ); 813 len = MIN(len, fifo8_num_used(&s->fifo)); 814 esp_fifo_pop_buf(&s->fifo, s->async_buf, len); 815 s->async_buf += len; 816 s->async_len -= len; 817 s->ti_size += len; 818 } else { 819 if (fifo8_is_empty(&s->fifo)) { 820 fifo8_push(&s->fifo, s->async_buf[0]); 821 s->async_buf++; 822 s->async_len--; 823 s->ti_size--; 824 } 825 } 826 827 if (s->async_len == 0) { 828 scsi_req_continue(s->current_req); 829 return; 830 } 831 832 s->rregs[ESP_RINTR] |= INTR_BS; 833 esp_raise_irq(s); 834 } 835 836 static void esp_pdma_cb(ESPState *s) 837 { 838 switch (s->pdma_cb) { 839 case SATN_PDMA_CB: 840 satn_pdma_cb(s); 841 break; 842 case SATN_STOP_PDMA_CB: 843 satn_stop_pdma_cb(s); 844 break; 845 case WRITE_RESPONSE_PDMA_CB: 846 write_response_pdma_cb(s); 847 break; 848 case DO_DMA_PDMA_CB: 849 do_dma_pdma_cb(s); 850 break; 851 default: 852 g_assert_not_reached(); 853 } 854 } 855 856 void esp_command_complete(SCSIRequest *req, size_t resid) 857 { 858 ESPState *s = req->hba_private; 859 int to_device = ((s->rregs[ESP_RSTAT] & 7) == STAT_DO); 860 861 trace_esp_command_complete(); 862 863 /* 864 * Non-DMA transfers from the target will leave the last byte in 865 * the FIFO so don't reset ti_size in this case 866 */ 867 if (s->dma || to_device) { 868 if (s->ti_size != 0) { 869 trace_esp_command_complete_unexpected(); 870 } 871 } 872 873 s->async_len = 0; 874 if (req->status) { 875 trace_esp_command_complete_fail(); 876 } 877 s->status = req->status; 878 879 /* 880 * Switch to status phase. For non-DMA transfers from the target the last 881 * byte is still in the FIFO 882 */ 883 esp_set_phase(s, STAT_ST); 884 if (s->ti_size == 0) { 885 /* 886 * Transfer complete: force TC to zero just in case a TI command was 887 * requested for more data than the command returns (Solaris 8 does 888 * this) 889 */ 890 esp_set_tc(s, 0); 891 esp_dma_ti_check(s); 892 } else { 893 /* 894 * Transfer truncated: raise INTR_BS to indicate early change of 895 * phase 896 */ 897 s->rregs[ESP_RINTR] |= INTR_BS; 898 esp_raise_irq(s); 899 s->ti_size = 0; 900 } 901 902 if (s->current_req) { 903 scsi_req_unref(s->current_req); 904 s->current_req = NULL; 905 s->current_dev = NULL; 906 } 907 } 908 909 void esp_transfer_data(SCSIRequest *req, uint32_t len) 910 { 911 ESPState *s = req->hba_private; 912 int to_device = ((s->rregs[ESP_RSTAT] & 7) == STAT_DO); 913 uint32_t dmalen = esp_get_tc(s); 914 915 assert(!s->do_cmd); 916 trace_esp_transfer_data(dmalen, s->ti_size); 917 s->async_len = len; 918 s->async_buf = scsi_req_get_buf(req); 919 920 if (!to_device && !s->data_in_ready) { 921 /* 922 * Initial incoming data xfer is complete so raise command 923 * completion interrupt 924 */ 925 s->data_in_ready = true; 926 s->rregs[ESP_RINTR] |= INTR_BS; 927 esp_raise_irq(s); 928 } 929 930 /* 931 * Always perform the initial transfer upon reception of the next TI 932 * command to ensure the DMA/non-DMA status of the command is correct. 933 * It is not possible to use s->dma directly in the section below as 934 * some OSs send non-DMA NOP commands after a DMA transfer. Hence if the 935 * async data transfer is delayed then s->dma is set incorrectly. 936 */ 937 938 if (s->ti_cmd == (CMD_TI | CMD_DMA)) { 939 /* When the SCSI layer returns more data, raise deferred INTR_BS */ 940 esp_dma_ti_check(s); 941 942 esp_do_dma(s); 943 } else if (s->ti_cmd == CMD_TI) { 944 esp_do_nodma(s); 945 } 946 } 947 948 static void handle_ti(ESPState *s) 949 { 950 uint32_t dmalen; 951 952 if (s->dma && !s->dma_enabled) { 953 s->dma_cb = handle_ti; 954 return; 955 } 956 957 s->ti_cmd = s->rregs[ESP_CMD]; 958 if (s->dma) { 959 dmalen = esp_get_tc(s); 960 trace_esp_handle_ti(dmalen); 961 esp_do_dma(s); 962 } else { 963 trace_esp_handle_ti(s->ti_size); 964 esp_do_nodma(s); 965 } 966 } 967 968 void esp_hard_reset(ESPState *s) 969 { 970 memset(s->rregs, 0, ESP_REGS); 971 memset(s->wregs, 0, ESP_REGS); 972 s->tchi_written = 0; 973 s->ti_size = 0; 974 s->async_len = 0; 975 fifo8_reset(&s->fifo); 976 fifo8_reset(&s->cmdfifo); 977 s->dma = 0; 978 s->do_cmd = 0; 979 s->dma_cb = NULL; 980 981 s->rregs[ESP_CFG1] = 7; 982 } 983 984 static void esp_soft_reset(ESPState *s) 985 { 986 qemu_irq_lower(s->irq); 987 qemu_irq_lower(s->irq_data); 988 esp_hard_reset(s); 989 } 990 991 static void esp_bus_reset(ESPState *s) 992 { 993 bus_cold_reset(BUS(&s->bus)); 994 } 995 996 static void parent_esp_reset(ESPState *s, int irq, int level) 997 { 998 if (level) { 999 esp_soft_reset(s); 1000 } 1001 } 1002 1003 static void esp_run_cmd(ESPState *s) 1004 { 1005 uint8_t cmd = s->rregs[ESP_CMD]; 1006 1007 if (cmd & CMD_DMA) { 1008 s->dma = 1; 1009 /* Reload DMA counter. */ 1010 if (esp_get_stc(s) == 0) { 1011 esp_set_tc(s, 0x10000); 1012 } else { 1013 esp_set_tc(s, esp_get_stc(s)); 1014 } 1015 } else { 1016 s->dma = 0; 1017 } 1018 switch (cmd & CMD_CMD) { 1019 case CMD_NOP: 1020 trace_esp_mem_writeb_cmd_nop(cmd); 1021 break; 1022 case CMD_FLUSH: 1023 trace_esp_mem_writeb_cmd_flush(cmd); 1024 fifo8_reset(&s->fifo); 1025 break; 1026 case CMD_RESET: 1027 trace_esp_mem_writeb_cmd_reset(cmd); 1028 esp_soft_reset(s); 1029 break; 1030 case CMD_BUSRESET: 1031 trace_esp_mem_writeb_cmd_bus_reset(cmd); 1032 esp_bus_reset(s); 1033 if (!(s->wregs[ESP_CFG1] & CFG1_RESREPT)) { 1034 s->rregs[ESP_RINTR] |= INTR_RST; 1035 esp_raise_irq(s); 1036 } 1037 break; 1038 case CMD_TI: 1039 trace_esp_mem_writeb_cmd_ti(cmd); 1040 handle_ti(s); 1041 break; 1042 case CMD_ICCS: 1043 trace_esp_mem_writeb_cmd_iccs(cmd); 1044 write_response(s); 1045 s->rregs[ESP_RINTR] |= INTR_FC; 1046 esp_set_phase(s, STAT_MI); 1047 break; 1048 case CMD_MSGACC: 1049 trace_esp_mem_writeb_cmd_msgacc(cmd); 1050 s->rregs[ESP_RINTR] |= INTR_DC; 1051 s->rregs[ESP_RSEQ] = 0; 1052 s->rregs[ESP_RFLAGS] = 0; 1053 esp_raise_irq(s); 1054 break; 1055 case CMD_PAD: 1056 trace_esp_mem_writeb_cmd_pad(cmd); 1057 s->rregs[ESP_RSTAT] = STAT_TC; 1058 s->rregs[ESP_RINTR] |= INTR_FC; 1059 s->rregs[ESP_RSEQ] = 0; 1060 break; 1061 case CMD_SATN: 1062 trace_esp_mem_writeb_cmd_satn(cmd); 1063 break; 1064 case CMD_RSTATN: 1065 trace_esp_mem_writeb_cmd_rstatn(cmd); 1066 break; 1067 case CMD_SEL: 1068 trace_esp_mem_writeb_cmd_sel(cmd); 1069 handle_s_without_atn(s); 1070 break; 1071 case CMD_SELATN: 1072 trace_esp_mem_writeb_cmd_selatn(cmd); 1073 handle_satn(s); 1074 break; 1075 case CMD_SELATNS: 1076 trace_esp_mem_writeb_cmd_selatns(cmd); 1077 handle_satn_stop(s); 1078 break; 1079 case CMD_ENSEL: 1080 trace_esp_mem_writeb_cmd_ensel(cmd); 1081 s->rregs[ESP_RINTR] = 0; 1082 break; 1083 case CMD_DISSEL: 1084 trace_esp_mem_writeb_cmd_dissel(cmd); 1085 s->rregs[ESP_RINTR] = 0; 1086 esp_raise_irq(s); 1087 break; 1088 default: 1089 trace_esp_error_unhandled_command(cmd); 1090 break; 1091 } 1092 } 1093 1094 uint64_t esp_reg_read(ESPState *s, uint32_t saddr) 1095 { 1096 uint32_t val; 1097 1098 switch (saddr) { 1099 case ESP_FIFO: 1100 if (s->dma_memory_read && s->dma_memory_write && 1101 (s->rregs[ESP_RSTAT] & STAT_PIO_MASK) == 0) { 1102 /* Data out. */ 1103 qemu_log_mask(LOG_UNIMP, "esp: PIO data read not implemented\n"); 1104 s->rregs[ESP_FIFO] = 0; 1105 } else { 1106 if ((s->rregs[ESP_RSTAT] & 0x7) == STAT_DI) { 1107 if (s->ti_size) { 1108 esp_do_nodma(s); 1109 } else { 1110 /* 1111 * The last byte of a non-DMA transfer has been read out 1112 * of the FIFO so switch to status phase 1113 */ 1114 esp_set_phase(s, STAT_ST); 1115 } 1116 } 1117 s->rregs[ESP_FIFO] = esp_fifo_pop(&s->fifo); 1118 } 1119 val = s->rregs[ESP_FIFO]; 1120 break; 1121 case ESP_RINTR: 1122 /* 1123 * Clear sequence step, interrupt register and all status bits 1124 * except TC 1125 */ 1126 val = s->rregs[ESP_RINTR]; 1127 s->rregs[ESP_RINTR] = 0; 1128 s->rregs[ESP_RSTAT] &= ~STAT_TC; 1129 /* 1130 * According to the datasheet ESP_RSEQ should be cleared, but as the 1131 * emulation currently defers information transfers to the next TI 1132 * command leave it for now so that pedantic guests such as the old 1133 * Linux 2.6 driver see the correct flags before the next SCSI phase 1134 * transition. 1135 * 1136 * s->rregs[ESP_RSEQ] = SEQ_0; 1137 */ 1138 esp_lower_irq(s); 1139 break; 1140 case ESP_TCHI: 1141 /* Return the unique id if the value has never been written */ 1142 if (!s->tchi_written) { 1143 val = s->chip_id; 1144 } else { 1145 val = s->rregs[saddr]; 1146 } 1147 break; 1148 case ESP_RFLAGS: 1149 /* Bottom 5 bits indicate number of bytes in FIFO */ 1150 val = fifo8_num_used(&s->fifo); 1151 break; 1152 default: 1153 val = s->rregs[saddr]; 1154 break; 1155 } 1156 1157 trace_esp_mem_readb(saddr, val); 1158 return val; 1159 } 1160 1161 void esp_reg_write(ESPState *s, uint32_t saddr, uint64_t val) 1162 { 1163 trace_esp_mem_writeb(saddr, s->wregs[saddr], val); 1164 switch (saddr) { 1165 case ESP_TCHI: 1166 s->tchi_written = true; 1167 /* fall through */ 1168 case ESP_TCLO: 1169 case ESP_TCMID: 1170 s->rregs[ESP_RSTAT] &= ~STAT_TC; 1171 break; 1172 case ESP_FIFO: 1173 if (s->do_cmd) { 1174 if (!fifo8_is_full(&s->fifo)) { 1175 esp_fifo_push(&s->fifo, val); 1176 esp_fifo_push(&s->cmdfifo, fifo8_pop(&s->fifo)); 1177 } 1178 1179 /* 1180 * If any unexpected message out/command phase data is 1181 * transferred using non-DMA, raise the interrupt 1182 */ 1183 if (s->rregs[ESP_CMD] == CMD_TI) { 1184 s->rregs[ESP_RINTR] |= INTR_BS; 1185 esp_raise_irq(s); 1186 } 1187 } else { 1188 esp_fifo_push(&s->fifo, val); 1189 } 1190 break; 1191 case ESP_CMD: 1192 s->rregs[saddr] = val; 1193 esp_run_cmd(s); 1194 break; 1195 case ESP_WBUSID ... ESP_WSYNO: 1196 break; 1197 case ESP_CFG1: 1198 case ESP_CFG2: case ESP_CFG3: 1199 case ESP_RES3: case ESP_RES4: 1200 s->rregs[saddr] = val; 1201 break; 1202 case ESP_WCCF ... ESP_WTEST: 1203 break; 1204 default: 1205 trace_esp_error_invalid_write(val, saddr); 1206 return; 1207 } 1208 s->wregs[saddr] = val; 1209 } 1210 1211 static bool esp_mem_accepts(void *opaque, hwaddr addr, 1212 unsigned size, bool is_write, 1213 MemTxAttrs attrs) 1214 { 1215 return (size == 1) || (is_write && size == 4); 1216 } 1217 1218 static bool esp_is_before_version_5(void *opaque, int version_id) 1219 { 1220 ESPState *s = ESP(opaque); 1221 1222 version_id = MIN(version_id, s->mig_version_id); 1223 return version_id < 5; 1224 } 1225 1226 static bool esp_is_version_5(void *opaque, int version_id) 1227 { 1228 ESPState *s = ESP(opaque); 1229 1230 version_id = MIN(version_id, s->mig_version_id); 1231 return version_id >= 5; 1232 } 1233 1234 static bool esp_is_version_6(void *opaque, int version_id) 1235 { 1236 ESPState *s = ESP(opaque); 1237 1238 version_id = MIN(version_id, s->mig_version_id); 1239 return version_id >= 6; 1240 } 1241 1242 int esp_pre_save(void *opaque) 1243 { 1244 ESPState *s = ESP(object_resolve_path_component( 1245 OBJECT(opaque), "esp")); 1246 1247 s->mig_version_id = vmstate_esp.version_id; 1248 return 0; 1249 } 1250 1251 static int esp_post_load(void *opaque, int version_id) 1252 { 1253 ESPState *s = ESP(opaque); 1254 int len, i; 1255 1256 version_id = MIN(version_id, s->mig_version_id); 1257 1258 if (version_id < 5) { 1259 esp_set_tc(s, s->mig_dma_left); 1260 1261 /* Migrate ti_buf to fifo */ 1262 len = s->mig_ti_wptr - s->mig_ti_rptr; 1263 for (i = 0; i < len; i++) { 1264 fifo8_push(&s->fifo, s->mig_ti_buf[i]); 1265 } 1266 1267 /* Migrate cmdbuf to cmdfifo */ 1268 for (i = 0; i < s->mig_cmdlen; i++) { 1269 fifo8_push(&s->cmdfifo, s->mig_cmdbuf[i]); 1270 } 1271 } 1272 1273 s->mig_version_id = vmstate_esp.version_id; 1274 return 0; 1275 } 1276 1277 /* 1278 * PDMA (or pseudo-DMA) is only used on the Macintosh and requires the 1279 * guest CPU to perform the transfers between the SCSI bus and memory 1280 * itself. This is indicated by the dma_memory_read and dma_memory_write 1281 * functions being NULL (in contrast to the ESP PCI device) whilst 1282 * dma_enabled is still set. 1283 */ 1284 1285 static bool esp_pdma_needed(void *opaque) 1286 { 1287 ESPState *s = ESP(opaque); 1288 1289 return s->dma_memory_read == NULL && s->dma_memory_write == NULL && 1290 s->dma_enabled; 1291 } 1292 1293 static const VMStateDescription vmstate_esp_pdma = { 1294 .name = "esp/pdma", 1295 .version_id = 0, 1296 .minimum_version_id = 0, 1297 .needed = esp_pdma_needed, 1298 .fields = (const VMStateField[]) { 1299 VMSTATE_UINT8(pdma_cb, ESPState), 1300 VMSTATE_END_OF_LIST() 1301 } 1302 }; 1303 1304 const VMStateDescription vmstate_esp = { 1305 .name = "esp", 1306 .version_id = 6, 1307 .minimum_version_id = 3, 1308 .post_load = esp_post_load, 1309 .fields = (const VMStateField[]) { 1310 VMSTATE_BUFFER(rregs, ESPState), 1311 VMSTATE_BUFFER(wregs, ESPState), 1312 VMSTATE_INT32(ti_size, ESPState), 1313 VMSTATE_UINT32_TEST(mig_ti_rptr, ESPState, esp_is_before_version_5), 1314 VMSTATE_UINT32_TEST(mig_ti_wptr, ESPState, esp_is_before_version_5), 1315 VMSTATE_BUFFER_TEST(mig_ti_buf, ESPState, esp_is_before_version_5), 1316 VMSTATE_UINT32(status, ESPState), 1317 VMSTATE_UINT32_TEST(mig_deferred_status, ESPState, 1318 esp_is_before_version_5), 1319 VMSTATE_BOOL_TEST(mig_deferred_complete, ESPState, 1320 esp_is_before_version_5), 1321 VMSTATE_UINT32(dma, ESPState), 1322 VMSTATE_STATIC_BUFFER(mig_cmdbuf, ESPState, 0, 1323 esp_is_before_version_5, 0, 16), 1324 VMSTATE_STATIC_BUFFER(mig_cmdbuf, ESPState, 4, 1325 esp_is_before_version_5, 16, 1326 sizeof(typeof_field(ESPState, mig_cmdbuf))), 1327 VMSTATE_UINT32_TEST(mig_cmdlen, ESPState, esp_is_before_version_5), 1328 VMSTATE_UINT32(do_cmd, ESPState), 1329 VMSTATE_UINT32_TEST(mig_dma_left, ESPState, esp_is_before_version_5), 1330 VMSTATE_BOOL_TEST(data_in_ready, ESPState, esp_is_version_5), 1331 VMSTATE_UINT8_TEST(cmdfifo_cdb_offset, ESPState, esp_is_version_5), 1332 VMSTATE_FIFO8_TEST(fifo, ESPState, esp_is_version_5), 1333 VMSTATE_FIFO8_TEST(cmdfifo, ESPState, esp_is_version_5), 1334 VMSTATE_UINT8_TEST(ti_cmd, ESPState, esp_is_version_5), 1335 VMSTATE_UINT8_TEST(lun, ESPState, esp_is_version_6), 1336 VMSTATE_END_OF_LIST() 1337 }, 1338 .subsections = (const VMStateDescription * const []) { 1339 &vmstate_esp_pdma, 1340 NULL 1341 } 1342 }; 1343 1344 static void sysbus_esp_mem_write(void *opaque, hwaddr addr, 1345 uint64_t val, unsigned int size) 1346 { 1347 SysBusESPState *sysbus = opaque; 1348 ESPState *s = ESP(&sysbus->esp); 1349 uint32_t saddr; 1350 1351 saddr = addr >> sysbus->it_shift; 1352 esp_reg_write(s, saddr, val); 1353 } 1354 1355 static uint64_t sysbus_esp_mem_read(void *opaque, hwaddr addr, 1356 unsigned int size) 1357 { 1358 SysBusESPState *sysbus = opaque; 1359 ESPState *s = ESP(&sysbus->esp); 1360 uint32_t saddr; 1361 1362 saddr = addr >> sysbus->it_shift; 1363 return esp_reg_read(s, saddr); 1364 } 1365 1366 static const MemoryRegionOps sysbus_esp_mem_ops = { 1367 .read = sysbus_esp_mem_read, 1368 .write = sysbus_esp_mem_write, 1369 .endianness = DEVICE_NATIVE_ENDIAN, 1370 .valid.accepts = esp_mem_accepts, 1371 }; 1372 1373 static void sysbus_esp_pdma_write(void *opaque, hwaddr addr, 1374 uint64_t val, unsigned int size) 1375 { 1376 SysBusESPState *sysbus = opaque; 1377 ESPState *s = ESP(&sysbus->esp); 1378 1379 trace_esp_pdma_write(size); 1380 1381 switch (size) { 1382 case 1: 1383 esp_pdma_write(s, val); 1384 break; 1385 case 2: 1386 esp_pdma_write(s, val >> 8); 1387 esp_pdma_write(s, val); 1388 break; 1389 } 1390 esp_pdma_cb(s); 1391 } 1392 1393 static uint64_t sysbus_esp_pdma_read(void *opaque, hwaddr addr, 1394 unsigned int size) 1395 { 1396 SysBusESPState *sysbus = opaque; 1397 ESPState *s = ESP(&sysbus->esp); 1398 uint64_t val = 0; 1399 1400 trace_esp_pdma_read(size); 1401 1402 switch (size) { 1403 case 1: 1404 val = esp_pdma_read(s); 1405 break; 1406 case 2: 1407 val = esp_pdma_read(s); 1408 val = (val << 8) | esp_pdma_read(s); 1409 break; 1410 } 1411 esp_pdma_cb(s); 1412 return val; 1413 } 1414 1415 static void *esp_load_request(QEMUFile *f, SCSIRequest *req) 1416 { 1417 ESPState *s = container_of(req->bus, ESPState, bus); 1418 1419 scsi_req_ref(req); 1420 s->current_req = req; 1421 return s; 1422 } 1423 1424 static const MemoryRegionOps sysbus_esp_pdma_ops = { 1425 .read = sysbus_esp_pdma_read, 1426 .write = sysbus_esp_pdma_write, 1427 .endianness = DEVICE_NATIVE_ENDIAN, 1428 .valid.min_access_size = 1, 1429 .valid.max_access_size = 4, 1430 .impl.min_access_size = 1, 1431 .impl.max_access_size = 2, 1432 }; 1433 1434 static const struct SCSIBusInfo esp_scsi_info = { 1435 .tcq = false, 1436 .max_target = ESP_MAX_DEVS, 1437 .max_lun = 7, 1438 1439 .load_request = esp_load_request, 1440 .transfer_data = esp_transfer_data, 1441 .complete = esp_command_complete, 1442 .cancel = esp_request_cancelled 1443 }; 1444 1445 static void sysbus_esp_gpio_demux(void *opaque, int irq, int level) 1446 { 1447 SysBusESPState *sysbus = SYSBUS_ESP(opaque); 1448 ESPState *s = ESP(&sysbus->esp); 1449 1450 switch (irq) { 1451 case 0: 1452 parent_esp_reset(s, irq, level); 1453 break; 1454 case 1: 1455 esp_dma_enable(s, irq, level); 1456 break; 1457 } 1458 } 1459 1460 static void sysbus_esp_realize(DeviceState *dev, Error **errp) 1461 { 1462 SysBusDevice *sbd = SYS_BUS_DEVICE(dev); 1463 SysBusESPState *sysbus = SYSBUS_ESP(dev); 1464 ESPState *s = ESP(&sysbus->esp); 1465 1466 if (!qdev_realize(DEVICE(s), NULL, errp)) { 1467 return; 1468 } 1469 1470 sysbus_init_irq(sbd, &s->irq); 1471 sysbus_init_irq(sbd, &s->irq_data); 1472 assert(sysbus->it_shift != -1); 1473 1474 s->chip_id = TCHI_FAS100A; 1475 memory_region_init_io(&sysbus->iomem, OBJECT(sysbus), &sysbus_esp_mem_ops, 1476 sysbus, "esp-regs", ESP_REGS << sysbus->it_shift); 1477 sysbus_init_mmio(sbd, &sysbus->iomem); 1478 memory_region_init_io(&sysbus->pdma, OBJECT(sysbus), &sysbus_esp_pdma_ops, 1479 sysbus, "esp-pdma", 4); 1480 sysbus_init_mmio(sbd, &sysbus->pdma); 1481 1482 qdev_init_gpio_in(dev, sysbus_esp_gpio_demux, 2); 1483 1484 scsi_bus_init(&s->bus, sizeof(s->bus), dev, &esp_scsi_info); 1485 } 1486 1487 static void sysbus_esp_hard_reset(DeviceState *dev) 1488 { 1489 SysBusESPState *sysbus = SYSBUS_ESP(dev); 1490 ESPState *s = ESP(&sysbus->esp); 1491 1492 esp_hard_reset(s); 1493 } 1494 1495 static void sysbus_esp_init(Object *obj) 1496 { 1497 SysBusESPState *sysbus = SYSBUS_ESP(obj); 1498 1499 object_initialize_child(obj, "esp", &sysbus->esp, TYPE_ESP); 1500 } 1501 1502 static const VMStateDescription vmstate_sysbus_esp_scsi = { 1503 .name = "sysbusespscsi", 1504 .version_id = 2, 1505 .minimum_version_id = 1, 1506 .pre_save = esp_pre_save, 1507 .fields = (const VMStateField[]) { 1508 VMSTATE_UINT8_V(esp.mig_version_id, SysBusESPState, 2), 1509 VMSTATE_STRUCT(esp, SysBusESPState, 0, vmstate_esp, ESPState), 1510 VMSTATE_END_OF_LIST() 1511 } 1512 }; 1513 1514 static void sysbus_esp_class_init(ObjectClass *klass, void *data) 1515 { 1516 DeviceClass *dc = DEVICE_CLASS(klass); 1517 1518 dc->realize = sysbus_esp_realize; 1519 dc->reset = sysbus_esp_hard_reset; 1520 dc->vmsd = &vmstate_sysbus_esp_scsi; 1521 set_bit(DEVICE_CATEGORY_STORAGE, dc->categories); 1522 } 1523 1524 static const TypeInfo sysbus_esp_info = { 1525 .name = TYPE_SYSBUS_ESP, 1526 .parent = TYPE_SYS_BUS_DEVICE, 1527 .instance_init = sysbus_esp_init, 1528 .instance_size = sizeof(SysBusESPState), 1529 .class_init = sysbus_esp_class_init, 1530 }; 1531 1532 static void esp_finalize(Object *obj) 1533 { 1534 ESPState *s = ESP(obj); 1535 1536 fifo8_destroy(&s->fifo); 1537 fifo8_destroy(&s->cmdfifo); 1538 } 1539 1540 static void esp_init(Object *obj) 1541 { 1542 ESPState *s = ESP(obj); 1543 1544 fifo8_create(&s->fifo, ESP_FIFO_SZ); 1545 fifo8_create(&s->cmdfifo, ESP_CMDFIFO_SZ); 1546 } 1547 1548 static void esp_class_init(ObjectClass *klass, void *data) 1549 { 1550 DeviceClass *dc = DEVICE_CLASS(klass); 1551 1552 /* internal device for sysbusesp/pciespscsi, not user-creatable */ 1553 dc->user_creatable = false; 1554 set_bit(DEVICE_CATEGORY_STORAGE, dc->categories); 1555 } 1556 1557 static const TypeInfo esp_info = { 1558 .name = TYPE_ESP, 1559 .parent = TYPE_DEVICE, 1560 .instance_init = esp_init, 1561 .instance_finalize = esp_finalize, 1562 .instance_size = sizeof(ESPState), 1563 .class_init = esp_class_init, 1564 }; 1565 1566 static void esp_register_types(void) 1567 { 1568 type_register_static(&sysbus_esp_info); 1569 type_register_static(&esp_info); 1570 } 1571 1572 type_init(esp_register_types) 1573