1 /* 2 * QEMU ESP/NCR53C9x emulation 3 * 4 * Copyright (c) 2005-2006 Fabrice Bellard 5 * Copyright (c) 2012 Herve Poussineau 6 * 7 * Permission is hereby granted, free of charge, to any person obtaining a copy 8 * of this software and associated documentation files (the "Software"), to deal 9 * in the Software without restriction, including without limitation the rights 10 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 11 * copies of the Software, and to permit persons to whom the Software is 12 * furnished to do so, subject to the following conditions: 13 * 14 * The above copyright notice and this permission notice shall be included in 15 * all copies or substantial portions of the Software. 16 * 17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 22 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 23 * THE SOFTWARE. 24 */ 25 26 #include "qemu/osdep.h" 27 #include "hw/sysbus.h" 28 #include "migration/vmstate.h" 29 #include "hw/irq.h" 30 #include "hw/scsi/esp.h" 31 #include "trace.h" 32 #include "qemu/log.h" 33 #include "qemu/module.h" 34 35 /* 36 * On Sparc32, this is the ESP (NCR53C90) part of chip STP2000 (Master I/O), 37 * also produced as NCR89C100. See 38 * http://www.ibiblio.org/pub/historic-linux/early-ports/Sparc/NCR/NCR89C100.txt 39 * and 40 * http://www.ibiblio.org/pub/historic-linux/early-ports/Sparc/NCR/NCR53C9X.txt 41 * 42 * On Macintosh Quadra it is a NCR53C96. 43 */ 44 45 static void esp_raise_irq(ESPState *s) 46 { 47 if (!(s->rregs[ESP_RSTAT] & STAT_INT)) { 48 s->rregs[ESP_RSTAT] |= STAT_INT; 49 qemu_irq_raise(s->irq); 50 trace_esp_raise_irq(); 51 } 52 } 53 54 static void esp_lower_irq(ESPState *s) 55 { 56 if (s->rregs[ESP_RSTAT] & STAT_INT) { 57 s->rregs[ESP_RSTAT] &= ~STAT_INT; 58 qemu_irq_lower(s->irq); 59 trace_esp_lower_irq(); 60 } 61 } 62 63 static void esp_raise_drq(ESPState *s) 64 { 65 qemu_irq_raise(s->irq_data); 66 trace_esp_raise_drq(); 67 } 68 69 static void esp_lower_drq(ESPState *s) 70 { 71 qemu_irq_lower(s->irq_data); 72 trace_esp_lower_drq(); 73 } 74 75 void esp_dma_enable(ESPState *s, int irq, int level) 76 { 77 if (level) { 78 s->dma_enabled = 1; 79 trace_esp_dma_enable(); 80 if (s->dma_cb) { 81 s->dma_cb(s); 82 s->dma_cb = NULL; 83 } 84 } else { 85 trace_esp_dma_disable(); 86 s->dma_enabled = 0; 87 } 88 } 89 90 void esp_request_cancelled(SCSIRequest *req) 91 { 92 ESPState *s = req->hba_private; 93 94 if (req == s->current_req) { 95 scsi_req_unref(s->current_req); 96 s->current_req = NULL; 97 s->current_dev = NULL; 98 s->async_len = 0; 99 } 100 } 101 102 static void esp_fifo_push(Fifo8 *fifo, uint8_t val) 103 { 104 if (fifo8_num_used(fifo) == fifo->capacity) { 105 trace_esp_error_fifo_overrun(); 106 return; 107 } 108 109 fifo8_push(fifo, val); 110 } 111 112 static uint8_t esp_fifo_pop(Fifo8 *fifo) 113 { 114 if (fifo8_is_empty(fifo)) { 115 return 0; 116 } 117 118 return fifo8_pop(fifo); 119 } 120 121 static uint32_t esp_fifo_pop_buf(Fifo8 *fifo, uint8_t *dest, int maxlen) 122 { 123 const uint8_t *buf; 124 uint32_t n, n2; 125 int len; 126 127 if (maxlen == 0) { 128 return 0; 129 } 130 131 len = maxlen; 132 buf = fifo8_pop_buf(fifo, len, &n); 133 if (dest) { 134 memcpy(dest, buf, n); 135 } 136 137 /* Add FIFO wraparound if needed */ 138 len -= n; 139 len = MIN(len, fifo8_num_used(fifo)); 140 if (len) { 141 buf = fifo8_pop_buf(fifo, len, &n2); 142 if (dest) { 143 memcpy(&dest[n], buf, n2); 144 } 145 n += n2; 146 } 147 148 return n; 149 } 150 151 static uint32_t esp_get_tc(ESPState *s) 152 { 153 uint32_t dmalen; 154 155 dmalen = s->rregs[ESP_TCLO]; 156 dmalen |= s->rregs[ESP_TCMID] << 8; 157 dmalen |= s->rregs[ESP_TCHI] << 16; 158 159 return dmalen; 160 } 161 162 static void esp_set_tc(ESPState *s, uint32_t dmalen) 163 { 164 uint32_t old_tc = esp_get_tc(s); 165 166 s->rregs[ESP_TCLO] = dmalen; 167 s->rregs[ESP_TCMID] = dmalen >> 8; 168 s->rregs[ESP_TCHI] = dmalen >> 16; 169 170 if (old_tc && dmalen == 0) { 171 s->rregs[ESP_RSTAT] |= STAT_TC; 172 } 173 } 174 175 static uint32_t esp_get_stc(ESPState *s) 176 { 177 uint32_t dmalen; 178 179 dmalen = s->wregs[ESP_TCLO]; 180 dmalen |= s->wregs[ESP_TCMID] << 8; 181 dmalen |= s->wregs[ESP_TCHI] << 16; 182 183 return dmalen; 184 } 185 186 static const char *esp_phase_names[8] = { 187 "DATA OUT", "DATA IN", "COMMAND", "STATUS", 188 "(reserved)", "(reserved)", "MESSAGE OUT", "MESSAGE IN" 189 }; 190 191 static void esp_set_phase(ESPState *s, uint8_t phase) 192 { 193 s->rregs[ESP_RSTAT] &= ~7; 194 s->rregs[ESP_RSTAT] |= phase; 195 196 trace_esp_set_phase(esp_phase_names[phase]); 197 } 198 199 static uint8_t esp_pdma_read(ESPState *s) 200 { 201 uint8_t val; 202 203 val = esp_fifo_pop(&s->fifo); 204 return val; 205 } 206 207 static void esp_pdma_write(ESPState *s, uint8_t val) 208 { 209 uint32_t dmalen = esp_get_tc(s); 210 211 if (dmalen == 0) { 212 return; 213 } 214 215 esp_fifo_push(&s->fifo, val); 216 217 dmalen--; 218 esp_set_tc(s, dmalen); 219 } 220 221 static void esp_set_pdma_cb(ESPState *s, enum pdma_cb cb) 222 { 223 s->pdma_cb = cb; 224 } 225 226 static int esp_select(ESPState *s) 227 { 228 int target; 229 230 target = s->wregs[ESP_WBUSID] & BUSID_DID; 231 232 s->ti_size = 0; 233 234 if (s->current_req) { 235 /* Started a new command before the old one finished. Cancel it. */ 236 scsi_req_cancel(s->current_req); 237 } 238 239 s->current_dev = scsi_device_find(&s->bus, 0, target, 0); 240 if (!s->current_dev) { 241 /* No such drive */ 242 s->rregs[ESP_RSTAT] = 0; 243 s->rregs[ESP_RINTR] = INTR_DC; 244 s->rregs[ESP_RSEQ] = SEQ_0; 245 esp_raise_irq(s); 246 return -1; 247 } 248 249 /* 250 * Note that we deliberately don't raise the IRQ here: this will be done 251 * either in do_command_phase() for DATA OUT transfers or by the deferred 252 * IRQ mechanism in esp_transfer_data() for DATA IN transfers 253 */ 254 s->rregs[ESP_RINTR] |= INTR_FC; 255 s->rregs[ESP_RSEQ] = SEQ_CD; 256 return 0; 257 } 258 259 static uint32_t get_cmd(ESPState *s, uint32_t maxlen) 260 { 261 uint8_t buf[ESP_CMDFIFO_SZ]; 262 uint32_t dmalen, n; 263 int target; 264 265 target = s->wregs[ESP_WBUSID] & BUSID_DID; 266 if (s->dma) { 267 dmalen = MIN(esp_get_tc(s), maxlen); 268 if (dmalen == 0) { 269 return 0; 270 } 271 if (s->dma_memory_read) { 272 s->dma_memory_read(s->dma_opaque, buf, dmalen); 273 dmalen = MIN(fifo8_num_free(&s->cmdfifo), dmalen); 274 fifo8_push_all(&s->cmdfifo, buf, dmalen); 275 esp_set_tc(s, esp_get_tc(s) - dmalen); 276 } else { 277 return 0; 278 } 279 } else { 280 dmalen = MIN(fifo8_num_used(&s->fifo), maxlen); 281 if (dmalen == 0) { 282 return 0; 283 } 284 n = esp_fifo_pop_buf(&s->fifo, buf, dmalen); 285 n = MIN(fifo8_num_free(&s->cmdfifo), n); 286 fifo8_push_all(&s->cmdfifo, buf, n); 287 } 288 trace_esp_get_cmd(dmalen, target); 289 290 return dmalen; 291 } 292 293 static void do_command_phase(ESPState *s) 294 { 295 uint32_t cmdlen; 296 int32_t datalen; 297 SCSIDevice *current_lun; 298 uint8_t buf[ESP_CMDFIFO_SZ]; 299 300 trace_esp_do_command_phase(s->lun); 301 cmdlen = fifo8_num_used(&s->cmdfifo); 302 if (!cmdlen || !s->current_dev) { 303 return; 304 } 305 esp_fifo_pop_buf(&s->cmdfifo, buf, cmdlen); 306 307 current_lun = scsi_device_find(&s->bus, 0, s->current_dev->id, s->lun); 308 if (!current_lun) { 309 /* No such drive */ 310 s->rregs[ESP_RSTAT] = 0; 311 s->rregs[ESP_RINTR] = INTR_DC; 312 s->rregs[ESP_RSEQ] = SEQ_0; 313 esp_raise_irq(s); 314 return; 315 } 316 317 s->current_req = scsi_req_new(current_lun, 0, s->lun, buf, cmdlen, s); 318 datalen = scsi_req_enqueue(s->current_req); 319 s->ti_size = datalen; 320 fifo8_reset(&s->cmdfifo); 321 if (datalen != 0) { 322 s->ti_cmd = 0; 323 if (datalen > 0) { 324 /* 325 * Switch to DATA IN phase but wait until initial data xfer is 326 * complete before raising the command completion interrupt 327 */ 328 s->data_in_ready = false; 329 esp_set_phase(s, STAT_DI); 330 } else { 331 esp_set_phase(s, STAT_DO); 332 s->rregs[ESP_RINTR] |= INTR_BS | INTR_FC; 333 esp_raise_irq(s); 334 esp_lower_drq(s); 335 } 336 scsi_req_continue(s->current_req); 337 return; 338 } 339 } 340 341 static void do_message_phase(ESPState *s) 342 { 343 if (s->cmdfifo_cdb_offset) { 344 uint8_t message = esp_fifo_pop(&s->cmdfifo); 345 346 trace_esp_do_identify(message); 347 s->lun = message & 7; 348 s->cmdfifo_cdb_offset--; 349 } 350 351 /* Ignore extended messages for now */ 352 if (s->cmdfifo_cdb_offset) { 353 int len = MIN(s->cmdfifo_cdb_offset, fifo8_num_used(&s->cmdfifo)); 354 esp_fifo_pop_buf(&s->cmdfifo, NULL, len); 355 s->cmdfifo_cdb_offset = 0; 356 } 357 } 358 359 static void do_cmd(ESPState *s) 360 { 361 do_message_phase(s); 362 assert(s->cmdfifo_cdb_offset == 0); 363 do_command_phase(s); 364 } 365 366 static void satn_pdma_cb(ESPState *s) 367 { 368 uint8_t buf[ESP_FIFO_SZ]; 369 int n; 370 371 /* Copy FIFO into cmdfifo */ 372 n = esp_fifo_pop_buf(&s->fifo, buf, fifo8_num_used(&s->fifo)); 373 n = MIN(fifo8_num_free(&s->cmdfifo), n); 374 fifo8_push_all(&s->cmdfifo, buf, n); 375 376 if (!esp_get_tc(s) && !fifo8_is_empty(&s->cmdfifo)) { 377 s->cmdfifo_cdb_offset = 1; 378 s->do_cmd = 0; 379 do_cmd(s); 380 } 381 } 382 383 static void handle_satn(ESPState *s) 384 { 385 int32_t cmdlen; 386 387 if (s->dma && !s->dma_enabled) { 388 s->dma_cb = handle_satn; 389 return; 390 } 391 esp_set_pdma_cb(s, SATN_PDMA_CB); 392 if (esp_select(s) < 0) { 393 return; 394 } 395 cmdlen = get_cmd(s, ESP_CMDFIFO_SZ); 396 if (cmdlen > 0) { 397 s->cmdfifo_cdb_offset = 1; 398 s->do_cmd = 0; 399 do_cmd(s); 400 } else if (cmdlen == 0) { 401 if (s->dma) { 402 esp_raise_drq(s); 403 } 404 s->do_cmd = 1; 405 /* Target present, but no cmd yet - switch to command phase */ 406 s->rregs[ESP_RSEQ] = SEQ_CD; 407 esp_set_phase(s, STAT_CD); 408 } 409 } 410 411 static void s_without_satn_pdma_cb(ESPState *s) 412 { 413 uint8_t buf[ESP_FIFO_SZ]; 414 int n; 415 416 /* Copy FIFO into cmdfifo */ 417 n = esp_fifo_pop_buf(&s->fifo, buf, fifo8_num_used(&s->fifo)); 418 n = MIN(fifo8_num_free(&s->cmdfifo), n); 419 fifo8_push_all(&s->cmdfifo, buf, n); 420 421 if (!esp_get_tc(s) && !fifo8_is_empty(&s->cmdfifo)) { 422 s->cmdfifo_cdb_offset = 0; 423 s->do_cmd = 0; 424 do_cmd(s); 425 } 426 } 427 428 static void handle_s_without_atn(ESPState *s) 429 { 430 int32_t cmdlen; 431 432 if (s->dma && !s->dma_enabled) { 433 s->dma_cb = handle_s_without_atn; 434 return; 435 } 436 esp_set_pdma_cb(s, S_WITHOUT_SATN_PDMA_CB); 437 if (esp_select(s) < 0) { 438 return; 439 } 440 cmdlen = get_cmd(s, ESP_CMDFIFO_SZ); 441 if (cmdlen > 0) { 442 s->cmdfifo_cdb_offset = 0; 443 s->do_cmd = 0; 444 do_cmd(s); 445 } else if (cmdlen == 0) { 446 if (s->dma) { 447 esp_raise_drq(s); 448 } 449 s->do_cmd = 1; 450 /* Target present, but no cmd yet - switch to command phase */ 451 s->rregs[ESP_RSEQ] = SEQ_CD; 452 esp_set_phase(s, STAT_CD); 453 } 454 } 455 456 static void satn_stop_pdma_cb(ESPState *s) 457 { 458 uint8_t buf[ESP_FIFO_SZ]; 459 int n; 460 461 /* Copy FIFO into cmdfifo */ 462 n = esp_fifo_pop_buf(&s->fifo, buf, fifo8_num_used(&s->fifo)); 463 n = MIN(fifo8_num_free(&s->cmdfifo), n); 464 fifo8_push_all(&s->cmdfifo, buf, n); 465 466 if (!esp_get_tc(s) && !fifo8_is_empty(&s->cmdfifo)) { 467 trace_esp_handle_satn_stop(fifo8_num_used(&s->cmdfifo)); 468 s->do_cmd = 1; 469 s->cmdfifo_cdb_offset = 1; 470 esp_set_phase(s, STAT_CD); 471 s->rregs[ESP_RSTAT] |= STAT_TC; 472 s->rregs[ESP_RINTR] |= INTR_BS | INTR_FC; 473 s->rregs[ESP_RSEQ] = SEQ_CD; 474 esp_raise_irq(s); 475 } 476 } 477 478 static void handle_satn_stop(ESPState *s) 479 { 480 int32_t cmdlen; 481 482 if (s->dma && !s->dma_enabled) { 483 s->dma_cb = handle_satn_stop; 484 return; 485 } 486 esp_set_pdma_cb(s, SATN_STOP_PDMA_CB); 487 if (esp_select(s) < 0) { 488 return; 489 } 490 cmdlen = get_cmd(s, 1); 491 if (cmdlen > 0) { 492 trace_esp_handle_satn_stop(fifo8_num_used(&s->cmdfifo)); 493 s->do_cmd = 1; 494 s->cmdfifo_cdb_offset = 1; 495 esp_set_phase(s, STAT_MO); 496 s->rregs[ESP_RINTR] |= INTR_BS | INTR_FC; 497 s->rregs[ESP_RSEQ] = SEQ_MO; 498 esp_raise_irq(s); 499 } else if (cmdlen == 0) { 500 if (s->dma) { 501 esp_raise_drq(s); 502 } 503 s->do_cmd = 1; 504 /* Target present, switch to message out phase */ 505 s->rregs[ESP_RSEQ] = SEQ_MO; 506 esp_set_phase(s, STAT_MO); 507 } 508 } 509 510 static void write_response_pdma_cb(ESPState *s) 511 { 512 esp_set_phase(s, STAT_ST); 513 s->rregs[ESP_RINTR] |= INTR_BS | INTR_FC; 514 s->rregs[ESP_RSEQ] = SEQ_CD; 515 esp_raise_irq(s); 516 } 517 518 static void write_response(ESPState *s) 519 { 520 uint8_t buf[2]; 521 522 trace_esp_write_response(s->status); 523 524 buf[0] = s->status; 525 buf[1] = 0; 526 527 if (s->dma) { 528 if (s->dma_memory_write) { 529 s->dma_memory_write(s->dma_opaque, buf, 2); 530 esp_set_phase(s, STAT_ST); 531 s->rregs[ESP_RINTR] |= INTR_BS | INTR_FC; 532 s->rregs[ESP_RSEQ] = SEQ_CD; 533 } else { 534 esp_set_pdma_cb(s, WRITE_RESPONSE_PDMA_CB); 535 esp_raise_drq(s); 536 return; 537 } 538 } else { 539 fifo8_reset(&s->fifo); 540 fifo8_push_all(&s->fifo, buf, 2); 541 s->rregs[ESP_RFLAGS] = 2; 542 } 543 esp_raise_irq(s); 544 } 545 546 static void esp_dma_ti_check(ESPState *s) 547 { 548 if (esp_get_tc(s) == 0 && fifo8_num_used(&s->fifo) < 2) { 549 s->rregs[ESP_RINTR] |= INTR_BS; 550 esp_raise_irq(s); 551 esp_lower_drq(s); 552 } 553 } 554 555 static void do_dma_pdma_cb(ESPState *s) 556 { 557 int to_device = ((s->rregs[ESP_RSTAT] & 7) == STAT_DO); 558 uint8_t buf[ESP_CMDFIFO_SZ]; 559 int len; 560 uint32_t n; 561 562 if (s->do_cmd) { 563 /* Copy FIFO into cmdfifo */ 564 n = esp_fifo_pop_buf(&s->fifo, buf, fifo8_num_used(&s->fifo)); 565 n = MIN(fifo8_num_free(&s->cmdfifo), n); 566 fifo8_push_all(&s->cmdfifo, buf, n); 567 568 /* Ensure we have received complete command after SATN and stop */ 569 if (esp_get_tc(s) || fifo8_is_empty(&s->cmdfifo)) { 570 return; 571 } 572 573 s->ti_size = 0; 574 if ((s->rregs[ESP_RSTAT] & 7) == STAT_CD) { 575 /* No command received */ 576 if (s->cmdfifo_cdb_offset == fifo8_num_used(&s->cmdfifo)) { 577 return; 578 } 579 580 /* Command has been received */ 581 s->do_cmd = 0; 582 do_cmd(s); 583 } else { 584 /* 585 * Extra message out bytes received: update cmdfifo_cdb_offset 586 * and then switch to command phase 587 */ 588 s->cmdfifo_cdb_offset = fifo8_num_used(&s->cmdfifo); 589 esp_set_phase(s, STAT_CD); 590 s->rregs[ESP_RSEQ] = SEQ_CD; 591 s->rregs[ESP_RINTR] |= INTR_BS; 592 esp_raise_irq(s); 593 } 594 return; 595 } 596 597 if (!s->current_req) { 598 return; 599 } 600 601 if (to_device) { 602 /* Copy FIFO data to device */ 603 len = MIN(s->async_len, ESP_FIFO_SZ); 604 len = MIN(len, fifo8_num_used(&s->fifo)); 605 n = esp_fifo_pop_buf(&s->fifo, s->async_buf, len); 606 s->async_buf += n; 607 s->async_len -= n; 608 s->ti_size += n; 609 610 if (s->async_len == 0 && fifo8_num_used(&s->fifo) < 2) { 611 /* Defer until the scsi layer has completed */ 612 scsi_req_continue(s->current_req); 613 return; 614 } 615 616 esp_dma_ti_check(s); 617 } else { 618 if (s->async_len == 0 && fifo8_num_used(&s->fifo) < 2) { 619 /* Defer until the scsi layer has completed */ 620 scsi_req_continue(s->current_req); 621 s->data_in_ready = false; 622 return; 623 } 624 625 esp_dma_ti_check(s); 626 627 /* Copy device data to FIFO */ 628 len = MIN(s->async_len, esp_get_tc(s)); 629 len = MIN(len, fifo8_num_free(&s->fifo)); 630 fifo8_push_all(&s->fifo, s->async_buf, len); 631 s->async_buf += len; 632 s->async_len -= len; 633 s->ti_size -= len; 634 esp_set_tc(s, esp_get_tc(s) - len); 635 } 636 } 637 638 static void esp_do_dma(ESPState *s) 639 { 640 uint32_t len, cmdlen; 641 int to_device = ((s->rregs[ESP_RSTAT] & 7) == STAT_DO); 642 uint8_t buf[ESP_CMDFIFO_SZ]; 643 int n; 644 645 len = esp_get_tc(s); 646 if (s->do_cmd) { 647 /* 648 * handle_ti_cmd() case: esp_do_dma() is called only from 649 * handle_ti_cmd() with do_cmd != NULL (see the assert()) 650 */ 651 cmdlen = fifo8_num_used(&s->cmdfifo); 652 trace_esp_do_dma(cmdlen, len); 653 if (s->dma_memory_read) { 654 len = MIN(len, fifo8_num_free(&s->cmdfifo)); 655 s->dma_memory_read(s->dma_opaque, buf, len); 656 fifo8_push_all(&s->cmdfifo, buf, len); 657 esp_set_tc(s, esp_get_tc(s) - len); 658 } else { 659 n = esp_fifo_pop_buf(&s->fifo, buf, fifo8_num_used(&s->fifo)); 660 n = MIN(fifo8_num_free(&s->cmdfifo), n); 661 fifo8_push_all(&s->cmdfifo, buf, n); 662 esp_set_tc(s, esp_get_tc(s) - n); 663 664 esp_set_pdma_cb(s, DO_DMA_PDMA_CB); 665 esp_raise_drq(s); 666 667 /* Ensure we have received complete command after SATN and stop */ 668 if (esp_get_tc(s) || fifo8_is_empty(&s->cmdfifo)) { 669 return; 670 } 671 } 672 trace_esp_handle_ti_cmd(cmdlen); 673 s->ti_size = 0; 674 if ((s->rregs[ESP_RSTAT] & 7) == STAT_CD) { 675 /* No command received */ 676 if (s->cmdfifo_cdb_offset == fifo8_num_used(&s->cmdfifo)) { 677 return; 678 } 679 680 /* Command has been received */ 681 s->do_cmd = 0; 682 do_cmd(s); 683 } else { 684 /* 685 * Extra message out bytes received: update cmdfifo_cdb_offset 686 * and then switch to command phase 687 */ 688 s->cmdfifo_cdb_offset = fifo8_num_used(&s->cmdfifo); 689 esp_set_phase(s, STAT_CD); 690 s->rregs[ESP_RSEQ] = SEQ_CD; 691 s->rregs[ESP_RINTR] |= INTR_BS; 692 esp_raise_irq(s); 693 } 694 return; 695 } 696 if (!s->current_req) { 697 return; 698 } 699 if (s->async_len == 0) { 700 /* Defer until data is available. */ 701 return; 702 } 703 if (len > s->async_len) { 704 len = s->async_len; 705 } 706 if (to_device) { 707 if (s->dma_memory_read) { 708 s->dma_memory_read(s->dma_opaque, s->async_buf, len); 709 710 esp_set_tc(s, esp_get_tc(s) - len); 711 s->async_buf += len; 712 s->async_len -= len; 713 s->ti_size += len; 714 715 if (s->async_len == 0 && fifo8_num_used(&s->fifo) < 2) { 716 /* Defer until the scsi layer has completed */ 717 scsi_req_continue(s->current_req); 718 return; 719 } 720 721 esp_dma_ti_check(s); 722 } else { 723 /* Copy FIFO data to device */ 724 len = MIN(s->async_len, ESP_FIFO_SZ); 725 len = MIN(len, fifo8_num_used(&s->fifo)); 726 n = esp_fifo_pop_buf(&s->fifo, s->async_buf, len); 727 s->async_buf += n; 728 s->async_len -= n; 729 s->ti_size += n; 730 731 esp_set_pdma_cb(s, DO_DMA_PDMA_CB); 732 esp_raise_drq(s); 733 734 if (s->async_len == 0 && fifo8_num_used(&s->fifo) < 2) { 735 /* Defer until the scsi layer has completed */ 736 scsi_req_continue(s->current_req); 737 return; 738 } 739 740 esp_dma_ti_check(s); 741 } 742 } else { 743 if (s->dma_memory_write) { 744 s->dma_memory_write(s->dma_opaque, s->async_buf, len); 745 746 esp_set_tc(s, esp_get_tc(s) - len); 747 s->async_buf += len; 748 s->async_len -= len; 749 s->ti_size -= len; 750 751 if (s->async_len == 0 && fifo8_num_used(&s->fifo) < 2) { 752 /* Defer until the scsi layer has completed */ 753 scsi_req_continue(s->current_req); 754 return; 755 } 756 757 esp_dma_ti_check(s); 758 } else { 759 /* Copy device data to FIFO */ 760 len = MIN(len, fifo8_num_free(&s->fifo)); 761 fifo8_push_all(&s->fifo, s->async_buf, len); 762 s->async_buf += len; 763 s->async_len -= len; 764 s->ti_size -= len; 765 esp_set_tc(s, esp_get_tc(s) - len); 766 esp_set_pdma_cb(s, DO_DMA_PDMA_CB); 767 esp_raise_drq(s); 768 769 if (s->async_len == 0 && fifo8_num_used(&s->fifo) < 2) { 770 /* Defer until the scsi layer has completed */ 771 scsi_req_continue(s->current_req); 772 return; 773 } 774 775 esp_dma_ti_check(s); 776 } 777 } 778 } 779 780 static void esp_do_nodma(ESPState *s) 781 { 782 int to_device = ((s->rregs[ESP_RSTAT] & 7) == STAT_DO); 783 uint8_t buf[ESP_FIFO_SZ]; 784 uint32_t cmdlen; 785 int len, n; 786 787 if (s->do_cmd) { 788 /* Copy FIFO into cmdfifo */ 789 n = esp_fifo_pop_buf(&s->fifo, buf, fifo8_num_used(&s->fifo)); 790 n = MIN(fifo8_num_free(&s->cmdfifo), n); 791 fifo8_push_all(&s->cmdfifo, buf, n); 792 793 cmdlen = fifo8_num_used(&s->cmdfifo); 794 trace_esp_handle_ti_cmd(cmdlen); 795 s->ti_size = 0; 796 if ((s->rregs[ESP_RSTAT] & 7) == STAT_CD) { 797 /* No command received */ 798 if (s->cmdfifo_cdb_offset == fifo8_num_used(&s->cmdfifo)) { 799 return; 800 } 801 802 /* Command has been received */ 803 s->do_cmd = 0; 804 do_cmd(s); 805 } else { 806 /* 807 * Extra message out bytes received: update cmdfifo_cdb_offset 808 * and then switch to command phase 809 */ 810 s->cmdfifo_cdb_offset = fifo8_num_used(&s->cmdfifo); 811 esp_set_phase(s, STAT_CD); 812 s->rregs[ESP_RSEQ] = SEQ_CD; 813 s->rregs[ESP_RINTR] |= INTR_BS; 814 esp_raise_irq(s); 815 } 816 return; 817 } 818 819 if (!s->current_req) { 820 return; 821 } 822 823 if (s->async_len == 0) { 824 /* Defer until data is available. */ 825 return; 826 } 827 828 if (to_device) { 829 len = MIN(s->async_len, ESP_FIFO_SZ); 830 len = MIN(len, fifo8_num_used(&s->fifo)); 831 esp_fifo_pop_buf(&s->fifo, s->async_buf, len); 832 s->async_buf += len; 833 s->async_len -= len; 834 s->ti_size += len; 835 } else { 836 if (fifo8_is_empty(&s->fifo)) { 837 fifo8_push(&s->fifo, s->async_buf[0]); 838 s->async_buf++; 839 s->async_len--; 840 s->ti_size--; 841 } 842 } 843 844 if (s->async_len == 0) { 845 scsi_req_continue(s->current_req); 846 return; 847 } 848 849 s->rregs[ESP_RINTR] |= INTR_BS; 850 esp_raise_irq(s); 851 } 852 853 static void esp_pdma_cb(ESPState *s) 854 { 855 switch (s->pdma_cb) { 856 case SATN_PDMA_CB: 857 satn_pdma_cb(s); 858 break; 859 case S_WITHOUT_SATN_PDMA_CB: 860 s_without_satn_pdma_cb(s); 861 break; 862 case SATN_STOP_PDMA_CB: 863 satn_stop_pdma_cb(s); 864 break; 865 case WRITE_RESPONSE_PDMA_CB: 866 write_response_pdma_cb(s); 867 break; 868 case DO_DMA_PDMA_CB: 869 do_dma_pdma_cb(s); 870 break; 871 default: 872 g_assert_not_reached(); 873 } 874 } 875 876 void esp_command_complete(SCSIRequest *req, size_t resid) 877 { 878 ESPState *s = req->hba_private; 879 int to_device = ((s->rregs[ESP_RSTAT] & 7) == STAT_DO); 880 881 trace_esp_command_complete(); 882 883 /* 884 * Non-DMA transfers from the target will leave the last byte in 885 * the FIFO so don't reset ti_size in this case 886 */ 887 if (s->dma || to_device) { 888 if (s->ti_size != 0) { 889 trace_esp_command_complete_unexpected(); 890 } 891 } 892 893 s->async_len = 0; 894 if (req->status) { 895 trace_esp_command_complete_fail(); 896 } 897 s->status = req->status; 898 899 /* 900 * Switch to status phase. For non-DMA transfers from the target the last 901 * byte is still in the FIFO 902 */ 903 esp_set_phase(s, STAT_ST); 904 if (s->ti_size == 0) { 905 /* 906 * Transfer complete: force TC to zero just in case a TI command was 907 * requested for more data than the command returns (Solaris 8 does 908 * this) 909 */ 910 esp_set_tc(s, 0); 911 esp_dma_ti_check(s); 912 } else { 913 /* 914 * Transfer truncated: raise INTR_BS to indicate early change of 915 * phase 916 */ 917 s->rregs[ESP_RINTR] |= INTR_BS; 918 esp_raise_irq(s); 919 s->ti_size = 0; 920 } 921 922 if (s->current_req) { 923 scsi_req_unref(s->current_req); 924 s->current_req = NULL; 925 s->current_dev = NULL; 926 } 927 } 928 929 void esp_transfer_data(SCSIRequest *req, uint32_t len) 930 { 931 ESPState *s = req->hba_private; 932 int to_device = ((s->rregs[ESP_RSTAT] & 7) == STAT_DO); 933 uint32_t dmalen = esp_get_tc(s); 934 935 assert(!s->do_cmd); 936 trace_esp_transfer_data(dmalen, s->ti_size); 937 s->async_len = len; 938 s->async_buf = scsi_req_get_buf(req); 939 940 if (!to_device && !s->data_in_ready) { 941 /* 942 * Initial incoming data xfer is complete so raise command 943 * completion interrupt 944 */ 945 s->data_in_ready = true; 946 s->rregs[ESP_RINTR] |= INTR_BS; 947 esp_raise_irq(s); 948 } 949 950 /* 951 * Always perform the initial transfer upon reception of the next TI 952 * command to ensure the DMA/non-DMA status of the command is correct. 953 * It is not possible to use s->dma directly in the section below as 954 * some OSs send non-DMA NOP commands after a DMA transfer. Hence if the 955 * async data transfer is delayed then s->dma is set incorrectly. 956 */ 957 958 if (s->ti_cmd == (CMD_TI | CMD_DMA)) { 959 /* When the SCSI layer returns more data, raise deferred INTR_BS */ 960 esp_dma_ti_check(s); 961 962 esp_do_dma(s); 963 } else if (s->ti_cmd == CMD_TI) { 964 esp_do_nodma(s); 965 } 966 } 967 968 static void handle_ti(ESPState *s) 969 { 970 uint32_t dmalen; 971 972 if (s->dma && !s->dma_enabled) { 973 s->dma_cb = handle_ti; 974 return; 975 } 976 977 s->ti_cmd = s->rregs[ESP_CMD]; 978 if (s->dma) { 979 dmalen = esp_get_tc(s); 980 trace_esp_handle_ti(dmalen); 981 esp_do_dma(s); 982 } else { 983 trace_esp_handle_ti(s->ti_size); 984 esp_do_nodma(s); 985 } 986 } 987 988 void esp_hard_reset(ESPState *s) 989 { 990 memset(s->rregs, 0, ESP_REGS); 991 memset(s->wregs, 0, ESP_REGS); 992 s->tchi_written = 0; 993 s->ti_size = 0; 994 s->async_len = 0; 995 fifo8_reset(&s->fifo); 996 fifo8_reset(&s->cmdfifo); 997 s->dma = 0; 998 s->do_cmd = 0; 999 s->dma_cb = NULL; 1000 1001 s->rregs[ESP_CFG1] = 7; 1002 } 1003 1004 static void esp_soft_reset(ESPState *s) 1005 { 1006 qemu_irq_lower(s->irq); 1007 qemu_irq_lower(s->irq_data); 1008 esp_hard_reset(s); 1009 } 1010 1011 static void esp_bus_reset(ESPState *s) 1012 { 1013 bus_cold_reset(BUS(&s->bus)); 1014 } 1015 1016 static void parent_esp_reset(ESPState *s, int irq, int level) 1017 { 1018 if (level) { 1019 esp_soft_reset(s); 1020 } 1021 } 1022 1023 static void esp_run_cmd(ESPState *s) 1024 { 1025 uint8_t cmd = s->rregs[ESP_CMD]; 1026 1027 if (cmd & CMD_DMA) { 1028 s->dma = 1; 1029 /* Reload DMA counter. */ 1030 if (esp_get_stc(s) == 0) { 1031 esp_set_tc(s, 0x10000); 1032 } else { 1033 esp_set_tc(s, esp_get_stc(s)); 1034 } 1035 } else { 1036 s->dma = 0; 1037 } 1038 switch (cmd & CMD_CMD) { 1039 case CMD_NOP: 1040 trace_esp_mem_writeb_cmd_nop(cmd); 1041 break; 1042 case CMD_FLUSH: 1043 trace_esp_mem_writeb_cmd_flush(cmd); 1044 fifo8_reset(&s->fifo); 1045 break; 1046 case CMD_RESET: 1047 trace_esp_mem_writeb_cmd_reset(cmd); 1048 esp_soft_reset(s); 1049 break; 1050 case CMD_BUSRESET: 1051 trace_esp_mem_writeb_cmd_bus_reset(cmd); 1052 esp_bus_reset(s); 1053 if (!(s->wregs[ESP_CFG1] & CFG1_RESREPT)) { 1054 s->rregs[ESP_RINTR] |= INTR_RST; 1055 esp_raise_irq(s); 1056 } 1057 break; 1058 case CMD_TI: 1059 trace_esp_mem_writeb_cmd_ti(cmd); 1060 handle_ti(s); 1061 break; 1062 case CMD_ICCS: 1063 trace_esp_mem_writeb_cmd_iccs(cmd); 1064 write_response(s); 1065 s->rregs[ESP_RINTR] |= INTR_FC; 1066 esp_set_phase(s, STAT_MI); 1067 break; 1068 case CMD_MSGACC: 1069 trace_esp_mem_writeb_cmd_msgacc(cmd); 1070 s->rregs[ESP_RINTR] |= INTR_DC; 1071 s->rregs[ESP_RSEQ] = 0; 1072 s->rregs[ESP_RFLAGS] = 0; 1073 esp_raise_irq(s); 1074 break; 1075 case CMD_PAD: 1076 trace_esp_mem_writeb_cmd_pad(cmd); 1077 s->rregs[ESP_RSTAT] = STAT_TC; 1078 s->rregs[ESP_RINTR] |= INTR_FC; 1079 s->rregs[ESP_RSEQ] = 0; 1080 break; 1081 case CMD_SATN: 1082 trace_esp_mem_writeb_cmd_satn(cmd); 1083 break; 1084 case CMD_RSTATN: 1085 trace_esp_mem_writeb_cmd_rstatn(cmd); 1086 break; 1087 case CMD_SEL: 1088 trace_esp_mem_writeb_cmd_sel(cmd); 1089 handle_s_without_atn(s); 1090 break; 1091 case CMD_SELATN: 1092 trace_esp_mem_writeb_cmd_selatn(cmd); 1093 handle_satn(s); 1094 break; 1095 case CMD_SELATNS: 1096 trace_esp_mem_writeb_cmd_selatns(cmd); 1097 handle_satn_stop(s); 1098 break; 1099 case CMD_ENSEL: 1100 trace_esp_mem_writeb_cmd_ensel(cmd); 1101 s->rregs[ESP_RINTR] = 0; 1102 break; 1103 case CMD_DISSEL: 1104 trace_esp_mem_writeb_cmd_dissel(cmd); 1105 s->rregs[ESP_RINTR] = 0; 1106 esp_raise_irq(s); 1107 break; 1108 default: 1109 trace_esp_error_unhandled_command(cmd); 1110 break; 1111 } 1112 } 1113 1114 uint64_t esp_reg_read(ESPState *s, uint32_t saddr) 1115 { 1116 uint32_t val; 1117 1118 switch (saddr) { 1119 case ESP_FIFO: 1120 if (s->dma_memory_read && s->dma_memory_write && 1121 (s->rregs[ESP_RSTAT] & STAT_PIO_MASK) == 0) { 1122 /* Data out. */ 1123 qemu_log_mask(LOG_UNIMP, "esp: PIO data read not implemented\n"); 1124 s->rregs[ESP_FIFO] = 0; 1125 } else { 1126 if ((s->rregs[ESP_RSTAT] & 0x7) == STAT_DI) { 1127 if (s->ti_size) { 1128 esp_do_nodma(s); 1129 } else { 1130 /* 1131 * The last byte of a non-DMA transfer has been read out 1132 * of the FIFO so switch to status phase 1133 */ 1134 esp_set_phase(s, STAT_ST); 1135 } 1136 } 1137 s->rregs[ESP_FIFO] = esp_fifo_pop(&s->fifo); 1138 } 1139 val = s->rregs[ESP_FIFO]; 1140 break; 1141 case ESP_RINTR: 1142 /* 1143 * Clear sequence step, interrupt register and all status bits 1144 * except TC 1145 */ 1146 val = s->rregs[ESP_RINTR]; 1147 s->rregs[ESP_RINTR] = 0; 1148 s->rregs[ESP_RSTAT] &= ~STAT_TC; 1149 /* 1150 * According to the datasheet ESP_RSEQ should be cleared, but as the 1151 * emulation currently defers information transfers to the next TI 1152 * command leave it for now so that pedantic guests such as the old 1153 * Linux 2.6 driver see the correct flags before the next SCSI phase 1154 * transition. 1155 * 1156 * s->rregs[ESP_RSEQ] = SEQ_0; 1157 */ 1158 esp_lower_irq(s); 1159 break; 1160 case ESP_TCHI: 1161 /* Return the unique id if the value has never been written */ 1162 if (!s->tchi_written) { 1163 val = s->chip_id; 1164 } else { 1165 val = s->rregs[saddr]; 1166 } 1167 break; 1168 case ESP_RFLAGS: 1169 /* Bottom 5 bits indicate number of bytes in FIFO */ 1170 val = fifo8_num_used(&s->fifo); 1171 break; 1172 default: 1173 val = s->rregs[saddr]; 1174 break; 1175 } 1176 1177 trace_esp_mem_readb(saddr, val); 1178 return val; 1179 } 1180 1181 void esp_reg_write(ESPState *s, uint32_t saddr, uint64_t val) 1182 { 1183 trace_esp_mem_writeb(saddr, s->wregs[saddr], val); 1184 switch (saddr) { 1185 case ESP_TCHI: 1186 s->tchi_written = true; 1187 /* fall through */ 1188 case ESP_TCLO: 1189 case ESP_TCMID: 1190 s->rregs[ESP_RSTAT] &= ~STAT_TC; 1191 break; 1192 case ESP_FIFO: 1193 if (s->do_cmd) { 1194 if (!fifo8_is_full(&s->fifo)) { 1195 esp_fifo_push(&s->fifo, val); 1196 esp_fifo_push(&s->cmdfifo, fifo8_pop(&s->fifo)); 1197 } 1198 1199 /* 1200 * If any unexpected message out/command phase data is 1201 * transferred using non-DMA, raise the interrupt 1202 */ 1203 if (s->rregs[ESP_CMD] == CMD_TI) { 1204 s->rregs[ESP_RINTR] |= INTR_BS; 1205 esp_raise_irq(s); 1206 } 1207 } else { 1208 esp_fifo_push(&s->fifo, val); 1209 } 1210 break; 1211 case ESP_CMD: 1212 s->rregs[saddr] = val; 1213 esp_run_cmd(s); 1214 break; 1215 case ESP_WBUSID ... ESP_WSYNO: 1216 break; 1217 case ESP_CFG1: 1218 case ESP_CFG2: case ESP_CFG3: 1219 case ESP_RES3: case ESP_RES4: 1220 s->rregs[saddr] = val; 1221 break; 1222 case ESP_WCCF ... ESP_WTEST: 1223 break; 1224 default: 1225 trace_esp_error_invalid_write(val, saddr); 1226 return; 1227 } 1228 s->wregs[saddr] = val; 1229 } 1230 1231 static bool esp_mem_accepts(void *opaque, hwaddr addr, 1232 unsigned size, bool is_write, 1233 MemTxAttrs attrs) 1234 { 1235 return (size == 1) || (is_write && size == 4); 1236 } 1237 1238 static bool esp_is_before_version_5(void *opaque, int version_id) 1239 { 1240 ESPState *s = ESP(opaque); 1241 1242 version_id = MIN(version_id, s->mig_version_id); 1243 return version_id < 5; 1244 } 1245 1246 static bool esp_is_version_5(void *opaque, int version_id) 1247 { 1248 ESPState *s = ESP(opaque); 1249 1250 version_id = MIN(version_id, s->mig_version_id); 1251 return version_id >= 5; 1252 } 1253 1254 static bool esp_is_version_6(void *opaque, int version_id) 1255 { 1256 ESPState *s = ESP(opaque); 1257 1258 version_id = MIN(version_id, s->mig_version_id); 1259 return version_id >= 6; 1260 } 1261 1262 int esp_pre_save(void *opaque) 1263 { 1264 ESPState *s = ESP(object_resolve_path_component( 1265 OBJECT(opaque), "esp")); 1266 1267 s->mig_version_id = vmstate_esp.version_id; 1268 return 0; 1269 } 1270 1271 static int esp_post_load(void *opaque, int version_id) 1272 { 1273 ESPState *s = ESP(opaque); 1274 int len, i; 1275 1276 version_id = MIN(version_id, s->mig_version_id); 1277 1278 if (version_id < 5) { 1279 esp_set_tc(s, s->mig_dma_left); 1280 1281 /* Migrate ti_buf to fifo */ 1282 len = s->mig_ti_wptr - s->mig_ti_rptr; 1283 for (i = 0; i < len; i++) { 1284 fifo8_push(&s->fifo, s->mig_ti_buf[i]); 1285 } 1286 1287 /* Migrate cmdbuf to cmdfifo */ 1288 for (i = 0; i < s->mig_cmdlen; i++) { 1289 fifo8_push(&s->cmdfifo, s->mig_cmdbuf[i]); 1290 } 1291 } 1292 1293 s->mig_version_id = vmstate_esp.version_id; 1294 return 0; 1295 } 1296 1297 /* 1298 * PDMA (or pseudo-DMA) is only used on the Macintosh and requires the 1299 * guest CPU to perform the transfers between the SCSI bus and memory 1300 * itself. This is indicated by the dma_memory_read and dma_memory_write 1301 * functions being NULL (in contrast to the ESP PCI device) whilst 1302 * dma_enabled is still set. 1303 */ 1304 1305 static bool esp_pdma_needed(void *opaque) 1306 { 1307 ESPState *s = ESP(opaque); 1308 1309 return s->dma_memory_read == NULL && s->dma_memory_write == NULL && 1310 s->dma_enabled; 1311 } 1312 1313 static const VMStateDescription vmstate_esp_pdma = { 1314 .name = "esp/pdma", 1315 .version_id = 0, 1316 .minimum_version_id = 0, 1317 .needed = esp_pdma_needed, 1318 .fields = (const VMStateField[]) { 1319 VMSTATE_UINT8(pdma_cb, ESPState), 1320 VMSTATE_END_OF_LIST() 1321 } 1322 }; 1323 1324 const VMStateDescription vmstate_esp = { 1325 .name = "esp", 1326 .version_id = 6, 1327 .minimum_version_id = 3, 1328 .post_load = esp_post_load, 1329 .fields = (const VMStateField[]) { 1330 VMSTATE_BUFFER(rregs, ESPState), 1331 VMSTATE_BUFFER(wregs, ESPState), 1332 VMSTATE_INT32(ti_size, ESPState), 1333 VMSTATE_UINT32_TEST(mig_ti_rptr, ESPState, esp_is_before_version_5), 1334 VMSTATE_UINT32_TEST(mig_ti_wptr, ESPState, esp_is_before_version_5), 1335 VMSTATE_BUFFER_TEST(mig_ti_buf, ESPState, esp_is_before_version_5), 1336 VMSTATE_UINT32(status, ESPState), 1337 VMSTATE_UINT32_TEST(mig_deferred_status, ESPState, 1338 esp_is_before_version_5), 1339 VMSTATE_BOOL_TEST(mig_deferred_complete, ESPState, 1340 esp_is_before_version_5), 1341 VMSTATE_UINT32(dma, ESPState), 1342 VMSTATE_STATIC_BUFFER(mig_cmdbuf, ESPState, 0, 1343 esp_is_before_version_5, 0, 16), 1344 VMSTATE_STATIC_BUFFER(mig_cmdbuf, ESPState, 4, 1345 esp_is_before_version_5, 16, 1346 sizeof(typeof_field(ESPState, mig_cmdbuf))), 1347 VMSTATE_UINT32_TEST(mig_cmdlen, ESPState, esp_is_before_version_5), 1348 VMSTATE_UINT32(do_cmd, ESPState), 1349 VMSTATE_UINT32_TEST(mig_dma_left, ESPState, esp_is_before_version_5), 1350 VMSTATE_BOOL_TEST(data_in_ready, ESPState, esp_is_version_5), 1351 VMSTATE_UINT8_TEST(cmdfifo_cdb_offset, ESPState, esp_is_version_5), 1352 VMSTATE_FIFO8_TEST(fifo, ESPState, esp_is_version_5), 1353 VMSTATE_FIFO8_TEST(cmdfifo, ESPState, esp_is_version_5), 1354 VMSTATE_UINT8_TEST(ti_cmd, ESPState, esp_is_version_5), 1355 VMSTATE_UINT8_TEST(lun, ESPState, esp_is_version_6), 1356 VMSTATE_END_OF_LIST() 1357 }, 1358 .subsections = (const VMStateDescription * const []) { 1359 &vmstate_esp_pdma, 1360 NULL 1361 } 1362 }; 1363 1364 static void sysbus_esp_mem_write(void *opaque, hwaddr addr, 1365 uint64_t val, unsigned int size) 1366 { 1367 SysBusESPState *sysbus = opaque; 1368 ESPState *s = ESP(&sysbus->esp); 1369 uint32_t saddr; 1370 1371 saddr = addr >> sysbus->it_shift; 1372 esp_reg_write(s, saddr, val); 1373 } 1374 1375 static uint64_t sysbus_esp_mem_read(void *opaque, hwaddr addr, 1376 unsigned int size) 1377 { 1378 SysBusESPState *sysbus = opaque; 1379 ESPState *s = ESP(&sysbus->esp); 1380 uint32_t saddr; 1381 1382 saddr = addr >> sysbus->it_shift; 1383 return esp_reg_read(s, saddr); 1384 } 1385 1386 static const MemoryRegionOps sysbus_esp_mem_ops = { 1387 .read = sysbus_esp_mem_read, 1388 .write = sysbus_esp_mem_write, 1389 .endianness = DEVICE_NATIVE_ENDIAN, 1390 .valid.accepts = esp_mem_accepts, 1391 }; 1392 1393 static void sysbus_esp_pdma_write(void *opaque, hwaddr addr, 1394 uint64_t val, unsigned int size) 1395 { 1396 SysBusESPState *sysbus = opaque; 1397 ESPState *s = ESP(&sysbus->esp); 1398 1399 trace_esp_pdma_write(size); 1400 1401 switch (size) { 1402 case 1: 1403 esp_pdma_write(s, val); 1404 break; 1405 case 2: 1406 esp_pdma_write(s, val >> 8); 1407 esp_pdma_write(s, val); 1408 break; 1409 } 1410 esp_pdma_cb(s); 1411 } 1412 1413 static uint64_t sysbus_esp_pdma_read(void *opaque, hwaddr addr, 1414 unsigned int size) 1415 { 1416 SysBusESPState *sysbus = opaque; 1417 ESPState *s = ESP(&sysbus->esp); 1418 uint64_t val = 0; 1419 1420 trace_esp_pdma_read(size); 1421 1422 switch (size) { 1423 case 1: 1424 val = esp_pdma_read(s); 1425 break; 1426 case 2: 1427 val = esp_pdma_read(s); 1428 val = (val << 8) | esp_pdma_read(s); 1429 break; 1430 } 1431 esp_pdma_cb(s); 1432 return val; 1433 } 1434 1435 static void *esp_load_request(QEMUFile *f, SCSIRequest *req) 1436 { 1437 ESPState *s = container_of(req->bus, ESPState, bus); 1438 1439 scsi_req_ref(req); 1440 s->current_req = req; 1441 return s; 1442 } 1443 1444 static const MemoryRegionOps sysbus_esp_pdma_ops = { 1445 .read = sysbus_esp_pdma_read, 1446 .write = sysbus_esp_pdma_write, 1447 .endianness = DEVICE_NATIVE_ENDIAN, 1448 .valid.min_access_size = 1, 1449 .valid.max_access_size = 4, 1450 .impl.min_access_size = 1, 1451 .impl.max_access_size = 2, 1452 }; 1453 1454 static const struct SCSIBusInfo esp_scsi_info = { 1455 .tcq = false, 1456 .max_target = ESP_MAX_DEVS, 1457 .max_lun = 7, 1458 1459 .load_request = esp_load_request, 1460 .transfer_data = esp_transfer_data, 1461 .complete = esp_command_complete, 1462 .cancel = esp_request_cancelled 1463 }; 1464 1465 static void sysbus_esp_gpio_demux(void *opaque, int irq, int level) 1466 { 1467 SysBusESPState *sysbus = SYSBUS_ESP(opaque); 1468 ESPState *s = ESP(&sysbus->esp); 1469 1470 switch (irq) { 1471 case 0: 1472 parent_esp_reset(s, irq, level); 1473 break; 1474 case 1: 1475 esp_dma_enable(s, irq, level); 1476 break; 1477 } 1478 } 1479 1480 static void sysbus_esp_realize(DeviceState *dev, Error **errp) 1481 { 1482 SysBusDevice *sbd = SYS_BUS_DEVICE(dev); 1483 SysBusESPState *sysbus = SYSBUS_ESP(dev); 1484 ESPState *s = ESP(&sysbus->esp); 1485 1486 if (!qdev_realize(DEVICE(s), NULL, errp)) { 1487 return; 1488 } 1489 1490 sysbus_init_irq(sbd, &s->irq); 1491 sysbus_init_irq(sbd, &s->irq_data); 1492 assert(sysbus->it_shift != -1); 1493 1494 s->chip_id = TCHI_FAS100A; 1495 memory_region_init_io(&sysbus->iomem, OBJECT(sysbus), &sysbus_esp_mem_ops, 1496 sysbus, "esp-regs", ESP_REGS << sysbus->it_shift); 1497 sysbus_init_mmio(sbd, &sysbus->iomem); 1498 memory_region_init_io(&sysbus->pdma, OBJECT(sysbus), &sysbus_esp_pdma_ops, 1499 sysbus, "esp-pdma", 4); 1500 sysbus_init_mmio(sbd, &sysbus->pdma); 1501 1502 qdev_init_gpio_in(dev, sysbus_esp_gpio_demux, 2); 1503 1504 scsi_bus_init(&s->bus, sizeof(s->bus), dev, &esp_scsi_info); 1505 } 1506 1507 static void sysbus_esp_hard_reset(DeviceState *dev) 1508 { 1509 SysBusESPState *sysbus = SYSBUS_ESP(dev); 1510 ESPState *s = ESP(&sysbus->esp); 1511 1512 esp_hard_reset(s); 1513 } 1514 1515 static void sysbus_esp_init(Object *obj) 1516 { 1517 SysBusESPState *sysbus = SYSBUS_ESP(obj); 1518 1519 object_initialize_child(obj, "esp", &sysbus->esp, TYPE_ESP); 1520 } 1521 1522 static const VMStateDescription vmstate_sysbus_esp_scsi = { 1523 .name = "sysbusespscsi", 1524 .version_id = 2, 1525 .minimum_version_id = 1, 1526 .pre_save = esp_pre_save, 1527 .fields = (const VMStateField[]) { 1528 VMSTATE_UINT8_V(esp.mig_version_id, SysBusESPState, 2), 1529 VMSTATE_STRUCT(esp, SysBusESPState, 0, vmstate_esp, ESPState), 1530 VMSTATE_END_OF_LIST() 1531 } 1532 }; 1533 1534 static void sysbus_esp_class_init(ObjectClass *klass, void *data) 1535 { 1536 DeviceClass *dc = DEVICE_CLASS(klass); 1537 1538 dc->realize = sysbus_esp_realize; 1539 dc->reset = sysbus_esp_hard_reset; 1540 dc->vmsd = &vmstate_sysbus_esp_scsi; 1541 set_bit(DEVICE_CATEGORY_STORAGE, dc->categories); 1542 } 1543 1544 static const TypeInfo sysbus_esp_info = { 1545 .name = TYPE_SYSBUS_ESP, 1546 .parent = TYPE_SYS_BUS_DEVICE, 1547 .instance_init = sysbus_esp_init, 1548 .instance_size = sizeof(SysBusESPState), 1549 .class_init = sysbus_esp_class_init, 1550 }; 1551 1552 static void esp_finalize(Object *obj) 1553 { 1554 ESPState *s = ESP(obj); 1555 1556 fifo8_destroy(&s->fifo); 1557 fifo8_destroy(&s->cmdfifo); 1558 } 1559 1560 static void esp_init(Object *obj) 1561 { 1562 ESPState *s = ESP(obj); 1563 1564 fifo8_create(&s->fifo, ESP_FIFO_SZ); 1565 fifo8_create(&s->cmdfifo, ESP_CMDFIFO_SZ); 1566 } 1567 1568 static void esp_class_init(ObjectClass *klass, void *data) 1569 { 1570 DeviceClass *dc = DEVICE_CLASS(klass); 1571 1572 /* internal device for sysbusesp/pciespscsi, not user-creatable */ 1573 dc->user_creatable = false; 1574 set_bit(DEVICE_CATEGORY_STORAGE, dc->categories); 1575 } 1576 1577 static const TypeInfo esp_info = { 1578 .name = TYPE_ESP, 1579 .parent = TYPE_DEVICE, 1580 .instance_init = esp_init, 1581 .instance_finalize = esp_finalize, 1582 .instance_size = sizeof(ESPState), 1583 .class_init = esp_class_init, 1584 }; 1585 1586 static void esp_register_types(void) 1587 { 1588 type_register_static(&sysbus_esp_info); 1589 type_register_static(&esp_info); 1590 } 1591 1592 type_init(esp_register_types) 1593