1 /* 2 * QEMU ESP/NCR53C9x emulation 3 * 4 * Copyright (c) 2005-2006 Fabrice Bellard 5 * Copyright (c) 2012 Herve Poussineau 6 * 7 * Permission is hereby granted, free of charge, to any person obtaining a copy 8 * of this software and associated documentation files (the "Software"), to deal 9 * in the Software without restriction, including without limitation the rights 10 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 11 * copies of the Software, and to permit persons to whom the Software is 12 * furnished to do so, subject to the following conditions: 13 * 14 * The above copyright notice and this permission notice shall be included in 15 * all copies or substantial portions of the Software. 16 * 17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 22 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 23 * THE SOFTWARE. 24 */ 25 26 #include "qemu/osdep.h" 27 #include "hw/sysbus.h" 28 #include "migration/vmstate.h" 29 #include "hw/irq.h" 30 #include "hw/scsi/esp.h" 31 #include "trace.h" 32 #include "qemu/log.h" 33 #include "qemu/module.h" 34 35 /* 36 * On Sparc32, this is the ESP (NCR53C90) part of chip STP2000 (Master I/O), 37 * also produced as NCR89C100. See 38 * http://www.ibiblio.org/pub/historic-linux/early-ports/Sparc/NCR/NCR89C100.txt 39 * and 40 * http://www.ibiblio.org/pub/historic-linux/early-ports/Sparc/NCR/NCR53C9X.txt 41 */ 42 43 static void esp_raise_irq(ESPState *s) 44 { 45 if (!(s->rregs[ESP_RSTAT] & STAT_INT)) { 46 s->rregs[ESP_RSTAT] |= STAT_INT; 47 qemu_irq_raise(s->irq); 48 trace_esp_raise_irq(); 49 } 50 } 51 52 static void esp_lower_irq(ESPState *s) 53 { 54 if (s->rregs[ESP_RSTAT] & STAT_INT) { 55 s->rregs[ESP_RSTAT] &= ~STAT_INT; 56 qemu_irq_lower(s->irq); 57 trace_esp_lower_irq(); 58 } 59 } 60 61 void esp_dma_enable(ESPState *s, int irq, int level) 62 { 63 if (level) { 64 s->dma_enabled = 1; 65 trace_esp_dma_enable(); 66 if (s->dma_cb) { 67 s->dma_cb(s); 68 s->dma_cb = NULL; 69 } 70 } else { 71 trace_esp_dma_disable(); 72 s->dma_enabled = 0; 73 } 74 } 75 76 void esp_request_cancelled(SCSIRequest *req) 77 { 78 ESPState *s = req->hba_private; 79 80 if (req == s->current_req) { 81 scsi_req_unref(s->current_req); 82 s->current_req = NULL; 83 s->current_dev = NULL; 84 } 85 } 86 87 static uint32_t get_cmd(ESPState *s, uint8_t *buf, uint8_t buflen) 88 { 89 uint32_t dmalen; 90 int target; 91 92 target = s->wregs[ESP_WBUSID] & BUSID_DID; 93 if (s->dma) { 94 dmalen = s->rregs[ESP_TCLO]; 95 dmalen |= s->rregs[ESP_TCMID] << 8; 96 dmalen |= s->rregs[ESP_TCHI] << 16; 97 if (dmalen > buflen) { 98 return 0; 99 } 100 s->dma_memory_read(s->dma_opaque, buf, dmalen); 101 } else { 102 dmalen = s->ti_size; 103 if (dmalen > TI_BUFSZ) { 104 return 0; 105 } 106 memcpy(buf, s->ti_buf, dmalen); 107 buf[0] = buf[2] >> 5; 108 } 109 trace_esp_get_cmd(dmalen, target); 110 111 s->ti_size = 0; 112 s->ti_rptr = 0; 113 s->ti_wptr = 0; 114 115 if (s->current_req) { 116 /* Started a new command before the old one finished. Cancel it. */ 117 scsi_req_cancel(s->current_req); 118 s->async_len = 0; 119 } 120 121 s->current_dev = scsi_device_find(&s->bus, 0, target, 0); 122 if (!s->current_dev) { 123 // No such drive 124 s->rregs[ESP_RSTAT] = 0; 125 s->rregs[ESP_RINTR] = INTR_DC; 126 s->rregs[ESP_RSEQ] = SEQ_0; 127 esp_raise_irq(s); 128 return 0; 129 } 130 return dmalen; 131 } 132 133 static void do_busid_cmd(ESPState *s, uint8_t *buf, uint8_t busid) 134 { 135 int32_t datalen; 136 int lun; 137 SCSIDevice *current_lun; 138 139 trace_esp_do_busid_cmd(busid); 140 lun = busid & 7; 141 current_lun = scsi_device_find(&s->bus, 0, s->current_dev->id, lun); 142 s->current_req = scsi_req_new(current_lun, 0, lun, buf, s); 143 datalen = scsi_req_enqueue(s->current_req); 144 s->ti_size = datalen; 145 if (datalen != 0) { 146 s->rregs[ESP_RSTAT] = STAT_TC; 147 s->dma_left = 0; 148 s->dma_counter = 0; 149 if (datalen > 0) { 150 s->rregs[ESP_RSTAT] |= STAT_DI; 151 } else { 152 s->rregs[ESP_RSTAT] |= STAT_DO; 153 } 154 scsi_req_continue(s->current_req); 155 } 156 s->rregs[ESP_RINTR] = INTR_BS | INTR_FC; 157 s->rregs[ESP_RSEQ] = SEQ_CD; 158 esp_raise_irq(s); 159 } 160 161 static void do_cmd(ESPState *s, uint8_t *buf) 162 { 163 uint8_t busid = buf[0]; 164 165 do_busid_cmd(s, &buf[1], busid); 166 } 167 168 static void handle_satn(ESPState *s) 169 { 170 uint8_t buf[32]; 171 int len; 172 173 if (s->dma && !s->dma_enabled) { 174 s->dma_cb = handle_satn; 175 return; 176 } 177 len = get_cmd(s, buf, sizeof(buf)); 178 if (len) 179 do_cmd(s, buf); 180 } 181 182 static void handle_s_without_atn(ESPState *s) 183 { 184 uint8_t buf[32]; 185 int len; 186 187 if (s->dma && !s->dma_enabled) { 188 s->dma_cb = handle_s_without_atn; 189 return; 190 } 191 len = get_cmd(s, buf, sizeof(buf)); 192 if (len) { 193 do_busid_cmd(s, buf, 0); 194 } 195 } 196 197 static void handle_satn_stop(ESPState *s) 198 { 199 if (s->dma && !s->dma_enabled) { 200 s->dma_cb = handle_satn_stop; 201 return; 202 } 203 s->cmdlen = get_cmd(s, s->cmdbuf, sizeof(s->cmdbuf)); 204 if (s->cmdlen) { 205 trace_esp_handle_satn_stop(s->cmdlen); 206 s->do_cmd = 1; 207 s->rregs[ESP_RSTAT] = STAT_TC | STAT_CD; 208 s->rregs[ESP_RINTR] = INTR_BS | INTR_FC; 209 s->rregs[ESP_RSEQ] = SEQ_CD; 210 esp_raise_irq(s); 211 } 212 } 213 214 static void write_response(ESPState *s) 215 { 216 trace_esp_write_response(s->status); 217 s->ti_buf[0] = s->status; 218 s->ti_buf[1] = 0; 219 if (s->dma) { 220 s->dma_memory_write(s->dma_opaque, s->ti_buf, 2); 221 s->rregs[ESP_RSTAT] = STAT_TC | STAT_ST; 222 s->rregs[ESP_RINTR] = INTR_BS | INTR_FC; 223 s->rregs[ESP_RSEQ] = SEQ_CD; 224 } else { 225 s->ti_size = 2; 226 s->ti_rptr = 0; 227 s->ti_wptr = 2; 228 s->rregs[ESP_RFLAGS] = 2; 229 } 230 esp_raise_irq(s); 231 } 232 233 static void esp_dma_done(ESPState *s) 234 { 235 s->rregs[ESP_RSTAT] |= STAT_TC; 236 s->rregs[ESP_RINTR] = INTR_BS; 237 s->rregs[ESP_RSEQ] = 0; 238 s->rregs[ESP_RFLAGS] = 0; 239 s->rregs[ESP_TCLO] = 0; 240 s->rregs[ESP_TCMID] = 0; 241 s->rregs[ESP_TCHI] = 0; 242 esp_raise_irq(s); 243 } 244 245 static void esp_do_dma(ESPState *s) 246 { 247 uint32_t len; 248 int to_device; 249 250 len = s->dma_left; 251 if (s->do_cmd) { 252 /* 253 * handle_ti_cmd() case: esp_do_dma() is called only from 254 * handle_ti_cmd() with do_cmd != NULL (see the assert()) 255 */ 256 trace_esp_do_dma(s->cmdlen, len); 257 assert (s->cmdlen <= sizeof(s->cmdbuf) && 258 len <= sizeof(s->cmdbuf) - s->cmdlen); 259 s->dma_memory_read(s->dma_opaque, &s->cmdbuf[s->cmdlen], len); 260 trace_esp_handle_ti_cmd(s->cmdlen); 261 s->ti_size = 0; 262 s->cmdlen = 0; 263 s->do_cmd = 0; 264 do_cmd(s, s->cmdbuf); 265 return; 266 } 267 if (s->async_len == 0) { 268 /* Defer until data is available. */ 269 return; 270 } 271 if (len > s->async_len) { 272 len = s->async_len; 273 } 274 to_device = (s->ti_size < 0); 275 if (to_device) { 276 s->dma_memory_read(s->dma_opaque, s->async_buf, len); 277 } else { 278 s->dma_memory_write(s->dma_opaque, s->async_buf, len); 279 } 280 s->dma_left -= len; 281 s->async_buf += len; 282 s->async_len -= len; 283 if (to_device) 284 s->ti_size += len; 285 else 286 s->ti_size -= len; 287 if (s->async_len == 0) { 288 scsi_req_continue(s->current_req); 289 /* If there is still data to be read from the device then 290 complete the DMA operation immediately. Otherwise defer 291 until the scsi layer has completed. */ 292 if (to_device || s->dma_left != 0 || s->ti_size == 0) { 293 return; 294 } 295 } 296 297 /* Partially filled a scsi buffer. Complete immediately. */ 298 esp_dma_done(s); 299 } 300 301 static void esp_report_command_complete(ESPState *s, uint32_t status) 302 { 303 trace_esp_command_complete(); 304 if (s->ti_size != 0) { 305 trace_esp_command_complete_unexpected(); 306 } 307 s->ti_size = 0; 308 s->dma_left = 0; 309 s->async_len = 0; 310 if (status) { 311 trace_esp_command_complete_fail(); 312 } 313 s->status = status; 314 s->rregs[ESP_RSTAT] = STAT_ST; 315 esp_dma_done(s); 316 if (s->current_req) { 317 scsi_req_unref(s->current_req); 318 s->current_req = NULL; 319 s->current_dev = NULL; 320 } 321 } 322 323 void esp_command_complete(SCSIRequest *req, uint32_t status, 324 size_t resid) 325 { 326 ESPState *s = req->hba_private; 327 328 if (s->rregs[ESP_RSTAT] & STAT_INT) { 329 /* Defer handling command complete until the previous 330 * interrupt has been handled. 331 */ 332 trace_esp_command_complete_deferred(); 333 s->deferred_status = status; 334 s->deferred_complete = true; 335 return; 336 } 337 esp_report_command_complete(s, status); 338 } 339 340 void esp_transfer_data(SCSIRequest *req, uint32_t len) 341 { 342 ESPState *s = req->hba_private; 343 344 assert(!s->do_cmd); 345 trace_esp_transfer_data(s->dma_left, s->ti_size); 346 s->async_len = len; 347 s->async_buf = scsi_req_get_buf(req); 348 if (s->dma_left) { 349 esp_do_dma(s); 350 } else if (s->dma_counter != 0 && s->ti_size <= 0) { 351 /* If this was the last part of a DMA transfer then the 352 completion interrupt is deferred to here. */ 353 esp_dma_done(s); 354 } 355 } 356 357 static void handle_ti(ESPState *s) 358 { 359 uint32_t dmalen, minlen; 360 361 if (s->dma && !s->dma_enabled) { 362 s->dma_cb = handle_ti; 363 return; 364 } 365 366 dmalen = s->rregs[ESP_TCLO]; 367 dmalen |= s->rregs[ESP_TCMID] << 8; 368 dmalen |= s->rregs[ESP_TCHI] << 16; 369 if (dmalen==0) { 370 dmalen=0x10000; 371 } 372 s->dma_counter = dmalen; 373 374 if (s->do_cmd) 375 minlen = (dmalen < ESP_CMDBUF_SZ) ? dmalen : ESP_CMDBUF_SZ; 376 else if (s->ti_size < 0) 377 minlen = (dmalen < -s->ti_size) ? dmalen : -s->ti_size; 378 else 379 minlen = (dmalen < s->ti_size) ? dmalen : s->ti_size; 380 trace_esp_handle_ti(minlen); 381 if (s->dma) { 382 s->dma_left = minlen; 383 s->rregs[ESP_RSTAT] &= ~STAT_TC; 384 esp_do_dma(s); 385 } else if (s->do_cmd) { 386 trace_esp_handle_ti_cmd(s->cmdlen); 387 s->ti_size = 0; 388 s->cmdlen = 0; 389 s->do_cmd = 0; 390 do_cmd(s, s->cmdbuf); 391 } 392 } 393 394 void esp_hard_reset(ESPState *s) 395 { 396 memset(s->rregs, 0, ESP_REGS); 397 memset(s->wregs, 0, ESP_REGS); 398 s->tchi_written = 0; 399 s->ti_size = 0; 400 s->ti_rptr = 0; 401 s->ti_wptr = 0; 402 s->dma = 0; 403 s->do_cmd = 0; 404 s->dma_cb = NULL; 405 406 s->rregs[ESP_CFG1] = 7; 407 } 408 409 static void esp_soft_reset(ESPState *s) 410 { 411 qemu_irq_lower(s->irq); 412 esp_hard_reset(s); 413 } 414 415 static void parent_esp_reset(ESPState *s, int irq, int level) 416 { 417 if (level) { 418 esp_soft_reset(s); 419 } 420 } 421 422 uint64_t esp_reg_read(ESPState *s, uint32_t saddr) 423 { 424 uint32_t old_val; 425 426 trace_esp_mem_readb(saddr, s->rregs[saddr]); 427 switch (saddr) { 428 case ESP_FIFO: 429 if ((s->rregs[ESP_RSTAT] & STAT_PIO_MASK) == 0) { 430 /* Data out. */ 431 qemu_log_mask(LOG_UNIMP, "esp: PIO data read not implemented\n"); 432 s->rregs[ESP_FIFO] = 0; 433 } else if (s->ti_rptr < s->ti_wptr) { 434 s->ti_size--; 435 s->rregs[ESP_FIFO] = s->ti_buf[s->ti_rptr++]; 436 } 437 if (s->ti_rptr == s->ti_wptr) { 438 s->ti_rptr = 0; 439 s->ti_wptr = 0; 440 } 441 break; 442 case ESP_RINTR: 443 /* Clear sequence step, interrupt register and all status bits 444 except TC */ 445 old_val = s->rregs[ESP_RINTR]; 446 s->rregs[ESP_RINTR] = 0; 447 s->rregs[ESP_RSTAT] &= ~STAT_TC; 448 s->rregs[ESP_RSEQ] = SEQ_CD; 449 esp_lower_irq(s); 450 if (s->deferred_complete) { 451 esp_report_command_complete(s, s->deferred_status); 452 s->deferred_complete = false; 453 } 454 return old_val; 455 case ESP_TCHI: 456 /* Return the unique id if the value has never been written */ 457 if (!s->tchi_written) { 458 return s->chip_id; 459 } 460 default: 461 break; 462 } 463 return s->rregs[saddr]; 464 } 465 466 void esp_reg_write(ESPState *s, uint32_t saddr, uint64_t val) 467 { 468 trace_esp_mem_writeb(saddr, s->wregs[saddr], val); 469 switch (saddr) { 470 case ESP_TCHI: 471 s->tchi_written = true; 472 /* fall through */ 473 case ESP_TCLO: 474 case ESP_TCMID: 475 s->rregs[ESP_RSTAT] &= ~STAT_TC; 476 break; 477 case ESP_FIFO: 478 if (s->do_cmd) { 479 if (s->cmdlen < ESP_CMDBUF_SZ) { 480 s->cmdbuf[s->cmdlen++] = val & 0xff; 481 } else { 482 trace_esp_error_fifo_overrun(); 483 } 484 } else if (s->ti_wptr == TI_BUFSZ - 1) { 485 trace_esp_error_fifo_overrun(); 486 } else { 487 s->ti_size++; 488 s->ti_buf[s->ti_wptr++] = val & 0xff; 489 } 490 break; 491 case ESP_CMD: 492 s->rregs[saddr] = val; 493 if (val & CMD_DMA) { 494 s->dma = 1; 495 /* Reload DMA counter. */ 496 s->rregs[ESP_TCLO] = s->wregs[ESP_TCLO]; 497 s->rregs[ESP_TCMID] = s->wregs[ESP_TCMID]; 498 s->rregs[ESP_TCHI] = s->wregs[ESP_TCHI]; 499 } else { 500 s->dma = 0; 501 } 502 switch(val & CMD_CMD) { 503 case CMD_NOP: 504 trace_esp_mem_writeb_cmd_nop(val); 505 break; 506 case CMD_FLUSH: 507 trace_esp_mem_writeb_cmd_flush(val); 508 //s->ti_size = 0; 509 s->rregs[ESP_RINTR] = INTR_FC; 510 s->rregs[ESP_RSEQ] = 0; 511 s->rregs[ESP_RFLAGS] = 0; 512 break; 513 case CMD_RESET: 514 trace_esp_mem_writeb_cmd_reset(val); 515 esp_soft_reset(s); 516 break; 517 case CMD_BUSRESET: 518 trace_esp_mem_writeb_cmd_bus_reset(val); 519 s->rregs[ESP_RINTR] = INTR_RST; 520 if (!(s->wregs[ESP_CFG1] & CFG1_RESREPT)) { 521 esp_raise_irq(s); 522 } 523 break; 524 case CMD_TI: 525 handle_ti(s); 526 break; 527 case CMD_ICCS: 528 trace_esp_mem_writeb_cmd_iccs(val); 529 write_response(s); 530 s->rregs[ESP_RINTR] = INTR_FC; 531 s->rregs[ESP_RSTAT] |= STAT_MI; 532 break; 533 case CMD_MSGACC: 534 trace_esp_mem_writeb_cmd_msgacc(val); 535 s->rregs[ESP_RINTR] = INTR_DC; 536 s->rregs[ESP_RSEQ] = 0; 537 s->rregs[ESP_RFLAGS] = 0; 538 esp_raise_irq(s); 539 break; 540 case CMD_PAD: 541 trace_esp_mem_writeb_cmd_pad(val); 542 s->rregs[ESP_RSTAT] = STAT_TC; 543 s->rregs[ESP_RINTR] = INTR_FC; 544 s->rregs[ESP_RSEQ] = 0; 545 break; 546 case CMD_SATN: 547 trace_esp_mem_writeb_cmd_satn(val); 548 break; 549 case CMD_RSTATN: 550 trace_esp_mem_writeb_cmd_rstatn(val); 551 break; 552 case CMD_SEL: 553 trace_esp_mem_writeb_cmd_sel(val); 554 handle_s_without_atn(s); 555 break; 556 case CMD_SELATN: 557 trace_esp_mem_writeb_cmd_selatn(val); 558 handle_satn(s); 559 break; 560 case CMD_SELATNS: 561 trace_esp_mem_writeb_cmd_selatns(val); 562 handle_satn_stop(s); 563 break; 564 case CMD_ENSEL: 565 trace_esp_mem_writeb_cmd_ensel(val); 566 s->rregs[ESP_RINTR] = 0; 567 break; 568 case CMD_DISSEL: 569 trace_esp_mem_writeb_cmd_dissel(val); 570 s->rregs[ESP_RINTR] = 0; 571 esp_raise_irq(s); 572 break; 573 default: 574 trace_esp_error_unhandled_command(val); 575 break; 576 } 577 break; 578 case ESP_WBUSID ... ESP_WSYNO: 579 break; 580 case ESP_CFG1: 581 case ESP_CFG2: case ESP_CFG3: 582 case ESP_RES3: case ESP_RES4: 583 s->rregs[saddr] = val; 584 break; 585 case ESP_WCCF ... ESP_WTEST: 586 break; 587 default: 588 trace_esp_error_invalid_write(val, saddr); 589 return; 590 } 591 s->wregs[saddr] = val; 592 } 593 594 static bool esp_mem_accepts(void *opaque, hwaddr addr, 595 unsigned size, bool is_write, 596 MemTxAttrs attrs) 597 { 598 return (size == 1) || (is_write && size == 4); 599 } 600 601 const VMStateDescription vmstate_esp = { 602 .name ="esp", 603 .version_id = 4, 604 .minimum_version_id = 3, 605 .fields = (VMStateField[]) { 606 VMSTATE_BUFFER(rregs, ESPState), 607 VMSTATE_BUFFER(wregs, ESPState), 608 VMSTATE_INT32(ti_size, ESPState), 609 VMSTATE_UINT32(ti_rptr, ESPState), 610 VMSTATE_UINT32(ti_wptr, ESPState), 611 VMSTATE_BUFFER(ti_buf, ESPState), 612 VMSTATE_UINT32(status, ESPState), 613 VMSTATE_UINT32(deferred_status, ESPState), 614 VMSTATE_BOOL(deferred_complete, ESPState), 615 VMSTATE_UINT32(dma, ESPState), 616 VMSTATE_PARTIAL_BUFFER(cmdbuf, ESPState, 16), 617 VMSTATE_BUFFER_START_MIDDLE_V(cmdbuf, ESPState, 16, 4), 618 VMSTATE_UINT32(cmdlen, ESPState), 619 VMSTATE_UINT32(do_cmd, ESPState), 620 VMSTATE_UINT32(dma_left, ESPState), 621 VMSTATE_END_OF_LIST() 622 } 623 }; 624 625 static void sysbus_esp_mem_write(void *opaque, hwaddr addr, 626 uint64_t val, unsigned int size) 627 { 628 SysBusESPState *sysbus = opaque; 629 uint32_t saddr; 630 631 saddr = addr >> sysbus->it_shift; 632 esp_reg_write(&sysbus->esp, saddr, val); 633 } 634 635 static uint64_t sysbus_esp_mem_read(void *opaque, hwaddr addr, 636 unsigned int size) 637 { 638 SysBusESPState *sysbus = opaque; 639 uint32_t saddr; 640 641 saddr = addr >> sysbus->it_shift; 642 return esp_reg_read(&sysbus->esp, saddr); 643 } 644 645 static const MemoryRegionOps sysbus_esp_mem_ops = { 646 .read = sysbus_esp_mem_read, 647 .write = sysbus_esp_mem_write, 648 .endianness = DEVICE_NATIVE_ENDIAN, 649 .valid.accepts = esp_mem_accepts, 650 }; 651 652 static const struct SCSIBusInfo esp_scsi_info = { 653 .tcq = false, 654 .max_target = ESP_MAX_DEVS, 655 .max_lun = 7, 656 657 .transfer_data = esp_transfer_data, 658 .complete = esp_command_complete, 659 .cancel = esp_request_cancelled 660 }; 661 662 static void sysbus_esp_gpio_demux(void *opaque, int irq, int level) 663 { 664 SysBusESPState *sysbus = ESP_STATE(opaque); 665 ESPState *s = &sysbus->esp; 666 667 switch (irq) { 668 case 0: 669 parent_esp_reset(s, irq, level); 670 break; 671 case 1: 672 esp_dma_enable(opaque, irq, level); 673 break; 674 } 675 } 676 677 static void sysbus_esp_realize(DeviceState *dev, Error **errp) 678 { 679 SysBusDevice *sbd = SYS_BUS_DEVICE(dev); 680 SysBusESPState *sysbus = ESP_STATE(dev); 681 ESPState *s = &sysbus->esp; 682 683 sysbus_init_irq(sbd, &s->irq); 684 assert(sysbus->it_shift != -1); 685 686 s->chip_id = TCHI_FAS100A; 687 memory_region_init_io(&sysbus->iomem, OBJECT(sysbus), &sysbus_esp_mem_ops, 688 sysbus, "esp", ESP_REGS << sysbus->it_shift); 689 sysbus_init_mmio(sbd, &sysbus->iomem); 690 691 qdev_init_gpio_in(dev, sysbus_esp_gpio_demux, 2); 692 693 scsi_bus_new(&s->bus, sizeof(s->bus), dev, &esp_scsi_info, NULL); 694 } 695 696 static void sysbus_esp_hard_reset(DeviceState *dev) 697 { 698 SysBusESPState *sysbus = ESP_STATE(dev); 699 esp_hard_reset(&sysbus->esp); 700 } 701 702 static const VMStateDescription vmstate_sysbus_esp_scsi = { 703 .name = "sysbusespscsi", 704 .version_id = 1, 705 .minimum_version_id = 1, 706 .fields = (VMStateField[]) { 707 VMSTATE_STRUCT(esp, SysBusESPState, 0, vmstate_esp, ESPState), 708 VMSTATE_END_OF_LIST() 709 } 710 }; 711 712 static void sysbus_esp_class_init(ObjectClass *klass, void *data) 713 { 714 DeviceClass *dc = DEVICE_CLASS(klass); 715 716 dc->realize = sysbus_esp_realize; 717 dc->reset = sysbus_esp_hard_reset; 718 dc->vmsd = &vmstate_sysbus_esp_scsi; 719 set_bit(DEVICE_CATEGORY_STORAGE, dc->categories); 720 } 721 722 static const TypeInfo sysbus_esp_info = { 723 .name = TYPE_ESP, 724 .parent = TYPE_SYS_BUS_DEVICE, 725 .instance_size = sizeof(SysBusESPState), 726 .class_init = sysbus_esp_class_init, 727 }; 728 729 static void esp_register_types(void) 730 { 731 type_register_static(&sysbus_esp_info); 732 } 733 734 type_init(esp_register_types) 735