1 /* 2 * QEMU ESP/NCR53C9x emulation 3 * 4 * Copyright (c) 2005-2006 Fabrice Bellard 5 * Copyright (c) 2012 Herve Poussineau 6 * 7 * Permission is hereby granted, free of charge, to any person obtaining a copy 8 * of this software and associated documentation files (the "Software"), to deal 9 * in the Software without restriction, including without limitation the rights 10 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 11 * copies of the Software, and to permit persons to whom the Software is 12 * furnished to do so, subject to the following conditions: 13 * 14 * The above copyright notice and this permission notice shall be included in 15 * all copies or substantial portions of the Software. 16 * 17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 22 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 23 * THE SOFTWARE. 24 */ 25 26 #include "qemu/osdep.h" 27 #include "hw/sysbus.h" 28 #include "migration/vmstate.h" 29 #include "hw/irq.h" 30 #include "hw/scsi/esp.h" 31 #include "trace.h" 32 #include "qemu/log.h" 33 #include "qemu/module.h" 34 35 /* 36 * On Sparc32, this is the ESP (NCR53C90) part of chip STP2000 (Master I/O), 37 * also produced as NCR89C100. See 38 * http://www.ibiblio.org/pub/historic-linux/early-ports/Sparc/NCR/NCR89C100.txt 39 * and 40 * http://www.ibiblio.org/pub/historic-linux/early-ports/Sparc/NCR/NCR53C9X.txt 41 * 42 * On Macintosh Quadra it is a NCR53C96. 43 */ 44 45 static void esp_raise_irq(ESPState *s) 46 { 47 if (!(s->rregs[ESP_RSTAT] & STAT_INT)) { 48 s->rregs[ESP_RSTAT] |= STAT_INT; 49 qemu_irq_raise(s->irq); 50 trace_esp_raise_irq(); 51 } 52 } 53 54 static void esp_lower_irq(ESPState *s) 55 { 56 if (s->rregs[ESP_RSTAT] & STAT_INT) { 57 s->rregs[ESP_RSTAT] &= ~STAT_INT; 58 qemu_irq_lower(s->irq); 59 trace_esp_lower_irq(); 60 } 61 } 62 63 static void esp_raise_drq(ESPState *s) 64 { 65 qemu_irq_raise(s->irq_data); 66 trace_esp_raise_drq(); 67 } 68 69 static void esp_lower_drq(ESPState *s) 70 { 71 qemu_irq_lower(s->irq_data); 72 trace_esp_lower_drq(); 73 } 74 75 void esp_dma_enable(ESPState *s, int irq, int level) 76 { 77 if (level) { 78 s->dma_enabled = 1; 79 trace_esp_dma_enable(); 80 if (s->dma_cb) { 81 s->dma_cb(s); 82 s->dma_cb = NULL; 83 } 84 } else { 85 trace_esp_dma_disable(); 86 s->dma_enabled = 0; 87 } 88 } 89 90 void esp_request_cancelled(SCSIRequest *req) 91 { 92 ESPState *s = req->hba_private; 93 94 if (req == s->current_req) { 95 scsi_req_unref(s->current_req); 96 s->current_req = NULL; 97 s->current_dev = NULL; 98 s->async_len = 0; 99 } 100 } 101 102 static void esp_fifo_push(Fifo8 *fifo, uint8_t val) 103 { 104 if (fifo8_num_used(fifo) == fifo->capacity) { 105 trace_esp_error_fifo_overrun(); 106 return; 107 } 108 109 fifo8_push(fifo, val); 110 } 111 112 static uint8_t esp_fifo_pop(Fifo8 *fifo) 113 { 114 if (fifo8_is_empty(fifo)) { 115 return 0; 116 } 117 118 return fifo8_pop(fifo); 119 } 120 121 static uint32_t esp_fifo_pop_buf(Fifo8 *fifo, uint8_t *dest, int maxlen) 122 { 123 const uint8_t *buf; 124 uint32_t n, n2; 125 int len; 126 127 if (maxlen == 0) { 128 return 0; 129 } 130 131 len = maxlen; 132 buf = fifo8_pop_buf(fifo, len, &n); 133 if (dest) { 134 memcpy(dest, buf, n); 135 } 136 137 /* Add FIFO wraparound if needed */ 138 len -= n; 139 len = MIN(len, fifo8_num_used(fifo)); 140 if (len) { 141 buf = fifo8_pop_buf(fifo, len, &n2); 142 if (dest) { 143 memcpy(&dest[n], buf, n2); 144 } 145 n += n2; 146 } 147 148 return n; 149 } 150 151 static uint32_t esp_get_tc(ESPState *s) 152 { 153 uint32_t dmalen; 154 155 dmalen = s->rregs[ESP_TCLO]; 156 dmalen |= s->rregs[ESP_TCMID] << 8; 157 dmalen |= s->rregs[ESP_TCHI] << 16; 158 159 return dmalen; 160 } 161 162 static void esp_set_tc(ESPState *s, uint32_t dmalen) 163 { 164 uint32_t old_tc = esp_get_tc(s); 165 166 s->rregs[ESP_TCLO] = dmalen; 167 s->rregs[ESP_TCMID] = dmalen >> 8; 168 s->rregs[ESP_TCHI] = dmalen >> 16; 169 170 if (old_tc && dmalen == 0) { 171 s->rregs[ESP_RSTAT] |= STAT_TC; 172 } 173 } 174 175 static uint32_t esp_get_stc(ESPState *s) 176 { 177 uint32_t dmalen; 178 179 dmalen = s->wregs[ESP_TCLO]; 180 dmalen |= s->wregs[ESP_TCMID] << 8; 181 dmalen |= s->wregs[ESP_TCHI] << 16; 182 183 return dmalen; 184 } 185 186 static const char *esp_phase_names[8] = { 187 "DATA OUT", "DATA IN", "COMMAND", "STATUS", 188 "(reserved)", "(reserved)", "MESSAGE OUT", "MESSAGE IN" 189 }; 190 191 static void esp_set_phase(ESPState *s, uint8_t phase) 192 { 193 s->rregs[ESP_RSTAT] &= ~7; 194 s->rregs[ESP_RSTAT] |= phase; 195 196 trace_esp_set_phase(esp_phase_names[phase]); 197 } 198 199 static uint8_t esp_pdma_read(ESPState *s) 200 { 201 uint8_t val; 202 203 val = esp_fifo_pop(&s->fifo); 204 return val; 205 } 206 207 static void esp_pdma_write(ESPState *s, uint8_t val) 208 { 209 uint32_t dmalen = esp_get_tc(s); 210 211 if (dmalen == 0) { 212 return; 213 } 214 215 esp_fifo_push(&s->fifo, val); 216 217 dmalen--; 218 esp_set_tc(s, dmalen); 219 } 220 221 static void esp_set_pdma_cb(ESPState *s, enum pdma_cb cb) 222 { 223 s->pdma_cb = cb; 224 } 225 226 static int esp_select(ESPState *s) 227 { 228 int target; 229 230 target = s->wregs[ESP_WBUSID] & BUSID_DID; 231 232 s->ti_size = 0; 233 234 if (s->current_req) { 235 /* Started a new command before the old one finished. Cancel it. */ 236 scsi_req_cancel(s->current_req); 237 } 238 239 s->current_dev = scsi_device_find(&s->bus, 0, target, 0); 240 if (!s->current_dev) { 241 /* No such drive */ 242 s->rregs[ESP_RSTAT] = 0; 243 s->rregs[ESP_RINTR] = INTR_DC; 244 s->rregs[ESP_RSEQ] = SEQ_0; 245 esp_raise_irq(s); 246 return -1; 247 } 248 249 /* 250 * Note that we deliberately don't raise the IRQ here: this will be done 251 * either in do_command_phase() for DATA OUT transfers or by the deferred 252 * IRQ mechanism in esp_transfer_data() for DATA IN transfers 253 */ 254 s->rregs[ESP_RINTR] |= INTR_FC; 255 s->rregs[ESP_RSEQ] = SEQ_CD; 256 return 0; 257 } 258 259 static uint32_t get_cmd(ESPState *s, uint32_t maxlen) 260 { 261 uint8_t buf[ESP_CMDFIFO_SZ]; 262 uint32_t dmalen, n; 263 int target; 264 265 target = s->wregs[ESP_WBUSID] & BUSID_DID; 266 if (s->dma) { 267 dmalen = MIN(esp_get_tc(s), maxlen); 268 if (dmalen == 0) { 269 return 0; 270 } 271 if (s->dma_memory_read) { 272 s->dma_memory_read(s->dma_opaque, buf, dmalen); 273 dmalen = MIN(fifo8_num_free(&s->cmdfifo), dmalen); 274 fifo8_push_all(&s->cmdfifo, buf, dmalen); 275 esp_set_tc(s, esp_get_tc(s) - dmalen); 276 } else { 277 return 0; 278 } 279 } else { 280 dmalen = MIN(fifo8_num_used(&s->fifo), maxlen); 281 if (dmalen == 0) { 282 return 0; 283 } 284 n = esp_fifo_pop_buf(&s->fifo, buf, dmalen); 285 n = MIN(fifo8_num_free(&s->cmdfifo), n); 286 fifo8_push_all(&s->cmdfifo, buf, n); 287 } 288 trace_esp_get_cmd(dmalen, target); 289 290 return dmalen; 291 } 292 293 static void do_command_phase(ESPState *s) 294 { 295 uint32_t cmdlen; 296 int32_t datalen; 297 SCSIDevice *current_lun; 298 uint8_t buf[ESP_CMDFIFO_SZ]; 299 300 trace_esp_do_command_phase(s->lun); 301 cmdlen = fifo8_num_used(&s->cmdfifo); 302 if (!cmdlen || !s->current_dev) { 303 return; 304 } 305 esp_fifo_pop_buf(&s->cmdfifo, buf, cmdlen); 306 307 current_lun = scsi_device_find(&s->bus, 0, s->current_dev->id, s->lun); 308 if (!current_lun) { 309 /* No such drive */ 310 s->rregs[ESP_RSTAT] = 0; 311 s->rregs[ESP_RINTR] = INTR_DC; 312 s->rregs[ESP_RSEQ] = SEQ_0; 313 esp_raise_irq(s); 314 return; 315 } 316 317 s->current_req = scsi_req_new(current_lun, 0, s->lun, buf, cmdlen, s); 318 datalen = scsi_req_enqueue(s->current_req); 319 s->ti_size = datalen; 320 fifo8_reset(&s->cmdfifo); 321 if (datalen != 0) { 322 s->ti_cmd = 0; 323 if (datalen > 0) { 324 /* 325 * Switch to DATA IN phase but wait until initial data xfer is 326 * complete before raising the command completion interrupt 327 */ 328 s->data_in_ready = false; 329 esp_set_phase(s, STAT_DI); 330 } else { 331 esp_set_phase(s, STAT_DO); 332 s->rregs[ESP_RINTR] |= INTR_BS | INTR_FC; 333 esp_raise_irq(s); 334 esp_lower_drq(s); 335 } 336 scsi_req_continue(s->current_req); 337 return; 338 } 339 } 340 341 static void do_message_phase(ESPState *s) 342 { 343 if (s->cmdfifo_cdb_offset) { 344 uint8_t message = esp_fifo_pop(&s->cmdfifo); 345 346 trace_esp_do_identify(message); 347 s->lun = message & 7; 348 s->cmdfifo_cdb_offset--; 349 } 350 351 /* Ignore extended messages for now */ 352 if (s->cmdfifo_cdb_offset) { 353 int len = MIN(s->cmdfifo_cdb_offset, fifo8_num_used(&s->cmdfifo)); 354 esp_fifo_pop_buf(&s->cmdfifo, NULL, len); 355 s->cmdfifo_cdb_offset = 0; 356 } 357 } 358 359 static void do_cmd(ESPState *s) 360 { 361 do_message_phase(s); 362 assert(s->cmdfifo_cdb_offset == 0); 363 do_command_phase(s); 364 } 365 366 static void satn_pdma_cb(ESPState *s) 367 { 368 uint8_t buf[ESP_FIFO_SZ]; 369 int n; 370 371 /* Copy FIFO into cmdfifo */ 372 n = esp_fifo_pop_buf(&s->fifo, buf, fifo8_num_used(&s->fifo)); 373 n = MIN(fifo8_num_free(&s->cmdfifo), n); 374 fifo8_push_all(&s->cmdfifo, buf, n); 375 376 if (!esp_get_tc(s) && !fifo8_is_empty(&s->cmdfifo)) { 377 s->cmdfifo_cdb_offset = 1; 378 s->do_cmd = 0; 379 do_cmd(s); 380 } 381 } 382 383 static void handle_satn(ESPState *s) 384 { 385 int32_t cmdlen; 386 387 if (s->dma && !s->dma_enabled) { 388 s->dma_cb = handle_satn; 389 return; 390 } 391 esp_set_pdma_cb(s, SATN_PDMA_CB); 392 if (esp_select(s) < 0) { 393 return; 394 } 395 cmdlen = get_cmd(s, ESP_CMDFIFO_SZ); 396 if (cmdlen > 0) { 397 s->cmdfifo_cdb_offset = 1; 398 s->do_cmd = 0; 399 do_cmd(s); 400 } else if (cmdlen == 0) { 401 if (s->dma) { 402 esp_raise_drq(s); 403 } 404 s->do_cmd = 1; 405 /* Target present, but no cmd yet - switch to command phase */ 406 s->rregs[ESP_RSEQ] = SEQ_CD; 407 esp_set_phase(s, STAT_CD); 408 } 409 } 410 411 static void s_without_satn_pdma_cb(ESPState *s) 412 { 413 uint8_t buf[ESP_FIFO_SZ]; 414 int n; 415 416 /* Copy FIFO into cmdfifo */ 417 n = esp_fifo_pop_buf(&s->fifo, buf, fifo8_num_used(&s->fifo)); 418 n = MIN(fifo8_num_free(&s->cmdfifo), n); 419 fifo8_push_all(&s->cmdfifo, buf, n); 420 421 if (!esp_get_tc(s) && !fifo8_is_empty(&s->cmdfifo)) { 422 s->cmdfifo_cdb_offset = 0; 423 s->do_cmd = 0; 424 do_cmd(s); 425 } 426 } 427 428 static void handle_s_without_atn(ESPState *s) 429 { 430 int32_t cmdlen; 431 432 if (s->dma && !s->dma_enabled) { 433 s->dma_cb = handle_s_without_atn; 434 return; 435 } 436 esp_set_pdma_cb(s, S_WITHOUT_SATN_PDMA_CB); 437 if (esp_select(s) < 0) { 438 return; 439 } 440 cmdlen = get_cmd(s, ESP_CMDFIFO_SZ); 441 if (cmdlen > 0) { 442 s->cmdfifo_cdb_offset = 0; 443 s->do_cmd = 0; 444 do_cmd(s); 445 } else if (cmdlen == 0) { 446 if (s->dma) { 447 esp_raise_drq(s); 448 } 449 s->do_cmd = 1; 450 /* Target present, but no cmd yet - switch to command phase */ 451 s->rregs[ESP_RSEQ] = SEQ_CD; 452 esp_set_phase(s, STAT_CD); 453 } 454 } 455 456 static void satn_stop_pdma_cb(ESPState *s) 457 { 458 uint8_t buf[ESP_FIFO_SZ]; 459 int n; 460 461 /* Copy FIFO into cmdfifo */ 462 n = esp_fifo_pop_buf(&s->fifo, buf, fifo8_num_used(&s->fifo)); 463 n = MIN(fifo8_num_free(&s->cmdfifo), n); 464 fifo8_push_all(&s->cmdfifo, buf, n); 465 466 if (!esp_get_tc(s) && !fifo8_is_empty(&s->cmdfifo)) { 467 trace_esp_handle_satn_stop(fifo8_num_used(&s->cmdfifo)); 468 s->do_cmd = 1; 469 s->cmdfifo_cdb_offset = 1; 470 esp_set_phase(s, STAT_CD); 471 s->rregs[ESP_RSTAT] |= STAT_TC; 472 s->rregs[ESP_RINTR] |= INTR_BS | INTR_FC; 473 s->rregs[ESP_RSEQ] = SEQ_CD; 474 esp_raise_irq(s); 475 } 476 } 477 478 static void handle_satn_stop(ESPState *s) 479 { 480 int32_t cmdlen; 481 482 if (s->dma && !s->dma_enabled) { 483 s->dma_cb = handle_satn_stop; 484 return; 485 } 486 esp_set_pdma_cb(s, SATN_STOP_PDMA_CB); 487 if (esp_select(s) < 0) { 488 return; 489 } 490 cmdlen = get_cmd(s, 1); 491 if (cmdlen > 0) { 492 trace_esp_handle_satn_stop(fifo8_num_used(&s->cmdfifo)); 493 s->do_cmd = 1; 494 s->cmdfifo_cdb_offset = 1; 495 esp_set_phase(s, STAT_MO); 496 s->rregs[ESP_RINTR] |= INTR_BS | INTR_FC; 497 s->rregs[ESP_RSEQ] = SEQ_MO; 498 esp_raise_irq(s); 499 } else if (cmdlen == 0) { 500 if (s->dma) { 501 esp_raise_drq(s); 502 } 503 s->do_cmd = 1; 504 /* Target present, switch to message out phase */ 505 s->rregs[ESP_RSEQ] = SEQ_MO; 506 esp_set_phase(s, STAT_MO); 507 } 508 } 509 510 static void write_response_pdma_cb(ESPState *s) 511 { 512 esp_set_phase(s, STAT_ST); 513 s->rregs[ESP_RINTR] |= INTR_BS | INTR_FC; 514 s->rregs[ESP_RSEQ] = SEQ_CD; 515 esp_raise_irq(s); 516 } 517 518 static void write_response(ESPState *s) 519 { 520 uint8_t buf[2]; 521 522 trace_esp_write_response(s->status); 523 524 buf[0] = s->status; 525 buf[1] = 0; 526 527 if (s->dma) { 528 if (s->dma_memory_write) { 529 s->dma_memory_write(s->dma_opaque, buf, 2); 530 esp_set_phase(s, STAT_ST); 531 s->rregs[ESP_RINTR] |= INTR_BS | INTR_FC; 532 s->rregs[ESP_RSEQ] = SEQ_CD; 533 } else { 534 esp_set_pdma_cb(s, WRITE_RESPONSE_PDMA_CB); 535 esp_raise_drq(s); 536 return; 537 } 538 } else { 539 fifo8_reset(&s->fifo); 540 fifo8_push_all(&s->fifo, buf, 2); 541 s->rregs[ESP_RFLAGS] = 2; 542 } 543 esp_raise_irq(s); 544 } 545 546 static void esp_dma_done(ESPState *s) 547 { 548 s->rregs[ESP_RINTR] |= INTR_BS; 549 esp_raise_irq(s); 550 } 551 552 static void do_dma_pdma_cb(ESPState *s) 553 { 554 int to_device = ((s->rregs[ESP_RSTAT] & 7) == STAT_DO); 555 uint8_t buf[ESP_CMDFIFO_SZ]; 556 int len; 557 uint32_t n; 558 559 if (s->do_cmd) { 560 /* Copy FIFO into cmdfifo */ 561 n = esp_fifo_pop_buf(&s->fifo, buf, fifo8_num_used(&s->fifo)); 562 n = MIN(fifo8_num_free(&s->cmdfifo), n); 563 fifo8_push_all(&s->cmdfifo, buf, n); 564 565 /* Ensure we have received complete command after SATN and stop */ 566 if (esp_get_tc(s) || fifo8_is_empty(&s->cmdfifo)) { 567 return; 568 } 569 570 s->ti_size = 0; 571 if ((s->rregs[ESP_RSTAT] & 7) == STAT_CD) { 572 /* No command received */ 573 if (s->cmdfifo_cdb_offset == fifo8_num_used(&s->cmdfifo)) { 574 return; 575 } 576 577 /* Command has been received */ 578 s->do_cmd = 0; 579 do_cmd(s); 580 } else { 581 /* 582 * Extra message out bytes received: update cmdfifo_cdb_offset 583 * and then switch to command phase 584 */ 585 s->cmdfifo_cdb_offset = fifo8_num_used(&s->cmdfifo); 586 esp_set_phase(s, STAT_CD); 587 s->rregs[ESP_RSEQ] = SEQ_CD; 588 s->rregs[ESP_RINTR] |= INTR_BS; 589 esp_raise_irq(s); 590 } 591 return; 592 } 593 594 if (!s->current_req) { 595 return; 596 } 597 598 if (to_device) { 599 /* Copy FIFO data to device */ 600 len = MIN(s->async_len, ESP_FIFO_SZ); 601 len = MIN(len, fifo8_num_used(&s->fifo)); 602 n = esp_fifo_pop_buf(&s->fifo, s->async_buf, len); 603 s->async_buf += n; 604 s->async_len -= n; 605 s->ti_size += n; 606 607 if (n < len) { 608 /* Unaligned accesses can cause FIFO wraparound */ 609 len = len - n; 610 n = esp_fifo_pop_buf(&s->fifo, s->async_buf, len); 611 s->async_buf += n; 612 s->async_len -= n; 613 s->ti_size += n; 614 } 615 616 if (s->async_len == 0) { 617 scsi_req_continue(s->current_req); 618 return; 619 } 620 621 if (esp_get_tc(s) == 0) { 622 esp_lower_drq(s); 623 esp_dma_done(s); 624 } 625 626 return; 627 } else { 628 if (s->async_len == 0 && fifo8_num_used(&s->fifo) < 2) { 629 /* Defer until the scsi layer has completed */ 630 scsi_req_continue(s->current_req); 631 s->data_in_ready = false; 632 return; 633 } 634 635 if (esp_get_tc(s) == 0 && fifo8_num_used(&s->fifo) < 2) { 636 esp_lower_drq(s); 637 esp_dma_done(s); 638 } 639 640 /* Copy device data to FIFO */ 641 len = MIN(s->async_len, esp_get_tc(s)); 642 len = MIN(len, fifo8_num_free(&s->fifo)); 643 fifo8_push_all(&s->fifo, s->async_buf, len); 644 s->async_buf += len; 645 s->async_len -= len; 646 s->ti_size -= len; 647 esp_set_tc(s, esp_get_tc(s) - len); 648 } 649 } 650 651 static void esp_do_dma(ESPState *s) 652 { 653 uint32_t len, cmdlen; 654 int to_device = ((s->rregs[ESP_RSTAT] & 7) == STAT_DO); 655 uint8_t buf[ESP_CMDFIFO_SZ]; 656 657 len = esp_get_tc(s); 658 if (s->do_cmd) { 659 /* 660 * handle_ti_cmd() case: esp_do_dma() is called only from 661 * handle_ti_cmd() with do_cmd != NULL (see the assert()) 662 */ 663 cmdlen = fifo8_num_used(&s->cmdfifo); 664 trace_esp_do_dma(cmdlen, len); 665 if (s->dma_memory_read) { 666 len = MIN(len, fifo8_num_free(&s->cmdfifo)); 667 s->dma_memory_read(s->dma_opaque, buf, len); 668 fifo8_push_all(&s->cmdfifo, buf, len); 669 esp_set_tc(s, esp_get_tc(s) - len); 670 } else { 671 esp_set_pdma_cb(s, DO_DMA_PDMA_CB); 672 esp_raise_drq(s); 673 return; 674 } 675 trace_esp_handle_ti_cmd(cmdlen); 676 s->ti_size = 0; 677 if ((s->rregs[ESP_RSTAT] & 7) == STAT_CD) { 678 /* No command received */ 679 if (s->cmdfifo_cdb_offset == fifo8_num_used(&s->cmdfifo)) { 680 return; 681 } 682 683 /* Command has been received */ 684 s->do_cmd = 0; 685 do_cmd(s); 686 } else { 687 /* 688 * Extra message out bytes received: update cmdfifo_cdb_offset 689 * and then switch to command phase 690 */ 691 s->cmdfifo_cdb_offset = fifo8_num_used(&s->cmdfifo); 692 esp_set_phase(s, STAT_CD); 693 s->rregs[ESP_RSEQ] = SEQ_CD; 694 s->rregs[ESP_RINTR] |= INTR_BS; 695 esp_raise_irq(s); 696 } 697 return; 698 } 699 if (!s->current_req) { 700 return; 701 } 702 if (s->async_len == 0) { 703 /* Defer until data is available. */ 704 return; 705 } 706 if (len > s->async_len) { 707 len = s->async_len; 708 } 709 if (to_device) { 710 if (s->dma_memory_read) { 711 s->dma_memory_read(s->dma_opaque, s->async_buf, len); 712 713 esp_set_tc(s, esp_get_tc(s) - len); 714 s->async_buf += len; 715 s->async_len -= len; 716 s->ti_size += len; 717 718 if (s->async_len == 0) { 719 scsi_req_continue(s->current_req); 720 /* 721 * If there is still data to be read from the device then 722 * complete the DMA operation immediately. Otherwise defer 723 * until the scsi layer has completed. 724 */ 725 return; 726 } 727 728 if (esp_get_tc(s) == 0) { 729 /* Partially filled a scsi buffer. Complete immediately. */ 730 esp_dma_done(s); 731 esp_lower_drq(s); 732 } 733 } else { 734 esp_set_pdma_cb(s, DO_DMA_PDMA_CB); 735 esp_raise_drq(s); 736 } 737 } else { 738 if (s->dma_memory_write) { 739 s->dma_memory_write(s->dma_opaque, s->async_buf, len); 740 741 esp_set_tc(s, esp_get_tc(s) - len); 742 s->async_buf += len; 743 s->async_len -= len; 744 s->ti_size -= len; 745 746 if (s->async_len == 0) { 747 scsi_req_continue(s->current_req); 748 return; 749 } 750 751 if (esp_get_tc(s) == 0) { 752 /* Partially filled a scsi buffer. Complete immediately. */ 753 esp_dma_done(s); 754 esp_lower_drq(s); 755 } 756 } else { 757 /* Copy device data to FIFO */ 758 len = MIN(len, fifo8_num_free(&s->fifo)); 759 fifo8_push_all(&s->fifo, s->async_buf, len); 760 s->async_buf += len; 761 s->async_len -= len; 762 s->ti_size -= len; 763 esp_set_tc(s, esp_get_tc(s) - len); 764 esp_set_pdma_cb(s, DO_DMA_PDMA_CB); 765 esp_raise_drq(s); 766 } 767 } 768 } 769 770 static void esp_do_nodma(ESPState *s) 771 { 772 int to_device = ((s->rregs[ESP_RSTAT] & 7) == STAT_DO); 773 uint8_t buf[ESP_FIFO_SZ]; 774 uint32_t cmdlen; 775 int len, n; 776 777 if (s->do_cmd) { 778 /* Copy FIFO into cmdfifo */ 779 n = esp_fifo_pop_buf(&s->fifo, buf, fifo8_num_used(&s->fifo)); 780 n = MIN(fifo8_num_free(&s->cmdfifo), n); 781 fifo8_push_all(&s->cmdfifo, buf, n); 782 783 cmdlen = fifo8_num_used(&s->cmdfifo); 784 trace_esp_handle_ti_cmd(cmdlen); 785 s->ti_size = 0; 786 if ((s->rregs[ESP_RSTAT] & 7) == STAT_CD) { 787 /* No command received */ 788 if (s->cmdfifo_cdb_offset == fifo8_num_used(&s->cmdfifo)) { 789 return; 790 } 791 792 /* Command has been received */ 793 s->do_cmd = 0; 794 do_cmd(s); 795 } else { 796 /* 797 * Extra message out bytes received: update cmdfifo_cdb_offset 798 * and then switch to command phase 799 */ 800 s->cmdfifo_cdb_offset = fifo8_num_used(&s->cmdfifo); 801 esp_set_phase(s, STAT_CD); 802 s->rregs[ESP_RSEQ] = SEQ_CD; 803 s->rregs[ESP_RINTR] |= INTR_BS; 804 esp_raise_irq(s); 805 } 806 return; 807 } 808 809 if (!s->current_req) { 810 return; 811 } 812 813 if (s->async_len == 0) { 814 /* Defer until data is available. */ 815 return; 816 } 817 818 if (to_device) { 819 len = MIN(s->async_len, ESP_FIFO_SZ); 820 len = MIN(len, fifo8_num_used(&s->fifo)); 821 esp_fifo_pop_buf(&s->fifo, s->async_buf, len); 822 s->async_buf += len; 823 s->async_len -= len; 824 s->ti_size += len; 825 } else { 826 if (fifo8_is_empty(&s->fifo)) { 827 fifo8_push(&s->fifo, s->async_buf[0]); 828 s->async_buf++; 829 s->async_len--; 830 s->ti_size--; 831 } 832 } 833 834 if (s->async_len == 0) { 835 scsi_req_continue(s->current_req); 836 return; 837 } 838 839 s->rregs[ESP_RINTR] |= INTR_BS; 840 esp_raise_irq(s); 841 } 842 843 static void esp_pdma_cb(ESPState *s) 844 { 845 switch (s->pdma_cb) { 846 case SATN_PDMA_CB: 847 satn_pdma_cb(s); 848 break; 849 case S_WITHOUT_SATN_PDMA_CB: 850 s_without_satn_pdma_cb(s); 851 break; 852 case SATN_STOP_PDMA_CB: 853 satn_stop_pdma_cb(s); 854 break; 855 case WRITE_RESPONSE_PDMA_CB: 856 write_response_pdma_cb(s); 857 break; 858 case DO_DMA_PDMA_CB: 859 do_dma_pdma_cb(s); 860 break; 861 default: 862 g_assert_not_reached(); 863 } 864 } 865 866 void esp_command_complete(SCSIRequest *req, size_t resid) 867 { 868 ESPState *s = req->hba_private; 869 int to_device = ((s->rregs[ESP_RSTAT] & 7) == STAT_DO); 870 871 trace_esp_command_complete(); 872 873 /* 874 * Non-DMA transfers from the target will leave the last byte in 875 * the FIFO so don't reset ti_size in this case 876 */ 877 if (s->dma || to_device) { 878 if (s->ti_size != 0) { 879 trace_esp_command_complete_unexpected(); 880 } 881 s->ti_size = 0; 882 } 883 884 s->async_len = 0; 885 if (req->status) { 886 trace_esp_command_complete_fail(); 887 } 888 s->status = req->status; 889 890 /* 891 * If the transfer is finished, switch to status phase. For non-DMA 892 * transfers from the target the last byte is still in the FIFO 893 */ 894 if (s->ti_size == 0) { 895 esp_set_phase(s, STAT_ST); 896 esp_dma_done(s); 897 esp_lower_drq(s); 898 } 899 900 if (s->current_req) { 901 scsi_req_unref(s->current_req); 902 s->current_req = NULL; 903 s->current_dev = NULL; 904 } 905 } 906 907 void esp_transfer_data(SCSIRequest *req, uint32_t len) 908 { 909 ESPState *s = req->hba_private; 910 int to_device = ((s->rregs[ESP_RSTAT] & 7) == STAT_DO); 911 uint32_t dmalen = esp_get_tc(s); 912 913 assert(!s->do_cmd); 914 trace_esp_transfer_data(dmalen, s->ti_size); 915 s->async_len = len; 916 s->async_buf = scsi_req_get_buf(req); 917 918 if (!to_device && !s->data_in_ready) { 919 /* 920 * Initial incoming data xfer is complete so raise command 921 * completion interrupt 922 */ 923 s->data_in_ready = true; 924 s->rregs[ESP_RINTR] |= INTR_BS; 925 esp_raise_irq(s); 926 } 927 928 if (s->ti_cmd == 0) { 929 /* 930 * Always perform the initial transfer upon reception of the next TI 931 * command to ensure the DMA/non-DMA status of the command is correct. 932 * It is not possible to use s->dma directly in the section below as 933 * some OSs send non-DMA NOP commands after a DMA transfer. Hence if the 934 * async data transfer is delayed then s->dma is set incorrectly. 935 */ 936 return; 937 } 938 939 if (s->ti_cmd == (CMD_TI | CMD_DMA)) { 940 if (dmalen) { 941 esp_do_dma(s); 942 } else if (s->ti_size <= 0) { 943 /* 944 * If this was the last part of a DMA transfer then the 945 * completion interrupt is deferred to here. 946 */ 947 esp_dma_done(s); 948 esp_lower_drq(s); 949 } 950 } else if (s->ti_cmd == CMD_TI) { 951 esp_do_nodma(s); 952 } 953 } 954 955 static void handle_ti(ESPState *s) 956 { 957 uint32_t dmalen; 958 959 if (s->dma && !s->dma_enabled) { 960 s->dma_cb = handle_ti; 961 return; 962 } 963 964 s->ti_cmd = s->rregs[ESP_CMD]; 965 if (s->dma) { 966 dmalen = esp_get_tc(s); 967 trace_esp_handle_ti(dmalen); 968 esp_do_dma(s); 969 } else { 970 trace_esp_handle_ti(s->ti_size); 971 esp_do_nodma(s); 972 } 973 } 974 975 void esp_hard_reset(ESPState *s) 976 { 977 memset(s->rregs, 0, ESP_REGS); 978 memset(s->wregs, 0, ESP_REGS); 979 s->tchi_written = 0; 980 s->ti_size = 0; 981 s->async_len = 0; 982 fifo8_reset(&s->fifo); 983 fifo8_reset(&s->cmdfifo); 984 s->dma = 0; 985 s->do_cmd = 0; 986 s->dma_cb = NULL; 987 988 s->rregs[ESP_CFG1] = 7; 989 } 990 991 static void esp_soft_reset(ESPState *s) 992 { 993 qemu_irq_lower(s->irq); 994 qemu_irq_lower(s->irq_data); 995 esp_hard_reset(s); 996 } 997 998 static void esp_bus_reset(ESPState *s) 999 { 1000 bus_cold_reset(BUS(&s->bus)); 1001 } 1002 1003 static void parent_esp_reset(ESPState *s, int irq, int level) 1004 { 1005 if (level) { 1006 esp_soft_reset(s); 1007 } 1008 } 1009 1010 static void esp_run_cmd(ESPState *s) 1011 { 1012 uint8_t cmd = s->rregs[ESP_CMD]; 1013 1014 if (cmd & CMD_DMA) { 1015 s->dma = 1; 1016 /* Reload DMA counter. */ 1017 if (esp_get_stc(s) == 0) { 1018 esp_set_tc(s, 0x10000); 1019 } else { 1020 esp_set_tc(s, esp_get_stc(s)); 1021 } 1022 } else { 1023 s->dma = 0; 1024 } 1025 switch (cmd & CMD_CMD) { 1026 case CMD_NOP: 1027 trace_esp_mem_writeb_cmd_nop(cmd); 1028 break; 1029 case CMD_FLUSH: 1030 trace_esp_mem_writeb_cmd_flush(cmd); 1031 fifo8_reset(&s->fifo); 1032 break; 1033 case CMD_RESET: 1034 trace_esp_mem_writeb_cmd_reset(cmd); 1035 esp_soft_reset(s); 1036 break; 1037 case CMD_BUSRESET: 1038 trace_esp_mem_writeb_cmd_bus_reset(cmd); 1039 esp_bus_reset(s); 1040 if (!(s->wregs[ESP_CFG1] & CFG1_RESREPT)) { 1041 s->rregs[ESP_RINTR] |= INTR_RST; 1042 esp_raise_irq(s); 1043 } 1044 break; 1045 case CMD_TI: 1046 trace_esp_mem_writeb_cmd_ti(cmd); 1047 handle_ti(s); 1048 break; 1049 case CMD_ICCS: 1050 trace_esp_mem_writeb_cmd_iccs(cmd); 1051 write_response(s); 1052 s->rregs[ESP_RINTR] |= INTR_FC; 1053 esp_set_phase(s, STAT_MI); 1054 break; 1055 case CMD_MSGACC: 1056 trace_esp_mem_writeb_cmd_msgacc(cmd); 1057 s->rregs[ESP_RINTR] |= INTR_DC; 1058 s->rregs[ESP_RSEQ] = 0; 1059 s->rregs[ESP_RFLAGS] = 0; 1060 esp_raise_irq(s); 1061 break; 1062 case CMD_PAD: 1063 trace_esp_mem_writeb_cmd_pad(cmd); 1064 s->rregs[ESP_RSTAT] = STAT_TC; 1065 s->rregs[ESP_RINTR] |= INTR_FC; 1066 s->rregs[ESP_RSEQ] = 0; 1067 break; 1068 case CMD_SATN: 1069 trace_esp_mem_writeb_cmd_satn(cmd); 1070 break; 1071 case CMD_RSTATN: 1072 trace_esp_mem_writeb_cmd_rstatn(cmd); 1073 break; 1074 case CMD_SEL: 1075 trace_esp_mem_writeb_cmd_sel(cmd); 1076 handle_s_without_atn(s); 1077 break; 1078 case CMD_SELATN: 1079 trace_esp_mem_writeb_cmd_selatn(cmd); 1080 handle_satn(s); 1081 break; 1082 case CMD_SELATNS: 1083 trace_esp_mem_writeb_cmd_selatns(cmd); 1084 handle_satn_stop(s); 1085 break; 1086 case CMD_ENSEL: 1087 trace_esp_mem_writeb_cmd_ensel(cmd); 1088 s->rregs[ESP_RINTR] = 0; 1089 break; 1090 case CMD_DISSEL: 1091 trace_esp_mem_writeb_cmd_dissel(cmd); 1092 s->rregs[ESP_RINTR] = 0; 1093 esp_raise_irq(s); 1094 break; 1095 default: 1096 trace_esp_error_unhandled_command(cmd); 1097 break; 1098 } 1099 } 1100 1101 uint64_t esp_reg_read(ESPState *s, uint32_t saddr) 1102 { 1103 uint32_t val; 1104 1105 switch (saddr) { 1106 case ESP_FIFO: 1107 if (s->dma_memory_read && s->dma_memory_write && 1108 (s->rregs[ESP_RSTAT] & STAT_PIO_MASK) == 0) { 1109 /* Data out. */ 1110 qemu_log_mask(LOG_UNIMP, "esp: PIO data read not implemented\n"); 1111 s->rregs[ESP_FIFO] = 0; 1112 } else { 1113 if ((s->rregs[ESP_RSTAT] & 0x7) == STAT_DI) { 1114 if (s->ti_size) { 1115 esp_do_nodma(s); 1116 } else { 1117 /* 1118 * The last byte of a non-DMA transfer has been read out 1119 * of the FIFO so switch to status phase 1120 */ 1121 esp_set_phase(s, STAT_ST); 1122 } 1123 } 1124 s->rregs[ESP_FIFO] = esp_fifo_pop(&s->fifo); 1125 } 1126 val = s->rregs[ESP_FIFO]; 1127 break; 1128 case ESP_RINTR: 1129 /* 1130 * Clear sequence step, interrupt register and all status bits 1131 * except TC 1132 */ 1133 val = s->rregs[ESP_RINTR]; 1134 s->rregs[ESP_RINTR] = 0; 1135 s->rregs[ESP_RSTAT] &= ~STAT_TC; 1136 /* 1137 * According to the datasheet ESP_RSEQ should be cleared, but as the 1138 * emulation currently defers information transfers to the next TI 1139 * command leave it for now so that pedantic guests such as the old 1140 * Linux 2.6 driver see the correct flags before the next SCSI phase 1141 * transition. 1142 * 1143 * s->rregs[ESP_RSEQ] = SEQ_0; 1144 */ 1145 esp_lower_irq(s); 1146 break; 1147 case ESP_TCHI: 1148 /* Return the unique id if the value has never been written */ 1149 if (!s->tchi_written) { 1150 val = s->chip_id; 1151 } else { 1152 val = s->rregs[saddr]; 1153 } 1154 break; 1155 case ESP_RFLAGS: 1156 /* Bottom 5 bits indicate number of bytes in FIFO */ 1157 val = fifo8_num_used(&s->fifo); 1158 break; 1159 default: 1160 val = s->rregs[saddr]; 1161 break; 1162 } 1163 1164 trace_esp_mem_readb(saddr, val); 1165 return val; 1166 } 1167 1168 void esp_reg_write(ESPState *s, uint32_t saddr, uint64_t val) 1169 { 1170 trace_esp_mem_writeb(saddr, s->wregs[saddr], val); 1171 switch (saddr) { 1172 case ESP_TCHI: 1173 s->tchi_written = true; 1174 /* fall through */ 1175 case ESP_TCLO: 1176 case ESP_TCMID: 1177 s->rregs[ESP_RSTAT] &= ~STAT_TC; 1178 break; 1179 case ESP_FIFO: 1180 if (s->do_cmd) { 1181 if (!fifo8_is_full(&s->fifo)) { 1182 esp_fifo_push(&s->fifo, val); 1183 esp_fifo_push(&s->cmdfifo, fifo8_pop(&s->fifo)); 1184 } 1185 1186 /* 1187 * If any unexpected message out/command phase data is 1188 * transferred using non-DMA, raise the interrupt 1189 */ 1190 if (s->rregs[ESP_CMD] == CMD_TI) { 1191 s->rregs[ESP_RINTR] |= INTR_BS; 1192 esp_raise_irq(s); 1193 } 1194 } else { 1195 esp_fifo_push(&s->fifo, val); 1196 } 1197 break; 1198 case ESP_CMD: 1199 s->rregs[saddr] = val; 1200 esp_run_cmd(s); 1201 break; 1202 case ESP_WBUSID ... ESP_WSYNO: 1203 break; 1204 case ESP_CFG1: 1205 case ESP_CFG2: case ESP_CFG3: 1206 case ESP_RES3: case ESP_RES4: 1207 s->rregs[saddr] = val; 1208 break; 1209 case ESP_WCCF ... ESP_WTEST: 1210 break; 1211 default: 1212 trace_esp_error_invalid_write(val, saddr); 1213 return; 1214 } 1215 s->wregs[saddr] = val; 1216 } 1217 1218 static bool esp_mem_accepts(void *opaque, hwaddr addr, 1219 unsigned size, bool is_write, 1220 MemTxAttrs attrs) 1221 { 1222 return (size == 1) || (is_write && size == 4); 1223 } 1224 1225 static bool esp_is_before_version_5(void *opaque, int version_id) 1226 { 1227 ESPState *s = ESP(opaque); 1228 1229 version_id = MIN(version_id, s->mig_version_id); 1230 return version_id < 5; 1231 } 1232 1233 static bool esp_is_version_5(void *opaque, int version_id) 1234 { 1235 ESPState *s = ESP(opaque); 1236 1237 version_id = MIN(version_id, s->mig_version_id); 1238 return version_id >= 5; 1239 } 1240 1241 static bool esp_is_version_6(void *opaque, int version_id) 1242 { 1243 ESPState *s = ESP(opaque); 1244 1245 version_id = MIN(version_id, s->mig_version_id); 1246 return version_id >= 6; 1247 } 1248 1249 int esp_pre_save(void *opaque) 1250 { 1251 ESPState *s = ESP(object_resolve_path_component( 1252 OBJECT(opaque), "esp")); 1253 1254 s->mig_version_id = vmstate_esp.version_id; 1255 return 0; 1256 } 1257 1258 static int esp_post_load(void *opaque, int version_id) 1259 { 1260 ESPState *s = ESP(opaque); 1261 int len, i; 1262 1263 version_id = MIN(version_id, s->mig_version_id); 1264 1265 if (version_id < 5) { 1266 esp_set_tc(s, s->mig_dma_left); 1267 1268 /* Migrate ti_buf to fifo */ 1269 len = s->mig_ti_wptr - s->mig_ti_rptr; 1270 for (i = 0; i < len; i++) { 1271 fifo8_push(&s->fifo, s->mig_ti_buf[i]); 1272 } 1273 1274 /* Migrate cmdbuf to cmdfifo */ 1275 for (i = 0; i < s->mig_cmdlen; i++) { 1276 fifo8_push(&s->cmdfifo, s->mig_cmdbuf[i]); 1277 } 1278 } 1279 1280 s->mig_version_id = vmstate_esp.version_id; 1281 return 0; 1282 } 1283 1284 /* 1285 * PDMA (or pseudo-DMA) is only used on the Macintosh and requires the 1286 * guest CPU to perform the transfers between the SCSI bus and memory 1287 * itself. This is indicated by the dma_memory_read and dma_memory_write 1288 * functions being NULL (in contrast to the ESP PCI device) whilst 1289 * dma_enabled is still set. 1290 */ 1291 1292 static bool esp_pdma_needed(void *opaque) 1293 { 1294 ESPState *s = ESP(opaque); 1295 1296 return s->dma_memory_read == NULL && s->dma_memory_write == NULL && 1297 s->dma_enabled; 1298 } 1299 1300 static const VMStateDescription vmstate_esp_pdma = { 1301 .name = "esp/pdma", 1302 .version_id = 0, 1303 .minimum_version_id = 0, 1304 .needed = esp_pdma_needed, 1305 .fields = (const VMStateField[]) { 1306 VMSTATE_UINT8(pdma_cb, ESPState), 1307 VMSTATE_END_OF_LIST() 1308 } 1309 }; 1310 1311 const VMStateDescription vmstate_esp = { 1312 .name = "esp", 1313 .version_id = 6, 1314 .minimum_version_id = 3, 1315 .post_load = esp_post_load, 1316 .fields = (const VMStateField[]) { 1317 VMSTATE_BUFFER(rregs, ESPState), 1318 VMSTATE_BUFFER(wregs, ESPState), 1319 VMSTATE_INT32(ti_size, ESPState), 1320 VMSTATE_UINT32_TEST(mig_ti_rptr, ESPState, esp_is_before_version_5), 1321 VMSTATE_UINT32_TEST(mig_ti_wptr, ESPState, esp_is_before_version_5), 1322 VMSTATE_BUFFER_TEST(mig_ti_buf, ESPState, esp_is_before_version_5), 1323 VMSTATE_UINT32(status, ESPState), 1324 VMSTATE_UINT32_TEST(mig_deferred_status, ESPState, 1325 esp_is_before_version_5), 1326 VMSTATE_BOOL_TEST(mig_deferred_complete, ESPState, 1327 esp_is_before_version_5), 1328 VMSTATE_UINT32(dma, ESPState), 1329 VMSTATE_STATIC_BUFFER(mig_cmdbuf, ESPState, 0, 1330 esp_is_before_version_5, 0, 16), 1331 VMSTATE_STATIC_BUFFER(mig_cmdbuf, ESPState, 4, 1332 esp_is_before_version_5, 16, 1333 sizeof(typeof_field(ESPState, mig_cmdbuf))), 1334 VMSTATE_UINT32_TEST(mig_cmdlen, ESPState, esp_is_before_version_5), 1335 VMSTATE_UINT32(do_cmd, ESPState), 1336 VMSTATE_UINT32_TEST(mig_dma_left, ESPState, esp_is_before_version_5), 1337 VMSTATE_BOOL_TEST(data_in_ready, ESPState, esp_is_version_5), 1338 VMSTATE_UINT8_TEST(cmdfifo_cdb_offset, ESPState, esp_is_version_5), 1339 VMSTATE_FIFO8_TEST(fifo, ESPState, esp_is_version_5), 1340 VMSTATE_FIFO8_TEST(cmdfifo, ESPState, esp_is_version_5), 1341 VMSTATE_UINT8_TEST(ti_cmd, ESPState, esp_is_version_5), 1342 VMSTATE_UINT8_TEST(lun, ESPState, esp_is_version_6), 1343 VMSTATE_END_OF_LIST() 1344 }, 1345 .subsections = (const VMStateDescription * const []) { 1346 &vmstate_esp_pdma, 1347 NULL 1348 } 1349 }; 1350 1351 static void sysbus_esp_mem_write(void *opaque, hwaddr addr, 1352 uint64_t val, unsigned int size) 1353 { 1354 SysBusESPState *sysbus = opaque; 1355 ESPState *s = ESP(&sysbus->esp); 1356 uint32_t saddr; 1357 1358 saddr = addr >> sysbus->it_shift; 1359 esp_reg_write(s, saddr, val); 1360 } 1361 1362 static uint64_t sysbus_esp_mem_read(void *opaque, hwaddr addr, 1363 unsigned int size) 1364 { 1365 SysBusESPState *sysbus = opaque; 1366 ESPState *s = ESP(&sysbus->esp); 1367 uint32_t saddr; 1368 1369 saddr = addr >> sysbus->it_shift; 1370 return esp_reg_read(s, saddr); 1371 } 1372 1373 static const MemoryRegionOps sysbus_esp_mem_ops = { 1374 .read = sysbus_esp_mem_read, 1375 .write = sysbus_esp_mem_write, 1376 .endianness = DEVICE_NATIVE_ENDIAN, 1377 .valid.accepts = esp_mem_accepts, 1378 }; 1379 1380 static void sysbus_esp_pdma_write(void *opaque, hwaddr addr, 1381 uint64_t val, unsigned int size) 1382 { 1383 SysBusESPState *sysbus = opaque; 1384 ESPState *s = ESP(&sysbus->esp); 1385 1386 trace_esp_pdma_write(size); 1387 1388 switch (size) { 1389 case 1: 1390 esp_pdma_write(s, val); 1391 break; 1392 case 2: 1393 esp_pdma_write(s, val >> 8); 1394 esp_pdma_write(s, val); 1395 break; 1396 } 1397 esp_pdma_cb(s); 1398 } 1399 1400 static uint64_t sysbus_esp_pdma_read(void *opaque, hwaddr addr, 1401 unsigned int size) 1402 { 1403 SysBusESPState *sysbus = opaque; 1404 ESPState *s = ESP(&sysbus->esp); 1405 uint64_t val = 0; 1406 1407 trace_esp_pdma_read(size); 1408 1409 switch (size) { 1410 case 1: 1411 val = esp_pdma_read(s); 1412 break; 1413 case 2: 1414 val = esp_pdma_read(s); 1415 val = (val << 8) | esp_pdma_read(s); 1416 break; 1417 } 1418 esp_pdma_cb(s); 1419 return val; 1420 } 1421 1422 static void *esp_load_request(QEMUFile *f, SCSIRequest *req) 1423 { 1424 ESPState *s = container_of(req->bus, ESPState, bus); 1425 1426 scsi_req_ref(req); 1427 s->current_req = req; 1428 return s; 1429 } 1430 1431 static const MemoryRegionOps sysbus_esp_pdma_ops = { 1432 .read = sysbus_esp_pdma_read, 1433 .write = sysbus_esp_pdma_write, 1434 .endianness = DEVICE_NATIVE_ENDIAN, 1435 .valid.min_access_size = 1, 1436 .valid.max_access_size = 4, 1437 .impl.min_access_size = 1, 1438 .impl.max_access_size = 2, 1439 }; 1440 1441 static const struct SCSIBusInfo esp_scsi_info = { 1442 .tcq = false, 1443 .max_target = ESP_MAX_DEVS, 1444 .max_lun = 7, 1445 1446 .load_request = esp_load_request, 1447 .transfer_data = esp_transfer_data, 1448 .complete = esp_command_complete, 1449 .cancel = esp_request_cancelled 1450 }; 1451 1452 static void sysbus_esp_gpio_demux(void *opaque, int irq, int level) 1453 { 1454 SysBusESPState *sysbus = SYSBUS_ESP(opaque); 1455 ESPState *s = ESP(&sysbus->esp); 1456 1457 switch (irq) { 1458 case 0: 1459 parent_esp_reset(s, irq, level); 1460 break; 1461 case 1: 1462 esp_dma_enable(s, irq, level); 1463 break; 1464 } 1465 } 1466 1467 static void sysbus_esp_realize(DeviceState *dev, Error **errp) 1468 { 1469 SysBusDevice *sbd = SYS_BUS_DEVICE(dev); 1470 SysBusESPState *sysbus = SYSBUS_ESP(dev); 1471 ESPState *s = ESP(&sysbus->esp); 1472 1473 if (!qdev_realize(DEVICE(s), NULL, errp)) { 1474 return; 1475 } 1476 1477 sysbus_init_irq(sbd, &s->irq); 1478 sysbus_init_irq(sbd, &s->irq_data); 1479 assert(sysbus->it_shift != -1); 1480 1481 s->chip_id = TCHI_FAS100A; 1482 memory_region_init_io(&sysbus->iomem, OBJECT(sysbus), &sysbus_esp_mem_ops, 1483 sysbus, "esp-regs", ESP_REGS << sysbus->it_shift); 1484 sysbus_init_mmio(sbd, &sysbus->iomem); 1485 memory_region_init_io(&sysbus->pdma, OBJECT(sysbus), &sysbus_esp_pdma_ops, 1486 sysbus, "esp-pdma", 4); 1487 sysbus_init_mmio(sbd, &sysbus->pdma); 1488 1489 qdev_init_gpio_in(dev, sysbus_esp_gpio_demux, 2); 1490 1491 scsi_bus_init(&s->bus, sizeof(s->bus), dev, &esp_scsi_info); 1492 } 1493 1494 static void sysbus_esp_hard_reset(DeviceState *dev) 1495 { 1496 SysBusESPState *sysbus = SYSBUS_ESP(dev); 1497 ESPState *s = ESP(&sysbus->esp); 1498 1499 esp_hard_reset(s); 1500 } 1501 1502 static void sysbus_esp_init(Object *obj) 1503 { 1504 SysBusESPState *sysbus = SYSBUS_ESP(obj); 1505 1506 object_initialize_child(obj, "esp", &sysbus->esp, TYPE_ESP); 1507 } 1508 1509 static const VMStateDescription vmstate_sysbus_esp_scsi = { 1510 .name = "sysbusespscsi", 1511 .version_id = 2, 1512 .minimum_version_id = 1, 1513 .pre_save = esp_pre_save, 1514 .fields = (const VMStateField[]) { 1515 VMSTATE_UINT8_V(esp.mig_version_id, SysBusESPState, 2), 1516 VMSTATE_STRUCT(esp, SysBusESPState, 0, vmstate_esp, ESPState), 1517 VMSTATE_END_OF_LIST() 1518 } 1519 }; 1520 1521 static void sysbus_esp_class_init(ObjectClass *klass, void *data) 1522 { 1523 DeviceClass *dc = DEVICE_CLASS(klass); 1524 1525 dc->realize = sysbus_esp_realize; 1526 dc->reset = sysbus_esp_hard_reset; 1527 dc->vmsd = &vmstate_sysbus_esp_scsi; 1528 set_bit(DEVICE_CATEGORY_STORAGE, dc->categories); 1529 } 1530 1531 static const TypeInfo sysbus_esp_info = { 1532 .name = TYPE_SYSBUS_ESP, 1533 .parent = TYPE_SYS_BUS_DEVICE, 1534 .instance_init = sysbus_esp_init, 1535 .instance_size = sizeof(SysBusESPState), 1536 .class_init = sysbus_esp_class_init, 1537 }; 1538 1539 static void esp_finalize(Object *obj) 1540 { 1541 ESPState *s = ESP(obj); 1542 1543 fifo8_destroy(&s->fifo); 1544 fifo8_destroy(&s->cmdfifo); 1545 } 1546 1547 static void esp_init(Object *obj) 1548 { 1549 ESPState *s = ESP(obj); 1550 1551 fifo8_create(&s->fifo, ESP_FIFO_SZ); 1552 fifo8_create(&s->cmdfifo, ESP_CMDFIFO_SZ); 1553 } 1554 1555 static void esp_class_init(ObjectClass *klass, void *data) 1556 { 1557 DeviceClass *dc = DEVICE_CLASS(klass); 1558 1559 /* internal device for sysbusesp/pciespscsi, not user-creatable */ 1560 dc->user_creatable = false; 1561 set_bit(DEVICE_CATEGORY_STORAGE, dc->categories); 1562 } 1563 1564 static const TypeInfo esp_info = { 1565 .name = TYPE_ESP, 1566 .parent = TYPE_DEVICE, 1567 .instance_init = esp_init, 1568 .instance_finalize = esp_finalize, 1569 .instance_size = sizeof(ESPState), 1570 .class_init = esp_class_init, 1571 }; 1572 1573 static void esp_register_types(void) 1574 { 1575 type_register_static(&sysbus_esp_info); 1576 type_register_static(&esp_info); 1577 } 1578 1579 type_init(esp_register_types) 1580