1 /* 2 * QEMU M48T59 and M48T08 NVRAM emulation (ISA bus interface) 3 * 4 * Copyright (c) 2003-2005, 2007 Jocelyn Mayer 5 * Copyright (c) 2013 Hervé Poussineau 6 * 7 * Permission is hereby granted, free of charge, to any person obtaining a copy 8 * of this software and associated documentation files (the "Software"), to deal 9 * in the Software without restriction, including without limitation the rights 10 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 11 * copies of the Software, and to permit persons to whom the Software is 12 * furnished to do so, subject to the following conditions: 13 * 14 * The above copyright notice and this permission notice shall be included in 15 * all copies or substantial portions of the Software. 16 * 17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 22 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 23 * THE SOFTWARE. 24 */ 25 26 #include "qemu/osdep.h" 27 #include "hw/isa/isa.h" 28 #include "hw/qdev-properties.h" 29 #include "hw/rtc/m48t59.h" 30 #include "m48t59-internal.h" 31 #include "qapi/error.h" 32 #include "qemu/module.h" 33 #include "qom/object.h" 34 35 #define TYPE_M48TXX_ISA "isa-m48txx" 36 typedef struct M48txxISADeviceClass M48txxISADeviceClass; 37 typedef struct M48txxISAState M48txxISAState; 38 DECLARE_OBJ_CHECKERS(M48txxISAState, M48txxISADeviceClass, 39 M48TXX_ISA, TYPE_M48TXX_ISA) 40 41 struct M48txxISAState { 42 ISADevice parent_obj; 43 M48t59State state; 44 uint32_t io_base; 45 uint8_t isairq; 46 MemoryRegion io; 47 }; 48 49 struct M48txxISADeviceClass { 50 DeviceClass parent_class; 51 M48txxInfo info; 52 }; 53 54 static M48txxInfo m48txx_isa_info[] = { 55 { 56 .bus_name = "isa-m48t59", 57 .model = 59, 58 .size = 0x2000, 59 } 60 }; 61 62 static uint32_t m48txx_isa_read(Nvram *obj, uint32_t addr) 63 { 64 M48txxISAState *d = M48TXX_ISA(obj); 65 return m48t59_read(&d->state, addr); 66 } 67 68 static void m48txx_isa_write(Nvram *obj, uint32_t addr, uint32_t val) 69 { 70 M48txxISAState *d = M48TXX_ISA(obj); 71 m48t59_write(&d->state, addr, val); 72 } 73 74 static void m48txx_isa_toggle_lock(Nvram *obj, int lock) 75 { 76 M48txxISAState *d = M48TXX_ISA(obj); 77 m48t59_toggle_lock(&d->state, lock); 78 } 79 80 static const Property m48t59_isa_properties[] = { 81 DEFINE_PROP_INT32("base-year", M48txxISAState, state.base_year, 0), 82 DEFINE_PROP_UINT32("iobase", M48txxISAState, io_base, 0x74), 83 DEFINE_PROP_UINT8("irq", M48txxISAState, isairq, 8), 84 }; 85 86 static void m48t59_reset_isa(DeviceState *d) 87 { 88 M48txxISAState *isa = M48TXX_ISA(d); 89 M48t59State *NVRAM = &isa->state; 90 91 m48t59_reset_common(NVRAM); 92 } 93 94 static void m48t59_isa_realize(DeviceState *dev, Error **errp) 95 { 96 M48txxISADeviceClass *u = M48TXX_ISA_GET_CLASS(dev); 97 ISADevice *isadev = ISA_DEVICE(dev); 98 M48txxISAState *d = M48TXX_ISA(dev); 99 M48t59State *s = &d->state; 100 101 if (d->isairq >= ISA_NUM_IRQS) { 102 error_setg(errp, "Maximum value for \"irq\" is: %u", ISA_NUM_IRQS - 1); 103 return; 104 } 105 106 s->model = u->info.model; 107 s->size = u->info.size; 108 s->IRQ = isa_get_irq(isadev, d->isairq); 109 m48t59_realize_common(s, errp); 110 memory_region_init_io(&d->io, OBJECT(dev), &m48t59_io_ops, s, "m48t59", 4); 111 if (d->io_base != 0) { 112 isa_register_ioport(isadev, &d->io, d->io_base); 113 } 114 } 115 116 static void m48txx_isa_class_init(ObjectClass *klass, void *data) 117 { 118 DeviceClass *dc = DEVICE_CLASS(klass); 119 NvramClass *nc = NVRAM_CLASS(klass); 120 121 dc->realize = m48t59_isa_realize; 122 device_class_set_legacy_reset(dc, m48t59_reset_isa); 123 device_class_set_props(dc, m48t59_isa_properties); 124 nc->read = m48txx_isa_read; 125 nc->write = m48txx_isa_write; 126 nc->toggle_lock = m48txx_isa_toggle_lock; 127 } 128 129 static void m48txx_isa_concrete_class_init(ObjectClass *klass, void *data) 130 { 131 M48txxISADeviceClass *u = M48TXX_ISA_CLASS(klass); 132 const M48txxInfo *info = data; 133 134 u->info = *info; 135 } 136 137 static const TypeInfo m48txx_isa_type_info = { 138 .name = TYPE_M48TXX_ISA, 139 .parent = TYPE_ISA_DEVICE, 140 .instance_size = sizeof(M48txxISAState), 141 .abstract = true, 142 .class_init = m48txx_isa_class_init, 143 .interfaces = (InterfaceInfo[]) { 144 { TYPE_NVRAM }, 145 { } 146 } 147 }; 148 149 static void m48t59_isa_register_types(void) 150 { 151 TypeInfo isa_type_info = { 152 .parent = TYPE_M48TXX_ISA, 153 .class_size = sizeof(M48txxISADeviceClass), 154 .class_init = m48txx_isa_concrete_class_init, 155 }; 156 int i; 157 158 type_register_static(&m48txx_isa_type_info); 159 160 for (i = 0; i < ARRAY_SIZE(m48txx_isa_info); i++) { 161 isa_type_info.name = m48txx_isa_info[i].bus_name; 162 isa_type_info.class_data = &m48txx_isa_info[i]; 163 type_register_static(&isa_type_info); 164 } 165 } 166 167 type_init(m48t59_isa_register_types) 168