1 /* 2 * Support for generating ACPI tables and passing them to Guests 3 * 4 * RISC-V virt ACPI generation 5 * 6 * Copyright (C) 2008-2010 Kevin O'Connor <kevin@koconnor.net> 7 * Copyright (C) 2006 Fabrice Bellard 8 * Copyright (C) 2013 Red Hat Inc 9 * Copyright (c) 2015 HUAWEI TECHNOLOGIES CO.,LTD. 10 * Copyright (C) 2021-2023 Ventana Micro Systems Inc 11 * 12 * This program is free software; you can redistribute it and/or modify 13 * it under the terms of the GNU General Public License as published by 14 * the Free Software Foundation; either version 2 of the License, or 15 * (at your option) any later version. 16 17 * This program is distributed in the hope that it will be useful, 18 * but WITHOUT ANY WARRANTY; without even the implied warranty of 19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 20 * GNU General Public License for more details. 21 22 * You should have received a copy of the GNU General Public License along 23 * with this program; if not, see <http://www.gnu.org/licenses/>. 24 */ 25 26 #include "qemu/osdep.h" 27 #include "hw/acpi/acpi-defs.h" 28 #include "hw/acpi/acpi.h" 29 #include "hw/acpi/aml-build.h" 30 #include "hw/acpi/pci.h" 31 #include "hw/acpi/utils.h" 32 #include "hw/intc/riscv_aclint.h" 33 #include "hw/nvram/fw_cfg_acpi.h" 34 #include "hw/pci-host/gpex.h" 35 #include "hw/riscv/virt.h" 36 #include "hw/riscv/numa.h" 37 #include "hw/virtio/virtio-acpi.h" 38 #include "migration/vmstate.h" 39 #include "qapi/error.h" 40 #include "qemu/error-report.h" 41 #include "system/reset.h" 42 43 #define ACPI_BUILD_TABLE_SIZE 0x20000 44 #define ACPI_BUILD_INTC_ID(socket, index) ((socket << 24) | (index)) 45 46 typedef struct AcpiBuildState { 47 /* Copy of table in RAM (for patching) */ 48 MemoryRegion *table_mr; 49 MemoryRegion *rsdp_mr; 50 MemoryRegion *linker_mr; 51 /* Is table patched? */ 52 bool patched; 53 } AcpiBuildState; 54 55 static void acpi_align_size(GArray *blob, unsigned align) 56 { 57 /* 58 * Align size to multiple of given size. This reduces the chance 59 * we need to change size in the future (breaking cross version migration). 60 */ 61 g_array_set_size(blob, ROUND_UP(acpi_data_len(blob), align)); 62 } 63 64 static void riscv_acpi_madt_add_rintc(uint32_t uid, 65 const CPUArchIdList *arch_ids, 66 GArray *entry, 67 RISCVVirtState *s) 68 { 69 uint8_t guest_index_bits = imsic_num_bits(s->aia_guests + 1); 70 uint64_t hart_id = arch_ids->cpus[uid].arch_id; 71 uint32_t imsic_size, local_cpu_id, socket_id; 72 uint64_t imsic_socket_addr, imsic_addr; 73 MachineState *ms = MACHINE(s); 74 75 socket_id = arch_ids->cpus[uid].props.node_id; 76 local_cpu_id = (arch_ids->cpus[uid].arch_id - 77 riscv_socket_first_hartid(ms, socket_id)) % 78 riscv_socket_hart_count(ms, socket_id); 79 imsic_socket_addr = s->memmap[VIRT_IMSIC_S].base + 80 (socket_id * VIRT_IMSIC_GROUP_MAX_SIZE); 81 imsic_size = IMSIC_HART_SIZE(guest_index_bits); 82 imsic_addr = imsic_socket_addr + local_cpu_id * imsic_size; 83 build_append_int_noprefix(entry, 0x18, 1); /* Type */ 84 build_append_int_noprefix(entry, 36, 1); /* Length */ 85 build_append_int_noprefix(entry, 1, 1); /* Version */ 86 build_append_int_noprefix(entry, 0, 1); /* Reserved */ 87 build_append_int_noprefix(entry, 0x1, 4); /* Flags */ 88 build_append_int_noprefix(entry, hart_id, 8); /* Hart ID */ 89 build_append_int_noprefix(entry, uid, 4); /* ACPI Processor UID */ 90 /* External Interrupt Controller ID */ 91 if (s->aia_type == VIRT_AIA_TYPE_APLIC) { 92 build_append_int_noprefix(entry, 93 ACPI_BUILD_INTC_ID( 94 arch_ids->cpus[uid].props.node_id, 95 local_cpu_id), 96 4); 97 } else if (s->aia_type == VIRT_AIA_TYPE_NONE) { 98 build_append_int_noprefix(entry, 99 ACPI_BUILD_INTC_ID( 100 arch_ids->cpus[uid].props.node_id, 101 2 * local_cpu_id + 1), 102 4); 103 } else { 104 build_append_int_noprefix(entry, 0, 4); 105 } 106 107 if (s->aia_type == VIRT_AIA_TYPE_APLIC_IMSIC) { 108 /* IMSIC Base address */ 109 build_append_int_noprefix(entry, imsic_addr, 8); 110 /* IMSIC Size */ 111 build_append_int_noprefix(entry, imsic_size, 4); 112 } else { 113 build_append_int_noprefix(entry, 0, 8); 114 build_append_int_noprefix(entry, 0, 4); 115 } 116 } 117 118 static void acpi_dsdt_add_cpus(Aml *scope, RISCVVirtState *s) 119 { 120 MachineClass *mc = MACHINE_GET_CLASS(s); 121 MachineState *ms = MACHINE(s); 122 const CPUArchIdList *arch_ids = mc->possible_cpu_arch_ids(ms); 123 124 for (int i = 0; i < arch_ids->len; i++) { 125 Aml *dev; 126 GArray *madt_buf = g_array_new(0, 1, 1); 127 128 dev = aml_device("C%.03X", i); 129 aml_append(dev, aml_name_decl("_HID", aml_string("ACPI0007"))); 130 aml_append(dev, aml_name_decl("_UID", 131 aml_int(arch_ids->cpus[i].arch_id))); 132 133 /* build _MAT object */ 134 riscv_acpi_madt_add_rintc(i, arch_ids, madt_buf, s); 135 aml_append(dev, aml_name_decl("_MAT", 136 aml_buffer(madt_buf->len, 137 (uint8_t *)madt_buf->data))); 138 g_array_free(madt_buf, true); 139 140 aml_append(scope, dev); 141 } 142 } 143 144 static void acpi_dsdt_add_plic_aplic(Aml *scope, uint8_t socket_count, 145 uint64_t mmio_base, uint64_t mmio_size, 146 const char *hid) 147 { 148 uint64_t plic_aplic_addr; 149 uint32_t gsi_base; 150 uint8_t socket; 151 152 for (socket = 0; socket < socket_count; socket++) { 153 plic_aplic_addr = mmio_base + mmio_size * socket; 154 gsi_base = VIRT_IRQCHIP_NUM_SOURCES * socket; 155 Aml *dev = aml_device("IC%.02X", socket); 156 aml_append(dev, aml_name_decl("_HID", aml_string("%s", hid))); 157 aml_append(dev, aml_name_decl("_UID", aml_int(socket))); 158 aml_append(dev, aml_name_decl("_GSB", aml_int(gsi_base))); 159 160 Aml *crs = aml_resource_template(); 161 aml_append(crs, aml_memory32_fixed(plic_aplic_addr, mmio_size, 162 AML_READ_WRITE)); 163 aml_append(dev, aml_name_decl("_CRS", crs)); 164 aml_append(scope, dev); 165 } 166 } 167 168 static void 169 acpi_dsdt_add_uart(Aml *scope, const MemMapEntry *uart_memmap, 170 uint32_t uart_irq) 171 { 172 Aml *dev = aml_device("COM0"); 173 aml_append(dev, aml_name_decl("_HID", aml_string("RSCV0003"))); 174 aml_append(dev, aml_name_decl("_UID", aml_int(0))); 175 176 Aml *crs = aml_resource_template(); 177 aml_append(crs, aml_memory32_fixed(uart_memmap->base, 178 uart_memmap->size, AML_READ_WRITE)); 179 aml_append(crs, 180 aml_interrupt(AML_CONSUMER, AML_LEVEL, AML_ACTIVE_HIGH, 181 AML_EXCLUSIVE, &uart_irq, 1)); 182 aml_append(dev, aml_name_decl("_CRS", crs)); 183 184 Aml *pkg = aml_package(2); 185 aml_append(pkg, aml_string("clock-frequency")); 186 aml_append(pkg, aml_int(3686400)); 187 188 Aml *UUID = aml_touuid("DAFFD814-6EBA-4D8C-8A91-BC9BBF4AA301"); 189 190 Aml *pkg1 = aml_package(1); 191 aml_append(pkg1, pkg); 192 193 Aml *package = aml_package(2); 194 aml_append(package, UUID); 195 aml_append(package, pkg1); 196 197 aml_append(dev, aml_name_decl("_DSD", package)); 198 aml_append(scope, dev); 199 } 200 201 /* 202 * Serial Port Console Redirection Table (SPCR) 203 * Rev: 1.10 204 */ 205 206 static void 207 spcr_setup(GArray *table_data, BIOSLinker *linker, RISCVVirtState *s) 208 { 209 const char name[] = "."; 210 AcpiSpcrData serial = { 211 .interface_type = 0x12, /* 16550 compatible */ 212 .base_addr.id = AML_AS_SYSTEM_MEMORY, 213 .base_addr.width = 32, 214 .base_addr.offset = 0, 215 .base_addr.size = 1, 216 .base_addr.addr = s->memmap[VIRT_UART0].base, 217 .interrupt_type = (1 << 4),/* Bit[4] RISC-V PLIC/APLIC */ 218 .pc_interrupt = 0, 219 .interrupt = UART0_IRQ, 220 .baud_rate = 7, /* 15200 */ 221 .parity = 0, 222 .stop_bits = 1, 223 .flow_control = 0, 224 .terminal_type = 3, /* ANSI */ 225 .language = 0, /* Language */ 226 .pci_device_id = 0xffff, /* not a PCI device*/ 227 .pci_vendor_id = 0xffff, /* not a PCI device*/ 228 .pci_bus = 0, 229 .pci_device = 0, 230 .pci_function = 0, 231 .pci_flags = 0, 232 .pci_segment = 0, 233 .uart_clk_freq = 0, 234 .precise_baudrate = 0, 235 .namespace_string_length = sizeof(name), 236 .namespace_string_offset = 88, 237 }; 238 239 build_spcr(table_data, linker, &serial, 4, s->oem_id, s->oem_table_id, 240 name); 241 } 242 243 /* RHCT Node[N] starts at offset 56 */ 244 #define RHCT_NODE_ARRAY_OFFSET 56 245 246 /* 247 * ACPI spec, Revision 6.5+ 248 * 5.2.36 RISC-V Hart Capabilities Table (RHCT) 249 * REF: https://github.com/riscv-non-isa/riscv-acpi/issues/16 250 * https://drive.google.com/file/d/1nP3nFiH4jkPMp6COOxP6123DCZKR-tia/view 251 * https://drive.google.com/file/d/1sKbOa8m1UZw1JkquZYe3F1zQBN1xXsaf/view 252 */ 253 static void build_rhct(GArray *table_data, 254 BIOSLinker *linker, 255 RISCVVirtState *s) 256 { 257 MachineClass *mc = MACHINE_GET_CLASS(s); 258 MachineState *ms = MACHINE(s); 259 const CPUArchIdList *arch_ids = mc->possible_cpu_arch_ids(ms); 260 size_t len, aligned_len; 261 uint32_t isa_offset, num_rhct_nodes, cmo_offset = 0; 262 RISCVCPU *cpu = &s->soc[0].harts[0]; 263 uint32_t mmu_offset = 0; 264 uint8_t satp_mode_max; 265 g_autofree char *isa = NULL; 266 267 AcpiTable table = { .sig = "RHCT", .rev = 1, .oem_id = s->oem_id, 268 .oem_table_id = s->oem_table_id }; 269 270 acpi_table_begin(&table, table_data); 271 272 build_append_int_noprefix(table_data, 0x0, 4); /* Reserved */ 273 274 /* Time Base Frequency */ 275 build_append_int_noprefix(table_data, 276 RISCV_ACLINT_DEFAULT_TIMEBASE_FREQ, 8); 277 278 /* ISA + N hart info */ 279 num_rhct_nodes = 1 + ms->smp.cpus; 280 if (cpu->cfg.ext_zicbom || cpu->cfg.ext_zicboz) { 281 num_rhct_nodes++; 282 } 283 284 if (cpu->cfg.satp_mode.supported != 0) { 285 num_rhct_nodes++; 286 } 287 288 /* Number of RHCT nodes*/ 289 build_append_int_noprefix(table_data, num_rhct_nodes, 4); 290 291 /* Offset to the RHCT node array */ 292 build_append_int_noprefix(table_data, RHCT_NODE_ARRAY_OFFSET, 4); 293 294 /* ISA String Node */ 295 isa_offset = table_data->len - table.table_offset; 296 build_append_int_noprefix(table_data, 0, 2); /* Type 0 */ 297 298 isa = riscv_isa_string(cpu); 299 len = 8 + strlen(isa) + 1; 300 aligned_len = (len % 2) ? (len + 1) : len; 301 302 build_append_int_noprefix(table_data, aligned_len, 2); /* Length */ 303 build_append_int_noprefix(table_data, 0x1, 2); /* Revision */ 304 305 /* ISA string length including NUL */ 306 build_append_int_noprefix(table_data, strlen(isa) + 1, 2); 307 g_array_append_vals(table_data, isa, strlen(isa) + 1); /* ISA string */ 308 309 if (aligned_len != len) { 310 build_append_int_noprefix(table_data, 0x0, 1); /* Optional Padding */ 311 } 312 313 /* CMO node */ 314 if (cpu->cfg.ext_zicbom || cpu->cfg.ext_zicboz) { 315 cmo_offset = table_data->len - table.table_offset; 316 build_append_int_noprefix(table_data, 1, 2); /* Type */ 317 build_append_int_noprefix(table_data, 10, 2); /* Length */ 318 build_append_int_noprefix(table_data, 0x1, 2); /* Revision */ 319 build_append_int_noprefix(table_data, 0, 1); /* Reserved */ 320 321 /* CBOM block size */ 322 if (cpu->cfg.cbom_blocksize) { 323 build_append_int_noprefix(table_data, 324 __builtin_ctz(cpu->cfg.cbom_blocksize), 325 1); 326 } else { 327 build_append_int_noprefix(table_data, 0, 1); 328 } 329 330 /* CBOP block size */ 331 build_append_int_noprefix(table_data, 0, 1); 332 333 /* CBOZ block size */ 334 if (cpu->cfg.cboz_blocksize) { 335 build_append_int_noprefix(table_data, 336 __builtin_ctz(cpu->cfg.cboz_blocksize), 337 1); 338 } else { 339 build_append_int_noprefix(table_data, 0, 1); 340 } 341 } 342 343 /* MMU node structure */ 344 if (cpu->cfg.satp_mode.supported != 0) { 345 satp_mode_max = satp_mode_max_from_map(cpu->cfg.satp_mode.map); 346 mmu_offset = table_data->len - table.table_offset; 347 build_append_int_noprefix(table_data, 2, 2); /* Type */ 348 build_append_int_noprefix(table_data, 8, 2); /* Length */ 349 build_append_int_noprefix(table_data, 0x1, 2); /* Revision */ 350 build_append_int_noprefix(table_data, 0, 1); /* Reserved */ 351 /* MMU Type */ 352 if (satp_mode_max == VM_1_10_SV57) { 353 build_append_int_noprefix(table_data, 2, 1); /* Sv57 */ 354 } else if (satp_mode_max == VM_1_10_SV48) { 355 build_append_int_noprefix(table_data, 1, 1); /* Sv48 */ 356 } else if (satp_mode_max == VM_1_10_SV39) { 357 build_append_int_noprefix(table_data, 0, 1); /* Sv39 */ 358 } else { 359 assert(1); 360 } 361 } 362 363 /* Hart Info Node */ 364 for (int i = 0; i < arch_ids->len; i++) { 365 len = 16; 366 int num_offsets = 1; 367 build_append_int_noprefix(table_data, 0xFFFF, 2); /* Type */ 368 369 /* Length */ 370 if (cmo_offset) { 371 len += 4; 372 num_offsets++; 373 } 374 375 if (mmu_offset) { 376 len += 4; 377 num_offsets++; 378 } 379 380 build_append_int_noprefix(table_data, len, 2); 381 build_append_int_noprefix(table_data, 0x1, 2); /* Revision */ 382 /* Number of offsets */ 383 build_append_int_noprefix(table_data, num_offsets, 2); 384 build_append_int_noprefix(table_data, i, 4); /* ACPI Processor UID */ 385 /* Offsets */ 386 build_append_int_noprefix(table_data, isa_offset, 4); 387 if (cmo_offset) { 388 build_append_int_noprefix(table_data, cmo_offset, 4); 389 } 390 391 if (mmu_offset) { 392 build_append_int_noprefix(table_data, mmu_offset, 4); 393 } 394 } 395 396 acpi_table_end(linker, &table); 397 } 398 399 /* FADT */ 400 static void build_fadt_rev6(GArray *table_data, 401 BIOSLinker *linker, 402 RISCVVirtState *s, 403 unsigned dsdt_tbl_offset) 404 { 405 AcpiFadtData fadt = { 406 .rev = 6, 407 .minor_ver = 5, 408 .flags = 1 << ACPI_FADT_F_HW_REDUCED_ACPI, 409 .xdsdt_tbl_offset = &dsdt_tbl_offset, 410 }; 411 412 build_fadt(table_data, linker, &fadt, s->oem_id, s->oem_table_id); 413 } 414 415 /* DSDT */ 416 static void build_dsdt(GArray *table_data, 417 BIOSLinker *linker, 418 RISCVVirtState *s) 419 { 420 Aml *scope, *dsdt; 421 MachineState *ms = MACHINE(s); 422 uint8_t socket_count; 423 const MemMapEntry *memmap = s->memmap; 424 AcpiTable table = { .sig = "DSDT", .rev = 2, .oem_id = s->oem_id, 425 .oem_table_id = s->oem_table_id }; 426 427 428 acpi_table_begin(&table, table_data); 429 dsdt = init_aml_allocator(); 430 431 /* 432 * When booting the VM with UEFI, UEFI takes ownership of the RTC hardware. 433 * While UEFI can use libfdt to disable the RTC device node in the DTB that 434 * it passes to the OS, it cannot modify AML. Therefore, we won't generate 435 * the RTC ACPI device at all when using UEFI. 436 */ 437 scope = aml_scope("\\_SB"); 438 acpi_dsdt_add_cpus(scope, s); 439 440 fw_cfg_acpi_dsdt_add(scope, &memmap[VIRT_FW_CFG]); 441 442 socket_count = riscv_socket_count(ms); 443 444 if (s->aia_type == VIRT_AIA_TYPE_NONE) { 445 acpi_dsdt_add_plic_aplic(scope, socket_count, memmap[VIRT_PLIC].base, 446 memmap[VIRT_PLIC].size, "RSCV0001"); 447 } else { 448 acpi_dsdt_add_plic_aplic(scope, socket_count, memmap[VIRT_APLIC_S].base, 449 memmap[VIRT_APLIC_S].size, "RSCV0002"); 450 } 451 452 acpi_dsdt_add_uart(scope, &memmap[VIRT_UART0], UART0_IRQ); 453 454 if (socket_count == 1) { 455 virtio_acpi_dsdt_add(scope, memmap[VIRT_VIRTIO].base, 456 memmap[VIRT_VIRTIO].size, 457 VIRTIO_IRQ, 0, VIRTIO_COUNT); 458 acpi_dsdt_add_gpex_host(scope, PCIE_IRQ); 459 } else if (socket_count == 2) { 460 virtio_acpi_dsdt_add(scope, memmap[VIRT_VIRTIO].base, 461 memmap[VIRT_VIRTIO].size, 462 VIRTIO_IRQ + VIRT_IRQCHIP_NUM_SOURCES, 0, 463 VIRTIO_COUNT); 464 acpi_dsdt_add_gpex_host(scope, PCIE_IRQ + VIRT_IRQCHIP_NUM_SOURCES); 465 } else { 466 virtio_acpi_dsdt_add(scope, memmap[VIRT_VIRTIO].base, 467 memmap[VIRT_VIRTIO].size, 468 VIRTIO_IRQ + VIRT_IRQCHIP_NUM_SOURCES, 0, 469 VIRTIO_COUNT); 470 acpi_dsdt_add_gpex_host(scope, PCIE_IRQ + VIRT_IRQCHIP_NUM_SOURCES * 2); 471 } 472 473 aml_append(dsdt, scope); 474 475 /* copy AML table into ACPI tables blob and patch header there */ 476 g_array_append_vals(table_data, dsdt->buf->data, dsdt->buf->len); 477 478 acpi_table_end(linker, &table); 479 free_aml_allocator(); 480 } 481 482 /* 483 * ACPI spec, Revision 6.5+ 484 * 5.2.12 Multiple APIC Description Table (MADT) 485 * REF: https://github.com/riscv-non-isa/riscv-acpi/issues/15 486 * https://drive.google.com/file/d/1R6k4MshhN3WTT-hwqAquu5nX6xSEqK2l/view 487 * https://drive.google.com/file/d/1oMGPyOD58JaPgMl1pKasT-VKsIKia7zR/view 488 */ 489 static void build_madt(GArray *table_data, 490 BIOSLinker *linker, 491 RISCVVirtState *s) 492 { 493 MachineClass *mc = MACHINE_GET_CLASS(s); 494 MachineState *ms = MACHINE(s); 495 const CPUArchIdList *arch_ids = mc->possible_cpu_arch_ids(ms); 496 uint8_t group_index_bits = imsic_num_bits(riscv_socket_count(ms)); 497 uint8_t guest_index_bits = imsic_num_bits(s->aia_guests + 1); 498 uint16_t imsic_max_hart_per_socket = 0; 499 uint8_t hart_index_bits; 500 uint64_t aplic_addr; 501 uint32_t gsi_base; 502 uint8_t socket; 503 504 for (socket = 0; socket < riscv_socket_count(ms); socket++) { 505 if (imsic_max_hart_per_socket < s->soc[socket].num_harts) { 506 imsic_max_hart_per_socket = s->soc[socket].num_harts; 507 } 508 } 509 510 hart_index_bits = imsic_num_bits(imsic_max_hart_per_socket); 511 512 AcpiTable table = { .sig = "APIC", .rev = 6, .oem_id = s->oem_id, 513 .oem_table_id = s->oem_table_id }; 514 515 acpi_table_begin(&table, table_data); 516 /* Local Interrupt Controller Address */ 517 build_append_int_noprefix(table_data, 0, 4); 518 build_append_int_noprefix(table_data, 0, 4); /* MADT Flags */ 519 520 /* RISC-V Local INTC structures per HART */ 521 for (int i = 0; i < arch_ids->len; i++) { 522 riscv_acpi_madt_add_rintc(i, arch_ids, table_data, s); 523 } 524 525 /* IMSIC */ 526 if (s->aia_type == VIRT_AIA_TYPE_APLIC_IMSIC) { 527 /* IMSIC */ 528 build_append_int_noprefix(table_data, 0x19, 1); /* Type */ 529 build_append_int_noprefix(table_data, 16, 1); /* Length */ 530 build_append_int_noprefix(table_data, 1, 1); /* Version */ 531 build_append_int_noprefix(table_data, 0, 1); /* Reserved */ 532 build_append_int_noprefix(table_data, 0, 4); /* Flags */ 533 /* Number of supervisor mode Interrupt Identities */ 534 build_append_int_noprefix(table_data, VIRT_IRQCHIP_NUM_MSIS, 2); 535 /* Number of guest mode Interrupt Identities */ 536 build_append_int_noprefix(table_data, VIRT_IRQCHIP_NUM_MSIS, 2); 537 /* Guest Index Bits */ 538 build_append_int_noprefix(table_data, guest_index_bits, 1); 539 /* Hart Index Bits */ 540 build_append_int_noprefix(table_data, hart_index_bits, 1); 541 /* Group Index Bits */ 542 build_append_int_noprefix(table_data, group_index_bits, 1); 543 /* Group Index Shift */ 544 build_append_int_noprefix(table_data, IMSIC_MMIO_GROUP_MIN_SHIFT, 1); 545 } 546 547 if (s->aia_type != VIRT_AIA_TYPE_NONE) { 548 /* APLICs */ 549 for (socket = 0; socket < riscv_socket_count(ms); socket++) { 550 aplic_addr = s->memmap[VIRT_APLIC_S].base + 551 s->memmap[VIRT_APLIC_S].size * socket; 552 gsi_base = VIRT_IRQCHIP_NUM_SOURCES * socket; 553 build_append_int_noprefix(table_data, 0x1A, 1); /* Type */ 554 build_append_int_noprefix(table_data, 36, 1); /* Length */ 555 build_append_int_noprefix(table_data, 1, 1); /* Version */ 556 build_append_int_noprefix(table_data, socket, 1); /* APLIC ID */ 557 build_append_int_noprefix(table_data, 0, 4); /* Flags */ 558 build_append_int_noprefix(table_data, 0, 8); /* Hardware ID */ 559 /* Number of IDCs */ 560 if (s->aia_type == VIRT_AIA_TYPE_APLIC) { 561 build_append_int_noprefix(table_data, 562 s->soc[socket].num_harts, 563 2); 564 } else { 565 build_append_int_noprefix(table_data, 0, 2); 566 } 567 /* Total External Interrupt Sources Supported */ 568 build_append_int_noprefix(table_data, VIRT_IRQCHIP_NUM_SOURCES, 2); 569 /* Global System Interrupt Base */ 570 build_append_int_noprefix(table_data, gsi_base, 4); 571 /* APLIC Address */ 572 build_append_int_noprefix(table_data, aplic_addr, 8); 573 /* APLIC size */ 574 build_append_int_noprefix(table_data, 575 s->memmap[VIRT_APLIC_S].size, 4); 576 } 577 } else { 578 /* PLICs */ 579 for (socket = 0; socket < riscv_socket_count(ms); socket++) { 580 aplic_addr = s->memmap[VIRT_PLIC].base + 581 s->memmap[VIRT_PLIC].size * socket; 582 gsi_base = VIRT_IRQCHIP_NUM_SOURCES * socket; 583 build_append_int_noprefix(table_data, 0x1B, 1); /* Type */ 584 build_append_int_noprefix(table_data, 36, 1); /* Length */ 585 build_append_int_noprefix(table_data, 1, 1); /* Version */ 586 build_append_int_noprefix(table_data, socket, 1); /* PLIC ID */ 587 build_append_int_noprefix(table_data, 0, 8); /* Hardware ID */ 588 /* Total External Interrupt Sources Supported */ 589 build_append_int_noprefix(table_data, 590 VIRT_IRQCHIP_NUM_SOURCES - 1, 2); 591 build_append_int_noprefix(table_data, 0, 2); /* Max Priority */ 592 build_append_int_noprefix(table_data, 0, 4); /* Flags */ 593 /* PLIC Size */ 594 build_append_int_noprefix(table_data, s->memmap[VIRT_PLIC].size, 4); 595 /* PLIC Address */ 596 build_append_int_noprefix(table_data, aplic_addr, 8); 597 /* Global System Interrupt Vector Base */ 598 build_append_int_noprefix(table_data, gsi_base, 4); 599 } 600 } 601 602 acpi_table_end(linker, &table); 603 } 604 605 /* 606 * ACPI spec, Revision 6.5+ 607 * 5.2.16 System Resource Affinity Table (SRAT) 608 * REF: https://github.com/riscv-non-isa/riscv-acpi/issues/25 609 * https://drive.google.com/file/d/1YTdDx2IPm5IeZjAW932EYU-tUtgS08tX/view 610 */ 611 static void 612 build_srat(GArray *table_data, BIOSLinker *linker, RISCVVirtState *vms) 613 { 614 int i; 615 uint64_t mem_base; 616 MachineClass *mc = MACHINE_GET_CLASS(vms); 617 MachineState *ms = MACHINE(vms); 618 const CPUArchIdList *cpu_list = mc->possible_cpu_arch_ids(ms); 619 AcpiTable table = { .sig = "SRAT", .rev = 3, .oem_id = vms->oem_id, 620 .oem_table_id = vms->oem_table_id }; 621 622 acpi_table_begin(&table, table_data); 623 build_append_int_noprefix(table_data, 1, 4); /* Reserved */ 624 build_append_int_noprefix(table_data, 0, 8); /* Reserved */ 625 626 for (i = 0; i < cpu_list->len; ++i) { 627 uint32_t nodeid = cpu_list->cpus[i].props.node_id; 628 /* 629 * 5.2.16.8 RINTC Affinity Structure 630 */ 631 build_append_int_noprefix(table_data, 7, 1); /* Type */ 632 build_append_int_noprefix(table_data, 20, 1); /* Length */ 633 build_append_int_noprefix(table_data, 0, 2); /* Reserved */ 634 build_append_int_noprefix(table_data, nodeid, 4); /* Proximity Domain */ 635 build_append_int_noprefix(table_data, i, 4); /* ACPI Processor UID */ 636 /* Flags, Table 5-70 */ 637 build_append_int_noprefix(table_data, 1 /* Flags: Enabled */, 4); 638 build_append_int_noprefix(table_data, 0, 4); /* Clock Domain */ 639 } 640 641 mem_base = vms->memmap[VIRT_DRAM].base; 642 for (i = 0; i < ms->numa_state->num_nodes; ++i) { 643 if (ms->numa_state->nodes[i].node_mem > 0) { 644 build_srat_memory(table_data, mem_base, 645 ms->numa_state->nodes[i].node_mem, i, 646 MEM_AFFINITY_ENABLED); 647 mem_base += ms->numa_state->nodes[i].node_mem; 648 } 649 } 650 651 acpi_table_end(linker, &table); 652 } 653 654 static void virt_acpi_build(RISCVVirtState *s, AcpiBuildTables *tables) 655 { 656 GArray *table_offsets; 657 unsigned dsdt, xsdt; 658 GArray *tables_blob = tables->table_data; 659 MachineState *ms = MACHINE(s); 660 661 table_offsets = g_array_new(false, true, 662 sizeof(uint32_t)); 663 664 bios_linker_loader_alloc(tables->linker, 665 ACPI_BUILD_TABLE_FILE, tables_blob, 666 64, false); 667 668 /* DSDT is pointed to by FADT */ 669 dsdt = tables_blob->len; 670 build_dsdt(tables_blob, tables->linker, s); 671 672 /* FADT and others pointed to by XSDT */ 673 acpi_add_table(table_offsets, tables_blob); 674 build_fadt_rev6(tables_blob, tables->linker, s, dsdt); 675 676 acpi_add_table(table_offsets, tables_blob); 677 build_madt(tables_blob, tables->linker, s); 678 679 acpi_add_table(table_offsets, tables_blob); 680 build_rhct(tables_blob, tables->linker, s); 681 682 acpi_add_table(table_offsets, tables_blob); 683 spcr_setup(tables_blob, tables->linker, s); 684 685 acpi_add_table(table_offsets, tables_blob); 686 { 687 AcpiMcfgInfo mcfg = { 688 .base = s->memmap[VIRT_PCIE_ECAM].base, 689 .size = s->memmap[VIRT_PCIE_ECAM].size, 690 }; 691 build_mcfg(tables_blob, tables->linker, &mcfg, s->oem_id, 692 s->oem_table_id); 693 } 694 695 if (ms->numa_state->num_nodes > 0) { 696 acpi_add_table(table_offsets, tables_blob); 697 build_srat(tables_blob, tables->linker, s); 698 if (ms->numa_state->have_numa_distance) { 699 acpi_add_table(table_offsets, tables_blob); 700 build_slit(tables_blob, tables->linker, ms, s->oem_id, 701 s->oem_table_id); 702 } 703 } 704 705 /* XSDT is pointed to by RSDP */ 706 xsdt = tables_blob->len; 707 build_xsdt(tables_blob, tables->linker, table_offsets, s->oem_id, 708 s->oem_table_id); 709 710 /* RSDP is in FSEG memory, so allocate it separately */ 711 { 712 AcpiRsdpData rsdp_data = { 713 .revision = 2, 714 .oem_id = s->oem_id, 715 .xsdt_tbl_offset = &xsdt, 716 .rsdt_tbl_offset = NULL, 717 }; 718 build_rsdp(tables->rsdp, tables->linker, &rsdp_data); 719 } 720 721 /* 722 * The align size is 128, warn if 64k is not enough therefore 723 * the align size could be resized. 724 */ 725 if (tables_blob->len > ACPI_BUILD_TABLE_SIZE / 2) { 726 warn_report("ACPI table size %u exceeds %d bytes," 727 " migration may not work", 728 tables_blob->len, ACPI_BUILD_TABLE_SIZE / 2); 729 error_printf("Try removing some objects."); 730 } 731 732 acpi_align_size(tables_blob, ACPI_BUILD_TABLE_SIZE); 733 734 /* Clean up memory that's no longer used */ 735 g_array_free(table_offsets, true); 736 } 737 738 static void acpi_ram_update(MemoryRegion *mr, GArray *data) 739 { 740 uint32_t size = acpi_data_len(data); 741 742 /* 743 * Make sure RAM size is correct - in case it got changed 744 * e.g. by migration 745 */ 746 memory_region_ram_resize(mr, size, &error_abort); 747 748 memcpy(memory_region_get_ram_ptr(mr), data->data, size); 749 memory_region_set_dirty(mr, 0, size); 750 } 751 752 static void virt_acpi_build_update(void *build_opaque) 753 { 754 AcpiBuildState *build_state = build_opaque; 755 AcpiBuildTables tables; 756 757 /* No state to update or already patched? Nothing to do. */ 758 if (!build_state || build_state->patched) { 759 return; 760 } 761 762 build_state->patched = true; 763 764 acpi_build_tables_init(&tables); 765 766 virt_acpi_build(RISCV_VIRT_MACHINE(qdev_get_machine()), &tables); 767 768 acpi_ram_update(build_state->table_mr, tables.table_data); 769 acpi_ram_update(build_state->rsdp_mr, tables.rsdp); 770 acpi_ram_update(build_state->linker_mr, tables.linker->cmd_blob); 771 772 acpi_build_tables_cleanup(&tables, true); 773 } 774 775 static void virt_acpi_build_reset(void *build_opaque) 776 { 777 AcpiBuildState *build_state = build_opaque; 778 build_state->patched = false; 779 } 780 781 static const VMStateDescription vmstate_virt_acpi_build = { 782 .name = "virt_acpi_build", 783 .version_id = 1, 784 .minimum_version_id = 1, 785 .fields = (const VMStateField[]) { 786 VMSTATE_BOOL(patched, AcpiBuildState), 787 VMSTATE_END_OF_LIST() 788 }, 789 }; 790 791 void virt_acpi_setup(RISCVVirtState *s) 792 { 793 AcpiBuildTables tables; 794 AcpiBuildState *build_state; 795 796 build_state = g_malloc0(sizeof *build_state); 797 798 acpi_build_tables_init(&tables); 799 virt_acpi_build(s, &tables); 800 801 /* Now expose it all to Guest */ 802 build_state->table_mr = acpi_add_rom_blob(virt_acpi_build_update, 803 build_state, tables.table_data, 804 ACPI_BUILD_TABLE_FILE); 805 assert(build_state->table_mr != NULL); 806 807 build_state->linker_mr = acpi_add_rom_blob(virt_acpi_build_update, 808 build_state, 809 tables.linker->cmd_blob, 810 ACPI_BUILD_LOADER_FILE); 811 812 build_state->rsdp_mr = acpi_add_rom_blob(virt_acpi_build_update, 813 build_state, tables.rsdp, 814 ACPI_BUILD_RSDP_FILE); 815 816 qemu_register_reset(virt_acpi_build_reset, build_state); 817 virt_acpi_build_reset(build_state); 818 vmstate_register(NULL, 0, &vmstate_virt_acpi_build, build_state); 819 820 /* 821 * Clean up tables but don't free the memory: we track it 822 * in build_state. 823 */ 824 acpi_build_tables_cleanup(&tables, false); 825 } 826