xref: /qemu/hw/riscv/spike.c (revision 732612856a8948a6ba1148322651743aa963b51c)
15b4beba1SMichael Clark /*
25b4beba1SMichael Clark  * QEMU RISC-V Spike Board
35b4beba1SMichael Clark  *
45b4beba1SMichael Clark  * Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu
55b4beba1SMichael Clark  * Copyright (c) 2017-2018 SiFive, Inc.
65b4beba1SMichael Clark  *
75b4beba1SMichael Clark  * This provides a RISC-V Board with the following devices:
85b4beba1SMichael Clark  *
95b4beba1SMichael Clark  * 0) HTIF Console and Poweroff
105b4beba1SMichael Clark  * 1) CLINT (Timer and IPI)
115b4beba1SMichael Clark  * 2) PLIC (Platform Level Interrupt Controller)
125b4beba1SMichael Clark  *
135b4beba1SMichael Clark  * This program is free software; you can redistribute it and/or modify it
145b4beba1SMichael Clark  * under the terms and conditions of the GNU General Public License,
155b4beba1SMichael Clark  * version 2 or later, as published by the Free Software Foundation.
165b4beba1SMichael Clark  *
175b4beba1SMichael Clark  * This program is distributed in the hope it will be useful, but WITHOUT
185b4beba1SMichael Clark  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
195b4beba1SMichael Clark  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
205b4beba1SMichael Clark  * more details.
215b4beba1SMichael Clark  *
225b4beba1SMichael Clark  * You should have received a copy of the GNU General Public License along with
235b4beba1SMichael Clark  * this program.  If not, see <http://www.gnu.org/licenses/>.
245b4beba1SMichael Clark  */
255b4beba1SMichael Clark 
265b4beba1SMichael Clark #include "qemu/osdep.h"
275b4beba1SMichael Clark #include "qemu/log.h"
285b4beba1SMichael Clark #include "qemu/error-report.h"
295b4beba1SMichael Clark #include "qapi/error.h"
305b4beba1SMichael Clark #include "hw/boards.h"
315b4beba1SMichael Clark #include "hw/loader.h"
325b4beba1SMichael Clark #include "hw/sysbus.h"
335b4beba1SMichael Clark #include "target/riscv/cpu.h"
345b4beba1SMichael Clark #include "hw/riscv/riscv_hart.h"
355b4beba1SMichael Clark #include "hw/riscv/spike.h"
360ac24d56SAlistair Francis #include "hw/riscv/boot.h"
37a7172791SAnup Patel #include "hw/riscv/numa.h"
3870eb9f9cSBin Meng #include "hw/char/riscv_htif.h"
39406fafd5SBin Meng #include "hw/intc/sifive_clint.h"
405b4beba1SMichael Clark #include "chardev/char.h"
415b4beba1SMichael Clark #include "sysemu/arch_init.h"
425b4beba1SMichael Clark #include "sysemu/device_tree.h"
43cd69e3a6SAlistair Francis #include "sysemu/qtest.h"
4446517dd4SMarkus Armbruster #include "sysemu/sysemu.h"
455aec3247SMichael Clark 
46*73261285SBin Meng static const MemMapEntry spike_memmap[] = {
479eb8b14aSBin Meng     [SPIKE_MROM] =     {     0x1000,     0xf000 },
485b4beba1SMichael Clark     [SPIKE_CLINT] =    {  0x2000000,    0x10000 },
495b4beba1SMichael Clark     [SPIKE_DRAM] =     { 0x80000000,        0x0 },
505b4beba1SMichael Clark };
515b4beba1SMichael Clark 
52*73261285SBin Meng static void create_fdt(SpikeState *s, const MemMapEntry *memmap,
53bd62c13eSAlistair Francis                        uint64_t mem_size, const char *cmdline, bool is_32_bit)
545b4beba1SMichael Clark {
555b4beba1SMichael Clark     void *fdt;
56a7172791SAnup Patel     uint64_t addr, size;
57a7172791SAnup Patel     unsigned long clint_addr;
58a7172791SAnup Patel     int cpu, socket;
59a7172791SAnup Patel     MachineState *mc = MACHINE(s);
60a7172791SAnup Patel     uint32_t *clint_cells;
61a7172791SAnup Patel     uint32_t cpu_phandle, intc_phandle, phandle = 1;
62a7172791SAnup Patel     char *name, *mem_name, *clint_name, *clust_name;
63a7172791SAnup Patel     char *core_name, *cpu_name, *intc_name;
645b4beba1SMichael Clark 
655b4beba1SMichael Clark     fdt = s->fdt = create_device_tree(&s->fdt_size);
665b4beba1SMichael Clark     if (!fdt) {
675b4beba1SMichael Clark         error_report("create_device_tree() failed");
685b4beba1SMichael Clark         exit(1);
695b4beba1SMichael Clark     }
705b4beba1SMichael Clark 
715b4beba1SMichael Clark     qemu_fdt_setprop_string(fdt, "/", "model", "ucbbar,spike-bare,qemu");
725b4beba1SMichael Clark     qemu_fdt_setprop_string(fdt, "/", "compatible", "ucbbar,spike-bare-dev");
735b4beba1SMichael Clark     qemu_fdt_setprop_cell(fdt, "/", "#size-cells", 0x2);
745b4beba1SMichael Clark     qemu_fdt_setprop_cell(fdt, "/", "#address-cells", 0x2);
755b4beba1SMichael Clark 
765b4beba1SMichael Clark     qemu_fdt_add_subnode(fdt, "/htif");
775b4beba1SMichael Clark     qemu_fdt_setprop_string(fdt, "/htif", "compatible", "ucb,htif0");
785b4beba1SMichael Clark 
795b4beba1SMichael Clark     qemu_fdt_add_subnode(fdt, "/soc");
805b4beba1SMichael Clark     qemu_fdt_setprop(fdt, "/soc", "ranges", NULL, 0);
81117caacfSAlistair Francis     qemu_fdt_setprop_string(fdt, "/soc", "compatible", "simple-bus");
825b4beba1SMichael Clark     qemu_fdt_setprop_cell(fdt, "/soc", "#size-cells", 0x2);
835b4beba1SMichael Clark     qemu_fdt_setprop_cell(fdt, "/soc", "#address-cells", 0x2);
845b4beba1SMichael Clark 
855b4beba1SMichael Clark     qemu_fdt_add_subnode(fdt, "/cpus");
862a8756edSMichael Clark     qemu_fdt_setprop_cell(fdt, "/cpus", "timebase-frequency",
872a8756edSMichael Clark         SIFIVE_CLINT_TIMEBASE_FREQ);
885b4beba1SMichael Clark     qemu_fdt_setprop_cell(fdt, "/cpus", "#size-cells", 0x0);
895b4beba1SMichael Clark     qemu_fdt_setprop_cell(fdt, "/cpus", "#address-cells", 0x1);
90a7172791SAnup Patel     qemu_fdt_add_subnode(fdt, "/cpus/cpu-map");
915b4beba1SMichael Clark 
92a7172791SAnup Patel     for (socket = (riscv_socket_count(mc) - 1); socket >= 0; socket--) {
93a7172791SAnup Patel         clust_name = g_strdup_printf("/cpus/cpu-map/cluster%d", socket);
94a7172791SAnup Patel         qemu_fdt_add_subnode(fdt, clust_name);
95a7172791SAnup Patel 
96a7172791SAnup Patel         clint_cells =  g_new0(uint32_t, s->soc[socket].num_harts * 4);
97a7172791SAnup Patel 
98a7172791SAnup Patel         for (cpu = s->soc[socket].num_harts - 1; cpu >= 0; cpu--) {
99a7172791SAnup Patel             cpu_phandle = phandle++;
100a7172791SAnup Patel 
101a7172791SAnup Patel             cpu_name = g_strdup_printf("/cpus/cpu@%d",
102a7172791SAnup Patel                 s->soc[socket].hartid_base + cpu);
103a7172791SAnup Patel             qemu_fdt_add_subnode(fdt, cpu_name);
104bd62c13eSAlistair Francis             if (is_32_bit) {
105a7172791SAnup Patel                 qemu_fdt_setprop_string(fdt, cpu_name, "mmu-type", "riscv,sv32");
106bd62c13eSAlistair Francis             } else {
107a7172791SAnup Patel                 qemu_fdt_setprop_string(fdt, cpu_name, "mmu-type", "riscv,sv48");
108bd62c13eSAlistair Francis             }
109a7172791SAnup Patel             name = riscv_isa_string(&s->soc[socket].harts[cpu]);
110a7172791SAnup Patel             qemu_fdt_setprop_string(fdt, cpu_name, "riscv,isa", name);
111a7172791SAnup Patel             g_free(name);
112a7172791SAnup Patel             qemu_fdt_setprop_string(fdt, cpu_name, "compatible", "riscv");
113a7172791SAnup Patel             qemu_fdt_setprop_string(fdt, cpu_name, "status", "okay");
114a7172791SAnup Patel             qemu_fdt_setprop_cell(fdt, cpu_name, "reg",
115a7172791SAnup Patel                 s->soc[socket].hartid_base + cpu);
116a7172791SAnup Patel             qemu_fdt_setprop_string(fdt, cpu_name, "device_type", "cpu");
117a7172791SAnup Patel             riscv_socket_fdt_write_id(mc, fdt, cpu_name, socket);
118a7172791SAnup Patel             qemu_fdt_setprop_cell(fdt, cpu_name, "phandle", cpu_phandle);
119a7172791SAnup Patel 
120a7172791SAnup Patel             intc_name = g_strdup_printf("%s/interrupt-controller", cpu_name);
121a7172791SAnup Patel             qemu_fdt_add_subnode(fdt, intc_name);
122a7172791SAnup Patel             intc_phandle = phandle++;
123a7172791SAnup Patel             qemu_fdt_setprop_cell(fdt, intc_name, "phandle", intc_phandle);
124a7172791SAnup Patel             qemu_fdt_setprop_string(fdt, intc_name, "compatible",
125a7172791SAnup Patel                 "riscv,cpu-intc");
126a7172791SAnup Patel             qemu_fdt_setprop(fdt, intc_name, "interrupt-controller", NULL, 0);
127a7172791SAnup Patel             qemu_fdt_setprop_cell(fdt, intc_name, "#interrupt-cells", 1);
128a7172791SAnup Patel 
129a7172791SAnup Patel             clint_cells[cpu * 4 + 0] = cpu_to_be32(intc_phandle);
130a7172791SAnup Patel             clint_cells[cpu * 4 + 1] = cpu_to_be32(IRQ_M_SOFT);
131a7172791SAnup Patel             clint_cells[cpu * 4 + 2] = cpu_to_be32(intc_phandle);
132a7172791SAnup Patel             clint_cells[cpu * 4 + 3] = cpu_to_be32(IRQ_M_TIMER);
133a7172791SAnup Patel 
134a7172791SAnup Patel             core_name = g_strdup_printf("%s/core%d", clust_name, cpu);
135a7172791SAnup Patel             qemu_fdt_add_subnode(fdt, core_name);
136a7172791SAnup Patel             qemu_fdt_setprop_cell(fdt, core_name, "cpu", cpu_phandle);
137a7172791SAnup Patel 
138a7172791SAnup Patel             g_free(core_name);
139a7172791SAnup Patel             g_free(intc_name);
140a7172791SAnup Patel             g_free(cpu_name);
1415b4beba1SMichael Clark         }
1425b4beba1SMichael Clark 
143a7172791SAnup Patel         addr = memmap[SPIKE_DRAM].base + riscv_socket_mem_offset(mc, socket);
144a7172791SAnup Patel         size = riscv_socket_mem_size(mc, socket);
145a7172791SAnup Patel         mem_name = g_strdup_printf("/memory@%lx", (long)addr);
146a7172791SAnup Patel         qemu_fdt_add_subnode(fdt, mem_name);
147a7172791SAnup Patel         qemu_fdt_setprop_cells(fdt, mem_name, "reg",
148a7172791SAnup Patel             addr >> 32, addr, size >> 32, size);
149a7172791SAnup Patel         qemu_fdt_setprop_string(fdt, mem_name, "device_type", "memory");
150a7172791SAnup Patel         riscv_socket_fdt_write_id(mc, fdt, mem_name, socket);
151a7172791SAnup Patel         g_free(mem_name);
152a7172791SAnup Patel 
153a7172791SAnup Patel         clint_addr = memmap[SPIKE_CLINT].base +
154a7172791SAnup Patel             (memmap[SPIKE_CLINT].size * socket);
155a7172791SAnup Patel         clint_name = g_strdup_printf("/soc/clint@%lx", clint_addr);
156a7172791SAnup Patel         qemu_fdt_add_subnode(fdt, clint_name);
157a7172791SAnup Patel         qemu_fdt_setprop_string(fdt, clint_name, "compatible", "riscv,clint0");
158a7172791SAnup Patel         qemu_fdt_setprop_cells(fdt, clint_name, "reg",
159a7172791SAnup Patel             0x0, clint_addr, 0x0, memmap[SPIKE_CLINT].size);
160a7172791SAnup Patel         qemu_fdt_setprop(fdt, clint_name, "interrupts-extended",
161a7172791SAnup Patel             clint_cells, s->soc[socket].num_harts * sizeof(uint32_t) * 4);
162a7172791SAnup Patel         riscv_socket_fdt_write_id(mc, fdt, clint_name, socket);
163a7172791SAnup Patel 
164a7172791SAnup Patel         g_free(clint_name);
165a7172791SAnup Patel         g_free(clint_cells);
166a7172791SAnup Patel         g_free(clust_name);
1675b4beba1SMichael Clark     }
168a7172791SAnup Patel 
169a7172791SAnup Patel     riscv_socket_fdt_write_distance_matrix(mc, fdt);
1705b4beba1SMichael Clark 
1717c28f4daSMichael Clark     if (cmdline) {
1725b4beba1SMichael Clark         qemu_fdt_add_subnode(fdt, "/chosen");
1735b4beba1SMichael Clark         qemu_fdt_setprop_string(fdt, "/chosen", "bootargs", cmdline);
1745b4beba1SMichael Clark     }
1757c28f4daSMichael Clark }
1765b4beba1SMichael Clark 
177cd69e3a6SAlistair Francis static void spike_board_init(MachineState *machine)
178cd69e3a6SAlistair Francis {
179*73261285SBin Meng     const MemMapEntry *memmap = spike_memmap;
180a7172791SAnup Patel     SpikeState *s = SPIKE_MACHINE(machine);
181cd69e3a6SAlistair Francis     MemoryRegion *system_memory = get_system_memory();
182cd69e3a6SAlistair Francis     MemoryRegion *main_mem = g_new(MemoryRegion, 1);
183cd69e3a6SAlistair Francis     MemoryRegion *mask_rom = g_new(MemoryRegion, 1);
18438bc4e34SAlistair Francis     target_ulong firmware_end_addr, kernel_start_addr;
18566b1205bSAtish Patra     uint32_t fdt_load_addr;
186dc144fe1SAtish Patra     uint64_t kernel_entry;
187a7172791SAnup Patel     char *soc_name;
188a7172791SAnup Patel     int i, base_hartid, hart_count;
189cd69e3a6SAlistair Francis 
190a7172791SAnup Patel     /* Check socket count limit */
191a7172791SAnup Patel     if (SPIKE_SOCKETS_MAX < riscv_socket_count(machine)) {
192a7172791SAnup Patel         error_report("number of sockets/nodes should be less than %d",
193a7172791SAnup Patel             SPIKE_SOCKETS_MAX);
194a7172791SAnup Patel         exit(1);
195a7172791SAnup Patel     }
196a7172791SAnup Patel 
197a7172791SAnup Patel     /* Initialize sockets */
198a7172791SAnup Patel     for (i = 0; i < riscv_socket_count(machine); i++) {
199a7172791SAnup Patel         if (!riscv_socket_check_hartids(machine, i)) {
200a7172791SAnup Patel             error_report("discontinuous hartids in socket%d", i);
201a7172791SAnup Patel             exit(1);
202a7172791SAnup Patel         }
203a7172791SAnup Patel 
204a7172791SAnup Patel         base_hartid = riscv_socket_first_hartid(machine, i);
205a7172791SAnup Patel         if (base_hartid < 0) {
206a7172791SAnup Patel             error_report("can't find hartid base for socket%d", i);
207a7172791SAnup Patel             exit(1);
208a7172791SAnup Patel         }
209a7172791SAnup Patel 
210a7172791SAnup Patel         hart_count = riscv_socket_hart_count(machine, i);
211a7172791SAnup Patel         if (hart_count < 0) {
212a7172791SAnup Patel             error_report("can't find hart count for socket%d", i);
213a7172791SAnup Patel             exit(1);
214a7172791SAnup Patel         }
215a7172791SAnup Patel 
216a7172791SAnup Patel         soc_name = g_strdup_printf("soc%d", i);
217a7172791SAnup Patel         object_initialize_child(OBJECT(machine), soc_name, &s->soc[i],
21875a6ed87SMarkus Armbruster                                 TYPE_RISCV_HART_ARRAY);
219a7172791SAnup Patel         g_free(soc_name);
220a7172791SAnup Patel         object_property_set_str(OBJECT(&s->soc[i]), "cpu-type",
221a7172791SAnup Patel                                 machine->cpu_type, &error_abort);
222a7172791SAnup Patel         object_property_set_int(OBJECT(&s->soc[i]), "hartid-base",
223a7172791SAnup Patel                                 base_hartid, &error_abort);
224a7172791SAnup Patel         object_property_set_int(OBJECT(&s->soc[i]), "num-harts",
225a7172791SAnup Patel                                 hart_count, &error_abort);
226a7172791SAnup Patel         sysbus_realize(SYS_BUS_DEVICE(&s->soc[i]), &error_abort);
227a7172791SAnup Patel 
228a7172791SAnup Patel         /* Core Local Interruptor (timer and IPI) for each socket */
229a7172791SAnup Patel         sifive_clint_create(
230a7172791SAnup Patel             memmap[SPIKE_CLINT].base + i * memmap[SPIKE_CLINT].size,
231a7172791SAnup Patel             memmap[SPIKE_CLINT].size, base_hartid, hart_count,
232a47ef6e9SBin Meng             SIFIVE_SIP_BASE, SIFIVE_TIMECMP_BASE, SIFIVE_TIME_BASE,
233a47ef6e9SBin Meng             SIFIVE_CLINT_TIMEBASE_FREQ, false);
234a7172791SAnup Patel     }
235cd69e3a6SAlistair Francis 
236cd69e3a6SAlistair Francis     /* register system main memory (actual RAM) */
237cd69e3a6SAlistair Francis     memory_region_init_ram(main_mem, NULL, "riscv.spike.ram",
238cd69e3a6SAlistair Francis                            machine->ram_size, &error_fatal);
239cd69e3a6SAlistair Francis     memory_region_add_subregion(system_memory, memmap[SPIKE_DRAM].base,
240cd69e3a6SAlistair Francis         main_mem);
241cd69e3a6SAlistair Francis 
242cd69e3a6SAlistair Francis     /* create device tree */
243bd62c13eSAlistair Francis     create_fdt(s, memmap, machine->ram_size, machine->kernel_cmdline,
244a8259b53SAlistair Francis                riscv_is_32bit(&s->soc[0]));
245cd69e3a6SAlistair Francis 
246cd69e3a6SAlistair Francis     /* boot rom */
247cd69e3a6SAlistair Francis     memory_region_init_rom(mask_rom, NULL, "riscv.spike.mrom",
248cd69e3a6SAlistair Francis                            memmap[SPIKE_MROM].size, &error_fatal);
249cd69e3a6SAlistair Francis     memory_region_add_subregion(system_memory, memmap[SPIKE_MROM].base,
250cd69e3a6SAlistair Francis                                 mask_rom);
251cd69e3a6SAlistair Francis 
252bd62c13eSAlistair Francis     /*
253bd62c13eSAlistair Francis      * Not like other RISC-V machines that use plain binary bios images,
254bd62c13eSAlistair Francis      * keeping ELF files here was intentional because BIN files don't work
255bd62c13eSAlistair Francis      * for the Spike machine as HTIF emulation depends on ELF parsing.
256bd62c13eSAlistair Francis      */
257a8259b53SAlistair Francis     if (riscv_is_32bit(&s->soc[0])) {
258bd62c13eSAlistair Francis         firmware_end_addr = riscv_find_and_load_firmware(machine,
259bd62c13eSAlistair Francis                                     "opensbi-riscv32-generic-fw_dynamic.elf",
2605b8a9863SAnup Patel                                     memmap[SPIKE_DRAM].base,
2615b8a9863SAnup Patel                                     htif_symbol_callback);
262bd62c13eSAlistair Francis     } else {
263bd62c13eSAlistair Francis         firmware_end_addr = riscv_find_and_load_firmware(machine,
264bd62c13eSAlistair Francis                                     "opensbi-riscv64-generic-fw_dynamic.elf",
265bd62c13eSAlistair Francis                                     memmap[SPIKE_DRAM].base,
266bd62c13eSAlistair Francis                                     htif_symbol_callback);
267bd62c13eSAlistair Francis     }
2685b8a9863SAnup Patel 
269cd69e3a6SAlistair Francis     if (machine->kernel_filename) {
270a8259b53SAlistair Francis         kernel_start_addr = riscv_calc_kernel_start_addr(&s->soc[0],
27138bc4e34SAlistair Francis                                                          firmware_end_addr);
27238bc4e34SAlistair Francis 
273dc144fe1SAtish Patra         kernel_entry = riscv_load_kernel(machine->kernel_filename,
27438bc4e34SAlistair Francis                                          kernel_start_addr,
2755b8a9863SAnup Patel                                          htif_symbol_callback);
2765b8a9863SAnup Patel 
2775b8a9863SAnup Patel         if (machine->initrd_filename) {
2785b8a9863SAnup Patel             hwaddr start;
2795b8a9863SAnup Patel             hwaddr end = riscv_load_initrd(machine->initrd_filename,
2805b8a9863SAnup Patel                                            machine->ram_size, kernel_entry,
2815b8a9863SAnup Patel                                            &start);
2825b8a9863SAnup Patel             qemu_fdt_setprop_cell(s->fdt, "/chosen",
2835b8a9863SAnup Patel                                   "linux,initrd-start", start);
2845b8a9863SAnup Patel             qemu_fdt_setprop_cell(s->fdt, "/chosen", "linux,initrd-end",
2855b8a9863SAnup Patel                                   end);
2865b8a9863SAnup Patel         }
287dc144fe1SAtish Patra     } else {
288dc144fe1SAtish Patra        /*
289dc144fe1SAtish Patra         * If dynamic firmware is used, it doesn't know where is the next mode
290dc144fe1SAtish Patra         * if kernel argument is not set.
291dc144fe1SAtish Patra         */
292dc144fe1SAtish Patra         kernel_entry = 0;
293cd69e3a6SAlistair Francis     }
294cd69e3a6SAlistair Francis 
29566b1205bSAtish Patra     /* Compute the fdt load address in dram */
29666b1205bSAtish Patra     fdt_load_addr = riscv_load_fdt(memmap[SPIKE_DRAM].base,
29766b1205bSAtish Patra                                    machine->ram_size, s->fdt);
29843cf723aSAtish Patra     /* load the reset vector */
299a8259b53SAlistair Francis     riscv_setup_rom_reset_vec(machine, &s->soc[0], memmap[SPIKE_DRAM].base,
30078936771SAlistair Francis                               memmap[SPIKE_MROM].base,
301dc144fe1SAtish Patra                               memmap[SPIKE_MROM].size, kernel_entry,
30266b1205bSAtish Patra                               fdt_load_addr, s->fdt);
303cd69e3a6SAlistair Francis 
304cd69e3a6SAlistair Francis     /* initialize HTIF using symbols found in load_kernel */
305a7172791SAnup Patel     htif_mm_init(system_memory, mask_rom,
306a7172791SAnup Patel                  &s->soc[0].harts[0].env, serial_hd(0));
307cd69e3a6SAlistair Francis }
308cd69e3a6SAlistair Francis 
309a7172791SAnup Patel static void spike_machine_instance_init(Object *obj)
310cd69e3a6SAlistair Francis {
311a7172791SAnup Patel }
312a7172791SAnup Patel 
313a7172791SAnup Patel static void spike_machine_class_init(ObjectClass *oc, void *data)
314a7172791SAnup Patel {
315a7172791SAnup Patel     MachineClass *mc = MACHINE_CLASS(oc);
316a7172791SAnup Patel 
317a7172791SAnup Patel     mc->desc = "RISC-V Spike board";
318cd69e3a6SAlistair Francis     mc->init = spike_board_init;
319a7172791SAnup Patel     mc->max_cpus = SPIKE_CPUS_MAX;
320ea0ac7f6SPhilippe Mathieu-Daudé     mc->is_default = true;
321dc4d4aaeSAlistair Francis     mc->default_cpu_type = TYPE_RISCV_CPU_BASE;
322a7172791SAnup Patel     mc->possible_cpu_arch_ids = riscv_numa_possible_cpu_arch_ids;
323a7172791SAnup Patel     mc->cpu_index_to_instance_props = riscv_numa_cpu_index_to_props;
324a7172791SAnup Patel     mc->get_default_cpu_node_id = riscv_numa_get_default_cpu_node_id;
325a7172791SAnup Patel     mc->numa_mem_supported = true;
3265b4beba1SMichael Clark }
3275b4beba1SMichael Clark 
328a7172791SAnup Patel static const TypeInfo spike_machine_typeinfo = {
329a7172791SAnup Patel     .name       = MACHINE_TYPE_NAME("spike"),
330a7172791SAnup Patel     .parent     = TYPE_MACHINE,
331a7172791SAnup Patel     .class_init = spike_machine_class_init,
332a7172791SAnup Patel     .instance_init = spike_machine_instance_init,
333a7172791SAnup Patel     .instance_size = sizeof(SpikeState),
334a7172791SAnup Patel };
335a7172791SAnup Patel 
336a7172791SAnup Patel static void spike_machine_init_register_types(void)
337a7172791SAnup Patel {
338a7172791SAnup Patel     type_register_static(&spike_machine_typeinfo);
339a7172791SAnup Patel }
340a7172791SAnup Patel 
341a7172791SAnup Patel type_init(spike_machine_init_register_types)
342