1 /* 2 * QEMU RISC-V Board Compatible with SiFive Freedom U SDK 3 * 4 * Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu 5 * Copyright (c) 2017 SiFive, Inc. 6 * Copyright (c) 2019 Bin Meng <bmeng.cn@gmail.com> 7 * 8 * Provides a board compatible with the SiFive Freedom U SDK: 9 * 10 * 0) UART 11 * 1) CLINT (Core Level Interruptor) 12 * 2) PLIC (Platform Level Interrupt Controller) 13 * 3) PRCI (Power, Reset, Clock, Interrupt) 14 * 4) OTP (One-Time Programmable) memory with stored serial number 15 * 5) GEM (Gigabit Ethernet Controller) and management block 16 * 17 * This board currently generates devicetree dynamically that indicates at least 18 * two harts and up to five harts. 19 * 20 * This program is free software; you can redistribute it and/or modify it 21 * under the terms and conditions of the GNU General Public License, 22 * version 2 or later, as published by the Free Software Foundation. 23 * 24 * This program is distributed in the hope it will be useful, but WITHOUT 25 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 26 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 27 * more details. 28 * 29 * You should have received a copy of the GNU General Public License along with 30 * this program. If not, see <http://www.gnu.org/licenses/>. 31 */ 32 33 #include "qemu/osdep.h" 34 #include "qemu/log.h" 35 #include "qemu/error-report.h" 36 #include "qapi/error.h" 37 #include "hw/boards.h" 38 #include "hw/loader.h" 39 #include "hw/sysbus.h" 40 #include "hw/char/serial.h" 41 #include "hw/cpu/cluster.h" 42 #include "hw/misc/unimp.h" 43 #include "target/riscv/cpu.h" 44 #include "hw/riscv/riscv_hart.h" 45 #include "hw/riscv/sifive_plic.h" 46 #include "hw/riscv/sifive_clint.h" 47 #include "hw/riscv/sifive_uart.h" 48 #include "hw/riscv/sifive_u.h" 49 #include "hw/riscv/boot.h" 50 #include "chardev/char.h" 51 #include "net/eth.h" 52 #include "sysemu/arch_init.h" 53 #include "sysemu/device_tree.h" 54 #include "sysemu/sysemu.h" 55 #include "exec/address-spaces.h" 56 57 #include <libfdt.h> 58 59 #define BIOS_FILENAME "opensbi-riscv64-sifive_u-fw_jump.bin" 60 61 static const struct MemmapEntry { 62 hwaddr base; 63 hwaddr size; 64 } sifive_u_memmap[] = { 65 [SIFIVE_U_DEBUG] = { 0x0, 0x100 }, 66 [SIFIVE_U_MROM] = { 0x1000, 0x11000 }, 67 [SIFIVE_U_CLINT] = { 0x2000000, 0x10000 }, 68 [SIFIVE_U_L2LIM] = { 0x8000000, 0x2000000 }, 69 [SIFIVE_U_PLIC] = { 0xc000000, 0x4000000 }, 70 [SIFIVE_U_PRCI] = { 0x10000000, 0x1000 }, 71 [SIFIVE_U_UART0] = { 0x10010000, 0x1000 }, 72 [SIFIVE_U_UART1] = { 0x10011000, 0x1000 }, 73 [SIFIVE_U_OTP] = { 0x10070000, 0x1000 }, 74 [SIFIVE_U_DRAM] = { 0x80000000, 0x0 }, 75 [SIFIVE_U_GEM] = { 0x10090000, 0x2000 }, 76 [SIFIVE_U_GEM_MGMT] = { 0x100a0000, 0x1000 }, 77 }; 78 79 #define OTP_SERIAL 1 80 #define GEM_REVISION 0x10070109 81 82 static void create_fdt(SiFiveUState *s, const struct MemmapEntry *memmap, 83 uint64_t mem_size, const char *cmdline) 84 { 85 MachineState *ms = MACHINE(qdev_get_machine()); 86 void *fdt; 87 int cpu; 88 uint32_t *cells; 89 char *nodename; 90 char ethclk_names[] = "pclk\0hclk"; 91 uint32_t plic_phandle, prci_phandle, phandle = 1; 92 uint32_t hfclk_phandle, rtcclk_phandle, phy_phandle; 93 94 fdt = s->fdt = create_device_tree(&s->fdt_size); 95 if (!fdt) { 96 error_report("create_device_tree() failed"); 97 exit(1); 98 } 99 100 qemu_fdt_setprop_string(fdt, "/", "model", "SiFive HiFive Unleashed A00"); 101 qemu_fdt_setprop_string(fdt, "/", "compatible", 102 "sifive,hifive-unleashed-a00"); 103 qemu_fdt_setprop_cell(fdt, "/", "#size-cells", 0x2); 104 qemu_fdt_setprop_cell(fdt, "/", "#address-cells", 0x2); 105 106 qemu_fdt_add_subnode(fdt, "/soc"); 107 qemu_fdt_setprop(fdt, "/soc", "ranges", NULL, 0); 108 qemu_fdt_setprop_string(fdt, "/soc", "compatible", "simple-bus"); 109 qemu_fdt_setprop_cell(fdt, "/soc", "#size-cells", 0x2); 110 qemu_fdt_setprop_cell(fdt, "/soc", "#address-cells", 0x2); 111 112 hfclk_phandle = phandle++; 113 nodename = g_strdup_printf("/hfclk"); 114 qemu_fdt_add_subnode(fdt, nodename); 115 qemu_fdt_setprop_cell(fdt, nodename, "phandle", hfclk_phandle); 116 qemu_fdt_setprop_string(fdt, nodename, "clock-output-names", "hfclk"); 117 qemu_fdt_setprop_cell(fdt, nodename, "clock-frequency", 118 SIFIVE_U_HFCLK_FREQ); 119 qemu_fdt_setprop_string(fdt, nodename, "compatible", "fixed-clock"); 120 qemu_fdt_setprop_cell(fdt, nodename, "#clock-cells", 0x0); 121 g_free(nodename); 122 123 rtcclk_phandle = phandle++; 124 nodename = g_strdup_printf("/rtcclk"); 125 qemu_fdt_add_subnode(fdt, nodename); 126 qemu_fdt_setprop_cell(fdt, nodename, "phandle", rtcclk_phandle); 127 qemu_fdt_setprop_string(fdt, nodename, "clock-output-names", "rtcclk"); 128 qemu_fdt_setprop_cell(fdt, nodename, "clock-frequency", 129 SIFIVE_U_RTCCLK_FREQ); 130 qemu_fdt_setprop_string(fdt, nodename, "compatible", "fixed-clock"); 131 qemu_fdt_setprop_cell(fdt, nodename, "#clock-cells", 0x0); 132 g_free(nodename); 133 134 nodename = g_strdup_printf("/memory@%lx", 135 (long)memmap[SIFIVE_U_DRAM].base); 136 qemu_fdt_add_subnode(fdt, nodename); 137 qemu_fdt_setprop_cells(fdt, nodename, "reg", 138 memmap[SIFIVE_U_DRAM].base >> 32, memmap[SIFIVE_U_DRAM].base, 139 mem_size >> 32, mem_size); 140 qemu_fdt_setprop_string(fdt, nodename, "device_type", "memory"); 141 g_free(nodename); 142 143 qemu_fdt_add_subnode(fdt, "/cpus"); 144 qemu_fdt_setprop_cell(fdt, "/cpus", "timebase-frequency", 145 SIFIVE_CLINT_TIMEBASE_FREQ); 146 qemu_fdt_setprop_cell(fdt, "/cpus", "#size-cells", 0x0); 147 qemu_fdt_setprop_cell(fdt, "/cpus", "#address-cells", 0x1); 148 149 for (cpu = ms->smp.cpus - 1; cpu >= 0; cpu--) { 150 int cpu_phandle = phandle++; 151 nodename = g_strdup_printf("/cpus/cpu@%d", cpu); 152 char *intc = g_strdup_printf("/cpus/cpu@%d/interrupt-controller", cpu); 153 char *isa; 154 qemu_fdt_add_subnode(fdt, nodename); 155 /* cpu 0 is the management hart that does not have mmu */ 156 if (cpu != 0) { 157 qemu_fdt_setprop_string(fdt, nodename, "mmu-type", "riscv,sv48"); 158 isa = riscv_isa_string(&s->soc.u_cpus.harts[cpu - 1]); 159 } else { 160 isa = riscv_isa_string(&s->soc.e_cpus.harts[0]); 161 } 162 qemu_fdt_setprop_string(fdt, nodename, "riscv,isa", isa); 163 qemu_fdt_setprop_string(fdt, nodename, "compatible", "riscv"); 164 qemu_fdt_setprop_string(fdt, nodename, "status", "okay"); 165 qemu_fdt_setprop_cell(fdt, nodename, "reg", cpu); 166 qemu_fdt_setprop_string(fdt, nodename, "device_type", "cpu"); 167 qemu_fdt_add_subnode(fdt, intc); 168 qemu_fdt_setprop_cell(fdt, intc, "phandle", cpu_phandle); 169 qemu_fdt_setprop_string(fdt, intc, "compatible", "riscv,cpu-intc"); 170 qemu_fdt_setprop(fdt, intc, "interrupt-controller", NULL, 0); 171 qemu_fdt_setprop_cell(fdt, intc, "#interrupt-cells", 1); 172 g_free(isa); 173 g_free(intc); 174 g_free(nodename); 175 } 176 177 cells = g_new0(uint32_t, ms->smp.cpus * 4); 178 for (cpu = 0; cpu < ms->smp.cpus; cpu++) { 179 nodename = 180 g_strdup_printf("/cpus/cpu@%d/interrupt-controller", cpu); 181 uint32_t intc_phandle = qemu_fdt_get_phandle(fdt, nodename); 182 cells[cpu * 4 + 0] = cpu_to_be32(intc_phandle); 183 cells[cpu * 4 + 1] = cpu_to_be32(IRQ_M_SOFT); 184 cells[cpu * 4 + 2] = cpu_to_be32(intc_phandle); 185 cells[cpu * 4 + 3] = cpu_to_be32(IRQ_M_TIMER); 186 g_free(nodename); 187 } 188 nodename = g_strdup_printf("/soc/clint@%lx", 189 (long)memmap[SIFIVE_U_CLINT].base); 190 qemu_fdt_add_subnode(fdt, nodename); 191 qemu_fdt_setprop_string(fdt, nodename, "compatible", "riscv,clint0"); 192 qemu_fdt_setprop_cells(fdt, nodename, "reg", 193 0x0, memmap[SIFIVE_U_CLINT].base, 194 0x0, memmap[SIFIVE_U_CLINT].size); 195 qemu_fdt_setprop(fdt, nodename, "interrupts-extended", 196 cells, ms->smp.cpus * sizeof(uint32_t) * 4); 197 g_free(cells); 198 g_free(nodename); 199 200 prci_phandle = phandle++; 201 nodename = g_strdup_printf("/soc/clock-controller@%lx", 202 (long)memmap[SIFIVE_U_PRCI].base); 203 qemu_fdt_add_subnode(fdt, nodename); 204 qemu_fdt_setprop_cell(fdt, nodename, "phandle", prci_phandle); 205 qemu_fdt_setprop_cell(fdt, nodename, "#clock-cells", 0x1); 206 qemu_fdt_setprop_cells(fdt, nodename, "clocks", 207 hfclk_phandle, rtcclk_phandle); 208 qemu_fdt_setprop_cells(fdt, nodename, "reg", 209 0x0, memmap[SIFIVE_U_PRCI].base, 210 0x0, memmap[SIFIVE_U_PRCI].size); 211 qemu_fdt_setprop_string(fdt, nodename, "compatible", 212 "sifive,fu540-c000-prci"); 213 g_free(nodename); 214 215 plic_phandle = phandle++; 216 cells = g_new0(uint32_t, ms->smp.cpus * 4 - 2); 217 for (cpu = 0; cpu < ms->smp.cpus; cpu++) { 218 nodename = 219 g_strdup_printf("/cpus/cpu@%d/interrupt-controller", cpu); 220 uint32_t intc_phandle = qemu_fdt_get_phandle(fdt, nodename); 221 /* cpu 0 is the management hart that does not have S-mode */ 222 if (cpu == 0) { 223 cells[0] = cpu_to_be32(intc_phandle); 224 cells[1] = cpu_to_be32(IRQ_M_EXT); 225 } else { 226 cells[cpu * 4 - 2] = cpu_to_be32(intc_phandle); 227 cells[cpu * 4 - 1] = cpu_to_be32(IRQ_M_EXT); 228 cells[cpu * 4 + 0] = cpu_to_be32(intc_phandle); 229 cells[cpu * 4 + 1] = cpu_to_be32(IRQ_S_EXT); 230 } 231 g_free(nodename); 232 } 233 nodename = g_strdup_printf("/soc/interrupt-controller@%lx", 234 (long)memmap[SIFIVE_U_PLIC].base); 235 qemu_fdt_add_subnode(fdt, nodename); 236 qemu_fdt_setprop_cell(fdt, nodename, "#interrupt-cells", 1); 237 qemu_fdt_setprop_string(fdt, nodename, "compatible", "riscv,plic0"); 238 qemu_fdt_setprop(fdt, nodename, "interrupt-controller", NULL, 0); 239 qemu_fdt_setprop(fdt, nodename, "interrupts-extended", 240 cells, (ms->smp.cpus * 4 - 2) * sizeof(uint32_t)); 241 qemu_fdt_setprop_cells(fdt, nodename, "reg", 242 0x0, memmap[SIFIVE_U_PLIC].base, 243 0x0, memmap[SIFIVE_U_PLIC].size); 244 qemu_fdt_setprop_cell(fdt, nodename, "riscv,ndev", 0x35); 245 qemu_fdt_setprop_cell(fdt, nodename, "phandle", plic_phandle); 246 plic_phandle = qemu_fdt_get_phandle(fdt, nodename); 247 g_free(cells); 248 g_free(nodename); 249 250 phy_phandle = phandle++; 251 nodename = g_strdup_printf("/soc/ethernet@%lx", 252 (long)memmap[SIFIVE_U_GEM].base); 253 qemu_fdt_add_subnode(fdt, nodename); 254 qemu_fdt_setprop_string(fdt, nodename, "compatible", 255 "sifive,fu540-c000-gem"); 256 qemu_fdt_setprop_cells(fdt, nodename, "reg", 257 0x0, memmap[SIFIVE_U_GEM].base, 258 0x0, memmap[SIFIVE_U_GEM].size, 259 0x0, memmap[SIFIVE_U_GEM_MGMT].base, 260 0x0, memmap[SIFIVE_U_GEM_MGMT].size); 261 qemu_fdt_setprop_string(fdt, nodename, "reg-names", "control"); 262 qemu_fdt_setprop_string(fdt, nodename, "phy-mode", "gmii"); 263 qemu_fdt_setprop_cell(fdt, nodename, "phy-handle", phy_phandle); 264 qemu_fdt_setprop_cell(fdt, nodename, "interrupt-parent", plic_phandle); 265 qemu_fdt_setprop_cell(fdt, nodename, "interrupts", SIFIVE_U_GEM_IRQ); 266 qemu_fdt_setprop_cells(fdt, nodename, "clocks", 267 prci_phandle, PRCI_CLK_GEMGXLPLL, prci_phandle, PRCI_CLK_GEMGXLPLL); 268 qemu_fdt_setprop(fdt, nodename, "clock-names", ethclk_names, 269 sizeof(ethclk_names)); 270 qemu_fdt_setprop(fdt, nodename, "local-mac-address", 271 s->soc.gem.conf.macaddr.a, ETH_ALEN); 272 qemu_fdt_setprop_cell(fdt, nodename, "#address-cells", 1); 273 qemu_fdt_setprop_cell(fdt, nodename, "#size-cells", 0); 274 275 qemu_fdt_add_subnode(fdt, "/aliases"); 276 qemu_fdt_setprop_string(fdt, "/aliases", "ethernet0", nodename); 277 278 g_free(nodename); 279 280 nodename = g_strdup_printf("/soc/ethernet@%lx/ethernet-phy@0", 281 (long)memmap[SIFIVE_U_GEM].base); 282 qemu_fdt_add_subnode(fdt, nodename); 283 qemu_fdt_setprop_cell(fdt, nodename, "phandle", phy_phandle); 284 qemu_fdt_setprop_cell(fdt, nodename, "reg", 0x0); 285 g_free(nodename); 286 287 nodename = g_strdup_printf("/soc/serial@%lx", 288 (long)memmap[SIFIVE_U_UART0].base); 289 qemu_fdt_add_subnode(fdt, nodename); 290 qemu_fdt_setprop_string(fdt, nodename, "compatible", "sifive,uart0"); 291 qemu_fdt_setprop_cells(fdt, nodename, "reg", 292 0x0, memmap[SIFIVE_U_UART0].base, 293 0x0, memmap[SIFIVE_U_UART0].size); 294 qemu_fdt_setprop_cells(fdt, nodename, "clocks", 295 prci_phandle, PRCI_CLK_TLCLK); 296 qemu_fdt_setprop_cell(fdt, nodename, "interrupt-parent", plic_phandle); 297 qemu_fdt_setprop_cell(fdt, nodename, "interrupts", SIFIVE_U_UART0_IRQ); 298 299 qemu_fdt_add_subnode(fdt, "/chosen"); 300 qemu_fdt_setprop_string(fdt, "/chosen", "stdout-path", nodename); 301 if (cmdline) { 302 qemu_fdt_setprop_string(fdt, "/chosen", "bootargs", cmdline); 303 } 304 305 qemu_fdt_setprop_string(fdt, "/aliases", "serial0", nodename); 306 307 g_free(nodename); 308 } 309 310 static void riscv_sifive_u_init(MachineState *machine) 311 { 312 const struct MemmapEntry *memmap = sifive_u_memmap; 313 314 SiFiveUState *s = g_new0(SiFiveUState, 1); 315 MemoryRegion *system_memory = get_system_memory(); 316 MemoryRegion *main_mem = g_new(MemoryRegion, 1); 317 int i; 318 319 /* Initialize SoC */ 320 object_initialize_child(OBJECT(machine), "soc", &s->soc, 321 sizeof(s->soc), TYPE_RISCV_U_SOC, 322 &error_abort, NULL); 323 object_property_set_bool(OBJECT(&s->soc), true, "realized", 324 &error_abort); 325 326 /* register RAM */ 327 memory_region_init_ram(main_mem, NULL, "riscv.sifive.u.ram", 328 machine->ram_size, &error_fatal); 329 memory_region_add_subregion(system_memory, memmap[SIFIVE_U_DRAM].base, 330 main_mem); 331 332 /* create device tree */ 333 create_fdt(s, memmap, machine->ram_size, machine->kernel_cmdline); 334 335 riscv_find_and_load_firmware(machine, BIOS_FILENAME, 336 memmap[SIFIVE_U_DRAM].base); 337 338 if (machine->kernel_filename) { 339 uint64_t kernel_entry = riscv_load_kernel(machine->kernel_filename); 340 341 if (machine->initrd_filename) { 342 hwaddr start; 343 hwaddr end = riscv_load_initrd(machine->initrd_filename, 344 machine->ram_size, kernel_entry, 345 &start); 346 qemu_fdt_setprop_cell(s->fdt, "/chosen", 347 "linux,initrd-start", start); 348 qemu_fdt_setprop_cell(s->fdt, "/chosen", "linux,initrd-end", 349 end); 350 } 351 } 352 353 /* reset vector */ 354 uint32_t reset_vec[8] = { 355 0x00000297, /* 1: auipc t0, %pcrel_hi(dtb) */ 356 0x02028593, /* addi a1, t0, %pcrel_lo(1b) */ 357 0xf1402573, /* csrr a0, mhartid */ 358 #if defined(TARGET_RISCV32) 359 0x0182a283, /* lw t0, 24(t0) */ 360 #elif defined(TARGET_RISCV64) 361 0x0182b283, /* ld t0, 24(t0) */ 362 #endif 363 0x00028067, /* jr t0 */ 364 0x00000000, 365 memmap[SIFIVE_U_DRAM].base, /* start: .dword DRAM_BASE */ 366 0x00000000, 367 /* dtb: */ 368 }; 369 370 /* copy in the reset vector in little_endian byte order */ 371 for (i = 0; i < sizeof(reset_vec) >> 2; i++) { 372 reset_vec[i] = cpu_to_le32(reset_vec[i]); 373 } 374 rom_add_blob_fixed_as("mrom.reset", reset_vec, sizeof(reset_vec), 375 memmap[SIFIVE_U_MROM].base, &address_space_memory); 376 377 /* copy in the device tree */ 378 if (fdt_pack(s->fdt) || fdt_totalsize(s->fdt) > 379 memmap[SIFIVE_U_MROM].size - sizeof(reset_vec)) { 380 error_report("not enough space to store device-tree"); 381 exit(1); 382 } 383 qemu_fdt_dumpdtb(s->fdt, fdt_totalsize(s->fdt)); 384 rom_add_blob_fixed_as("mrom.fdt", s->fdt, fdt_totalsize(s->fdt), 385 memmap[SIFIVE_U_MROM].base + sizeof(reset_vec), 386 &address_space_memory); 387 } 388 389 static void riscv_sifive_u_soc_init(Object *obj) 390 { 391 MachineState *ms = MACHINE(qdev_get_machine()); 392 SiFiveUSoCState *s = RISCV_U_SOC(obj); 393 394 object_initialize_child(obj, "e-cluster", &s->e_cluster, 395 sizeof(s->e_cluster), TYPE_CPU_CLUSTER, 396 &error_abort, NULL); 397 qdev_prop_set_uint32(DEVICE(&s->e_cluster), "cluster-id", 0); 398 399 object_initialize_child(OBJECT(&s->e_cluster), "e-cpus", 400 &s->e_cpus, sizeof(s->e_cpus), 401 TYPE_RISCV_HART_ARRAY, &error_abort, 402 NULL); 403 qdev_prop_set_uint32(DEVICE(&s->e_cpus), "num-harts", 1); 404 qdev_prop_set_uint32(DEVICE(&s->e_cpus), "hartid-base", 0); 405 qdev_prop_set_string(DEVICE(&s->e_cpus), "cpu-type", SIFIVE_E_CPU); 406 407 object_initialize_child(obj, "u-cluster", &s->u_cluster, 408 sizeof(s->u_cluster), TYPE_CPU_CLUSTER, 409 &error_abort, NULL); 410 qdev_prop_set_uint32(DEVICE(&s->u_cluster), "cluster-id", 1); 411 412 object_initialize_child(OBJECT(&s->u_cluster), "u-cpus", 413 &s->u_cpus, sizeof(s->u_cpus), 414 TYPE_RISCV_HART_ARRAY, &error_abort, 415 NULL); 416 qdev_prop_set_uint32(DEVICE(&s->u_cpus), "num-harts", ms->smp.cpus - 1); 417 qdev_prop_set_uint32(DEVICE(&s->u_cpus), "hartid-base", 1); 418 qdev_prop_set_string(DEVICE(&s->u_cpus), "cpu-type", SIFIVE_U_CPU); 419 420 sysbus_init_child_obj(obj, "prci", &s->prci, sizeof(s->prci), 421 TYPE_SIFIVE_U_PRCI); 422 sysbus_init_child_obj(obj, "otp", &s->otp, sizeof(s->otp), 423 TYPE_SIFIVE_U_OTP); 424 qdev_prop_set_uint32(DEVICE(&s->otp), "serial", OTP_SERIAL); 425 sysbus_init_child_obj(obj, "gem", &s->gem, sizeof(s->gem), 426 TYPE_CADENCE_GEM); 427 } 428 429 static void riscv_sifive_u_soc_realize(DeviceState *dev, Error **errp) 430 { 431 MachineState *ms = MACHINE(qdev_get_machine()); 432 SiFiveUSoCState *s = RISCV_U_SOC(dev); 433 const struct MemmapEntry *memmap = sifive_u_memmap; 434 MemoryRegion *system_memory = get_system_memory(); 435 MemoryRegion *mask_rom = g_new(MemoryRegion, 1); 436 MemoryRegion *l2lim_mem = g_new(MemoryRegion, 1); 437 qemu_irq plic_gpios[SIFIVE_U_PLIC_NUM_SOURCES]; 438 char *plic_hart_config; 439 size_t plic_hart_config_len; 440 int i; 441 Error *err = NULL; 442 NICInfo *nd = &nd_table[0]; 443 444 object_property_set_bool(OBJECT(&s->e_cpus), true, "realized", 445 &error_abort); 446 object_property_set_bool(OBJECT(&s->u_cpus), true, "realized", 447 &error_abort); 448 /* 449 * The cluster must be realized after the RISC-V hart array container, 450 * as the container's CPU object is only created on realize, and the 451 * CPU must exist and have been parented into the cluster before the 452 * cluster is realized. 453 */ 454 object_property_set_bool(OBJECT(&s->e_cluster), true, "realized", 455 &error_abort); 456 object_property_set_bool(OBJECT(&s->u_cluster), true, "realized", 457 &error_abort); 458 459 /* boot rom */ 460 memory_region_init_rom(mask_rom, NULL, "riscv.sifive.u.mrom", 461 memmap[SIFIVE_U_MROM].size, &error_fatal); 462 memory_region_add_subregion(system_memory, memmap[SIFIVE_U_MROM].base, 463 mask_rom); 464 465 /* 466 * Add L2-LIM at reset size. 467 * This should be reduced in size as the L2 Cache Controller WayEnable 468 * register is incremented. Unfortunately I don't see a nice (or any) way 469 * to handle reducing or blocking out the L2 LIM while still allowing it 470 * be re returned to all enabled after a reset. For the time being, just 471 * leave it enabled all the time. This won't break anything, but will be 472 * too generous to misbehaving guests. 473 */ 474 memory_region_init_ram(l2lim_mem, NULL, "riscv.sifive.u.l2lim", 475 memmap[SIFIVE_U_L2LIM].size, &error_fatal); 476 memory_region_add_subregion(system_memory, memmap[SIFIVE_U_L2LIM].base, 477 l2lim_mem); 478 479 /* create PLIC hart topology configuration string */ 480 plic_hart_config_len = (strlen(SIFIVE_U_PLIC_HART_CONFIG) + 1) * 481 ms->smp.cpus; 482 plic_hart_config = g_malloc0(plic_hart_config_len); 483 for (i = 0; i < ms->smp.cpus; i++) { 484 if (i != 0) { 485 strncat(plic_hart_config, "," SIFIVE_U_PLIC_HART_CONFIG, 486 plic_hart_config_len); 487 } else { 488 strncat(plic_hart_config, "M", plic_hart_config_len); 489 } 490 plic_hart_config_len -= (strlen(SIFIVE_U_PLIC_HART_CONFIG) + 1); 491 } 492 493 /* MMIO */ 494 s->plic = sifive_plic_create(memmap[SIFIVE_U_PLIC].base, 495 plic_hart_config, 496 SIFIVE_U_PLIC_NUM_SOURCES, 497 SIFIVE_U_PLIC_NUM_PRIORITIES, 498 SIFIVE_U_PLIC_PRIORITY_BASE, 499 SIFIVE_U_PLIC_PENDING_BASE, 500 SIFIVE_U_PLIC_ENABLE_BASE, 501 SIFIVE_U_PLIC_ENABLE_STRIDE, 502 SIFIVE_U_PLIC_CONTEXT_BASE, 503 SIFIVE_U_PLIC_CONTEXT_STRIDE, 504 memmap[SIFIVE_U_PLIC].size); 505 sifive_uart_create(system_memory, memmap[SIFIVE_U_UART0].base, 506 serial_hd(0), qdev_get_gpio_in(DEVICE(s->plic), SIFIVE_U_UART0_IRQ)); 507 sifive_uart_create(system_memory, memmap[SIFIVE_U_UART1].base, 508 serial_hd(1), qdev_get_gpio_in(DEVICE(s->plic), SIFIVE_U_UART1_IRQ)); 509 sifive_clint_create(memmap[SIFIVE_U_CLINT].base, 510 memmap[SIFIVE_U_CLINT].size, ms->smp.cpus, 511 SIFIVE_SIP_BASE, SIFIVE_TIMECMP_BASE, SIFIVE_TIME_BASE); 512 513 object_property_set_bool(OBJECT(&s->prci), true, "realized", &err); 514 sysbus_mmio_map(SYS_BUS_DEVICE(&s->prci), 0, memmap[SIFIVE_U_PRCI].base); 515 516 object_property_set_bool(OBJECT(&s->otp), true, "realized", &err); 517 sysbus_mmio_map(SYS_BUS_DEVICE(&s->otp), 0, memmap[SIFIVE_U_OTP].base); 518 519 for (i = 0; i < SIFIVE_U_PLIC_NUM_SOURCES; i++) { 520 plic_gpios[i] = qdev_get_gpio_in(DEVICE(s->plic), i); 521 } 522 523 if (nd->used) { 524 qemu_check_nic_model(nd, TYPE_CADENCE_GEM); 525 qdev_set_nic_properties(DEVICE(&s->gem), nd); 526 } 527 object_property_set_int(OBJECT(&s->gem), GEM_REVISION, "revision", 528 &error_abort); 529 object_property_set_bool(OBJECT(&s->gem), true, "realized", &err); 530 if (err) { 531 error_propagate(errp, err); 532 return; 533 } 534 sysbus_mmio_map(SYS_BUS_DEVICE(&s->gem), 0, memmap[SIFIVE_U_GEM].base); 535 sysbus_connect_irq(SYS_BUS_DEVICE(&s->gem), 0, 536 plic_gpios[SIFIVE_U_GEM_IRQ]); 537 538 create_unimplemented_device("riscv.sifive.u.gem-mgmt", 539 memmap[SIFIVE_U_GEM_MGMT].base, memmap[SIFIVE_U_GEM_MGMT].size); 540 } 541 542 static void riscv_sifive_u_machine_init(MachineClass *mc) 543 { 544 mc->desc = "RISC-V Board compatible with SiFive U SDK"; 545 mc->init = riscv_sifive_u_init; 546 mc->max_cpus = SIFIVE_U_MANAGEMENT_CPU_COUNT + SIFIVE_U_COMPUTE_CPU_COUNT; 547 mc->min_cpus = SIFIVE_U_MANAGEMENT_CPU_COUNT + 1; 548 mc->default_cpus = mc->min_cpus; 549 } 550 551 DEFINE_MACHINE("sifive_u", riscv_sifive_u_machine_init) 552 553 static void riscv_sifive_u_soc_class_init(ObjectClass *oc, void *data) 554 { 555 DeviceClass *dc = DEVICE_CLASS(oc); 556 557 dc->realize = riscv_sifive_u_soc_realize; 558 /* Reason: Uses serial_hds in realize function, thus can't be used twice */ 559 dc->user_creatable = false; 560 } 561 562 static const TypeInfo riscv_sifive_u_soc_type_info = { 563 .name = TYPE_RISCV_U_SOC, 564 .parent = TYPE_DEVICE, 565 .instance_size = sizeof(SiFiveUSoCState), 566 .instance_init = riscv_sifive_u_soc_init, 567 .class_init = riscv_sifive_u_soc_class_init, 568 }; 569 570 static void riscv_sifive_u_soc_register_types(void) 571 { 572 type_register_static(&riscv_sifive_u_soc_type_info); 573 } 574 575 type_init(riscv_sifive_u_soc_register_types) 576