1 /* 2 * QEMU RISC-V Board Compatible with SiFive Freedom U SDK 3 * 4 * Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu 5 * Copyright (c) 2017 SiFive, Inc. 6 * 7 * Provides a board compatible with the SiFive Freedom U SDK: 8 * 9 * 0) UART 10 * 1) CLINT (Core Level Interruptor) 11 * 2) PLIC (Platform Level Interrupt Controller) 12 * 13 * This board currently uses a hardcoded devicetree that indicates one hart. 14 * 15 * This program is free software; you can redistribute it and/or modify it 16 * under the terms and conditions of the GNU General Public License, 17 * version 2 or later, as published by the Free Software Foundation. 18 * 19 * This program is distributed in the hope it will be useful, but WITHOUT 20 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 21 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 22 * more details. 23 * 24 * You should have received a copy of the GNU General Public License along with 25 * this program. If not, see <http://www.gnu.org/licenses/>. 26 */ 27 28 #include "qemu/osdep.h" 29 #include "qemu/log.h" 30 #include "qemu/error-report.h" 31 #include "qapi/error.h" 32 #include "hw/hw.h" 33 #include "hw/boards.h" 34 #include "hw/loader.h" 35 #include "hw/sysbus.h" 36 #include "hw/char/serial.h" 37 #include "target/riscv/cpu.h" 38 #include "hw/riscv/riscv_hart.h" 39 #include "hw/riscv/sifive_plic.h" 40 #include "hw/riscv/sifive_clint.h" 41 #include "hw/riscv/sifive_uart.h" 42 #include "hw/riscv/sifive_prci.h" 43 #include "hw/riscv/sifive_u.h" 44 #include "chardev/char.h" 45 #include "sysemu/arch_init.h" 46 #include "sysemu/device_tree.h" 47 #include "exec/address-spaces.h" 48 #include "elf.h" 49 50 #include <libfdt.h> 51 52 static const struct MemmapEntry { 53 hwaddr base; 54 hwaddr size; 55 } sifive_u_memmap[] = { 56 [SIFIVE_U_DEBUG] = { 0x0, 0x100 }, 57 [SIFIVE_U_MROM] = { 0x1000, 0x11000 }, 58 [SIFIVE_U_CLINT] = { 0x2000000, 0x10000 }, 59 [SIFIVE_U_PLIC] = { 0xc000000, 0x4000000 }, 60 [SIFIVE_U_UART0] = { 0x10013000, 0x1000 }, 61 [SIFIVE_U_UART1] = { 0x10023000, 0x1000 }, 62 [SIFIVE_U_DRAM] = { 0x80000000, 0x0 }, 63 [SIFIVE_U_GEM] = { 0x100900FC, 0x2000 }, 64 }; 65 66 #define GEM_REVISION 0x10070109 67 68 static target_ulong load_kernel(const char *kernel_filename) 69 { 70 uint64_t kernel_entry, kernel_high; 71 72 if (load_elf(kernel_filename, NULL, NULL, NULL, 73 &kernel_entry, NULL, &kernel_high, 74 0, EM_RISCV, 1, 0) < 0) { 75 error_report("could not load kernel '%s'", kernel_filename); 76 exit(1); 77 } 78 return kernel_entry; 79 } 80 81 static void create_fdt(SiFiveUState *s, const struct MemmapEntry *memmap, 82 uint64_t mem_size, const char *cmdline) 83 { 84 void *fdt; 85 int cpu; 86 uint32_t *cells; 87 char *nodename; 88 char ethclk_names[] = "pclk\0hclk\0tx_clk"; 89 uint32_t plic_phandle, ethclk_phandle, phandle = 1; 90 91 fdt = s->fdt = create_device_tree(&s->fdt_size); 92 if (!fdt) { 93 error_report("create_device_tree() failed"); 94 exit(1); 95 } 96 97 qemu_fdt_setprop_string(fdt, "/", "model", "ucbbar,spike-bare,qemu"); 98 qemu_fdt_setprop_string(fdt, "/", "compatible", "ucbbar,spike-bare-dev"); 99 qemu_fdt_setprop_cell(fdt, "/", "#size-cells", 0x2); 100 qemu_fdt_setprop_cell(fdt, "/", "#address-cells", 0x2); 101 102 qemu_fdt_add_subnode(fdt, "/soc"); 103 qemu_fdt_setprop(fdt, "/soc", "ranges", NULL, 0); 104 qemu_fdt_setprop_string(fdt, "/soc", "compatible", "simple-bus"); 105 qemu_fdt_setprop_cell(fdt, "/soc", "#size-cells", 0x2); 106 qemu_fdt_setprop_cell(fdt, "/soc", "#address-cells", 0x2); 107 108 nodename = g_strdup_printf("/memory@%lx", 109 (long)memmap[SIFIVE_U_DRAM].base); 110 qemu_fdt_add_subnode(fdt, nodename); 111 qemu_fdt_setprop_cells(fdt, nodename, "reg", 112 memmap[SIFIVE_U_DRAM].base >> 32, memmap[SIFIVE_U_DRAM].base, 113 mem_size >> 32, mem_size); 114 qemu_fdt_setprop_string(fdt, nodename, "device_type", "memory"); 115 g_free(nodename); 116 117 qemu_fdt_add_subnode(fdt, "/cpus"); 118 qemu_fdt_setprop_cell(fdt, "/cpus", "timebase-frequency", 119 SIFIVE_CLINT_TIMEBASE_FREQ); 120 qemu_fdt_setprop_cell(fdt, "/cpus", "#size-cells", 0x0); 121 qemu_fdt_setprop_cell(fdt, "/cpus", "#address-cells", 0x1); 122 123 for (cpu = s->soc.cpus.num_harts - 1; cpu >= 0; cpu--) { 124 int cpu_phandle = phandle++; 125 nodename = g_strdup_printf("/cpus/cpu@%d", cpu); 126 char *intc = g_strdup_printf("/cpus/cpu@%d/interrupt-controller", cpu); 127 char *isa = riscv_isa_string(&s->soc.cpus.harts[cpu]); 128 qemu_fdt_add_subnode(fdt, nodename); 129 qemu_fdt_setprop_cell(fdt, nodename, "clock-frequency", 130 SIFIVE_U_CLOCK_FREQ); 131 qemu_fdt_setprop_string(fdt, nodename, "mmu-type", "riscv,sv48"); 132 qemu_fdt_setprop_string(fdt, nodename, "riscv,isa", isa); 133 qemu_fdt_setprop_string(fdt, nodename, "compatible", "riscv"); 134 qemu_fdt_setprop_string(fdt, nodename, "status", "okay"); 135 qemu_fdt_setprop_cell(fdt, nodename, "reg", cpu); 136 qemu_fdt_setprop_string(fdt, nodename, "device_type", "cpu"); 137 qemu_fdt_add_subnode(fdt, intc); 138 qemu_fdt_setprop_cell(fdt, intc, "phandle", cpu_phandle); 139 qemu_fdt_setprop_cell(fdt, intc, "linux,phandle", cpu_phandle); 140 qemu_fdt_setprop_string(fdt, intc, "compatible", "riscv,cpu-intc"); 141 qemu_fdt_setprop(fdt, intc, "interrupt-controller", NULL, 0); 142 qemu_fdt_setprop_cell(fdt, intc, "#interrupt-cells", 1); 143 g_free(isa); 144 g_free(intc); 145 g_free(nodename); 146 } 147 148 cells = g_new0(uint32_t, s->soc.cpus.num_harts * 4); 149 for (cpu = 0; cpu < s->soc.cpus.num_harts; cpu++) { 150 nodename = 151 g_strdup_printf("/cpus/cpu@%d/interrupt-controller", cpu); 152 uint32_t intc_phandle = qemu_fdt_get_phandle(fdt, nodename); 153 cells[cpu * 4 + 0] = cpu_to_be32(intc_phandle); 154 cells[cpu * 4 + 1] = cpu_to_be32(IRQ_M_SOFT); 155 cells[cpu * 4 + 2] = cpu_to_be32(intc_phandle); 156 cells[cpu * 4 + 3] = cpu_to_be32(IRQ_M_TIMER); 157 g_free(nodename); 158 } 159 nodename = g_strdup_printf("/soc/clint@%lx", 160 (long)memmap[SIFIVE_U_CLINT].base); 161 qemu_fdt_add_subnode(fdt, nodename); 162 qemu_fdt_setprop_string(fdt, nodename, "compatible", "riscv,clint0"); 163 qemu_fdt_setprop_cells(fdt, nodename, "reg", 164 0x0, memmap[SIFIVE_U_CLINT].base, 165 0x0, memmap[SIFIVE_U_CLINT].size); 166 qemu_fdt_setprop(fdt, nodename, "interrupts-extended", 167 cells, s->soc.cpus.num_harts * sizeof(uint32_t) * 4); 168 g_free(cells); 169 g_free(nodename); 170 171 plic_phandle = phandle++; 172 cells = g_new0(uint32_t, s->soc.cpus.num_harts * 4); 173 for (cpu = 0; cpu < s->soc.cpus.num_harts; cpu++) { 174 nodename = 175 g_strdup_printf("/cpus/cpu@%d/interrupt-controller", cpu); 176 uint32_t intc_phandle = qemu_fdt_get_phandle(fdt, nodename); 177 cells[cpu * 4 + 0] = cpu_to_be32(intc_phandle); 178 cells[cpu * 4 + 1] = cpu_to_be32(IRQ_M_EXT); 179 cells[cpu * 4 + 2] = cpu_to_be32(intc_phandle); 180 cells[cpu * 4 + 3] = cpu_to_be32(IRQ_S_EXT); 181 g_free(nodename); 182 } 183 nodename = g_strdup_printf("/soc/interrupt-controller@%lx", 184 (long)memmap[SIFIVE_U_PLIC].base); 185 qemu_fdt_add_subnode(fdt, nodename); 186 qemu_fdt_setprop_cell(fdt, nodename, "#interrupt-cells", 1); 187 qemu_fdt_setprop_string(fdt, nodename, "compatible", "riscv,plic0"); 188 qemu_fdt_setprop(fdt, nodename, "interrupt-controller", NULL, 0); 189 qemu_fdt_setprop(fdt, nodename, "interrupts-extended", 190 cells, s->soc.cpus.num_harts * sizeof(uint32_t) * 4); 191 qemu_fdt_setprop_cells(fdt, nodename, "reg", 192 0x0, memmap[SIFIVE_U_PLIC].base, 193 0x0, memmap[SIFIVE_U_PLIC].size); 194 qemu_fdt_setprop_string(fdt, nodename, "reg-names", "control"); 195 qemu_fdt_setprop_cell(fdt, nodename, "riscv,max-priority", 7); 196 qemu_fdt_setprop_cell(fdt, nodename, "riscv,ndev", 0x35); 197 qemu_fdt_setprop_cells(fdt, nodename, "phandle", plic_phandle); 198 qemu_fdt_setprop_cells(fdt, nodename, "linux,phandle", plic_phandle); 199 plic_phandle = qemu_fdt_get_phandle(fdt, nodename); 200 g_free(cells); 201 g_free(nodename); 202 203 ethclk_phandle = phandle++; 204 nodename = g_strdup_printf("/soc/ethclk"); 205 qemu_fdt_add_subnode(fdt, nodename); 206 qemu_fdt_setprop_string(fdt, nodename, "compatible", "fixed-clock"); 207 qemu_fdt_setprop_cell(fdt, nodename, "#clock-cells", 0x0); 208 qemu_fdt_setprop_cell(fdt, nodename, "clock-frequency", 209 SIFIVE_U_GEM_CLOCK_FREQ); 210 qemu_fdt_setprop_cell(fdt, nodename, "phandle", ethclk_phandle); 211 qemu_fdt_setprop_cell(fdt, nodename, "linux,phandle", ethclk_phandle); 212 ethclk_phandle = qemu_fdt_get_phandle(fdt, nodename); 213 g_free(nodename); 214 215 nodename = g_strdup_printf("/soc/ethernet@%lx", 216 (long)memmap[SIFIVE_U_GEM].base); 217 qemu_fdt_add_subnode(fdt, nodename); 218 qemu_fdt_setprop_string(fdt, nodename, "compatible", "cdns,macb"); 219 qemu_fdt_setprop_cells(fdt, nodename, "reg", 220 0x0, memmap[SIFIVE_U_GEM].base, 221 0x0, memmap[SIFIVE_U_GEM].size); 222 qemu_fdt_setprop_string(fdt, nodename, "reg-names", "control"); 223 qemu_fdt_setprop_string(fdt, nodename, "phy-mode", "gmii"); 224 qemu_fdt_setprop_cells(fdt, nodename, "interrupt-parent", plic_phandle); 225 qemu_fdt_setprop_cells(fdt, nodename, "interrupts", SIFIVE_U_GEM_IRQ); 226 qemu_fdt_setprop_cells(fdt, nodename, "clocks", 227 ethclk_phandle, ethclk_phandle, ethclk_phandle); 228 qemu_fdt_setprop(fdt, nodename, "clocks-names", ethclk_names, 229 sizeof(ethclk_names)); 230 qemu_fdt_setprop_cells(fdt, nodename, "#address-cells", 1); 231 qemu_fdt_setprop_cells(fdt, nodename, "#size-cells", 0); 232 g_free(nodename); 233 234 nodename = g_strdup_printf("/soc/ethernet@%lx/ethernet-phy@0", 235 (long)memmap[SIFIVE_U_GEM].base); 236 qemu_fdt_add_subnode(fdt, nodename); 237 qemu_fdt_setprop_cells(fdt, nodename, "reg", 0x0); 238 g_free(nodename); 239 240 nodename = g_strdup_printf("/soc/uart@%lx", 241 (long)memmap[SIFIVE_U_UART0].base); 242 qemu_fdt_add_subnode(fdt, nodename); 243 qemu_fdt_setprop_string(fdt, nodename, "compatible", "sifive,uart0"); 244 qemu_fdt_setprop_cells(fdt, nodename, "reg", 245 0x0, memmap[SIFIVE_U_UART0].base, 246 0x0, memmap[SIFIVE_U_UART0].size); 247 qemu_fdt_setprop_cell(fdt, nodename, "clock-frequency", 248 SIFIVE_U_CLOCK_FREQ / 2); 249 qemu_fdt_setprop_cells(fdt, nodename, "interrupt-parent", plic_phandle); 250 qemu_fdt_setprop_cells(fdt, nodename, "interrupts", SIFIVE_U_UART0_IRQ); 251 252 qemu_fdt_add_subnode(fdt, "/chosen"); 253 qemu_fdt_setprop_string(fdt, "/chosen", "stdout-path", nodename); 254 if (cmdline) { 255 qemu_fdt_setprop_string(fdt, "/chosen", "bootargs", cmdline); 256 } 257 g_free(nodename); 258 } 259 260 static void riscv_sifive_u_init(MachineState *machine) 261 { 262 const struct MemmapEntry *memmap = sifive_u_memmap; 263 264 SiFiveUState *s = g_new0(SiFiveUState, 1); 265 MemoryRegion *system_memory = get_system_memory(); 266 MemoryRegion *main_mem = g_new(MemoryRegion, 1); 267 int i; 268 269 /* Initialize SoC */ 270 object_initialize_child(OBJECT(machine), "soc", &s->soc, 271 sizeof(s->soc), TYPE_RISCV_U_SOC, 272 &error_abort, NULL); 273 object_property_set_bool(OBJECT(&s->soc), true, "realized", 274 &error_abort); 275 276 /* register RAM */ 277 memory_region_init_ram(main_mem, NULL, "riscv.sifive.u.ram", 278 machine->ram_size, &error_fatal); 279 memory_region_add_subregion(system_memory, memmap[SIFIVE_U_DRAM].base, 280 main_mem); 281 282 /* create device tree */ 283 create_fdt(s, memmap, machine->ram_size, machine->kernel_cmdline); 284 285 if (machine->kernel_filename) { 286 load_kernel(machine->kernel_filename); 287 } 288 289 /* reset vector */ 290 uint32_t reset_vec[8] = { 291 0x00000297, /* 1: auipc t0, %pcrel_hi(dtb) */ 292 0x02028593, /* addi a1, t0, %pcrel_lo(1b) */ 293 0xf1402573, /* csrr a0, mhartid */ 294 #if defined(TARGET_RISCV32) 295 0x0182a283, /* lw t0, 24(t0) */ 296 #elif defined(TARGET_RISCV64) 297 0x0182b283, /* ld t0, 24(t0) */ 298 #endif 299 0x00028067, /* jr t0 */ 300 0x00000000, 301 memmap[SIFIVE_U_DRAM].base, /* start: .dword DRAM_BASE */ 302 0x00000000, 303 /* dtb: */ 304 }; 305 306 /* copy in the reset vector in little_endian byte order */ 307 for (i = 0; i < sizeof(reset_vec) >> 2; i++) { 308 reset_vec[i] = cpu_to_le32(reset_vec[i]); 309 } 310 rom_add_blob_fixed_as("mrom.reset", reset_vec, sizeof(reset_vec), 311 memmap[SIFIVE_U_MROM].base, &address_space_memory); 312 313 /* copy in the device tree */ 314 if (fdt_pack(s->fdt) || fdt_totalsize(s->fdt) > 315 memmap[SIFIVE_U_MROM].size - sizeof(reset_vec)) { 316 error_report("not enough space to store device-tree"); 317 exit(1); 318 } 319 qemu_fdt_dumpdtb(s->fdt, fdt_totalsize(s->fdt)); 320 rom_add_blob_fixed_as("mrom.fdt", s->fdt, fdt_totalsize(s->fdt), 321 memmap[SIFIVE_U_MROM].base + sizeof(reset_vec), 322 &address_space_memory); 323 } 324 325 static void riscv_sifive_u_soc_init(Object *obj) 326 { 327 SiFiveUSoCState *s = RISCV_U_SOC(obj); 328 329 object_initialize_child(obj, "cpus", &s->cpus, sizeof(s->cpus), 330 TYPE_RISCV_HART_ARRAY, &error_abort, NULL); 331 object_property_set_str(OBJECT(&s->cpus), SIFIVE_U_CPU, "cpu-type", 332 &error_abort); 333 object_property_set_int(OBJECT(&s->cpus), smp_cpus, "num-harts", 334 &error_abort); 335 336 sysbus_init_child_obj(obj, "gem", &s->gem, sizeof(s->gem), 337 TYPE_CADENCE_GEM); 338 } 339 340 static void riscv_sifive_u_soc_realize(DeviceState *dev, Error **errp) 341 { 342 SiFiveUSoCState *s = RISCV_U_SOC(dev); 343 const struct MemmapEntry *memmap = sifive_u_memmap; 344 MemoryRegion *system_memory = get_system_memory(); 345 MemoryRegion *mask_rom = g_new(MemoryRegion, 1); 346 qemu_irq plic_gpios[SIFIVE_U_PLIC_NUM_SOURCES]; 347 char *plic_hart_config; 348 size_t plic_hart_config_len; 349 int i; 350 Error *err = NULL; 351 NICInfo *nd = &nd_table[0]; 352 353 object_property_set_bool(OBJECT(&s->cpus), true, "realized", 354 &error_abort); 355 356 /* boot rom */ 357 memory_region_init_rom(mask_rom, NULL, "riscv.sifive.u.mrom", 358 memmap[SIFIVE_U_MROM].size, &error_fatal); 359 memory_region_add_subregion(system_memory, memmap[SIFIVE_U_MROM].base, 360 mask_rom); 361 362 /* create PLIC hart topology configuration string */ 363 plic_hart_config_len = (strlen(SIFIVE_U_PLIC_HART_CONFIG) + 1) * smp_cpus; 364 plic_hart_config = g_malloc0(plic_hart_config_len); 365 for (i = 0; i < smp_cpus; i++) { 366 if (i != 0) { 367 strncat(plic_hart_config, ",", plic_hart_config_len); 368 } 369 strncat(plic_hart_config, SIFIVE_U_PLIC_HART_CONFIG, 370 plic_hart_config_len); 371 plic_hart_config_len -= (strlen(SIFIVE_U_PLIC_HART_CONFIG) + 1); 372 } 373 374 /* MMIO */ 375 s->plic = sifive_plic_create(memmap[SIFIVE_U_PLIC].base, 376 plic_hart_config, 377 SIFIVE_U_PLIC_NUM_SOURCES, 378 SIFIVE_U_PLIC_NUM_PRIORITIES, 379 SIFIVE_U_PLIC_PRIORITY_BASE, 380 SIFIVE_U_PLIC_PENDING_BASE, 381 SIFIVE_U_PLIC_ENABLE_BASE, 382 SIFIVE_U_PLIC_ENABLE_STRIDE, 383 SIFIVE_U_PLIC_CONTEXT_BASE, 384 SIFIVE_U_PLIC_CONTEXT_STRIDE, 385 memmap[SIFIVE_U_PLIC].size); 386 sifive_uart_create(system_memory, memmap[SIFIVE_U_UART0].base, 387 serial_hd(0), qdev_get_gpio_in(DEVICE(s->plic), SIFIVE_U_UART0_IRQ)); 388 sifive_uart_create(system_memory, memmap[SIFIVE_U_UART1].base, 389 serial_hd(1), qdev_get_gpio_in(DEVICE(s->plic), SIFIVE_U_UART1_IRQ)); 390 sifive_clint_create(memmap[SIFIVE_U_CLINT].base, 391 memmap[SIFIVE_U_CLINT].size, smp_cpus, 392 SIFIVE_SIP_BASE, SIFIVE_TIMECMP_BASE, SIFIVE_TIME_BASE); 393 394 for (i = 0; i < SIFIVE_U_PLIC_NUM_SOURCES; i++) { 395 plic_gpios[i] = qdev_get_gpio_in(DEVICE(s->plic), i); 396 } 397 398 if (nd->used) { 399 qemu_check_nic_model(nd, TYPE_CADENCE_GEM); 400 qdev_set_nic_properties(DEVICE(&s->gem), nd); 401 } 402 object_property_set_int(OBJECT(&s->gem), GEM_REVISION, "revision", 403 &error_abort); 404 object_property_set_bool(OBJECT(&s->gem), true, "realized", &err); 405 if (err) { 406 error_propagate(errp, err); 407 return; 408 } 409 sysbus_mmio_map(SYS_BUS_DEVICE(&s->gem), 0, memmap[SIFIVE_U_GEM].base); 410 sysbus_connect_irq(SYS_BUS_DEVICE(&s->gem), 0, 411 plic_gpios[SIFIVE_U_GEM_IRQ]); 412 } 413 414 static void riscv_sifive_u_machine_init(MachineClass *mc) 415 { 416 mc->desc = "RISC-V Board compatible with SiFive U SDK"; 417 mc->init = riscv_sifive_u_init; 418 /* The real hardware has 5 CPUs, but one of them is a small embedded power 419 * management CPU. 420 */ 421 mc->max_cpus = 4; 422 } 423 424 DEFINE_MACHINE("sifive_u", riscv_sifive_u_machine_init) 425 426 static void riscv_sifive_u_soc_class_init(ObjectClass *oc, void *data) 427 { 428 DeviceClass *dc = DEVICE_CLASS(oc); 429 430 dc->realize = riscv_sifive_u_soc_realize; 431 /* Reason: Uses serial_hds in realize function, thus can't be used twice */ 432 dc->user_creatable = false; 433 } 434 435 static const TypeInfo riscv_sifive_u_soc_type_info = { 436 .name = TYPE_RISCV_U_SOC, 437 .parent = TYPE_DEVICE, 438 .instance_size = sizeof(SiFiveUSoCState), 439 .instance_init = riscv_sifive_u_soc_init, 440 .class_init = riscv_sifive_u_soc_class_init, 441 }; 442 443 static void riscv_sifive_u_soc_register_types(void) 444 { 445 type_register_static(&riscv_sifive_u_soc_type_info); 446 } 447 448 type_init(riscv_sifive_u_soc_register_types) 449