1 /* 2 * QEMU RISCV Hart Array 3 * 4 * Copyright (c) 2017 SiFive, Inc. 5 * 6 * Holds the state of a homogeneous array of RISC-V harts 7 * 8 * This program is free software; you can redistribute it and/or modify it 9 * under the terms and conditions of the GNU General Public License, 10 * version 2 or later, as published by the Free Software Foundation. 11 * 12 * This program is distributed in the hope it will be useful, but WITHOUT 13 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 14 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 15 * more details. 16 * 17 * You should have received a copy of the GNU General Public License along with 18 * this program. If not, see <http://www.gnu.org/licenses/>. 19 */ 20 21 #include "qemu/osdep.h" 22 #include "qapi/error.h" 23 #include "qemu/module.h" 24 #include "system/reset.h" 25 #include "system/qtest.h" 26 #include "qemu/cutils.h" 27 #include "hw/sysbus.h" 28 #include "target/riscv/cpu.h" 29 #include "hw/qdev-properties.h" 30 #include "hw/riscv/riscv_hart.h" 31 #include "qemu/error-report.h" 32 33 static const Property riscv_harts_props[] = { 34 DEFINE_PROP_UINT32("num-harts", RISCVHartArrayState, num_harts, 1), 35 DEFINE_PROP_UINT32("hartid-base", RISCVHartArrayState, hartid_base, 0), 36 DEFINE_PROP_STRING("cpu-type", RISCVHartArrayState, cpu_type), 37 DEFINE_PROP_UINT64("resetvec", RISCVHartArrayState, resetvec, 38 DEFAULT_RSTVEC), 39 40 /* 41 * Smrnmi implementation-defined interrupt and exception trap handlers. 42 * 43 * When an RNMI interrupt is detected, the hart then enters M-mode and 44 * jumps to the address defined by "rnmi-interrupt-vector". 45 * 46 * When the hart encounters an exception while executing in M-mode with 47 * the mnstatus.NMIE bit clear, the hart then jumps to the address 48 * defined by "rnmi-exception-vector". 49 */ 50 DEFINE_PROP_ARRAY("rnmi-interrupt-vector", RISCVHartArrayState, 51 num_rnmi_irqvec, rnmi_irqvec, qdev_prop_uint64, 52 uint64_t), 53 DEFINE_PROP_ARRAY("rnmi-exception-vector", RISCVHartArrayState, 54 num_rnmi_excpvec, rnmi_excpvec, qdev_prop_uint64, 55 uint64_t), 56 }; 57 58 static void riscv_harts_cpu_reset(void *opaque) 59 { 60 RISCVCPU *cpu = opaque; 61 cpu_reset(CPU(cpu)); 62 } 63 64 #ifndef CONFIG_USER_ONLY 65 static void csr_call(char *cmd, uint64_t cpu_num, int csrno, uint64_t *val) 66 { 67 RISCVCPU *cpu = RISCV_CPU(cpu_by_arch_id(cpu_num)); 68 CPURISCVState *env = &cpu->env; 69 70 int ret = RISCV_EXCP_NONE; 71 if (strcmp(cmd, "get_csr") == 0) { 72 ret = riscv_csrr(env, csrno, (target_ulong *)val); 73 } else if (strcmp(cmd, "set_csr") == 0) { 74 ret = riscv_csrrw(env, csrno, NULL, *(target_ulong *)val, 75 MAKE_64BIT_MASK(0, TARGET_LONG_BITS)); 76 } 77 78 g_assert(ret == RISCV_EXCP_NONE); 79 } 80 81 static bool csr_qtest_callback(CharBackend *chr, gchar **words) 82 { 83 if (strcmp(words[0], "csr") == 0) { 84 85 uint64_t cpu; 86 uint64_t val; 87 int rc, csr; 88 89 rc = qemu_strtou64(words[2], NULL, 0, &cpu); 90 g_assert(rc == 0); 91 rc = qemu_strtoi(words[3], NULL, 0, &csr); 92 g_assert(rc == 0); 93 rc = qemu_strtou64(words[4], NULL, 0, &val); 94 g_assert(rc == 0); 95 csr_call(words[1], cpu, csr, &val); 96 97 qtest_sendf(chr, "OK 0 "TARGET_FMT_lx"\n", (target_ulong)val); 98 99 return true; 100 } 101 102 return false; 103 } 104 105 static void riscv_cpu_register_csr_qtest_callback(void) 106 { 107 static GOnce once; 108 g_once(&once, (GThreadFunc)qtest_set_command_cb, csr_qtest_callback); 109 } 110 #endif 111 112 static bool riscv_hart_realize(RISCVHartArrayState *s, int idx, 113 char *cpu_type, Error **errp) 114 { 115 object_initialize_child(OBJECT(s), "harts[*]", &s->harts[idx], cpu_type); 116 qdev_prop_set_uint64(DEVICE(&s->harts[idx]), "resetvec", s->resetvec); 117 118 if (s->harts[idx].cfg.ext_smrnmi) { 119 if (idx < s->num_rnmi_irqvec) { 120 qdev_prop_set_uint64(DEVICE(&s->harts[idx]), 121 "rnmi-interrupt-vector", s->rnmi_irqvec[idx]); 122 } 123 124 if (idx < s->num_rnmi_excpvec) { 125 qdev_prop_set_uint64(DEVICE(&s->harts[idx]), 126 "rnmi-exception-vector", s->rnmi_excpvec[idx]); 127 } 128 } else { 129 if (s->num_rnmi_irqvec > 0) { 130 warn_report_once("rnmi-interrupt-vector property is ignored " 131 "because Smrnmi extension is not enabled."); 132 } 133 134 if (s->num_rnmi_excpvec > 0) { 135 warn_report_once("rnmi-exception-vector property is ignored " 136 "because Smrnmi extension is not enabled."); 137 } 138 } 139 140 s->harts[idx].env.mhartid = s->hartid_base + idx; 141 qemu_register_reset(riscv_harts_cpu_reset, &s->harts[idx]); 142 return qdev_realize(DEVICE(&s->harts[idx]), NULL, errp); 143 } 144 145 static void riscv_harts_realize(DeviceState *dev, Error **errp) 146 { 147 RISCVHartArrayState *s = RISCV_HART_ARRAY(dev); 148 int n; 149 150 s->harts = g_new0(RISCVCPU, s->num_harts); 151 152 #ifndef CONFIG_USER_ONLY 153 riscv_cpu_register_csr_qtest_callback(); 154 #endif 155 156 for (n = 0; n < s->num_harts; n++) { 157 if (!riscv_hart_realize(s, n, s->cpu_type, errp)) { 158 return; 159 } 160 } 161 } 162 163 static void riscv_harts_class_init(ObjectClass *klass, void *data) 164 { 165 DeviceClass *dc = DEVICE_CLASS(klass); 166 167 device_class_set_props(dc, riscv_harts_props); 168 dc->realize = riscv_harts_realize; 169 } 170 171 static const TypeInfo riscv_harts_info = { 172 .name = TYPE_RISCV_HART_ARRAY, 173 .parent = TYPE_SYS_BUS_DEVICE, 174 .instance_size = sizeof(RISCVHartArrayState), 175 .class_init = riscv_harts_class_init, 176 }; 177 178 static void riscv_harts_register_types(void) 179 { 180 type_register_static(&riscv_harts_info); 181 } 182 183 type_init(riscv_harts_register_types) 184