1 /* 2 * QEMU emulation of an RISC-V IOMMU Platform Device 3 * 4 * Copyright (C) 2022-2023 Rivos Inc. 5 * 6 * This program is free software; you can redistribute it and/or modify it 7 * under the terms and conditions of the GNU General Public License, 8 * version 2 or later, as published by the Free Software Foundation. 9 * 10 * This program is distributed in the hope that it will be useful, 11 * but WITHOUT ANY WARRANTY; without even the implied warranty of 12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 13 * GNU General Public License for more details. 14 * 15 * You should have received a copy of the GNU General Public License along 16 * with this program; if not, see <http://www.gnu.org/licenses/>. 17 */ 18 19 #include "qemu/osdep.h" 20 #include "hw/irq.h" 21 #include "hw/pci/pci_bus.h" 22 #include "hw/qdev-properties.h" 23 #include "hw/sysbus.h" 24 #include "qapi/error.h" 25 #include "qemu/error-report.h" 26 #include "qemu/host-utils.h" 27 #include "qemu/module.h" 28 #include "qom/object.h" 29 #include "trace.h" 30 31 #include "riscv-iommu.h" 32 33 #define RISCV_IOMMU_SYSDEV_ICVEC_VECTORS 0x3333 34 35 #define RISCV_IOMMU_PCI_MSIX_VECTORS 5 36 37 /* RISC-V IOMMU System Platform Device Emulation */ 38 39 struct RISCVIOMMUStateSys { 40 SysBusDevice parent; 41 uint64_t addr; 42 uint32_t base_irq; 43 DeviceState *irqchip; 44 RISCVIOMMUState iommu; 45 46 /* Wired int support */ 47 qemu_irq irqs[RISCV_IOMMU_INTR_COUNT]; 48 49 /* Memory Regions for MSIX table and pending bit entries. */ 50 MemoryRegion msix_table_mmio; 51 MemoryRegion msix_pba_mmio; 52 uint8_t *msix_table; 53 uint8_t *msix_pba; 54 }; 55 56 static uint64_t msix_table_mmio_read(void *opaque, hwaddr addr, 57 unsigned size) 58 { 59 RISCVIOMMUStateSys *s = opaque; 60 61 g_assert(addr + size <= RISCV_IOMMU_PCI_MSIX_VECTORS * PCI_MSIX_ENTRY_SIZE); 62 return pci_get_long(s->msix_table + addr); 63 } 64 65 static void msix_table_mmio_write(void *opaque, hwaddr addr, 66 uint64_t val, unsigned size) 67 { 68 RISCVIOMMUStateSys *s = opaque; 69 70 g_assert(addr + size <= RISCV_IOMMU_PCI_MSIX_VECTORS * PCI_MSIX_ENTRY_SIZE); 71 pci_set_long(s->msix_table + addr, val); 72 } 73 74 static const MemoryRegionOps msix_table_mmio_ops = { 75 .read = msix_table_mmio_read, 76 .write = msix_table_mmio_write, 77 .endianness = DEVICE_LITTLE_ENDIAN, 78 .valid = { 79 .min_access_size = 4, 80 .max_access_size = 8, 81 }, 82 .impl = { 83 .max_access_size = 4, 84 }, 85 }; 86 87 static uint64_t msix_pba_mmio_read(void *opaque, hwaddr addr, 88 unsigned size) 89 { 90 RISCVIOMMUStateSys *s = opaque; 91 92 return pci_get_long(s->msix_pba + addr); 93 } 94 95 static void msix_pba_mmio_write(void *opaque, hwaddr addr, 96 uint64_t val, unsigned size) 97 { 98 } 99 100 static const MemoryRegionOps msix_pba_mmio_ops = { 101 .read = msix_pba_mmio_read, 102 .write = msix_pba_mmio_write, 103 .endianness = DEVICE_LITTLE_ENDIAN, 104 .valid = { 105 .min_access_size = 4, 106 .max_access_size = 8, 107 }, 108 .impl = { 109 .max_access_size = 4, 110 }, 111 }; 112 113 static void riscv_iommu_sysdev_init_msi(RISCVIOMMUStateSys *s, 114 uint32_t n_vectors) 115 { 116 RISCVIOMMUState *iommu = &s->iommu; 117 uint32_t table_size = n_vectors * PCI_MSIX_ENTRY_SIZE; 118 uint32_t table_offset = RISCV_IOMMU_REG_MSI_CONFIG; 119 uint32_t pba_size = QEMU_ALIGN_UP(n_vectors, 64) / 8; 120 uint32_t pba_offset = RISCV_IOMMU_REG_MSI_CONFIG + 256; 121 122 s->msix_table = g_malloc0(table_size); 123 s->msix_pba = g_malloc0(pba_size); 124 125 memory_region_init_io(&s->msix_table_mmio, OBJECT(s), &msix_table_mmio_ops, 126 s, "msix-table", table_size); 127 memory_region_add_subregion(&iommu->regs_mr, table_offset, 128 &s->msix_table_mmio); 129 130 memory_region_init_io(&s->msix_pba_mmio, OBJECT(s), &msix_pba_mmio_ops, s, 131 "msix-pba", pba_size); 132 memory_region_add_subregion(&iommu->regs_mr, pba_offset, 133 &s->msix_pba_mmio); 134 } 135 136 static void riscv_iommu_sysdev_send_MSI(RISCVIOMMUStateSys *s, 137 uint32_t vector) 138 { 139 uint8_t *table_entry = s->msix_table + vector * PCI_MSIX_ENTRY_SIZE; 140 uint64_t msi_addr = pci_get_quad(table_entry + PCI_MSIX_ENTRY_LOWER_ADDR); 141 uint32_t msi_data = pci_get_long(table_entry + PCI_MSIX_ENTRY_DATA); 142 MemTxResult result; 143 144 address_space_stl_le(&address_space_memory, msi_addr, 145 msi_data, MEMTXATTRS_UNSPECIFIED, &result); 146 trace_riscv_iommu_sys_msi_sent(vector, msi_addr, msi_data, result); 147 } 148 149 static void riscv_iommu_sysdev_notify(RISCVIOMMUState *iommu, 150 unsigned vector) 151 { 152 RISCVIOMMUStateSys *s = container_of(iommu, RISCVIOMMUStateSys, iommu); 153 uint32_t fctl = riscv_iommu_reg_get32(iommu, RISCV_IOMMU_REG_FCTL); 154 155 if (fctl & RISCV_IOMMU_FCTL_WSI) { 156 qemu_irq_pulse(s->irqs[vector]); 157 trace_riscv_iommu_sys_irq_sent(vector); 158 return; 159 } 160 161 riscv_iommu_sysdev_send_MSI(s, vector); 162 } 163 164 static void riscv_iommu_sys_realize(DeviceState *dev, Error **errp) 165 { 166 RISCVIOMMUStateSys *s = RISCV_IOMMU_SYS(dev); 167 SysBusDevice *sysdev = SYS_BUS_DEVICE(s); 168 PCIBus *pci_bus; 169 qemu_irq irq; 170 171 qdev_realize(DEVICE(&s->iommu), NULL, errp); 172 sysbus_init_mmio(SYS_BUS_DEVICE(dev), &s->iommu.regs_mr); 173 if (s->addr) { 174 sysbus_mmio_map(SYS_BUS_DEVICE(s), 0, s->addr); 175 } 176 177 pci_bus = (PCIBus *) object_resolve_path_type("", TYPE_PCI_BUS, NULL); 178 if (pci_bus) { 179 riscv_iommu_pci_setup_iommu(&s->iommu, pci_bus, errp); 180 } 181 182 s->iommu.notify = riscv_iommu_sysdev_notify; 183 184 /* 4 IRQs are defined starting from s->base_irq */ 185 for (int i = 0; i < RISCV_IOMMU_INTR_COUNT; i++) { 186 sysbus_init_irq(sysdev, &s->irqs[i]); 187 irq = qdev_get_gpio_in(s->irqchip, s->base_irq + i); 188 sysbus_connect_irq(sysdev, i, irq); 189 } 190 191 riscv_iommu_sysdev_init_msi(s, RISCV_IOMMU_PCI_MSIX_VECTORS); 192 } 193 194 static void riscv_iommu_sys_init(Object *obj) 195 { 196 RISCVIOMMUStateSys *s = RISCV_IOMMU_SYS(obj); 197 RISCVIOMMUState *iommu = &s->iommu; 198 199 object_initialize_child(obj, "iommu", iommu, TYPE_RISCV_IOMMU); 200 qdev_alias_all_properties(DEVICE(iommu), obj); 201 202 iommu->icvec_avail_vectors = RISCV_IOMMU_SYSDEV_ICVEC_VECTORS; 203 riscv_iommu_set_cap_igs(iommu, RISCV_IOMMU_CAP_IGS_BOTH); 204 } 205 206 static const Property riscv_iommu_sys_properties[] = { 207 DEFINE_PROP_UINT64("addr", RISCVIOMMUStateSys, addr, 0), 208 DEFINE_PROP_UINT32("base-irq", RISCVIOMMUStateSys, base_irq, 0), 209 DEFINE_PROP_LINK("irqchip", RISCVIOMMUStateSys, irqchip, 210 TYPE_DEVICE, DeviceState *), 211 }; 212 213 static void riscv_iommu_sys_reset_hold(Object *obj, ResetType type) 214 { 215 RISCVIOMMUStateSys *sys = RISCV_IOMMU_SYS(obj); 216 RISCVIOMMUState *iommu = &sys->iommu; 217 218 riscv_iommu_reset(iommu); 219 220 trace_riscv_iommu_sys_reset_hold(type); 221 } 222 223 static void riscv_iommu_sys_class_init(ObjectClass *klass, const void *data) 224 { 225 DeviceClass *dc = DEVICE_CLASS(klass); 226 ResettableClass *rc = RESETTABLE_CLASS(klass); 227 228 rc->phases.hold = riscv_iommu_sys_reset_hold; 229 230 dc->realize = riscv_iommu_sys_realize; 231 set_bit(DEVICE_CATEGORY_MISC, dc->categories); 232 device_class_set_props(dc, riscv_iommu_sys_properties); 233 } 234 235 static const TypeInfo riscv_iommu_sys = { 236 .name = TYPE_RISCV_IOMMU_SYS, 237 .parent = TYPE_SYS_BUS_DEVICE, 238 .class_init = riscv_iommu_sys_class_init, 239 .instance_init = riscv_iommu_sys_init, 240 .instance_size = sizeof(RISCVIOMMUStateSys), 241 }; 242 243 static void riscv_iommu_register_sys(void) 244 { 245 type_register_static(&riscv_iommu_sys); 246 } 247 248 type_init(riscv_iommu_register_sys) 249