1 /* 2 * QEMU emulation of an RISC-V IOMMU Platform Device 3 * 4 * Copyright (C) 2022-2023 Rivos Inc. 5 * 6 * This program is free software; you can redistribute it and/or modify it 7 * under the terms and conditions of the GNU General Public License, 8 * version 2 or later, as published by the Free Software Foundation. 9 * 10 * This program is distributed in the hope that it will be useful, 11 * but WITHOUT ANY WARRANTY; without even the implied warranty of 12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 13 * GNU General Public License for more details. 14 * 15 * You should have received a copy of the GNU General Public License along 16 * with this program; if not, see <http://www.gnu.org/licenses/>. 17 */ 18 19 #include "qemu/osdep.h" 20 #include "hw/irq.h" 21 #include "hw/pci/pci_bus.h" 22 #include "hw/qdev-properties.h" 23 #include "hw/sysbus.h" 24 #include "qapi/error.h" 25 #include "qemu/error-report.h" 26 #include "qemu/host-utils.h" 27 #include "qemu/module.h" 28 #include "qom/object.h" 29 #include "trace.h" 30 31 #include "riscv-iommu.h" 32 33 #define RISCV_IOMMU_SYSDEV_ICVEC_VECTORS 0x3333 34 35 #define RISCV_IOMMU_PCI_MSIX_VECTORS 5 36 37 /* RISC-V IOMMU System Platform Device Emulation */ 38 39 struct RISCVIOMMUStateSys { 40 SysBusDevice parent; 41 uint64_t addr; 42 uint32_t base_irq; 43 DeviceState *irqchip; 44 RISCVIOMMUState iommu; 45 46 /* Wired int support */ 47 qemu_irq irqs[RISCV_IOMMU_INTR_COUNT]; 48 49 /* Memory Regions for MSIX table and pending bit entries. */ 50 MemoryRegion msix_table_mmio; 51 MemoryRegion msix_pba_mmio; 52 uint8_t *msix_table; 53 uint8_t *msix_pba; 54 }; 55 56 struct RISCVIOMMUSysClass { 57 /*< public >*/ 58 DeviceRealize parent_realize; 59 ResettablePhases parent_phases; 60 }; 61 62 static uint64_t msix_table_mmio_read(void *opaque, hwaddr addr, 63 unsigned size) 64 { 65 RISCVIOMMUStateSys *s = opaque; 66 67 g_assert(addr + size <= RISCV_IOMMU_PCI_MSIX_VECTORS * PCI_MSIX_ENTRY_SIZE); 68 return pci_get_long(s->msix_table + addr); 69 } 70 71 static void msix_table_mmio_write(void *opaque, hwaddr addr, 72 uint64_t val, unsigned size) 73 { 74 RISCVIOMMUStateSys *s = opaque; 75 76 g_assert(addr + size <= RISCV_IOMMU_PCI_MSIX_VECTORS * PCI_MSIX_ENTRY_SIZE); 77 pci_set_long(s->msix_table + addr, val); 78 } 79 80 static const MemoryRegionOps msix_table_mmio_ops = { 81 .read = msix_table_mmio_read, 82 .write = msix_table_mmio_write, 83 .endianness = DEVICE_LITTLE_ENDIAN, 84 .valid = { 85 .min_access_size = 4, 86 .max_access_size = 8, 87 }, 88 .impl = { 89 .max_access_size = 4, 90 }, 91 }; 92 93 static uint64_t msix_pba_mmio_read(void *opaque, hwaddr addr, 94 unsigned size) 95 { 96 RISCVIOMMUStateSys *s = opaque; 97 98 return pci_get_long(s->msix_pba + addr); 99 } 100 101 static void msix_pba_mmio_write(void *opaque, hwaddr addr, 102 uint64_t val, unsigned size) 103 { 104 } 105 106 static const MemoryRegionOps msix_pba_mmio_ops = { 107 .read = msix_pba_mmio_read, 108 .write = msix_pba_mmio_write, 109 .endianness = DEVICE_LITTLE_ENDIAN, 110 .valid = { 111 .min_access_size = 4, 112 .max_access_size = 8, 113 }, 114 .impl = { 115 .max_access_size = 4, 116 }, 117 }; 118 119 static void riscv_iommu_sysdev_init_msi(RISCVIOMMUStateSys *s, 120 uint32_t n_vectors) 121 { 122 RISCVIOMMUState *iommu = &s->iommu; 123 uint32_t table_size = n_vectors * PCI_MSIX_ENTRY_SIZE; 124 uint32_t table_offset = RISCV_IOMMU_REG_MSI_CONFIG; 125 uint32_t pba_size = QEMU_ALIGN_UP(n_vectors, 64) / 8; 126 uint32_t pba_offset = RISCV_IOMMU_REG_MSI_CONFIG + 256; 127 128 s->msix_table = g_malloc0(table_size); 129 s->msix_pba = g_malloc0(pba_size); 130 131 memory_region_init_io(&s->msix_table_mmio, OBJECT(s), &msix_table_mmio_ops, 132 s, "msix-table", table_size); 133 memory_region_add_subregion(&iommu->regs_mr, table_offset, 134 &s->msix_table_mmio); 135 136 memory_region_init_io(&s->msix_pba_mmio, OBJECT(s), &msix_pba_mmio_ops, s, 137 "msix-pba", pba_size); 138 memory_region_add_subregion(&iommu->regs_mr, pba_offset, 139 &s->msix_pba_mmio); 140 } 141 142 static void riscv_iommu_sysdev_send_MSI(RISCVIOMMUStateSys *s, 143 uint32_t vector) 144 { 145 uint8_t *table_entry = s->msix_table + vector * PCI_MSIX_ENTRY_SIZE; 146 uint64_t msi_addr = pci_get_quad(table_entry + PCI_MSIX_ENTRY_LOWER_ADDR); 147 uint32_t msi_data = pci_get_long(table_entry + PCI_MSIX_ENTRY_DATA); 148 MemTxResult result; 149 150 address_space_stl_le(&address_space_memory, msi_addr, 151 msi_data, MEMTXATTRS_UNSPECIFIED, &result); 152 trace_riscv_iommu_sys_msi_sent(vector, msi_addr, msi_data, result); 153 } 154 155 static void riscv_iommu_sysdev_notify(RISCVIOMMUState *iommu, 156 unsigned vector) 157 { 158 RISCVIOMMUStateSys *s = container_of(iommu, RISCVIOMMUStateSys, iommu); 159 uint32_t fctl = riscv_iommu_reg_get32(iommu, RISCV_IOMMU_REG_FCTL); 160 161 if (fctl & RISCV_IOMMU_FCTL_WSI) { 162 qemu_irq_pulse(s->irqs[vector]); 163 trace_riscv_iommu_sys_irq_sent(vector); 164 return; 165 } 166 167 riscv_iommu_sysdev_send_MSI(s, vector); 168 } 169 170 static void riscv_iommu_sys_realize(DeviceState *dev, Error **errp) 171 { 172 RISCVIOMMUStateSys *s = RISCV_IOMMU_SYS(dev); 173 SysBusDevice *sysdev = SYS_BUS_DEVICE(s); 174 PCIBus *pci_bus; 175 qemu_irq irq; 176 177 qdev_realize(DEVICE(&s->iommu), NULL, errp); 178 sysbus_init_mmio(SYS_BUS_DEVICE(dev), &s->iommu.regs_mr); 179 if (s->addr) { 180 sysbus_mmio_map(SYS_BUS_DEVICE(s), 0, s->addr); 181 } 182 183 pci_bus = (PCIBus *) object_resolve_path_type("", TYPE_PCI_BUS, NULL); 184 if (pci_bus) { 185 riscv_iommu_pci_setup_iommu(&s->iommu, pci_bus, errp); 186 } 187 188 s->iommu.notify = riscv_iommu_sysdev_notify; 189 190 /* 4 IRQs are defined starting from s->base_irq */ 191 for (int i = 0; i < RISCV_IOMMU_INTR_COUNT; i++) { 192 sysbus_init_irq(sysdev, &s->irqs[i]); 193 irq = qdev_get_gpio_in(s->irqchip, s->base_irq + i); 194 sysbus_connect_irq(sysdev, i, irq); 195 } 196 197 riscv_iommu_sysdev_init_msi(s, RISCV_IOMMU_PCI_MSIX_VECTORS); 198 } 199 200 static void riscv_iommu_sys_init(Object *obj) 201 { 202 RISCVIOMMUStateSys *s = RISCV_IOMMU_SYS(obj); 203 RISCVIOMMUState *iommu = &s->iommu; 204 205 object_initialize_child(obj, "iommu", iommu, TYPE_RISCV_IOMMU); 206 qdev_alias_all_properties(DEVICE(iommu), obj); 207 208 iommu->icvec_avail_vectors = RISCV_IOMMU_SYSDEV_ICVEC_VECTORS; 209 riscv_iommu_set_cap_igs(iommu, RISCV_IOMMU_CAP_IGS_BOTH); 210 } 211 212 static const Property riscv_iommu_sys_properties[] = { 213 DEFINE_PROP_UINT64("addr", RISCVIOMMUStateSys, addr, 0), 214 DEFINE_PROP_UINT32("base-irq", RISCVIOMMUStateSys, base_irq, 0), 215 DEFINE_PROP_LINK("irqchip", RISCVIOMMUStateSys, irqchip, 216 TYPE_DEVICE, DeviceState *), 217 }; 218 219 static void riscv_iommu_sys_reset_hold(Object *obj, ResetType type) 220 { 221 RISCVIOMMUStateSys *sys = RISCV_IOMMU_SYS(obj); 222 RISCVIOMMUState *iommu = &sys->iommu; 223 224 riscv_iommu_reset(iommu); 225 226 trace_riscv_iommu_sys_reset_hold(type); 227 } 228 229 static void riscv_iommu_sys_class_init(ObjectClass *klass, const void *data) 230 { 231 DeviceClass *dc = DEVICE_CLASS(klass); 232 ResettableClass *rc = RESETTABLE_CLASS(klass); 233 234 rc->phases.hold = riscv_iommu_sys_reset_hold; 235 236 dc->realize = riscv_iommu_sys_realize; 237 set_bit(DEVICE_CATEGORY_MISC, dc->categories); 238 device_class_set_props(dc, riscv_iommu_sys_properties); 239 } 240 241 static const TypeInfo riscv_iommu_sys = { 242 .name = TYPE_RISCV_IOMMU_SYS, 243 .parent = TYPE_SYS_BUS_DEVICE, 244 .class_init = riscv_iommu_sys_class_init, 245 .instance_init = riscv_iommu_sys_init, 246 .instance_size = sizeof(RISCVIOMMUStateSys), 247 }; 248 249 static void riscv_iommu_register_sys(void) 250 { 251 type_register_static(&riscv_iommu_sys); 252 } 253 254 type_init(riscv_iommu_register_sys) 255