1 /* 2 * QEMU emulation of an RISC-V IOMMU Platform Device 3 * 4 * Copyright (C) 2022-2023 Rivos Inc. 5 * 6 * This program is free software; you can redistribute it and/or modify it 7 * under the terms and conditions of the GNU General Public License, 8 * version 2 or later, as published by the Free Software Foundation. 9 * 10 * This program is distributed in the hope that it will be useful, 11 * but WITHOUT ANY WARRANTY; without even the implied warranty of 12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 13 * GNU General Public License for more details. 14 * 15 * You should have received a copy of the GNU General Public License along 16 * with this program; if not, see <http://www.gnu.org/licenses/>. 17 */ 18 19 #include "qemu/osdep.h" 20 #include "hw/irq.h" 21 #include "hw/pci/pci_bus.h" 22 #include "hw/qdev-properties.h" 23 #include "hw/sysbus.h" 24 #include "qapi/error.h" 25 #include "qemu/error-report.h" 26 #include "qemu/host-utils.h" 27 #include "qemu/module.h" 28 #include "qom/object.h" 29 #include "exec/exec-all.h" 30 #include "trace.h" 31 32 #include "riscv-iommu.h" 33 34 #define RISCV_IOMMU_SYSDEV_ICVEC_VECTORS 0x3333 35 36 #define RISCV_IOMMU_PCI_MSIX_VECTORS 5 37 38 /* RISC-V IOMMU System Platform Device Emulation */ 39 40 struct RISCVIOMMUStateSys { 41 SysBusDevice parent; 42 uint64_t addr; 43 uint32_t base_irq; 44 DeviceState *irqchip; 45 RISCVIOMMUState iommu; 46 47 /* Wired int support */ 48 qemu_irq irqs[RISCV_IOMMU_INTR_COUNT]; 49 50 /* Memory Regions for MSIX table and pending bit entries. */ 51 MemoryRegion msix_table_mmio; 52 MemoryRegion msix_pba_mmio; 53 uint8_t *msix_table; 54 uint8_t *msix_pba; 55 }; 56 57 static uint64_t msix_table_mmio_read(void *opaque, hwaddr addr, 58 unsigned size) 59 { 60 RISCVIOMMUStateSys *s = opaque; 61 62 g_assert(addr + size <= RISCV_IOMMU_PCI_MSIX_VECTORS * PCI_MSIX_ENTRY_SIZE); 63 return pci_get_long(s->msix_table + addr); 64 } 65 66 static void msix_table_mmio_write(void *opaque, hwaddr addr, 67 uint64_t val, unsigned size) 68 { 69 RISCVIOMMUStateSys *s = opaque; 70 71 g_assert(addr + size <= RISCV_IOMMU_PCI_MSIX_VECTORS * PCI_MSIX_ENTRY_SIZE); 72 pci_set_long(s->msix_table + addr, val); 73 } 74 75 static const MemoryRegionOps msix_table_mmio_ops = { 76 .read = msix_table_mmio_read, 77 .write = msix_table_mmio_write, 78 .endianness = DEVICE_LITTLE_ENDIAN, 79 .valid = { 80 .min_access_size = 4, 81 .max_access_size = 8, 82 }, 83 .impl = { 84 .max_access_size = 4, 85 }, 86 }; 87 88 static uint64_t msix_pba_mmio_read(void *opaque, hwaddr addr, 89 unsigned size) 90 { 91 RISCVIOMMUStateSys *s = opaque; 92 93 return pci_get_long(s->msix_pba + addr); 94 } 95 96 static void msix_pba_mmio_write(void *opaque, hwaddr addr, 97 uint64_t val, unsigned size) 98 { 99 } 100 101 static const MemoryRegionOps msix_pba_mmio_ops = { 102 .read = msix_pba_mmio_read, 103 .write = msix_pba_mmio_write, 104 .endianness = DEVICE_LITTLE_ENDIAN, 105 .valid = { 106 .min_access_size = 4, 107 .max_access_size = 8, 108 }, 109 .impl = { 110 .max_access_size = 4, 111 }, 112 }; 113 114 static void riscv_iommu_sysdev_init_msi(RISCVIOMMUStateSys *s, 115 uint32_t n_vectors) 116 { 117 RISCVIOMMUState *iommu = &s->iommu; 118 uint32_t table_size = table_size = n_vectors * PCI_MSIX_ENTRY_SIZE; 119 uint32_t table_offset = RISCV_IOMMU_REG_MSI_CONFIG; 120 uint32_t pba_size = QEMU_ALIGN_UP(n_vectors, 64) / 8; 121 uint32_t pba_offset = RISCV_IOMMU_REG_MSI_CONFIG + 256; 122 123 s->msix_table = g_malloc0(table_size); 124 s->msix_pba = g_malloc0(pba_size); 125 126 memory_region_init_io(&s->msix_table_mmio, OBJECT(s), &msix_table_mmio_ops, 127 s, "msix-table", table_size); 128 memory_region_add_subregion(&iommu->regs_mr, table_offset, 129 &s->msix_table_mmio); 130 131 memory_region_init_io(&s->msix_pba_mmio, OBJECT(s), &msix_pba_mmio_ops, s, 132 "msix-pba", pba_size); 133 memory_region_add_subregion(&iommu->regs_mr, pba_offset, 134 &s->msix_pba_mmio); 135 } 136 137 static void riscv_iommu_sysdev_send_MSI(RISCVIOMMUStateSys *s, 138 uint32_t vector) 139 { 140 uint8_t *table_entry = s->msix_table + vector * PCI_MSIX_ENTRY_SIZE; 141 uint64_t msi_addr = pci_get_quad(table_entry + PCI_MSIX_ENTRY_LOWER_ADDR); 142 uint32_t msi_data = pci_get_long(table_entry + PCI_MSIX_ENTRY_DATA); 143 MemTxResult result; 144 145 address_space_stl_le(&address_space_memory, msi_addr, 146 msi_data, MEMTXATTRS_UNSPECIFIED, &result); 147 trace_riscv_iommu_sys_msi_sent(vector, msi_addr, msi_data, result); 148 } 149 150 static void riscv_iommu_sysdev_notify(RISCVIOMMUState *iommu, 151 unsigned vector) 152 { 153 RISCVIOMMUStateSys *s = container_of(iommu, RISCVIOMMUStateSys, iommu); 154 uint32_t fctl = riscv_iommu_reg_get32(iommu, RISCV_IOMMU_REG_FCTL); 155 156 if (fctl & RISCV_IOMMU_FCTL_WSI) { 157 qemu_irq_pulse(s->irqs[vector]); 158 trace_riscv_iommu_sys_irq_sent(vector); 159 return; 160 } 161 162 riscv_iommu_sysdev_send_MSI(s, vector); 163 } 164 165 static void riscv_iommu_sys_realize(DeviceState *dev, Error **errp) 166 { 167 RISCVIOMMUStateSys *s = RISCV_IOMMU_SYS(dev); 168 SysBusDevice *sysdev = SYS_BUS_DEVICE(s); 169 PCIBus *pci_bus; 170 qemu_irq irq; 171 172 qdev_realize(DEVICE(&s->iommu), NULL, errp); 173 sysbus_init_mmio(SYS_BUS_DEVICE(dev), &s->iommu.regs_mr); 174 if (s->addr) { 175 sysbus_mmio_map(SYS_BUS_DEVICE(s), 0, s->addr); 176 } 177 178 pci_bus = (PCIBus *) object_resolve_path_type("", TYPE_PCI_BUS, NULL); 179 if (pci_bus) { 180 riscv_iommu_pci_setup_iommu(&s->iommu, pci_bus, errp); 181 } 182 183 s->iommu.notify = riscv_iommu_sysdev_notify; 184 185 /* 4 IRQs are defined starting from s->base_irq */ 186 for (int i = 0; i < RISCV_IOMMU_INTR_COUNT; i++) { 187 sysbus_init_irq(sysdev, &s->irqs[i]); 188 irq = qdev_get_gpio_in(s->irqchip, s->base_irq + i); 189 sysbus_connect_irq(sysdev, i, irq); 190 } 191 192 riscv_iommu_sysdev_init_msi(s, RISCV_IOMMU_PCI_MSIX_VECTORS); 193 } 194 195 static void riscv_iommu_sys_init(Object *obj) 196 { 197 RISCVIOMMUStateSys *s = RISCV_IOMMU_SYS(obj); 198 RISCVIOMMUState *iommu = &s->iommu; 199 200 object_initialize_child(obj, "iommu", iommu, TYPE_RISCV_IOMMU); 201 qdev_alias_all_properties(DEVICE(iommu), obj); 202 203 iommu->icvec_avail_vectors = RISCV_IOMMU_SYSDEV_ICVEC_VECTORS; 204 riscv_iommu_set_cap_igs(iommu, RISCV_IOMMU_CAP_IGS_BOTH); 205 } 206 207 static Property riscv_iommu_sys_properties[] = { 208 DEFINE_PROP_UINT64("addr", RISCVIOMMUStateSys, addr, 0), 209 DEFINE_PROP_UINT32("base-irq", RISCVIOMMUStateSys, base_irq, 0), 210 DEFINE_PROP_LINK("irqchip", RISCVIOMMUStateSys, irqchip, 211 TYPE_DEVICE, DeviceState *), 212 DEFINE_PROP_END_OF_LIST(), 213 }; 214 215 static void riscv_iommu_sys_class_init(ObjectClass *klass, void *data) 216 { 217 DeviceClass *dc = DEVICE_CLASS(klass); 218 dc->realize = riscv_iommu_sys_realize; 219 set_bit(DEVICE_CATEGORY_MISC, dc->categories); 220 device_class_set_props(dc, riscv_iommu_sys_properties); 221 } 222 223 static const TypeInfo riscv_iommu_sys = { 224 .name = TYPE_RISCV_IOMMU_SYS, 225 .parent = TYPE_SYS_BUS_DEVICE, 226 .class_init = riscv_iommu_sys_class_init, 227 .instance_init = riscv_iommu_sys_init, 228 .instance_size = sizeof(RISCVIOMMUStateSys), 229 }; 230 231 static void riscv_iommu_register_sys(void) 232 { 233 type_register_static(&riscv_iommu_sys); 234 } 235 236 type_init(riscv_iommu_register_sys) 237