1 /* 2 * QEMU emulation of an RISC-V IOMMU 3 * 4 * Copyright (C) 2022-2023 Rivos Inc. 5 * 6 * This program is free software; you can redistribute it and/or modify it 7 * under the terms and conditions of the GNU General Public License, 8 * version 2 or later, as published by the Free Software Foundation. 9 * 10 * This program is distributed in the hope that it will be useful, 11 * but WITHOUT ANY WARRANTY; without even the implied warranty of 12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 13 * GNU General Public License for more details. 14 * 15 * You should have received a copy of the GNU General Public License along 16 * with this program; if not, see <http://www.gnu.org/licenses/>. 17 */ 18 19 #include "qemu/osdep.h" 20 #include "hw/pci/msi.h" 21 #include "hw/pci/msix.h" 22 #include "hw/pci/pci_bus.h" 23 #include "hw/qdev-properties.h" 24 #include "hw/riscv/riscv_hart.h" 25 #include "migration/vmstate.h" 26 #include "qapi/error.h" 27 #include "qemu/error-report.h" 28 #include "qemu/host-utils.h" 29 #include "qom/object.h" 30 31 #include "cpu_bits.h" 32 #include "riscv-iommu.h" 33 #include "riscv-iommu-bits.h" 34 #include "trace.h" 35 36 /* RISC-V IOMMU PCI Device Emulation */ 37 #define RISCV_PCI_CLASS_SYSTEM_IOMMU 0x0806 38 39 /* 40 * 4 MSIx vectors for ICVEC, one for MRIF. The spec mentions in 41 * the "Placement and data flow" section that: 42 * 43 * "The interfaces related to recording an incoming MSI in a memory-resident 44 * interrupt file (MRIF) are implementation-specific. The partitioning of 45 * responsibility between the IOMMU and the IO bridge for recording the 46 * incoming MSI in an MRIF and generating the associated notice MSI are 47 * implementation-specific." 48 * 49 * We're making a design decision to create the MSIx for MRIF in the 50 * IOMMU MSIx emulation. 51 */ 52 #define RISCV_IOMMU_PCI_MSIX_VECTORS 5 53 54 /* 55 * 4 vectors that can be used by civ, fiv, pmiv and piv. Number of 56 * vectors is represented by 2^N, where N = number of writable bits 57 * in each cause. For 4 vectors we'll write 0b11 (3) in each reg. 58 */ 59 #define RISCV_IOMMU_PCI_ICVEC_VECTORS 0x3333 60 61 typedef struct RISCVIOMMUStatePci { 62 PCIDevice pci; /* Parent PCIe device state */ 63 uint16_t vendor_id; 64 uint16_t device_id; 65 uint8_t revision; 66 MemoryRegion bar0; /* PCI BAR (including MSI-x config) */ 67 RISCVIOMMUState iommu; /* common IOMMU state */ 68 } RISCVIOMMUStatePci; 69 70 struct RISCVIOMMUPciClass { 71 /*< public >*/ 72 DeviceRealize parent_realize; 73 ResettablePhases parent_phases; 74 }; 75 76 /* interrupt delivery callback */ 77 static void riscv_iommu_pci_notify(RISCVIOMMUState *iommu, unsigned vector) 78 { 79 RISCVIOMMUStatePci *s = container_of(iommu, RISCVIOMMUStatePci, iommu); 80 81 if (msix_enabled(&(s->pci))) { 82 msix_notify(&(s->pci), vector); 83 } 84 } 85 86 static void riscv_iommu_pci_realize(PCIDevice *dev, Error **errp) 87 { 88 RISCVIOMMUStatePci *s = DO_UPCAST(RISCVIOMMUStatePci, pci, dev); 89 RISCVIOMMUState *iommu = &s->iommu; 90 uint8_t *pci_conf = dev->config; 91 Error *err = NULL; 92 93 pci_set_word(pci_conf + PCI_VENDOR_ID, s->vendor_id); 94 pci_set_word(pci_conf + PCI_SUBSYSTEM_VENDOR_ID, s->vendor_id); 95 pci_set_word(pci_conf + PCI_DEVICE_ID, s->device_id); 96 pci_set_word(pci_conf + PCI_SUBSYSTEM_ID, s->device_id); 97 pci_set_byte(pci_conf + PCI_REVISION_ID, s->revision); 98 99 /* Set device id for trace / debug */ 100 DEVICE(iommu)->id = g_strdup_printf("%02x:%02x.%01x", 101 pci_dev_bus_num(dev), PCI_SLOT(dev->devfn), PCI_FUNC(dev->devfn)); 102 qdev_realize(DEVICE(iommu), NULL, errp); 103 104 memory_region_init(&s->bar0, OBJECT(s), "riscv-iommu-bar0", 105 QEMU_ALIGN_UP(memory_region_size(&iommu->regs_mr), TARGET_PAGE_SIZE)); 106 memory_region_add_subregion(&s->bar0, 0, &iommu->regs_mr); 107 108 pcie_endpoint_cap_init(dev, 0); 109 110 pci_register_bar(dev, 0, PCI_BASE_ADDRESS_SPACE_MEMORY | 111 PCI_BASE_ADDRESS_MEM_TYPE_64, &s->bar0); 112 113 int ret = msix_init(dev, RISCV_IOMMU_PCI_MSIX_VECTORS, 114 &s->bar0, 0, RISCV_IOMMU_REG_MSI_CONFIG, 115 &s->bar0, 0, RISCV_IOMMU_REG_MSI_CONFIG + 256, 0, &err); 116 117 if (ret == -ENOTSUP) { 118 /* 119 * MSI-x is not supported by the platform. 120 * Driver should use timer/polling based notification handlers. 121 */ 122 warn_report_err(err); 123 } else if (ret < 0) { 124 error_propagate(errp, err); 125 return; 126 } else { 127 /* Mark all ICVEC MSIx vectors as used */ 128 for (int i = 0; i < RISCV_IOMMU_PCI_MSIX_VECTORS; i++) { 129 msix_vector_use(dev, i); 130 } 131 132 iommu->notify = riscv_iommu_pci_notify; 133 } 134 135 PCIBus *bus = pci_device_root_bus(dev); 136 if (!bus) { 137 error_setg(errp, "can't find PCIe root port for %02x:%02x.%x", 138 pci_bus_num(pci_get_bus(dev)), PCI_SLOT(dev->devfn), 139 PCI_FUNC(dev->devfn)); 140 return; 141 } 142 143 riscv_iommu_pci_setup_iommu(iommu, bus, errp); 144 } 145 146 static void riscv_iommu_pci_exit(PCIDevice *pci_dev) 147 { 148 pci_setup_iommu(pci_device_root_bus(pci_dev), NULL, NULL); 149 } 150 151 static const VMStateDescription riscv_iommu_vmstate = { 152 .name = "riscv-iommu", 153 .unmigratable = 1 154 }; 155 156 static void riscv_iommu_pci_init(Object *obj) 157 { 158 RISCVIOMMUStatePci *s = RISCV_IOMMU_PCI(obj); 159 RISCVIOMMUState *iommu = &s->iommu; 160 161 object_initialize_child(obj, "iommu", iommu, TYPE_RISCV_IOMMU); 162 qdev_alias_all_properties(DEVICE(iommu), obj); 163 164 iommu->icvec_avail_vectors = RISCV_IOMMU_PCI_ICVEC_VECTORS; 165 riscv_iommu_set_cap_igs(iommu, RISCV_IOMMU_CAP_IGS_MSI); 166 } 167 168 static const Property riscv_iommu_pci_properties[] = { 169 DEFINE_PROP_UINT16("vendor-id", RISCVIOMMUStatePci, vendor_id, 170 PCI_VENDOR_ID_REDHAT), 171 DEFINE_PROP_UINT16("device-id", RISCVIOMMUStatePci, device_id, 172 PCI_DEVICE_ID_REDHAT_RISCV_IOMMU), 173 DEFINE_PROP_UINT8("revision", RISCVIOMMUStatePci, revision, 0x01), 174 }; 175 176 static void riscv_iommu_pci_reset_hold(Object *obj, ResetType type) 177 { 178 RISCVIOMMUStatePci *pci = RISCV_IOMMU_PCI(obj); 179 RISCVIOMMUState *iommu = &pci->iommu; 180 181 riscv_iommu_reset(iommu); 182 183 trace_riscv_iommu_pci_reset_hold(type); 184 } 185 186 static void riscv_iommu_pci_class_init(ObjectClass *klass, void *data) 187 { 188 DeviceClass *dc = DEVICE_CLASS(klass); 189 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); 190 ResettableClass *rc = RESETTABLE_CLASS(klass); 191 192 rc->phases.hold = riscv_iommu_pci_reset_hold; 193 194 k->realize = riscv_iommu_pci_realize; 195 k->exit = riscv_iommu_pci_exit; 196 k->class_id = RISCV_PCI_CLASS_SYSTEM_IOMMU; 197 dc->desc = "RISCV-IOMMU DMA Remapping device"; 198 dc->vmsd = &riscv_iommu_vmstate; 199 dc->hotpluggable = false; 200 dc->user_creatable = true; 201 set_bit(DEVICE_CATEGORY_MISC, dc->categories); 202 device_class_set_props(dc, riscv_iommu_pci_properties); 203 } 204 205 static const TypeInfo riscv_iommu_pci = { 206 .name = TYPE_RISCV_IOMMU_PCI, 207 .parent = TYPE_PCI_DEVICE, 208 .class_init = riscv_iommu_pci_class_init, 209 .instance_init = riscv_iommu_pci_init, 210 .instance_size = sizeof(RISCVIOMMUStatePci), 211 .interfaces = (InterfaceInfo[]) { 212 { INTERFACE_PCIE_DEVICE }, 213 { }, 214 }, 215 }; 216 217 static void riscv_iommu_register_pci_types(void) 218 { 219 type_register_static(&riscv_iommu_pci); 220 } 221 222 type_init(riscv_iommu_register_pci_types); 223