1fe0fe473SAlistair Francis /* 2fe0fe473SAlistair Francis * QEMU RISC-V Board Compatible with OpenTitan FPGA platform 3fe0fe473SAlistair Francis * 4fe0fe473SAlistair Francis * Copyright (c) 2020 Western Digital 5fe0fe473SAlistair Francis * 6fe0fe473SAlistair Francis * Provides a board compatible with the OpenTitan FPGA platform: 7fe0fe473SAlistair Francis * 8fe0fe473SAlistair Francis * This program is free software; you can redistribute it and/or modify it 9fe0fe473SAlistair Francis * under the terms and conditions of the GNU General Public License, 10fe0fe473SAlistair Francis * version 2 or later, as published by the Free Software Foundation. 11fe0fe473SAlistair Francis * 12fe0fe473SAlistair Francis * This program is distributed in the hope it will be useful, but WITHOUT 13fe0fe473SAlistair Francis * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 14fe0fe473SAlistair Francis * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 15fe0fe473SAlistair Francis * more details. 16fe0fe473SAlistair Francis * 17fe0fe473SAlistair Francis * You should have received a copy of the GNU General Public License along with 18fe0fe473SAlistair Francis * this program. If not, see <http://www.gnu.org/licenses/>. 19fe0fe473SAlistair Francis */ 20fe0fe473SAlistair Francis 21fe0fe473SAlistair Francis #include "qemu/osdep.h" 2291b1fbdcSBin Meng #include "qemu/cutils.h" 23fe0fe473SAlistair Francis #include "hw/riscv/opentitan.h" 24fe0fe473SAlistair Francis #include "qapi/error.h" 25cc37d98bSRichard Henderson #include "qemu/error-report.h" 26fe0fe473SAlistair Francis #include "hw/boards.h" 27fe0fe473SAlistair Francis #include "hw/misc/unimp.h" 28fe0fe473SAlistair Francis #include "hw/riscv/boot.h" 29888c9af2SAlistair Francis #include "qemu/units.h" 30b9fc5135SAlistair Francis #include "sysemu/sysemu.h" 31fe0fe473SAlistair Francis 325379c1d0SWilfred Mallawa /* 335379c1d0SWilfred Mallawa * This version of the OpenTitan machine currently supports 345379c1d0SWilfred Mallawa * OpenTitan RTL version: 357ae71462SWilfred Mallawa * <lowRISC/opentitan@565e4af39760a123c59a184aa2f5812a961fde47> 365379c1d0SWilfred Mallawa * 375379c1d0SWilfred Mallawa * MMIO mapping as per (specified commit): 385379c1d0SWilfred Mallawa * lowRISC/opentitan: hw/top_earlgrey/sw/autogen/top_earlgrey_memory.h 395379c1d0SWilfred Mallawa */ 4073261285SBin Meng static const MemMapEntry ibex_memmap[] = { 41bf8803c6SWilfred Mallawa [IBEX_DEV_ROM] = { 0x00008000, 0x8000 }, 42bf8803c6SWilfred Mallawa [IBEX_DEV_RAM] = { 0x10000000, 0x20000 }, 43bf8803c6SWilfred Mallawa [IBEX_DEV_FLASH] = { 0x20000000, 0x100000 }, 447ae71462SWilfred Mallawa [IBEX_DEV_UART] = { 0x40000000, 0x40 }, 457ae71462SWilfred Mallawa [IBEX_DEV_GPIO] = { 0x40040000, 0x40 }, 467ae71462SWilfred Mallawa [IBEX_DEV_SPI_DEVICE] = { 0x40050000, 0x2000 }, 477ae71462SWilfred Mallawa [IBEX_DEV_I2C] = { 0x40080000, 0x80 }, 487ae71462SWilfred Mallawa [IBEX_DEV_PATTGEN] = { 0x400e0000, 0x40 }, 497ae71462SWilfred Mallawa [IBEX_DEV_TIMER] = { 0x40100000, 0x200 }, 507ae71462SWilfred Mallawa [IBEX_DEV_OTP_CTRL] = { 0x40130000, 0x2000 }, 517ae71462SWilfred Mallawa [IBEX_DEV_LC_CTRL] = { 0x40140000, 0x100 }, 527ae71462SWilfred Mallawa [IBEX_DEV_ALERT_HANDLER] = { 0x40150000, 0x800 }, 537ae71462SWilfred Mallawa [IBEX_DEV_SPI_HOST0] = { 0x40300000, 0x40 }, 547ae71462SWilfred Mallawa [IBEX_DEV_SPI_HOST1] = { 0x40310000, 0x40 }, 555379c1d0SWilfred Mallawa [IBEX_DEV_USBDEV] = { 0x40320000, 0x1000 }, 567ae71462SWilfred Mallawa [IBEX_DEV_PWRMGR] = { 0x40400000, 0x80 }, 577ae71462SWilfred Mallawa [IBEX_DEV_RSTMGR] = { 0x40410000, 0x80 }, 587ae71462SWilfred Mallawa [IBEX_DEV_CLKMGR] = { 0x40420000, 0x80 }, 59d31e970aSAlistair Francis [IBEX_DEV_PINMUX] = { 0x40460000, 0x1000 }, 607ae71462SWilfred Mallawa [IBEX_DEV_AON_TIMER] = { 0x40470000, 0x40 }, 617ae71462SWilfred Mallawa [IBEX_DEV_SENSOR_CTRL] = { 0x40490000, 0x40 }, 627ae71462SWilfred Mallawa [IBEX_DEV_FLASH_CTRL] = { 0x41000000, 0x200 }, 637ae71462SWilfred Mallawa [IBEX_DEV_AES] = { 0x41100000, 0x100 }, 64d31e970aSAlistair Francis [IBEX_DEV_HMAC] = { 0x41110000, 0x1000 }, 65d31e970aSAlistair Francis [IBEX_DEV_KMAC] = { 0x41120000, 0x1000 }, 66ef631006SAlistair Francis [IBEX_DEV_OTBN] = { 0x41130000, 0x10000 }, 677ae71462SWilfred Mallawa [IBEX_DEV_KEYMGR] = { 0x41140000, 0x100 }, 687ae71462SWilfred Mallawa [IBEX_DEV_CSRNG] = { 0x41150000, 0x80 }, 697ae71462SWilfred Mallawa [IBEX_DEV_ENTROPY] = { 0x41160000, 0x100 }, 707ae71462SWilfred Mallawa [IBEX_DEV_EDNO] = { 0x41170000, 0x80 }, 717ae71462SWilfred Mallawa [IBEX_DEV_EDN1] = { 0x41180000, 0x80 }, 727ae71462SWilfred Mallawa [IBEX_DEV_SRAM_CTRL] = { 0x411c0000, 0x20 }, 737ae71462SWilfred Mallawa [IBEX_DEV_IBEX_CFG] = { 0x411f0000, 0x100 }, 747ae71462SWilfred Mallawa [IBEX_DEV_PLIC] = { 0x48000000, 0x8000000 }, 75bb7e0cdeSAlistair Francis [IBEX_DEV_FLASH_VIRTUAL] = { 0x80000000, 0x80000 }, 76fe0fe473SAlistair Francis }; 77fe0fe473SAlistair Francis 789b29697fSPhilippe Mathieu-Daudé static void opentitan_machine_init(MachineState *machine) 79fe0fe473SAlistair Francis { 8091b1fbdcSBin Meng MachineClass *mc = MACHINE_GET_CLASS(machine); 81a828ba9dSPhilippe Mathieu-Daudé OpenTitanState *s = OPENTITAN_MACHINE(machine); 8273261285SBin Meng const MemMapEntry *memmap = ibex_memmap; 83fe0fe473SAlistair Francis MemoryRegion *sys_mem = get_system_memory(); 84*d3592955SJim Shu RISCVBootInfo boot_info; 8591b1fbdcSBin Meng 8691b1fbdcSBin Meng if (machine->ram_size != mc->default_ram_size) { 8791b1fbdcSBin Meng char *sz = size_to_str(mc->default_ram_size); 8891b1fbdcSBin Meng error_report("Invalid RAM size, should be %s", sz); 8991b1fbdcSBin Meng g_free(sz); 9091b1fbdcSBin Meng exit(EXIT_FAILURE); 9191b1fbdcSBin Meng } 92fe0fe473SAlistair Francis 93fe0fe473SAlistair Francis /* Initialize SoC */ 94fe0fe473SAlistair Francis object_initialize_child(OBJECT(machine), "soc", &s->soc, 959fc7fc4dSMarkus Armbruster TYPE_RISCV_IBEX_SOC); 968f972e5bSAlistair Francis qdev_realize(DEVICE(&s->soc), NULL, &error_fatal); 97fe0fe473SAlistair Francis 98fe0fe473SAlistair Francis memory_region_add_subregion(sys_mem, 9991b1fbdcSBin Meng memmap[IBEX_DEV_RAM].base, machine->ram); 100fe0fe473SAlistair Francis 101fe0fe473SAlistair Francis if (machine->firmware) { 10255c13659SSamuel Holland hwaddr firmware_load_addr = memmap[IBEX_DEV_RAM].base; 10355c13659SSamuel Holland riscv_load_firmware(machine->firmware, &firmware_load_addr, NULL); 104fe0fe473SAlistair Francis } 105fe0fe473SAlistair Francis 106*d3592955SJim Shu riscv_boot_info_init(&boot_info, &s->soc.cpus); 107fe0fe473SAlistair Francis if (machine->kernel_filename) { 108*d3592955SJim Shu riscv_load_kernel(machine, &boot_info, 109487d73fcSDaniel Henrique Barboza memmap[IBEX_DEV_RAM].base, 110487d73fcSDaniel Henrique Barboza false, NULL); 111fe0fe473SAlistair Francis } 112fe0fe473SAlistair Francis } 113fe0fe473SAlistair Francis 1148696b74aSPhilippe Mathieu-Daudé static void opentitan_machine_class_init(ObjectClass *oc, void *data) 115fe0fe473SAlistair Francis { 1168696b74aSPhilippe Mathieu-Daudé MachineClass *mc = MACHINE_CLASS(oc); 1178696b74aSPhilippe Mathieu-Daudé 118fe0fe473SAlistair Francis mc->desc = "RISC-V Board compatible with OpenTitan"; 1199b29697fSPhilippe Mathieu-Daudé mc->init = opentitan_machine_init; 120fe0fe473SAlistair Francis mc->max_cpus = 1; 121fe0fe473SAlistair Francis mc->default_cpu_type = TYPE_RISCV_CPU_IBEX; 12291b1fbdcSBin Meng mc->default_ram_id = "riscv.lowrisc.ibex.ram"; 12391b1fbdcSBin Meng mc->default_ram_size = ibex_memmap[IBEX_DEV_RAM].size; 124fe0fe473SAlistair Francis } 125fe0fe473SAlistair Francis 12689494462SBin Meng static void lowrisc_ibex_soc_init(Object *obj) 127fe0fe473SAlistair Francis { 128fe0fe473SAlistair Francis LowRISCIbexSoCState *s = RISCV_IBEX_SOC(obj); 129fe0fe473SAlistair Francis 130db873cc5SMarkus Armbruster object_initialize_child(obj, "cpus", &s->cpus, TYPE_RISCV_HART_ARRAY); 131b9fc5135SAlistair Francis 132ef631006SAlistair Francis object_initialize_child(obj, "plic", &s->plic, TYPE_SIFIVE_PLIC); 133cc411260SAlistair Francis 134cc411260SAlistair Francis object_initialize_child(obj, "uart", &s->uart, TYPE_IBEX_UART); 1353ef64344SAlistair Francis 1363ef64344SAlistair Francis object_initialize_child(obj, "timer", &s->timer, TYPE_IBEX_TIMER); 1379972479fSWilfred Mallawa 1389972479fSWilfred Mallawa for (int i = 0; i < OPENTITAN_NUM_SPI_HOSTS; i++) { 1399972479fSWilfred Mallawa object_initialize_child(obj, "spi_host[*]", &s->spi_host[i], 1409972479fSWilfred Mallawa TYPE_IBEX_SPI_HOST); 1419972479fSWilfred Mallawa } 142fe0fe473SAlistair Francis } 143fe0fe473SAlistair Francis 14489494462SBin Meng static void lowrisc_ibex_soc_realize(DeviceState *dev_soc, Error **errp) 145fe0fe473SAlistair Francis { 14673261285SBin Meng const MemMapEntry *memmap = ibex_memmap; 1479972479fSWilfred Mallawa DeviceState *dev; 1489972479fSWilfred Mallawa SysBusDevice *busdev; 149fe0fe473SAlistair Francis MachineState *ms = MACHINE(qdev_get_machine()); 150fe0fe473SAlistair Francis LowRISCIbexSoCState *s = RISCV_IBEX_SOC(dev_soc); 151fe0fe473SAlistair Francis MemoryRegion *sys_mem = get_system_memory(); 152e5cc6aaeSAlistair Francis int i; 153fe0fe473SAlistair Francis 1545325cc34SMarkus Armbruster object_property_set_str(OBJECT(&s->cpus), "cpu-type", ms->cpu_type, 155fe0fe473SAlistair Francis &error_abort); 1565325cc34SMarkus Armbruster object_property_set_int(OBJECT(&s->cpus), "num-harts", ms->smp.cpus, 157fe0fe473SAlistair Francis &error_abort); 158a06fded8SAlistair Francis object_property_set_int(OBJECT(&s->cpus), "resetvec", s->resetvec, 159bf8803c6SWilfred Mallawa &error_abort); 16091a3387dSTsukasa OI sysbus_realize(SYS_BUS_DEVICE(&s->cpus), &error_fatal); 161fe0fe473SAlistair Francis 162fe0fe473SAlistair Francis /* Boot ROM */ 163fe0fe473SAlistair Francis memory_region_init_rom(&s->rom, OBJECT(dev_soc), "riscv.lowrisc.ibex.rom", 16430c717cbSEduardo Habkost memmap[IBEX_DEV_ROM].size, &error_fatal); 165fe0fe473SAlistair Francis memory_region_add_subregion(sys_mem, 16630c717cbSEduardo Habkost memmap[IBEX_DEV_ROM].base, &s->rom); 167fe0fe473SAlistair Francis 168fe0fe473SAlistair Francis /* Flash memory */ 169fe0fe473SAlistair Francis memory_region_init_rom(&s->flash_mem, OBJECT(dev_soc), "riscv.lowrisc.ibex.flash", 17030c717cbSEduardo Habkost memmap[IBEX_DEV_FLASH].size, &error_fatal); 171bb7e0cdeSAlistair Francis memory_region_init_alias(&s->flash_alias, OBJECT(dev_soc), 172bb7e0cdeSAlistair Francis "riscv.lowrisc.ibex.flash_virtual", &s->flash_mem, 0, 173bb7e0cdeSAlistair Francis memmap[IBEX_DEV_FLASH_VIRTUAL].size); 17430c717cbSEduardo Habkost memory_region_add_subregion(sys_mem, memmap[IBEX_DEV_FLASH].base, 175fe0fe473SAlistair Francis &s->flash_mem); 176bb7e0cdeSAlistair Francis memory_region_add_subregion(sys_mem, memmap[IBEX_DEV_FLASH_VIRTUAL].base, 177bb7e0cdeSAlistair Francis &s->flash_alias); 178fe0fe473SAlistair Francis 179b9fc5135SAlistair Francis /* PLIC */ 180ef631006SAlistair Francis qdev_prop_set_string(DEVICE(&s->plic), "hart-config", "M"); 181ef631006SAlistair Francis qdev_prop_set_uint32(DEVICE(&s->plic), "num-sources", 180); 182ef631006SAlistair Francis qdev_prop_set_uint32(DEVICE(&s->plic), "num-priorities", 3); 183ef631006SAlistair Francis qdev_prop_set_uint32(DEVICE(&s->plic), "pending-base", 0x1000); 184ef631006SAlistair Francis qdev_prop_set_uint32(DEVICE(&s->plic), "enable-base", 0x2000); 1850df470c3SWilfred Mallawa qdev_prop_set_uint32(DEVICE(&s->plic), "enable-stride", 32); 1869b144ed4SAlistair Francis qdev_prop_set_uint32(DEVICE(&s->plic), "context-base", 0x200000); 1879b144ed4SAlistair Francis qdev_prop_set_uint32(DEVICE(&s->plic), "context-stride", 8); 188ef631006SAlistair Francis qdev_prop_set_uint32(DEVICE(&s->plic), "aperture-size", memmap[IBEX_DEV_PLIC].size); 189ef631006SAlistair Francis 190668f62ecSMarkus Armbruster if (!sysbus_realize(SYS_BUS_DEVICE(&s->plic), errp)) { 191b9fc5135SAlistair Francis return; 192b9fc5135SAlistair Francis } 19330c717cbSEduardo Habkost sysbus_mmio_map(SYS_BUS_DEVICE(&s->plic), 0, memmap[IBEX_DEV_PLIC].base); 194b9fc5135SAlistair Francis 195e5cc6aaeSAlistair Francis for (i = 0; i < ms->smp.cpus; i++) { 196e5cc6aaeSAlistair Francis CPUState *cpu = qemu_get_cpu(i); 197e5cc6aaeSAlistair Francis 198ef631006SAlistair Francis qdev_connect_gpio_out(DEVICE(&s->plic), ms->smp.cpus + i, 199e5cc6aaeSAlistair Francis qdev_get_gpio_in(DEVICE(cpu), IRQ_M_EXT)); 200e5cc6aaeSAlistair Francis } 201e5cc6aaeSAlistair Francis 202cc411260SAlistair Francis /* UART */ 203cc411260SAlistair Francis qdev_prop_set_chr(DEVICE(&(s->uart)), "chardev", serial_hd(0)); 204668f62ecSMarkus Armbruster if (!sysbus_realize(SYS_BUS_DEVICE(&s->uart), errp)) { 205cc411260SAlistair Francis return; 206cc411260SAlistair Francis } 20730c717cbSEduardo Habkost sysbus_mmio_map(SYS_BUS_DEVICE(&s->uart), 0, memmap[IBEX_DEV_UART].base); 208cc411260SAlistair Francis sysbus_connect_irq(SYS_BUS_DEVICE(&s->uart), 209cc411260SAlistair Francis 0, qdev_get_gpio_in(DEVICE(&s->plic), 210d4cad544SAlistair Francis IBEX_UART0_TX_WATERMARK_IRQ)); 211cc411260SAlistair Francis sysbus_connect_irq(SYS_BUS_DEVICE(&s->uart), 212cc411260SAlistair Francis 1, qdev_get_gpio_in(DEVICE(&s->plic), 213d4cad544SAlistair Francis IBEX_UART0_RX_WATERMARK_IRQ)); 214cc411260SAlistair Francis sysbus_connect_irq(SYS_BUS_DEVICE(&s->uart), 215cc411260SAlistair Francis 2, qdev_get_gpio_in(DEVICE(&s->plic), 216d4cad544SAlistair Francis IBEX_UART0_TX_EMPTY_IRQ)); 217cc411260SAlistair Francis sysbus_connect_irq(SYS_BUS_DEVICE(&s->uart), 218cc411260SAlistair Francis 3, qdev_get_gpio_in(DEVICE(&s->plic), 219d4cad544SAlistair Francis IBEX_UART0_RX_OVERFLOW_IRQ)); 220cc411260SAlistair Francis 2213ef64344SAlistair Francis if (!sysbus_realize(SYS_BUS_DEVICE(&s->timer), errp)) { 2223ef64344SAlistair Francis return; 2233ef64344SAlistair Francis } 2243ef64344SAlistair Francis sysbus_mmio_map(SYS_BUS_DEVICE(&s->timer), 0, memmap[IBEX_DEV_TIMER].base); 2253ef64344SAlistair Francis sysbus_connect_irq(SYS_BUS_DEVICE(&s->timer), 2263ef64344SAlistair Francis 0, qdev_get_gpio_in(DEVICE(&s->plic), 2273ef64344SAlistair Francis IBEX_TIMER_TIMEREXPIRED0_0)); 22857a3a622SAlistair Francis qdev_connect_gpio_out(DEVICE(&s->timer), 0, 22957a3a622SAlistair Francis qdev_get_gpio_in(DEVICE(qemu_get_cpu(0)), 23057a3a622SAlistair Francis IRQ_M_TIMER)); 2313ef64344SAlistair Francis 2329972479fSWilfred Mallawa /* SPI-Hosts */ 233010f5557SAlistair Francis for (i = 0; i < OPENTITAN_NUM_SPI_HOSTS; ++i) { 2349972479fSWilfred Mallawa dev = DEVICE(&(s->spi_host[i])); 2359972479fSWilfred Mallawa if (!sysbus_realize(SYS_BUS_DEVICE(&s->spi_host[i]), errp)) { 2369972479fSWilfred Mallawa return; 2379972479fSWilfred Mallawa } 2389972479fSWilfred Mallawa busdev = SYS_BUS_DEVICE(dev); 2399972479fSWilfred Mallawa sysbus_mmio_map(busdev, 0, memmap[IBEX_DEV_SPI_HOST0 + i].base); 2409972479fSWilfred Mallawa 2419972479fSWilfred Mallawa switch (i) { 2429972479fSWilfred Mallawa case OPENTITAN_SPI_HOST0: 2439972479fSWilfred Mallawa sysbus_connect_irq(busdev, 0, qdev_get_gpio_in(DEVICE(&s->plic), 2449972479fSWilfred Mallawa IBEX_SPI_HOST0_ERR_IRQ)); 2459972479fSWilfred Mallawa sysbus_connect_irq(busdev, 1, qdev_get_gpio_in(DEVICE(&s->plic), 2469972479fSWilfred Mallawa IBEX_SPI_HOST0_SPI_EVENT_IRQ)); 2479972479fSWilfred Mallawa break; 2489972479fSWilfred Mallawa case OPENTITAN_SPI_HOST1: 2499972479fSWilfred Mallawa sysbus_connect_irq(busdev, 0, qdev_get_gpio_in(DEVICE(&s->plic), 2509972479fSWilfred Mallawa IBEX_SPI_HOST1_ERR_IRQ)); 2519972479fSWilfred Mallawa sysbus_connect_irq(busdev, 1, qdev_get_gpio_in(DEVICE(&s->plic), 2529972479fSWilfred Mallawa IBEX_SPI_HOST1_SPI_EVENT_IRQ)); 2539972479fSWilfred Mallawa break; 2549972479fSWilfred Mallawa } 2559972479fSWilfred Mallawa } 2569972479fSWilfred Mallawa 257fe0fe473SAlistair Francis create_unimplemented_device("riscv.lowrisc.ibex.gpio", 25830c717cbSEduardo Habkost memmap[IBEX_DEV_GPIO].base, memmap[IBEX_DEV_GPIO].size); 259aecabd50SWilfred Mallawa create_unimplemented_device("riscv.lowrisc.ibex.spi_device", 260aecabd50SWilfred Mallawa memmap[IBEX_DEV_SPI_DEVICE].base, memmap[IBEX_DEV_SPI_DEVICE].size); 261d31e970aSAlistair Francis create_unimplemented_device("riscv.lowrisc.ibex.i2c", 262d31e970aSAlistair Francis memmap[IBEX_DEV_I2C].base, memmap[IBEX_DEV_I2C].size); 263d31e970aSAlistair Francis create_unimplemented_device("riscv.lowrisc.ibex.pattgen", 264d31e970aSAlistair Francis memmap[IBEX_DEV_PATTGEN].base, memmap[IBEX_DEV_PATTGEN].size); 265d31e970aSAlistair Francis create_unimplemented_device("riscv.lowrisc.ibex.sensor_ctrl", 266d31e970aSAlistair Francis memmap[IBEX_DEV_SENSOR_CTRL].base, memmap[IBEX_DEV_SENSOR_CTRL].size); 267d31e970aSAlistair Francis create_unimplemented_device("riscv.lowrisc.ibex.otp_ctrl", 268d31e970aSAlistair Francis memmap[IBEX_DEV_OTP_CTRL].base, memmap[IBEX_DEV_OTP_CTRL].size); 269bf8803c6SWilfred Mallawa create_unimplemented_device("riscv.lowrisc.ibex.lc_ctrl", 270bf8803c6SWilfred Mallawa memmap[IBEX_DEV_LC_CTRL].base, memmap[IBEX_DEV_LC_CTRL].size); 271fe0fe473SAlistair Francis create_unimplemented_device("riscv.lowrisc.ibex.pwrmgr", 27230c717cbSEduardo Habkost memmap[IBEX_DEV_PWRMGR].base, memmap[IBEX_DEV_PWRMGR].size); 273fe0fe473SAlistair Francis create_unimplemented_device("riscv.lowrisc.ibex.rstmgr", 27430c717cbSEduardo Habkost memmap[IBEX_DEV_RSTMGR].base, memmap[IBEX_DEV_RSTMGR].size); 275fe0fe473SAlistair Francis create_unimplemented_device("riscv.lowrisc.ibex.clkmgr", 27630c717cbSEduardo Habkost memmap[IBEX_DEV_CLKMGR].base, memmap[IBEX_DEV_CLKMGR].size); 277d31e970aSAlistair Francis create_unimplemented_device("riscv.lowrisc.ibex.pinmux", 278d31e970aSAlistair Francis memmap[IBEX_DEV_PINMUX].base, memmap[IBEX_DEV_PINMUX].size); 279aefd1108SWilfred Mallawa create_unimplemented_device("riscv.lowrisc.ibex.aon_timer", 280aefd1108SWilfred Mallawa memmap[IBEX_DEV_AON_TIMER].base, memmap[IBEX_DEV_AON_TIMER].size); 281d31e970aSAlistair Francis create_unimplemented_device("riscv.lowrisc.ibex.usbdev", 282d31e970aSAlistair Francis memmap[IBEX_DEV_USBDEV].base, memmap[IBEX_DEV_USBDEV].size); 283d31e970aSAlistair Francis create_unimplemented_device("riscv.lowrisc.ibex.flash_ctrl", 284d31e970aSAlistair Francis memmap[IBEX_DEV_FLASH_CTRL].base, memmap[IBEX_DEV_FLASH_CTRL].size); 285fe0fe473SAlistair Francis create_unimplemented_device("riscv.lowrisc.ibex.aes", 28630c717cbSEduardo Habkost memmap[IBEX_DEV_AES].base, memmap[IBEX_DEV_AES].size); 287fe0fe473SAlistair Francis create_unimplemented_device("riscv.lowrisc.ibex.hmac", 28830c717cbSEduardo Habkost memmap[IBEX_DEV_HMAC].base, memmap[IBEX_DEV_HMAC].size); 289d31e970aSAlistair Francis create_unimplemented_device("riscv.lowrisc.ibex.kmac", 290d31e970aSAlistair Francis memmap[IBEX_DEV_KMAC].base, memmap[IBEX_DEV_KMAC].size); 291d31e970aSAlistair Francis create_unimplemented_device("riscv.lowrisc.ibex.keymgr", 292d31e970aSAlistair Francis memmap[IBEX_DEV_KEYMGR].base, memmap[IBEX_DEV_KEYMGR].size); 293d31e970aSAlistair Francis create_unimplemented_device("riscv.lowrisc.ibex.csrng", 294d31e970aSAlistair Francis memmap[IBEX_DEV_CSRNG].base, memmap[IBEX_DEV_CSRNG].size); 295d31e970aSAlistair Francis create_unimplemented_device("riscv.lowrisc.ibex.entropy", 296d31e970aSAlistair Francis memmap[IBEX_DEV_ENTROPY].base, memmap[IBEX_DEV_ENTROPY].size); 297d31e970aSAlistair Francis create_unimplemented_device("riscv.lowrisc.ibex.edn0", 298d31e970aSAlistair Francis memmap[IBEX_DEV_EDNO].base, memmap[IBEX_DEV_EDNO].size); 299d31e970aSAlistair Francis create_unimplemented_device("riscv.lowrisc.ibex.edn1", 300d31e970aSAlistair Francis memmap[IBEX_DEV_EDN1].base, memmap[IBEX_DEV_EDN1].size); 301fe0fe473SAlistair Francis create_unimplemented_device("riscv.lowrisc.ibex.alert_handler", 30230c717cbSEduardo Habkost memmap[IBEX_DEV_ALERT_HANDLER].base, memmap[IBEX_DEV_ALERT_HANDLER].size); 3037ae71462SWilfred Mallawa create_unimplemented_device("riscv.lowrisc.ibex.sram_ctrl", 3047ae71462SWilfred Mallawa memmap[IBEX_DEV_SRAM_CTRL].base, memmap[IBEX_DEV_SRAM_CTRL].size); 305d31e970aSAlistair Francis create_unimplemented_device("riscv.lowrisc.ibex.otbn", 306d31e970aSAlistair Francis memmap[IBEX_DEV_OTBN].base, memmap[IBEX_DEV_OTBN].size); 3077ae71462SWilfred Mallawa create_unimplemented_device("riscv.lowrisc.ibex.ibex_cfg", 3087ae71462SWilfred Mallawa memmap[IBEX_DEV_IBEX_CFG].base, memmap[IBEX_DEV_IBEX_CFG].size); 309fe0fe473SAlistair Francis } 310fe0fe473SAlistair Francis 311766bade2SRichard Henderson static const Property lowrisc_ibex_soc_props[] = { 312a06fded8SAlistair Francis DEFINE_PROP_UINT32("resetvec", LowRISCIbexSoCState, resetvec, 0x20000400), 313a06fded8SAlistair Francis DEFINE_PROP_END_OF_LIST() 314a06fded8SAlistair Francis }; 315a06fded8SAlistair Francis 31689494462SBin Meng static void lowrisc_ibex_soc_class_init(ObjectClass *oc, void *data) 317fe0fe473SAlistair Francis { 318fe0fe473SAlistair Francis DeviceClass *dc = DEVICE_CLASS(oc); 319fe0fe473SAlistair Francis 320a06fded8SAlistair Francis device_class_set_props(dc, lowrisc_ibex_soc_props); 32189494462SBin Meng dc->realize = lowrisc_ibex_soc_realize; 322fe0fe473SAlistair Francis /* Reason: Uses serial_hds in realize function, thus can't be used twice */ 323fe0fe473SAlistair Francis dc->user_creatable = false; 324fe0fe473SAlistair Francis } 325fe0fe473SAlistair Francis 326e0782b11SPhilippe Mathieu-Daudé static const TypeInfo open_titan_types[] = { 327e0782b11SPhilippe Mathieu-Daudé { 328fe0fe473SAlistair Francis .name = TYPE_RISCV_IBEX_SOC, 329fe0fe473SAlistair Francis .parent = TYPE_DEVICE, 330fe0fe473SAlistair Francis .instance_size = sizeof(LowRISCIbexSoCState), 33189494462SBin Meng .instance_init = lowrisc_ibex_soc_init, 33289494462SBin Meng .class_init = lowrisc_ibex_soc_class_init, 3338696b74aSPhilippe Mathieu-Daudé }, { 3348696b74aSPhilippe Mathieu-Daudé .name = TYPE_OPENTITAN_MACHINE, 3358696b74aSPhilippe Mathieu-Daudé .parent = TYPE_MACHINE, 336a828ba9dSPhilippe Mathieu-Daudé .instance_size = sizeof(OpenTitanState), 3378696b74aSPhilippe Mathieu-Daudé .class_init = opentitan_machine_class_init, 338e0782b11SPhilippe Mathieu-Daudé } 339fe0fe473SAlistair Francis }; 340fe0fe473SAlistair Francis 341e0782b11SPhilippe Mathieu-Daudé DEFINE_TYPES(open_titan_types) 342