1fe0fe473SAlistair Francis /* 2fe0fe473SAlistair Francis * QEMU RISC-V Board Compatible with OpenTitan FPGA platform 3fe0fe473SAlistair Francis * 4fe0fe473SAlistair Francis * Copyright (c) 2020 Western Digital 5fe0fe473SAlistair Francis * 6fe0fe473SAlistair Francis * Provides a board compatible with the OpenTitan FPGA platform: 7fe0fe473SAlistair Francis * 8fe0fe473SAlistair Francis * This program is free software; you can redistribute it and/or modify it 9fe0fe473SAlistair Francis * under the terms and conditions of the GNU General Public License, 10fe0fe473SAlistair Francis * version 2 or later, as published by the Free Software Foundation. 11fe0fe473SAlistair Francis * 12fe0fe473SAlistair Francis * This program is distributed in the hope it will be useful, but WITHOUT 13fe0fe473SAlistair Francis * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 14fe0fe473SAlistair Francis * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 15fe0fe473SAlistair Francis * more details. 16fe0fe473SAlistair Francis * 17fe0fe473SAlistair Francis * You should have received a copy of the GNU General Public License along with 18fe0fe473SAlistair Francis * this program. If not, see <http://www.gnu.org/licenses/>. 19fe0fe473SAlistair Francis */ 20fe0fe473SAlistair Francis 21fe0fe473SAlistair Francis #include "qemu/osdep.h" 22fe0fe473SAlistair Francis #include "hw/riscv/opentitan.h" 23fe0fe473SAlistair Francis #include "qapi/error.h" 24fe0fe473SAlistair Francis #include "hw/boards.h" 25fe0fe473SAlistair Francis #include "hw/misc/unimp.h" 26fe0fe473SAlistair Francis #include "hw/riscv/boot.h" 27fe0fe473SAlistair Francis #include "exec/address-spaces.h" 28888c9af2SAlistair Francis #include "qemu/units.h" 29b9fc5135SAlistair Francis #include "sysemu/sysemu.h" 30fe0fe473SAlistair Francis 31fe0fe473SAlistair Francis static const struct MemmapEntry { 32fe0fe473SAlistair Francis hwaddr base; 33fe0fe473SAlistair Francis hwaddr size; 34fe0fe473SAlistair Francis } ibex_memmap[] = { 3530c717cbSEduardo Habkost [IBEX_DEV_ROM] = { 0x00008000, 16 * KiB }, 3630c717cbSEduardo Habkost [IBEX_DEV_RAM] = { 0x10000000, 0x10000 }, 3730c717cbSEduardo Habkost [IBEX_DEV_FLASH] = { 0x20000000, 0x80000 }, 38*d31e970aSAlistair Francis [IBEX_DEV_UART] = { 0x40000000, 0x1000 }, 39*d31e970aSAlistair Francis [IBEX_DEV_GPIO] = { 0x40040000, 0x1000 }, 40*d31e970aSAlistair Francis [IBEX_DEV_SPI] = { 0x40050000, 0x1000 }, 41*d31e970aSAlistair Francis [IBEX_DEV_I2C] = { 0x40080000, 0x1000 }, 42*d31e970aSAlistair Francis [IBEX_DEV_PATTGEN] = { 0x400e0000, 0x1000 }, 43*d31e970aSAlistair Francis [IBEX_DEV_RV_TIMER] = { 0x40100000, 0x1000 }, 44*d31e970aSAlistair Francis [IBEX_DEV_SENSOR_CTRL] = { 0x40110000, 0x1000 }, 45*d31e970aSAlistair Francis [IBEX_DEV_OTP_CTRL] = { 0x40130000, 0x4000 }, 46*d31e970aSAlistair Francis [IBEX_DEV_PWRMGR] = { 0x40400000, 0x1000 }, 47*d31e970aSAlistair Francis [IBEX_DEV_RSTMGR] = { 0x40410000, 0x1000 }, 48*d31e970aSAlistair Francis [IBEX_DEV_CLKMGR] = { 0x40420000, 0x1000 }, 49*d31e970aSAlistair Francis [IBEX_DEV_PINMUX] = { 0x40460000, 0x1000 }, 50*d31e970aSAlistair Francis [IBEX_DEV_PADCTRL] = { 0x40470000, 0x1000 }, 51*d31e970aSAlistair Francis [IBEX_DEV_USBDEV] = { 0x40500000, 0x1000 }, 52*d31e970aSAlistair Francis [IBEX_DEV_FLASH_CTRL] = { 0x41000000, 0x1000 }, 53*d31e970aSAlistair Francis [IBEX_DEV_PLIC] = { 0x41010000, 0x1000 }, 54*d31e970aSAlistair Francis [IBEX_DEV_AES] = { 0x41100000, 0x1000 }, 55*d31e970aSAlistair Francis [IBEX_DEV_HMAC] = { 0x41110000, 0x1000 }, 56*d31e970aSAlistair Francis [IBEX_DEV_KMAC] = { 0x41120000, 0x1000 }, 57*d31e970aSAlistair Francis [IBEX_DEV_KEYMGR] = { 0x41130000, 0x1000 }, 58*d31e970aSAlistair Francis [IBEX_DEV_CSRNG] = { 0x41150000, 0x1000 }, 59*d31e970aSAlistair Francis [IBEX_DEV_ENTROPY] = { 0x41160000, 0x1000 }, 60*d31e970aSAlistair Francis [IBEX_DEV_EDNO] = { 0x41170000, 0x1000 }, 61*d31e970aSAlistair Francis [IBEX_DEV_EDN1] = { 0x41180000, 0x1000 }, 62*d31e970aSAlistair Francis [IBEX_DEV_ALERT_HANDLER] = { 0x411b0000, 0x1000 }, 63*d31e970aSAlistair Francis [IBEX_DEV_NMI_GEN] = { 0x411c0000, 0x1000 }, 64*d31e970aSAlistair Francis [IBEX_DEV_OTBN] = { 0x411d0000, 0x10000 }, 65fe0fe473SAlistair Francis }; 66fe0fe473SAlistair Francis 6789494462SBin Meng static void opentitan_board_init(MachineState *machine) 68fe0fe473SAlistair Francis { 69fe0fe473SAlistair Francis const struct MemmapEntry *memmap = ibex_memmap; 70fe0fe473SAlistair Francis OpenTitanState *s = g_new0(OpenTitanState, 1); 71fe0fe473SAlistair Francis MemoryRegion *sys_mem = get_system_memory(); 72fe0fe473SAlistair Francis MemoryRegion *main_mem = g_new(MemoryRegion, 1); 73fe0fe473SAlistair Francis 74fe0fe473SAlistair Francis /* Initialize SoC */ 75fe0fe473SAlistair Francis object_initialize_child(OBJECT(machine), "soc", &s->soc, 769fc7fc4dSMarkus Armbruster TYPE_RISCV_IBEX_SOC); 77ce189ab2SMarkus Armbruster qdev_realize(DEVICE(&s->soc), NULL, &error_abort); 78fe0fe473SAlistair Francis 79fe0fe473SAlistair Francis memory_region_init_ram(main_mem, NULL, "riscv.lowrisc.ibex.ram", 8030c717cbSEduardo Habkost memmap[IBEX_DEV_RAM].size, &error_fatal); 81fe0fe473SAlistair Francis memory_region_add_subregion(sys_mem, 8230c717cbSEduardo Habkost memmap[IBEX_DEV_RAM].base, main_mem); 83fe0fe473SAlistair Francis 84fe0fe473SAlistair Francis if (machine->firmware) { 8530c717cbSEduardo Habkost riscv_load_firmware(machine->firmware, memmap[IBEX_DEV_RAM].base, NULL); 86fe0fe473SAlistair Francis } 87fe0fe473SAlistair Francis 88fe0fe473SAlistair Francis if (machine->kernel_filename) { 8938bc4e34SAlistair Francis riscv_load_kernel(machine->kernel_filename, 9038bc4e34SAlistair Francis memmap[IBEX_DEV_RAM].base, NULL); 91fe0fe473SAlistair Francis } 92fe0fe473SAlistair Francis } 93fe0fe473SAlistair Francis 9489494462SBin Meng static void opentitan_machine_init(MachineClass *mc) 95fe0fe473SAlistair Francis { 96fe0fe473SAlistair Francis mc->desc = "RISC-V Board compatible with OpenTitan"; 9789494462SBin Meng mc->init = opentitan_board_init; 98fe0fe473SAlistair Francis mc->max_cpus = 1; 99fe0fe473SAlistair Francis mc->default_cpu_type = TYPE_RISCV_CPU_IBEX; 100fe0fe473SAlistair Francis } 101fe0fe473SAlistair Francis 10289494462SBin Meng DEFINE_MACHINE("opentitan", opentitan_machine_init) 103fe0fe473SAlistair Francis 10489494462SBin Meng static void lowrisc_ibex_soc_init(Object *obj) 105fe0fe473SAlistair Francis { 106fe0fe473SAlistair Francis LowRISCIbexSoCState *s = RISCV_IBEX_SOC(obj); 107fe0fe473SAlistair Francis 108db873cc5SMarkus Armbruster object_initialize_child(obj, "cpus", &s->cpus, TYPE_RISCV_HART_ARRAY); 109b9fc5135SAlistair Francis 110b9fc5135SAlistair Francis object_initialize_child(obj, "plic", &s->plic, TYPE_IBEX_PLIC); 111cc411260SAlistair Francis 112cc411260SAlistair Francis object_initialize_child(obj, "uart", &s->uart, TYPE_IBEX_UART); 113fe0fe473SAlistair Francis } 114fe0fe473SAlistair Francis 11589494462SBin Meng static void lowrisc_ibex_soc_realize(DeviceState *dev_soc, Error **errp) 116fe0fe473SAlistair Francis { 117fe0fe473SAlistair Francis const struct MemmapEntry *memmap = ibex_memmap; 118fe0fe473SAlistair Francis MachineState *ms = MACHINE(qdev_get_machine()); 119fe0fe473SAlistair Francis LowRISCIbexSoCState *s = RISCV_IBEX_SOC(dev_soc); 120fe0fe473SAlistair Francis MemoryRegion *sys_mem = get_system_memory(); 121fe0fe473SAlistair Francis 1225325cc34SMarkus Armbruster object_property_set_str(OBJECT(&s->cpus), "cpu-type", ms->cpu_type, 123fe0fe473SAlistair Francis &error_abort); 1245325cc34SMarkus Armbruster object_property_set_int(OBJECT(&s->cpus), "num-harts", ms->smp.cpus, 125fe0fe473SAlistair Francis &error_abort); 12673f6ed97SBin Meng object_property_set_int(OBJECT(&s->cpus), "resetvec", 0x8090, &error_abort); 127db873cc5SMarkus Armbruster sysbus_realize(SYS_BUS_DEVICE(&s->cpus), &error_abort); 128fe0fe473SAlistair Francis 129fe0fe473SAlistair Francis /* Boot ROM */ 130fe0fe473SAlistair Francis memory_region_init_rom(&s->rom, OBJECT(dev_soc), "riscv.lowrisc.ibex.rom", 13130c717cbSEduardo Habkost memmap[IBEX_DEV_ROM].size, &error_fatal); 132fe0fe473SAlistair Francis memory_region_add_subregion(sys_mem, 13330c717cbSEduardo Habkost memmap[IBEX_DEV_ROM].base, &s->rom); 134fe0fe473SAlistair Francis 135fe0fe473SAlistair Francis /* Flash memory */ 136fe0fe473SAlistair Francis memory_region_init_rom(&s->flash_mem, OBJECT(dev_soc), "riscv.lowrisc.ibex.flash", 13730c717cbSEduardo Habkost memmap[IBEX_DEV_FLASH].size, &error_fatal); 13830c717cbSEduardo Habkost memory_region_add_subregion(sys_mem, memmap[IBEX_DEV_FLASH].base, 139fe0fe473SAlistair Francis &s->flash_mem); 140fe0fe473SAlistair Francis 141b9fc5135SAlistair Francis /* PLIC */ 142668f62ecSMarkus Armbruster if (!sysbus_realize(SYS_BUS_DEVICE(&s->plic), errp)) { 143b9fc5135SAlistair Francis return; 144b9fc5135SAlistair Francis } 14530c717cbSEduardo Habkost sysbus_mmio_map(SYS_BUS_DEVICE(&s->plic), 0, memmap[IBEX_DEV_PLIC].base); 146b9fc5135SAlistair Francis 147cc411260SAlistair Francis /* UART */ 148cc411260SAlistair Francis qdev_prop_set_chr(DEVICE(&(s->uart)), "chardev", serial_hd(0)); 149668f62ecSMarkus Armbruster if (!sysbus_realize(SYS_BUS_DEVICE(&s->uart), errp)) { 150cc411260SAlistair Francis return; 151cc411260SAlistair Francis } 15230c717cbSEduardo Habkost sysbus_mmio_map(SYS_BUS_DEVICE(&s->uart), 0, memmap[IBEX_DEV_UART].base); 153cc411260SAlistair Francis sysbus_connect_irq(SYS_BUS_DEVICE(&s->uart), 154cc411260SAlistair Francis 0, qdev_get_gpio_in(DEVICE(&s->plic), 155cc411260SAlistair Francis IBEX_UART_TX_WATERMARK_IRQ)); 156cc411260SAlistair Francis sysbus_connect_irq(SYS_BUS_DEVICE(&s->uart), 157cc411260SAlistair Francis 1, qdev_get_gpio_in(DEVICE(&s->plic), 158cc411260SAlistair Francis IBEX_UART_RX_WATERMARK_IRQ)); 159cc411260SAlistair Francis sysbus_connect_irq(SYS_BUS_DEVICE(&s->uart), 160cc411260SAlistair Francis 2, qdev_get_gpio_in(DEVICE(&s->plic), 161cc411260SAlistair Francis IBEX_UART_TX_EMPTY_IRQ)); 162cc411260SAlistair Francis sysbus_connect_irq(SYS_BUS_DEVICE(&s->uart), 163cc411260SAlistair Francis 3, qdev_get_gpio_in(DEVICE(&s->plic), 164cc411260SAlistair Francis IBEX_UART_RX_OVERFLOW_IRQ)); 165cc411260SAlistair Francis 166fe0fe473SAlistair Francis create_unimplemented_device("riscv.lowrisc.ibex.gpio", 16730c717cbSEduardo Habkost memmap[IBEX_DEV_GPIO].base, memmap[IBEX_DEV_GPIO].size); 168fe0fe473SAlistair Francis create_unimplemented_device("riscv.lowrisc.ibex.spi", 16930c717cbSEduardo Habkost memmap[IBEX_DEV_SPI].base, memmap[IBEX_DEV_SPI].size); 170*d31e970aSAlistair Francis create_unimplemented_device("riscv.lowrisc.ibex.i2c", 171*d31e970aSAlistair Francis memmap[IBEX_DEV_I2C].base, memmap[IBEX_DEV_I2C].size); 172*d31e970aSAlistair Francis create_unimplemented_device("riscv.lowrisc.ibex.pattgen", 173*d31e970aSAlistair Francis memmap[IBEX_DEV_PATTGEN].base, memmap[IBEX_DEV_PATTGEN].size); 174fe0fe473SAlistair Francis create_unimplemented_device("riscv.lowrisc.ibex.rv_timer", 17530c717cbSEduardo Habkost memmap[IBEX_DEV_RV_TIMER].base, memmap[IBEX_DEV_RV_TIMER].size); 176*d31e970aSAlistair Francis create_unimplemented_device("riscv.lowrisc.ibex.sensor_ctrl", 177*d31e970aSAlistair Francis memmap[IBEX_DEV_SENSOR_CTRL].base, memmap[IBEX_DEV_SENSOR_CTRL].size); 178*d31e970aSAlistair Francis create_unimplemented_device("riscv.lowrisc.ibex.otp_ctrl", 179*d31e970aSAlistair Francis memmap[IBEX_DEV_OTP_CTRL].base, memmap[IBEX_DEV_OTP_CTRL].size); 180fe0fe473SAlistair Francis create_unimplemented_device("riscv.lowrisc.ibex.pwrmgr", 18130c717cbSEduardo Habkost memmap[IBEX_DEV_PWRMGR].base, memmap[IBEX_DEV_PWRMGR].size); 182fe0fe473SAlistair Francis create_unimplemented_device("riscv.lowrisc.ibex.rstmgr", 18330c717cbSEduardo Habkost memmap[IBEX_DEV_RSTMGR].base, memmap[IBEX_DEV_RSTMGR].size); 184fe0fe473SAlistair Francis create_unimplemented_device("riscv.lowrisc.ibex.clkmgr", 18530c717cbSEduardo Habkost memmap[IBEX_DEV_CLKMGR].base, memmap[IBEX_DEV_CLKMGR].size); 186*d31e970aSAlistair Francis create_unimplemented_device("riscv.lowrisc.ibex.pinmux", 187*d31e970aSAlistair Francis memmap[IBEX_DEV_PINMUX].base, memmap[IBEX_DEV_PINMUX].size); 188*d31e970aSAlistair Francis create_unimplemented_device("riscv.lowrisc.ibex.padctrl", 189*d31e970aSAlistair Francis memmap[IBEX_DEV_PADCTRL].base, memmap[IBEX_DEV_PADCTRL].size); 190*d31e970aSAlistair Francis create_unimplemented_device("riscv.lowrisc.ibex.usbdev", 191*d31e970aSAlistair Francis memmap[IBEX_DEV_USBDEV].base, memmap[IBEX_DEV_USBDEV].size); 192*d31e970aSAlistair Francis create_unimplemented_device("riscv.lowrisc.ibex.flash_ctrl", 193*d31e970aSAlistair Francis memmap[IBEX_DEV_FLASH_CTRL].base, memmap[IBEX_DEV_FLASH_CTRL].size); 194fe0fe473SAlistair Francis create_unimplemented_device("riscv.lowrisc.ibex.aes", 19530c717cbSEduardo Habkost memmap[IBEX_DEV_AES].base, memmap[IBEX_DEV_AES].size); 196fe0fe473SAlistair Francis create_unimplemented_device("riscv.lowrisc.ibex.hmac", 19730c717cbSEduardo Habkost memmap[IBEX_DEV_HMAC].base, memmap[IBEX_DEV_HMAC].size); 198*d31e970aSAlistair Francis create_unimplemented_device("riscv.lowrisc.ibex.kmac", 199*d31e970aSAlistair Francis memmap[IBEX_DEV_KMAC].base, memmap[IBEX_DEV_KMAC].size); 200*d31e970aSAlistair Francis create_unimplemented_device("riscv.lowrisc.ibex.keymgr", 201*d31e970aSAlistair Francis memmap[IBEX_DEV_KEYMGR].base, memmap[IBEX_DEV_KEYMGR].size); 202*d31e970aSAlistair Francis create_unimplemented_device("riscv.lowrisc.ibex.csrng", 203*d31e970aSAlistair Francis memmap[IBEX_DEV_CSRNG].base, memmap[IBEX_DEV_CSRNG].size); 204*d31e970aSAlistair Francis create_unimplemented_device("riscv.lowrisc.ibex.entropy", 205*d31e970aSAlistair Francis memmap[IBEX_DEV_ENTROPY].base, memmap[IBEX_DEV_ENTROPY].size); 206*d31e970aSAlistair Francis create_unimplemented_device("riscv.lowrisc.ibex.edn0", 207*d31e970aSAlistair Francis memmap[IBEX_DEV_EDNO].base, memmap[IBEX_DEV_EDNO].size); 208*d31e970aSAlistair Francis create_unimplemented_device("riscv.lowrisc.ibex.edn1", 209*d31e970aSAlistair Francis memmap[IBEX_DEV_EDN1].base, memmap[IBEX_DEV_EDN1].size); 210fe0fe473SAlistair Francis create_unimplemented_device("riscv.lowrisc.ibex.alert_handler", 21130c717cbSEduardo Habkost memmap[IBEX_DEV_ALERT_HANDLER].base, memmap[IBEX_DEV_ALERT_HANDLER].size); 212fe0fe473SAlistair Francis create_unimplemented_device("riscv.lowrisc.ibex.nmi_gen", 21330c717cbSEduardo Habkost memmap[IBEX_DEV_NMI_GEN].base, memmap[IBEX_DEV_NMI_GEN].size); 214*d31e970aSAlistair Francis create_unimplemented_device("riscv.lowrisc.ibex.otbn", 215*d31e970aSAlistair Francis memmap[IBEX_DEV_OTBN].base, memmap[IBEX_DEV_OTBN].size); 216fe0fe473SAlistair Francis } 217fe0fe473SAlistair Francis 21889494462SBin Meng static void lowrisc_ibex_soc_class_init(ObjectClass *oc, void *data) 219fe0fe473SAlistair Francis { 220fe0fe473SAlistair Francis DeviceClass *dc = DEVICE_CLASS(oc); 221fe0fe473SAlistair Francis 22289494462SBin Meng dc->realize = lowrisc_ibex_soc_realize; 223fe0fe473SAlistair Francis /* Reason: Uses serial_hds in realize function, thus can't be used twice */ 224fe0fe473SAlistair Francis dc->user_creatable = false; 225fe0fe473SAlistair Francis } 226fe0fe473SAlistair Francis 22789494462SBin Meng static const TypeInfo lowrisc_ibex_soc_type_info = { 228fe0fe473SAlistair Francis .name = TYPE_RISCV_IBEX_SOC, 229fe0fe473SAlistair Francis .parent = TYPE_DEVICE, 230fe0fe473SAlistair Francis .instance_size = sizeof(LowRISCIbexSoCState), 23189494462SBin Meng .instance_init = lowrisc_ibex_soc_init, 23289494462SBin Meng .class_init = lowrisc_ibex_soc_class_init, 233fe0fe473SAlistair Francis }; 234fe0fe473SAlistair Francis 23589494462SBin Meng static void lowrisc_ibex_soc_register_types(void) 236fe0fe473SAlistair Francis { 23789494462SBin Meng type_register_static(&lowrisc_ibex_soc_type_info); 238fe0fe473SAlistair Francis } 239fe0fe473SAlistair Francis 24089494462SBin Meng type_init(lowrisc_ibex_soc_register_types) 241